On Tue, Aug 27, 2013 at 8:04 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Dear Yuvaraj,
On 08/26/2013 06:20 PM, Yuvaraj Kumar wrote:
On Fri, Aug 23, 2013 at 7:14 PM, Jaehoon Chung jh80.ch...@samsung.com
wrote:
Hi Yuvaraj,
On 08/23/2013 08:15 PM, Yuvaraj Kumar C D wrote:
Currently
Hi Mike,
On Mon, Aug 19, 2013 at 2:18 PM, Padma Venkat padma@gmail.com wrote:
Hi Mike,
On Fri, Aug 16, 2013 at 1:19 PM, Padmavathi Venna padm...@samsung.com wrote:
This patch set adds support for audio subsystem clks on Exynos5420.
Exynos5420
audio subsystem has a gate bit for ADMA
--- Original Message ---
Sender : Doug Andersondiand...@google.com
Date : Aug 24, 2013 09:18 (GMT+05:30)
Title : Re: [PATCH V3] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
Yuvaraj,
On Thu, Aug 22, 2013 at 11:25 PM, Yuvaraj Cd wrote:
b.card-detect-delay
Hi Sherman,
Thank you for the patch.
On Sunday 25 August 2013 19:41:39 Sherman Yin wrote:
When setting pin configuration in the pinctrl framework, pin_config_set() or
pin_config_group_set() is called in a loop to set one configuration at a
time for the specified pin or group.
This patch 1)
Hi,
[trimming down to relevant context]
+endpoint node
+-
+
+- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
+ video-interfaces.txt. This property can be only used to specify number
+ of data lanes, i.e. the array's content is unused, only its length
This patch implements pinctrl for s5pv210 and adds required device tree
bindings.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-exynos.c | 58 +++
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
This patch depends on
mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
changes
Hi,
Just a few nits...
On 08/27/2013 11:19 AM, Mateusz Krawczuk wrote:
This patch implements pinctrl for s5pv210 and adds required device tree
bindings.
Would be good to wrap this to not exceed 80 columns.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
[...]
diff
Am Dienstag, 27. August 2013, 03:11:26 schrieb Dan Carpenter:
If irq == NUM_EINT then it writes one space beyond the end of the
eint_data-domains[] array.
Thanks for catching this.
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
Reviewed-by: Heiko Stuebner he...@sntech.de
diff
This patch removes the global variables in the driver file and
group them into a structure.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
Note: This patch is rebased on kgene's for-next branch
Hello Wim,
Thanks for reviewing the patch.
Posted Version 4 addressing your comments.
Best Wishes,
Leela Krishna Amudala.
On Fri, Aug 23, 2013 at 8:19 PM, Wim Van Sebroeck w...@iguana.be wrote:
Hi Leela,
---
Note: This patch is rebased on kgene's for-next branch and tested on
On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
This patch depends on
Hi Andrejz,
On Monday 26 August 2013 14:34:21 Andrzej Hajda wrote:
On 08/23/2013 02:53 PM, Laurent Pinchart wrote:
On Wednesday 21 August 2013 16:41:31 Andrzej Hajda wrote:
Driver for Samsung S5K5BAF UXGA 1/5 2M CMOS Image Sensor
with embedded SoC ISP.
The driver exposes the sensor as
On Tue, Aug 27, 2013 at 4:31 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is
On 08/27/2013 11:30 AM, Sylwester Nawrocki wrote:
Hi,
Just a few nits...
On 08/27/2013 11:19 AM, Mateusz Krawczuk wrote:
This patch implements pinctrl for s5pv210 and adds required device tree
bindings.
Would be good to wrap this to not exceed 80 columns.
Signed-off-by: Mateusz Krawczuk
Fixes the watchdog DT node name for Exynos5 as per the DT node naming
convention also update status property for Exynos5250 SoC.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi|2 +-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
2 files
Hi Mateusz,
Is this a series of 4 patches? Apparently I have received only this one.
On Tuesday 27 of August 2013 11:19:31 Mateusz Krawczuk wrote:
This patch implements pinctrl for s5pv210 and adds required device tree
bindings.
This should be wrapped to have lines shorter than 80 characters.
Add watchdog device tree node for exynos5420
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..9fadc23
This patchset does the following things
- Fixes the watchdog DT node name to follow convention
- Adds watchdog DT node to Exynos5420 SoC
Note: This series is rebased and tested on Kgene's for-next branch
Leela Krishna Amudala (2):
ARM: dts: Fix the watchdog DT node name for
Hi Sylwester,
On Tuesday 27 of August 2013 11:30:09 Sylwester Nawrocki wrote:
Hi,
Just a few nits...
On 08/27/2013 11:19 AM, Mateusz Krawczuk wrote:
This patch implements pinctrl for s5pv210 and adds required device tree
bindings.
Would be good to wrap this to not exceed 80 columns.
On 08/27/2013 02:22 PM, Tomasz Figa wrote:
Hi Mateusz,
Is this a series of 4 patches? Apparently I have received only this one.
No, I send wrong version of this patch, other patches are completely
unrelated to this one.
On Tuesday 27 of August 2013 11:19:31 Mateusz Krawczuk wrote:
This
Hi Yuvaraj,
On Tuesday 27 of August 2013 17:32:52 Yuvaraj Kumar wrote:
On Tue, Aug 27, 2013 at 4:31 PM, Mark Rutland mark.rutl...@arm.com
wrote:
On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420
This patch implements pinctrl support and adds device tree bindings
for s5pv210.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt | 3 +-
drivers/pinctrl/Kconfig| 2 +-
Hi Mateusz,
On Tuesday 27 of August 2013 15:08:10 Mateusz Krawczuk wrote:
This patch implements pinctrl support and adds device tree bindings
for s5pv210.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt | 3 +-
On Tue, Aug 27, 2013 at 01:02:52PM +0100, Yuvaraj Kumar wrote:
On Tue, Aug 27, 2013 at 4:31 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a
On Sun, Aug 25, 2013 at 02:23:18PM +0200, Sylwester Nawrocki wrote:
On 08/23/2013 11:46 AM, Dan Carpenter wrote:
[ Going through some old warnings... ]
Hello Sylwester Nawrocki,
This is a semi-automatic email about new static checker warnings.
The patch babde1c243b2: [media] V4L: Add
On 08/27/2013 04:19 PM, Dan Carpenter wrote:
On Sun, Aug 25, 2013 at 02:23:18PM +0200, Sylwester Nawrocki wrote:
On 08/23/2013 11:46 AM, Dan Carpenter wrote:
[ Going through some old warnings... ]
Hello Sylwester Nawrocki,
This is a semi-automatic email about new static checker warnings.
On 08/24/2013 12:45 AM, Stephen Warren wrote:
On 08/23/2013 10:01 AM, Sylwester Nawrocki wrote:
On 08/18/2013 10:14 PM, Sylwester Nawrocki wrote:
This patch enables the JPEG codec on S5PV210 and Exynos4210 SoCs. There
are
some differences in newer versions of the JPEG codec IP on SoCs
On 08/27/13 13:08, Kevin Hilman wrote:
amit daniel kachhapamit.dan...@samsung.com writes:
Submitted the V2 version of this patch with your suggestion.
So will there be an updated branch (and pull request) with these changes?
OK, Bart's concern makes sense so I replaced with Amit's v2
On 08/27/13 10:14, Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-20 17:33:21)
This patch modifies PLL6552 and PLL6553 clock drivers to use recently
added common Samsung PLL registration method.
Signed-off-by: Tomasz Figatomasz.f...@gmail.com
Sigh. This change won't apply on top of
On 23-08-2013 19:08, Rafael J. Wysocki wrote:
On Friday, August 23, 2013 06:03:14 PM Eduardo Valentin wrote:
When registering a new thermal_device, the thermal framework
will always add a hwmon sysfs interface.
This patch adds a flag to make this behavior optional. Now
when registering a new
On Tuesday 27 August 2013 02:08:16 Tomasz Figa wrote:
Well, if we could drop legacy board file support for them and keep them as
DT only, support for them could be reasonably simple. Basically the code
in arch/arm would be limited to a single .c file per SoC (e.g. mach-
s5pv210-dt.c), a
On Tue, Aug 13, 2013 at 02:11:27PM +0530, Tushar Behera wrote:
On 12 July 2013 12:27, Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Jul 10, 2013 at 10:42:27AM -0700, Julius Werner wrote:
Hi Felipe,
This is intended to pull down a reset signal line, not to switch power
to the device.
On Wed, Aug 28, 2013 at 12:57:25AM +0900, Kukjin Kim wrote:
On 08/27/13 13:08, Kevin Hilman wrote:
amit daniel kachhapamit.dan...@samsung.com writes:
Submitted the V2 version of this patch with your suggestion.
So will there be an updated branch (and pull request) with these changes?
Hi,
On Mon, Aug 26, 2013 at 01:44:49PM +0530, Kishon Vijay Abraham I wrote:
On Wednesday 21 August 2013 11:16 AM, Kishon Vijay Abraham I wrote:
Added a generic PHY framework that provides a set of APIs for the PHY
drivers
to create/destroy a PHY and APIs for the PHY users to obtain a
*Ping!*
Are there still unanswered concerns left with this patch? I hope my
prior mails could clear up why I think that the PMU register
description in the device tree for a specific PHY is represents the
hardware more accurately after my patch, and my analysis of the
Exynos4 situation currently
On Tuesday, August 27, 2013 02:26:41 PM Eduardo Valentin wrote:
On 23-08-2013 19:08, Rafael J. Wysocki wrote:
On Friday, August 23, 2013 06:03:14 PM Eduardo Valentin wrote:
When registering a new thermal_device, the thermal framework
will always add a hwmon sysfs interface.
This patch
Most DT ARM machs require common clock providers initialized before timers.
Currently, arch/arm machs use .init_time to call clk_of_init right before
clocksource_of_init. This prevents to remove that hook and use the default
hook instead. clk_of_init is safe to call for non-DT platforms, so add
With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Kukjin Kim kgene@samsung.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc:
requiring clocks as late as the other machs, the
patch to protect of_clk_init() from being called twice, has been dropped.
The RFCv2 is based on next-20130827 and has been compile tested for
multi_v7_defconfig and mach-dove. All single patches have also been sent
to the respective maintainers
This series tries to provide a basic dmaengine driver for the s3c24xx
SoCs to subsequently retire the old one with custom API.
Since v2 only some small fixes to the dma driver itself were added.
Since v1 three big changes happened (appart from fixing received comments):
For one the limitation
Each dma channel has its own clock. The upcoming dma driver wants to
handle these itself and therefore needs to be able to get the correct
clock for a channel.
Therefore rename the dma clocks to dma.X for s3c2412, s3c2416 and
s3c2443. This does not change the behaviour for the old dma driver at
This adds a new driver to support the s3c24xx dma using the dmaengine
and makes the old one in mach-s3c24xx obsolete in the long run.
Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
with numerous virtual channels being mapped to a lot less physical ones.
The driver
This includes defining the mapping for the request sources.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Linus Walleij linus.wall...@linaro.org
---
changes since v1:
- follow new pdata definition
arch/arm/mach-s3c24xx/common.c| 106 +
The spi-s3c64xx device is also used on the s3c2416 and s3c2443 SoCs.
The driver also already uses only generic dma-engine operations.
Therefore add another elif to set the s3c24xx filter.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Linus Walleij linus.wall...@linaro.org
---
On Tue, Aug 27, 2013 at 11:27:55PM +0200, Sebastian Hesselbarth wrote:
Most DT ARM machs require common clock providers initialized before timers.
Currently, arch/arm machs use .init_time to call clk_of_init right before
clocksource_of_init. This prevents to remove that hook and use the default
On 08/28/13 00:19, Sören Brinkmann wrote:
On Tue, Aug 27, 2013 at 11:27:55PM +0200, Sebastian Hesselbarth wrote:
Most DT ARM machs require common clock providers initialized before timers.
Currently, arch/arm machs use .init_time to call clk_of_init right before
clocksource_of_init. This
On Tuesday 27 August 2013 11:32:12 Sherman Yin wrote:
When setting pin configuration in the pinctrl framework, pin_config_set() or
pin_config_group_set() is called in a loop to set one configuration at a
time for the specified pin or group.
This patch 1) removes the loop and 2) changes the
On Wed, Aug 28, 2013 at 12:58:39AM +0200, Sebastian Hesselbarth wrote:
On 08/28/13 00:19, Sören Brinkmann wrote:
On Tue, Aug 27, 2013 at 11:27:55PM +0200, Sebastian Hesselbarth wrote:
Most DT ARM machs require common clock providers initialized before timers.
Currently, arch/arm machs use
Olof Johansson wrote:
On Wed, Aug 28, 2013 at 12:57:25AM +0900, Kukjin Kim wrote:
On 08/27/13 13:08, Kevin Hilman wrote:
amit daniel kachhapamit.dan...@samsung.com writes:
Submitted the V2 version of this patch with your suggestion.
So will there be an updated branch (and pull
The following changes since commit ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos-v2
for you to fetch changes up
On 二, 2013-08-27 at 23:17 +0200, Rafael J. Wysocki wrote:
On Tuesday, August 27, 2013 02:26:41 PM Eduardo Valentin wrote:
On 23-08-2013 19:08, Rafael J. Wysocki wrote:
On Friday, August 23, 2013 06:03:14 PM Eduardo Valentin wrote:
When registering a new thermal_device, the thermal
Quoting Padmavathi Venna (2013-08-16 00:49:36)
From: Andrew Bresticker abres...@chromium.org
Different Exynos SoCs have different names for certain input clocks
to the AudioSS block. Since the order in which clock providers are
probed is not guaranteed, we can't use the device-tree to pass
Hi Arnd, Olof and Kevin,
Sorry for a bit late pull-request.
Here is s3c64xx DT series and common clk stuff. It took some time due to
dependency problem with the clk tree, and fixed now by merge clk-s3c64xx
branch in Mike's clk tree. So many clock patches are included in 1st
pull-request but most
The following changes since commit 1ca2dad9588ac09310154a480f8f9cf400760a31:
Merge branch 'clk-next-s3c64xx-delta' into v3.12-next/common-clk-s3c64xx
(2013-08-28 01:03:31 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
The following changes since commit c095ba7224d8edc71dcef0d655911399a8bd4a3f:
Linux 3.11-rc4 (2013-08-04 13:46:46 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-clk-s3c64xx
for you to fetch changes up to
On Tuesday 27 of August 2013 17:43:41 Mike Turquette wrote:
Quoting Padmavathi Venna (2013-08-16 00:49:36)
From: Andrew Bresticker abres...@chromium.org
Different Exynos SoCs have different names for certain input clocks
to the AudioSS block. Since the order in which clock providers
On 28 August 2013 00:14, Felipe Balbi ba...@ti.com wrote:
On Tue, Aug 13, 2013 at 02:11:27PM +0530, Tushar Behera wrote:
On 12 July 2013 12:27, Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Jul 10, 2013 at 10:42:27AM -0700, Julius Werner wrote:
Hi Felipe,
This is intended to pull down
Hi Mike,
On Thu, Aug 22, 2013 at 12:30 PM, Vikas Sajjan sajjan.li...@gmail.com wrote:
Hi Mike,
On Wed, Aug 14, 2013 at 9:07 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Vikas,
On Wednesday 14 of August 2013 10:36:53 Vikas Sajjan wrote:
Hi Mike,
On Mon, Aug 12, 2013 at 3:32 PM, Vikas
On 23 May 2013 10:55, Naveen Krishna Ch naveenkrishna...@gmail.com wrote:
On 23 May 2013 02:46, Jonathan Cameron ji...@kernel.org wrote:
On 05/20/2013 06:09 PM, Doug Anderson wrote:
Naveen,
On Sun, May 19, 2013 at 11:34 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
The
This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c |4 ++
The FALL interrupt related en, status bits are available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.
This patch corrects the same for exyns5250 and exynos5440
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
This patch adds code to handle the misplaced TRIMINFO register
incase of Exynos5420.
On Exynos5420 we have a TRIMINFO register being misplaced for
TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a contains data for TMU channel 4
TRIMINFO at
The below patchset adds the TMU support for Exynos5420
1. correct the fall interrupt en, status bit fields
Fixes an existing bug in the register field access
2. Add TMU support for Exynos5420 SoCs
Adds support for Exynos5420. (These changes were tested on a different
kernel version)
3.
Hi Yuvaraj
On Fri, Aug 23, 2013 at 4:45 PM, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
changes from V1:
1.Added a new RFC patch
mmc: dw_mmc: socfpga: move socfpga private init
2.Avoid code duplication in
mmc: dw_mmc: exynos: add a quirk for
On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
The FALL interrupt related en, status bits are available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.
This patch corrects the same for exyns5250 and
On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
Signed-off-by: Naveen Krishna Chatradhi
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