Re: [PATCH v2 00/12] clk/exynos convert clock IDs to macros
On 10/06/2013 10:27 PM, Mike Turquette wrote: Quoting Kukjin Kim (2013-10-04 19:16:56) Mike Turquette wrote: Quoting Kukjin Kim (2013-09-30 03:11:41) Mike Turquette wrote: Quoting Sylwester Nawrocki (2013-09-16 07:33:45) On 09/12/2013 12:50 PM, Kukjin Kim wrote: Well...I'm not sure changing to use macro is better or not at this moment... I think it is. ;) It's really less error prone to have symbolic names instead of the plain numbers. The clock ids are defined in one place and it is more clear what a clock is by looking at symbolic name. It's especially annoying to use plain numbers where are are many clock in a single node, like 10 or more. What are you main concerns with this ? I think having the symbolic names is a win for readability. Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though. Mike, can you give me your ack on clk stuff? Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight. Let me know if it causes problems for you for me to take it. Uhm, I think dt changes can make ugly conflicts because of spread dt changing? Sure, go ahead and take the patches then. Acked-by: Mike Turquette mturque...@linaro.org Regards, Mike I can create patchset based on different git branch if neccessary. Regards Andrzej - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND] [PATCH V3] ARM: dts: Add DMA controller node info on Exynos5420.
From: Padmavathi Venna padm...@samsung.com
This patch adds dma controller node info on Exynos5420.
Exynos5420 has adma for audio IPs. As adma clk is dependent
on audss clk provider that will be added later.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
Change since V2:
- Removed adma node as adma clock is dependent audss clock provider.
Changes since V1:
- In V1, dma node common stuff was added in common exynos5.dtsi file.
This was removed as per Kukjin comment and added in exynos5420.dtsi.
arch/arm/boot/dts/exynos5420.dtsi | 52 +
1 file changed, 52 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..15465f8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -186,6 +186,58 @@
status = okay;
};
+ amba {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = arm,amba-bus;
+ interrupt-parent = gic;
+ ranges;
+
+ pdma0: pdma@121A {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121A 0x1000;
+ interrupts = 0 34 0;
+ clocks = clock 362;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@121B {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121B 0x1000;
+ interrupts = 0 35 0;
+ clocks = clock 363;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ mdma0: mdma@1080 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1080 0x1000;
+ interrupts = 0 33 0;
+ clocks = clock 473;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+
+ mdma1: mdma@11C1 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x11C1 0x1000;
+ interrupts = 0 124 0;
+ clocks = clock 442;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+ };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
--
1.7.10.4
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[RESEND] [PATCH] ARM: dts: Add SPI nodes to the exynos5420 device tree file
Add SPI device tree nodes to Exynos5420 SoC
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Reviewed-by: Andrew Bresticker abres...@chromium.org
---
Note: This patch is rebased on Kgene's for-next branch and is dependent on
[RESEND,V3] ARM: dts: Add DMA controller node info on Exynos5420.
https://patchwork.kernel.org/patch/2995181/
arch/arm/boot/dts/exynos5420.dtsi | 51 +
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 15465f8..8d9e980 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -27,6 +27,9 @@
pinctrl2 = pinctrl_2;
pinctrl3 = pinctrl_3;
pinctrl4 = pinctrl_4;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
};
cpus {
@@ -238,6 +241,54 @@
};
};
+ spi_0: spi@12d2 {
+ compatible = samsung,exynos4210-spi;
+ reg = 0x12d2 0x100;
+ interrupts = 0 66 0;
+ dmas = pdma0 5
+ pdma0 4;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ clocks = clock 271, clock 135;
+ clock-names = spi, spi_busclk0;
+ status = disabled;
+ };
+
+ spi_1: spi@12d3 {
+ compatible = samsung,exynos4210-spi;
+ reg = 0x12d3 0x100;
+ interrupts = 0 67 0;
+ dmas = pdma1 5
+ pdma1 4;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi1_bus;
+ clocks = clock 272, clock 136;
+ clock-names = spi, spi_busclk0;
+ status = disabled;
+ };
+
+ spi_2: spi@12d4 {
+ compatible = samsung,exynos4210-spi;
+ reg = 0x12d4 0x100;
+ interrupts = 0 68 0;
+ dmas = pdma0 7
+ pdma0 6;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi2_bus;
+ clocks = clock 273, clock 137;
+ clock-names = spi, spi_busclk0;
+ status = disabled;
+ };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
--
1.7.10.4
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Re: [PATCH v5 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
Hi Vinod, with the removed double-retrival of the cookie state, is the driver ok now? Because I think kgene needs an ack on it. Thanks Heiko Am Mittwoch, 18. September 2013, 21:19:54 schrieb Heiko Stübner: This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run. Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later. On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral. Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver. Signed-off-by: Heiko Stuebner he...@sntech.de Acked-by: Linus Walleij linus.wall...@linaro.org --- changes since v4: - fix the unnecessary double retrieval of the cookie status pointed out by Vinod Koul changes since v3: - address comments from Tomasz Figa: - fixed a lot of nitpics - and added a rudimentary mechanism to select higher bus-widths for memcpy - address more comments from Vinod Koul - reorder dma_control contents changes since v2: - add missing channel validation in s3c24xx_dma_phy_free when repurposing a physical channel for another virtual channel - address comments from Vinod Koul: - fix naming of constants to prevent conflicts - better handle the unlikely case of an interrupt happening on an unused channel changes since v1: - address comments from Linus Walleij - support sg-lists with more than 1 element - add support for earlier s3c24xx SoCs - redo the channeldata definitions: - no need for static ids for the virtual channels - provide a way to encode constraints for earlier variants - better base for later dt bindings drivers/dma/Kconfig | 12 + drivers/dma/Makefile |1 + drivers/dma/s3c24xx-dma.c | 1340 + include/linux/platform_data/dma-s3c24xx.h | 43 + 4 files changed, 1396 insertions(+) create mode 100644 drivers/dma/s3c24xx-dma.c create mode 100644 include/linux/platform_data/dma-s3c24xx.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 526ec77..d639115 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -154,6 +154,18 @@ config TEGRA20_APB_DMA This DMA controller transfers data from memory to peripheral fifo or vice versa. It does not support memory to memory data transfer. +config S3C24XX_DMAC + tristate Samsung S3C24XX DMA support + depends on ARCH_S3C24XX !S3C24XX_DMA + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support for the Samsung S3C24XX DMA controller driver. The + DMA controller is having multiple DMA channels which can be + configured for different peripherals like audio, UART, SPI. + The DMA controller can transfer data from memory to peripheral, + periphal to memory, periphal to periphal and memory to memory. + source drivers/dma/sh/Kconfig config COH901318 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index db89035..0ce2da9 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o +obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o obj-$(CONFIG_PL330_DMA) += pl330.o obj-$(CONFIG_PCH_DMA) += pch_dma.o obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c new file mode 100644 index 000..56c9253 --- /dev/null +++ b/drivers/dma/s3c24xx-dma.c @@ -0,0 +1,1340 @@ +/* + * S3C24XX DMA handling + * + * Copyright (c) 2013 Heiko Stuebner he...@sntech.de + * + * based on amba-pl08x.c + * + * Copyright (c) 2006 ARM Ltd. + * Copyright (c) 2010 ST-Ericsson SA + * + * Author: Peter Pearse peter.pea...@arm.com + * Author: Linus Walleij linus.wall...@stericsson.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * The DMA controllers in S3C24XX SoCs have a varying number of DMA signals + * that can be routed to any of the 4 to 8 hardware-channels. + * + * Therefore on these DMA controllers the number of channels +
RE: [PATCH v5 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
Heiko Stübner wrote: Hi Vinod, with the removed double-retrival of the cookie state, is the driver ok now? Because I think kgene needs an ack on it. Yes! Vinod, do you OK on this? If you have any concerns, please kindly let us know. Thanks, Kukjin Thanks Heiko Am Mittwoch, 18. September 2013, 21:19:54 schrieb Heiko Stübner: This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run. Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later. On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral. Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver. Signed-off-by: Heiko Stuebner he...@sntech.de Acked-by: Linus Walleij linus.wall...@linaro.org --- changes since v4: - fix the unnecessary double retrieval of the cookie status pointed out by Vinod Koul changes since v3: - address comments from Tomasz Figa: - fixed a lot of nitpics - and added a rudimentary mechanism to select higher bus-widths for memcpy - address more comments from Vinod Koul - reorder dma_control contents changes since v2: - add missing channel validation in s3c24xx_dma_phy_free when repurposing a physical channel for another virtual channel - address comments from Vinod Koul: - fix naming of constants to prevent conflicts - better handle the unlikely case of an interrupt happening on an unused channel changes since v1: - address comments from Linus Walleij - support sg-lists with more than 1 element - add support for earlier s3c24xx SoCs - redo the channeldata definitions: - no need for static ids for the virtual channels - provide a way to encode constraints for earlier variants - better base for later dt bindings drivers/dma/Kconfig | 12 + drivers/dma/Makefile |1 + drivers/dma/s3c24xx-dma.c | 1340 + include/linux/platform_data/dma-s3c24xx.h | 43 + 4 files changed, 1396 insertions(+) create mode 100644 drivers/dma/s3c24xx-dma.c create mode 100644 include/linux/platform_data/dma-s3c24xx.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 526ec77..d639115 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -154,6 +154,18 @@ config TEGRA20_APB_DMA This DMA controller transfers data from memory to peripheral fifo or vice versa. It does not support memory to memory data transfer. +config S3C24XX_DMAC + tristate Samsung S3C24XX DMA support + depends on ARCH_S3C24XX !S3C24XX_DMA + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support for the Samsung S3C24XX DMA controller driver. The + DMA controller is having multiple DMA channels which can be + configured for different peripherals like audio, UART, SPI. + The DMA controller can transfer data from memory to peripheral, + periphal to memory, periphal to periphal and memory to memory. + source drivers/dma/sh/Kconfig config COH901318 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index db89035..0ce2da9 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o +obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o obj-$(CONFIG_PL330_DMA) += pl330.o obj-$(CONFIG_PCH_DMA) += pch_dma.o obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c new file mode 100644 index 000..56c9253 --- /dev/null +++ b/drivers/dma/s3c24xx-dma.c @@ -0,0 +1,1340 @@ +/* + * S3C24XX DMA handling + * + * Copyright (c) 2013 Heiko Stuebner he...@sntech.de + * + * based on amba-pl08x.c + * + * Copyright (c) 2006 ARM Ltd. + * Copyright (c) 2010 ST-Ericsson SA + * + * Author: Peter Pearse peter.pea...@arm.com + * Author: Linus Walleij linus.wall...@stericsson.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later
Re: Re: Ask for help on SPI slave side driver support
On Sat, Oct 05, 2013 at 12:25:10AM +0800, YouShenghui wrote: At 2013-09-30 17:33:17,Mark Brown broo...@kernel.org wrote: On Mon, Sep 30, 2013 at 01:20:42AM +0200, Tomasz Figa wrote: Mark will probably know better, but AFAIK there is no API for slave mode SPI available in Linux kernel. Please correct me if I'm wrong. That's correct. The code mentioned in the post from your link was some internal vendor code, which is unlikely to be available publicly. However support for slave mode from hardware side seems more or less similar to master mode, which means that assuming you can add some kernel API for it, the modification to the spi-s3c64xx wouldn't be too big. There were some people working on slave mode (or at least talking about it) but I don't think they ever sent it. It'd probably just be the same as master mode but with transfers triggered from /CS instead of from driver action. The biggest trick would be making sure the transfer is running before the master actually starts sending data The formatting of your mail is really bad, I can barely read it. Please check the configuration of your mail program, there are some suggstions for common clients in Documentation/email-clients.txt. Thanks for Mark for your answer. But how could I trigger from /CS? Could I enable transfer in open syscall? I'd expect this to be done in-kernel, at least in the first instance. signature.asc Description: Digital signature
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Re: [PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos SoCs
On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo pullip@samsung.com wrote: Signed-off-by: Cho KyongHo pullip@samsung.com --- .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++ arch/arm/boot/dts/exynos4.dtsi | 122 arch/arm/boot/dts/exynos4210.dtsi | 25 ++ arch/arm/boot/dts/exynos4x12.dtsi | 76 + arch/arm/boot/dts/exynos5250.dtsi | 291 5 files changed, 617 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt new file mode 100644 index 000..92f0a33 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt @@ -0,0 +1,103 @@ +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit) + +Samsung's Exynos architecture contains System MMU that enables scattered +physical memory chunks visible as a contiguous region to DMA-capable peripheral +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. + +System MMU is a sort of IOMMU and support identical translation table format to +ARMv7 translation tables with minimum set of page properties including access +permissions, shareability and security protection. In addition, System MMU has +another capabilities like L2 TLB or block-fetch buffers to minimize translation +latency. + +A System MMU is dedicated to a single master peripheral device. Thus, it is +important to specify the correct System MMU in the device node of its master +device. Whereas a System MMU is dedicated to a master device, the master device +may have more than one System MMU. + +Required properties: +- compatible: Should be samsung,exynos4210-sysmmu +- reg: A tuple of base address and size of System MMU registers. +- interrupt-parent: The phandle of the interrupt controller of System MMU +- interrupts: A tuple of numbers that indicates the interrupt source. +- clock-names: Should be sysmmu if the System MMU is needed to gate its clock. + Please refer to the following documents: + Documentation/devicetree/bindings/clock/clock-bindings.txt + Documentation/devicetree/bindings/clock/exynos4-clock.txt + Documentation/devicetree/bindings/clock/exynos5250-clock.txt + Optional master if the clock to the System MMU is gated by + another gate clock other than sysmmu. The System MMU driver + sets master the parent of sysmmu. + Exynos4 SoCs, there needs no master clocks. + Exynos5 SoCs, some System MMUs must have master clocks. +- clocks: Required if the System MMU is needed to gate its clock. + Please refer to the documents listed above. +- samsung,power-domain: Required if the System MMU is needed to gate its power. + Please refer to the following document: + Documentation/devicetree/bindings/arm/exynos/power_domain.txt + +Required properties for the master peripheral devices: +- iommu: phandles to the System MMUs of the device You have not addressed my comments from the last version. We do not need 2 (or more) different ways to describe the connection between masters and iommu's. Use mmu-masters property here to describe the connection. Rob -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/6] ARM: EXYNOS: add Exynos Dual Cluster Support
On Fri, Oct 04, 2013 at 03:51:31PM -0400, Nicolas Pitre wrote:
On Wed, 2 Oct 2013, Dave Martin wrote:
On Tue, Oct 01, 2013 at 08:17:04PM +0400, Vyacheslav Tyrtov wrote:
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ int ret;
+ local_irq_disable();
Should there be a local_fiq_disable() here also?
No. In fact this is paired with
+ arch_spin_lock(exynos_lock);
to create the equivalent of a arch_spin_lock_irq(). And the reason is:
/*
* We can't use regular spinlocks. In the switcher case, it is possible
* for an outbound CPU to call power_down() after its inbound counterpart
* is already live using the same logical CPU number which trips lockdep
* debugging.
*/
Otherwise we simply would have used spin_lock_irq().
Duh, of course. Looks like I suffered temporary brain failure there.
No FIQs are supposed to ever race with this code.
There is an anomaly though: FIQ and external abort don't seem to get
explicitly masked anywhere, either on the suspend or powerdown paths.
Sometimes either or both remains unmasked (I tried some trace in the
TC2 MCPM backend to confirm this.)
Looks like a possible omission in the arch/arm/ suspend and shutdown
code, rather than a problem specific to MCPM.
Shouldn't be an issue for this series, though.
Cheers
---Dave
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Re: [PATCH 2/3] Phy: Exynos: Add Exynos5250 sata phy driver
On Tue, Oct 1, 2013 at 6:21 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Tuesday 01 October 2013 12:03 PM, Yuvaraj Kumar C D wrote:
This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
phy comprises of CMU and TRSV blocks which are of I2C register Map.
So this patch also adds a i2c client driver, which is used configure
the CMU and TRSV block of exynos5250 SATA PHY.
Why not make the Exynos5250 sata phy as a i2c client driver instead?
This patch incorporates the generic phy framework to deal with sata
phy.
This patch depends on the below patch
[1].drivers: phy: add generic PHY framework
by Kishon Vijay Abraham Ikis...@ti.com
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Signed-off-by: Girish K S ks.g...@samsung.com
Signed-off-by: Vasanth Ananthan vasant...@samsung.com
---
drivers/phy/Kconfig |6 +
drivers/phy/Makefile |1 +
drivers/phy/exynos/Kconfig |5 +
drivers/phy/exynos/Makefile |5 +
drivers/phy/exynos/exynos5250_phy_i2c.c | 53 +++
drivers/phy/exynos/sata_phy_exynos5250.c | 248
++
drivers/phy/exynos/sata_phy_exynos5250.h | 33
7 files changed, 351 insertions(+)
create mode 100644 drivers/phy/exynos/Kconfig
create mode 100644 drivers/phy/exynos/Makefile
create mode 100644 drivers/phy/exynos/exynos5250_phy_i2c.c
create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.c
create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5f85909..ab3d1c6 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -11,3 +11,9 @@ menuconfig GENERIC_PHY
devices present in the kernel. This layer will have the generic
API by which phy drivers can create PHY using the phy framework and
phy users can obtain reference to the PHY.
+
+if GENERIC_PHY
NAK. Just select GENERIC_PHY from your driver Kconfig.
+
+source drivers/phy/exynos/Kconfig
+
+endif
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9e9560f..e0223d7 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_GENERIC_PHY)+= phy-core.o
+obj-$(CONFIG_PHY_SAMSUNG_SATA) += exynos/
simply have phy-exynos5250 in drivers/phy.
ok.
diff --git a/drivers/phy/exynos/Kconfig b/drivers/phy/exynos/Kconfig
new file mode 100644
index 000..fa125fb
--- /dev/null
+++ b/drivers/phy/exynos/Kconfig
@@ -0,0 +1,5 @@
+config PHY_SAMSUNG_SATA
+ tristate Samsung Sata SerDes/PHY driver
+ help
+ Support for Samsung sata SerDes/Phy found on Samsung
+ SoCs.
diff --git a/drivers/phy/exynos/Makefile b/drivers/phy/exynos/Makefile
new file mode 100644
index 000..50dc7eb
--- /dev/null
+++ b/drivers/phy/exynos/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the exynos phy drivers.
+#
+ccflags-y := -Idrivers/phy/exynos
+obj-$(CONFIG_PHY_SAMSUNG_SATA) += sata_phy_exynos5250.o
exynos5250_phy_i2c.o
diff --git a/drivers/phy/exynos/exynos5250_phy_i2c.c
b/drivers/phy/exynos/exynos5250_phy_i2c.c
new file mode 100644
index 000..9c75d3b
--- /dev/null
+++ b/drivers/phy/exynos/exynos5250_phy_i2c.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Author:
+ * Yuvaraj C D yuvaraj...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/i2c.h
+#include linux/module.h
+#include sata_phy_exynos5250.h
+
+static int exynos_sata_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *i2c_id)
+{
+ sataphy_attach_i2c_client(client);
+
+ dev_info(client-adapter-dev,
+ attached %s into i2c adapter successfully\n,
+ client-name);
+
+ return 0;
+}
+
+static int exynos_sata_i2c_remove(struct i2c_client *client)
+{
+ dev_info(client-adapter-dev,
+ detached %s from i2c adapter successfully\n,
+ client-name);
+
+ return 0;
+}
+
+static const struct i2c_device_id phy_i2c_device_match[] = {
+ { sata-phy-i2c, 0 },
+};
+MODULE_DEVICE_TABLE(of, phy_i2c_device_match);
+
+struct i2c_driver sataphy_i2c_driver = {
+ .probe= exynos_sata_i2c_probe,
+ .id_table = phy_i2c_device_match,
+ .remove = exynos_sata_i2c_remove,
+ .driver = {
+ .name = sata-phy-i2c,
+ .owner = THIS_MODULE,
+ .of_match_table = (void *)phy_i2c_device_match,
+ },
+};
As I just mentioned above, we can merge this driver with the below one.
True, Initially it was merged.But already existing
Re: [PATCH v5 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
On Wed, Sep 18, 2013 at 09:19:54PM +0200, Heiko Stübner wrote: This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run. Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later. On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral. Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver. Signed-off-by: Heiko Stuebner he...@sntech.de Acked-by: Linus Walleij linus.wall...@linaro.org Acked-by: Vinod Koul vinod.k...@intel.com -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/6] ARM: EXYNOS: add Exynos Dual Cluster Support
On Mon, 7 Oct 2013, Dave Martin wrote: On Fri, Oct 04, 2013 at 03:51:31PM -0400, Nicolas Pitre wrote: No FIQs are supposed to ever race with this code. There is an anomaly though: FIQ and external abort don't seem to get explicitly masked anywhere, either on the suspend or powerdown paths. Sometimes either or both remains unmasked (I tried some trace in the TC2 MCPM backend to confirm this.) Looks like a possible omission in the arch/arm/ suspend and shutdown code, rather than a problem specific to MCPM. Possibly, yes. Feel free to post a patch. Nicolas -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: fix PL330 MDMA1 address in DT for Universal C210 board
On 09/24/13 19:41, Bartlomiej Zolnierkiewicz wrote: Hi, On Tuesday, September 24, 2013 07:38:13 PM Kukjin Kim wrote: Bartlomiej Zolnierkiewicz wrote: Hi Kukjin, Hi Bart, Could you please apply this patch? Can you make sure there is no rev1 for universal c210 board? Universal C210 always used Exynos4210 rev0. OK, applied. Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add HDMI related I2C nodes for Arndale board
On 10/01/13 13:31, Tushar Behera wrote:
From: Sachin Kamatsachin.ka...@linaro.org
Updated I2C nodes for HDMI-DDC and HDMI-PHY for Arndale board.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
Signed-off-by: Tushar Beheratushar.beh...@linaro.org
---
arch/arm/boot/dts/exynos5250-arndale.dts | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..3a11fa0 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -324,7 +324,14 @@
};
i2c@12C8 {
- status = disabled;
+ samsung,i2c-sda-delay =100;
+ samsung,i2c-max-bus-freq =66000;
+ samsung,i2c-slave-addr =0x50;
+
+ hdmiddc@50 {
+ compatible = samsung,exynos4210-hdmiddc;
+ reg =0x50;
+ };
};
i2c@12C9 {
@@ -362,6 +369,17 @@
status = disabled;
};
+ i2c@12CE {
+ samsung,i2c-sda-delay =100;
+ samsung,i2c-max-bus-freq =66000;
+ samsung,i2c-slave-addr =0x38;
+
+ hdmiphy@38 {
+ compatible = samsung,exynos4212-hdmiphy;
+ reg =0x38;
+ };
+ };
+
i2c@121D {
status = disabled;
};
Applied, thanks.
Kukjin
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Re: [PATCH] MAINTAINERS: Add DTS files to patterns for Samsung platform
On 09/17/13 22:42, Mark Brown wrote: From: Mark Brownbroo...@linaro.org Help ensure that updates to the Samsung device trees get sent to the Samsung maintainers for review by adding file patterns to MAINTAINERS. Signed-off-by: Mark Brownbroo...@linaro.org --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6d0dabe..50e3b1f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1154,6 +1154,8 @@ L:linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) L:linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) W:http://www.fluff.org/ben/linux/ S:Maintained +F: arch/arm/boot/dts/s3c* +F: arch/arm/boot/dts/exynos* F:arch/arm/plat-samsung/ F:arch/arm/mach-s3c24*/ F:arch/arm/mach-s3c64xx/ Applied, thanks. Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v5 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
Vinod Koul wrote: On Wed, Sep 18, 2013 at 09:19:54PM +0200, Heiko Stübner wrote: This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run. Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later. On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral. Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver. Signed-off-by: Heiko Stuebner he...@sntech.de Acked-by: Linus Walleij linus.wall...@linaro.org Acked-by: Vinod Koul vinod.k...@intel.com Vinod, thanks for your ack :-) Applied this whole series. Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos SoCs
On Mon, 07 Oct 2013 08:44:54 -0500, Rob Herring wrote: On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo pullip@samsung.com wrote: Signed-off-by: Cho KyongHo pullip@samsung.com --- .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++ arch/arm/boot/dts/exynos4.dtsi | 122 arch/arm/boot/dts/exynos4210.dtsi | 25 ++ arch/arm/boot/dts/exynos4x12.dtsi | 76 + arch/arm/boot/dts/exynos5250.dtsi | 291 5 files changed, 617 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt new file mode 100644 index 000..92f0a33 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt @@ -0,0 +1,103 @@ +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit) + +Samsung's Exynos architecture contains System MMU that enables scattered +physical memory chunks visible as a contiguous region to DMA-capable peripheral +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. + +System MMU is a sort of IOMMU and support identical translation table format to +ARMv7 translation tables with minimum set of page properties including access +permissions, shareability and security protection. In addition, System MMU has +another capabilities like L2 TLB or block-fetch buffers to minimize translation +latency. + +A System MMU is dedicated to a single master peripheral device. Thus, it is +important to specify the correct System MMU in the device node of its master +device. Whereas a System MMU is dedicated to a master device, the master device +may have more than one System MMU. + +Required properties: +- compatible: Should be samsung,exynos4210-sysmmu +- reg: A tuple of base address and size of System MMU registers. +- interrupt-parent: The phandle of the interrupt controller of System MMU +- interrupts: A tuple of numbers that indicates the interrupt source. +- clock-names: Should be sysmmu if the System MMU is needed to gate its clock. + Please refer to the following documents: + Documentation/devicetree/bindings/clock/clock-bindings.txt + Documentation/devicetree/bindings/clock/exynos4-clock.txt + Documentation/devicetree/bindings/clock/exynos5250-clock.txt + Optional master if the clock to the System MMU is gated by + another gate clock other than sysmmu. The System MMU driver + sets master the parent of sysmmu. + Exynos4 SoCs, there needs no master clocks. + Exynos5 SoCs, some System MMUs must have master clocks. +- clocks: Required if the System MMU is needed to gate its clock. + Please refer to the documents listed above. +- samsung,power-domain: Required if the System MMU is needed to gate its power. + Please refer to the following document: + Documentation/devicetree/bindings/arm/exynos/power_domain.txt + +Required properties for the master peripheral devices: +- iommu: phandles to the System MMUs of the device You have not addressed my comments from the last version. We do not need 2 (or more) different ways to describe the connection between masters and iommu's. Use mmu-masters property here to describe the connection. Sorry, I forgot to reply. I just thought the meaning of your comment that it should be align with ARM System MMU. I now understand and it should be changed to mmu-masters property because it is now in the kernel. Thank you. Rob -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
