Re: [PATCH 3/4] mfd: sec-core: Add cells for S5M8767-clocks
On Tue, Nov 5, 2013 at 5:04 PM, Tushar Behera tushar.beh...@linaro.org wrote:
On 5 November 2013 13:27, Kyungmin Park kmp...@infradead.org wrote:
On Tue, Nov 5, 2013 at 3:29 PM, Tushar Behera tushar.beh...@linaro.org
wrote:
On 31 October 2013 21:46, Lee Jones lee.jo...@linaro.org wrote:
On Thu, 31 Oct 2013, Tushar Behera wrote:
S5M8767 chip has 3 crystal oscillators running at 32KHz. These are
supported by s2mps11-clk driver.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
CC: Lee Jones lee.jo...@linaro.org
---
drivers/mfd/sec-core.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
index 34c18fb..020b86b 100644
--- a/drivers/mfd/sec-core.c
+++ b/drivers/mfd/sec-core.c
@@ -56,7 +56,9 @@ static struct mfd_cell s5m8767_devs[] = {
.name = s5m8767-pmic,
}, {
.name = s5m-rtc,
- },
+ }, {
+ .name = s5m8767-clk,
Do you want to handle these as clock? previous time, it's
implemented at regulator. please see drivers/regulator/max* series.
Thank you,
Kyungmin Park
There is already a clock-implementation available for this kind of
device (through clk-s2mps11). I would like to extend that support.
Also for MAX77686, it is implemented through clock subsystem.
Yes it's possible, but losts of MAX chips are implemented already with
regulator.
but in case of maxim chip. it's voltage instead of clock. doesn't
better to use regulaor?
Ah I confused between 32KHz and Safeout. okay it's 32KHz clock. okay
it's better to use clock.
Ignore previous comments.
Thank you,
Kyungmin Park
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Re: [PATCH 1/1] Documentation/pwm: Update supported SoC name for pwm-samsung
Hi Thierry, On 30 October 2013 10:09, Sachin Kamat sachin.ka...@linaro.org wrote: Updated supported SoC name for pwm-samsung. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- .../devicetree/bindings/pwm/pwm-samsung.txt|2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt index d61fccd..5538de9 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt @@ -15,7 +15,7 @@ Required properties: samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, Exynos4210 rev0 SoCs samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, - Exynos4x12 and Exynos5250 SoCs + Exynos4x12, Exynos5250 and Exynos5420 SoCs - reg: base address and size of register area - interrupts: list of timer interrupts (one interrupt per timer, starting at timer 0) -- 1.7.9.5 Can you please pick this one too? -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
Hi,
On 01.11.2013 20:58, Tomasz Figa wrote:
Hi,
On Monday 14 of October 2013 19:08:23 Vyacheslav Tyrtov wrote:
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251
+ include/dt-bindings/clock/exynos5410.h
| 175 ++ 4 files changed, 464 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5410-clock.txt create
mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
The driver looks pretty good now, thanks for addressing my comments to
previous version. There are still few issues remaining, though. Please see
my comments inline.
[snip]
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644
index 000..c5eba08
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
[snip]
+static struct of_device_id ext_clk_match[] __initdata = {
+ { .compatible = samsung,clock-oscclk, .data = (void *)0, },
+ { },
+};
I don't see anything in binding documentation mentioning this compatible
value. Anyway, since there is already a generic binding for fixed rate
clocks, this shouldn't be needed at all.
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic(%s: failed to map registers\n, __func__);
+
+ samsung_clk_init(np, reg_base, CLK_NR_CLKS,
+ exynos5410_clk_regs,
ARRAY_SIZE(exynos5410_clk_regs),
+ NULL, 0);
+ samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
+ ARRAY_SIZE(exynos5410_frt_ext_clks),
+ ext_clk_match);
This call could be dropped after moving to generic fixed rate clock
bindings.
Best regards,
Tomasz
Already done. Will be added in patch v3.
Thank you for comments, Tomasz.
Best regards,
Tarek Dakhran
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Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday 05 of November 2013 12:50:18 Vivek Gautam wrote: Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). I meant there is a single PHY used with the USB 3.0 controller (dwc3) and it is different from the PHY used with the USB 2.0 controller (s3c-hsotg aka dwc2). The USB 3.0 PHY and controller blocks also support USB 2.0 operation, though. So we were both right. ;) Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] Sent: Tuesday, November 05, 2013 8:20 AM To: Kishon Vijay Abraham I Cc: Kamil Debski; Vivek Gautam; Linux USB Mailing List; linux-samsung- s...@vger.kernel.org; linux-ker...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-...@vger.kernel.org; Greg KH; Kukjin Kim; Sylwester Nawrocki; Tomasz Figa; Felipe Balbi; Julius Werner; Jingoo Han Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? [snip] Best wishes, Kamil Debski -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] ARM: dts: Fix sysreg node name in exynos4.dtsi
On 05/11/13 07:18, Sachin Kamat wrote: Fix the name as per DT node naming convention. - rename the node to syscon which is a more generic name. - append the register value to the node name. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Reviewed-by: Tomasz Figa t.f...@samsung.com Thanks Sachin. Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6] iio: exynos_adc: use wait_for_completion_timeout instead of interruptible
1. The irq routine is so simple (just one register read) shouldn't be long
Hence, reduce the timeout to 100milli secs,
2. With 100ms of wait time, interruptible is very much unnecessary.
Hence, use wait_for_completion_timeout instead of
wait_for_completion_interruptible_timeout
3. Reset software if a timeout happens.
4. Add reinit_completion() before the wait_for_completion_timeout in raw_read()
Note: submitted for review at https://patchwork.kernel.org/patch/2279591/
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Lars-Peter Clausen l...@metafoo.de
Reviewed-on: https://chromium-review.googlesource.com/172724
Reviewed-by: Doug Anderson diand...@chromium.org
---
Changes since v1:
As per discussion at
http://marc.info/?l=linux-kernelm=136517637228869w=3
Changes since v2:
None.
Rebased and reposting.
Changes since v3:
1. commit message change and
2. removed an unncessary assignment
Changes since v4:
Moved INIT_COMPLETION call to the starting of the function
Changes since v5:
INIT_COMPLETION was replaced by reinit_completion
(tree-wide: use reinit_completion instead of INIT_COMPLETION).
Use it to avoid the following build error:
undefined identifier 'INIT_COMPLETION'
drivers/iio/adc/exynos_adc.c | 69
1 file changed, 38 insertions(+), 31 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 0f2ca60..a675751 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -81,7 +81,7 @@ enum adc_version {
#define ADC_CON_EN_START (1u 0)
#define ADC_DATX_MASK 0xFFF
-#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(1000))
+#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
struct exynos_adc {
void __iomem*regs;
@@ -111,6 +111,30 @@ static inline unsigned int exynos_adc_get_version(struct
platform_device *pdev)
return (unsigned int)match-data;
}
+static void exynos_adc_hw_init(struct exynos_adc *info)
+{
+ u32 con1, con2;
+
+ if (info-version == ADC_V2) {
+ con1 = ADC_V2_CON1_SOFT_RESET;
+ writel(con1, ADC_V2_CON1(info-regs));
+
+ con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
+ ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
+ writel(con2, ADC_V2_CON2(info-regs));
+
+ /* Enable interrupts */
+ writel(1, ADC_V2_INT_EN(info-regs));
+ } else {
+ /* set default prescaler values and Enable prescaler */
+ con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
+
+ /* Enable 12-bit ADC resolution */
+ con1 |= ADC_V1_CON_RES;
+ writel(con1, ADC_V1_CON(info-regs));
+ }
+}
+
static int exynos_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
@@ -120,11 +144,13 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
struct exynos_adc *info = iio_priv(indio_dev);
unsigned long timeout;
u32 con1, con2;
+ int ret;
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
mutex_lock(indio_dev-mlock);
+ reinit_completion(info-completion);
/* Select the channel to be used and Trigger conversion */
if (info-version == ADC_V2) {
@@ -144,16 +170,21 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
ADC_V1_CON(info-regs));
}
- timeout = wait_for_completion_interruptible_timeout
+ timeout = wait_for_completion_timeout
(info-completion, EXYNOS_ADC_TIMEOUT);
- *val = info-value;
+ if (timeout == 0) {
+ dev_warn(indio_dev-dev, Conversion timed out! Resetting\n);
+ exynos_adc_hw_init(info);
+ ret = -ETIMEDOUT;
+ } else {
+ *val = info-value;
+ *val2 = 0;
+ ret = IIO_VAL_INT;
+ }
mutex_unlock(indio_dev-mlock);
- if (timeout == 0)
- return -ETIMEDOUT;
-
- return IIO_VAL_INT;
+ return ret;
}
static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
@@ -225,30 +256,6 @@ static int exynos_adc_remove_devices(struct device *dev,
void *c)
return 0;
}
-static void exynos_adc_hw_init(struct exynos_adc *info)
-{
- u32 con1, con2;
-
- if (info-version == ADC_V2) {
- con1 = ADC_V2_CON1_SOFT_RESET;
- writel(con1, ADC_V2_CON1(info-regs));
-
- con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
- ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
- writel(con2, ADC_V2_CON2(info-regs));
-
- /* Enable interrupts */
- writel(1, ADC_V2_INT_EN(info-regs));
- } else {
- /* set default prescaler values and
Re: [PATCH v3 2/2] ARM: dts: Update Samsung sysreg binding document
On 05/11/13 07:18, Sachin Kamat wrote:
Added a binding example for reference and updated the
node name. While at it also removed the name description
as it is not necessary.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
I'm not sure we need an example in each and every binding,
but anyway
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
Changes since v2:
* Removed node name description as suggested by Tomasz Figa.
---
.../devicetree/bindings/arm/samsung/sysreg.txt |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
index 5039c0a12f55..0ab3251a6ec2 100644
--- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
@@ -1,7 +1,12 @@
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
Properties:
- - name : should be 'sysreg';
- compatible : should contain samsung,chip name-sysreg, syscon;
For Exynos4 SoC series it should be samsung,exynos4-sysreg, syscon;
- reg : offset and length of the register set.
+
+Example:
+ syscon@1001 {
+ compatible = samsung,exynos4-sysreg, syscon;
+ reg = 0x1001 0x400;
+ };
--
Thanks,
Sylwester
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Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 1/2] [media] exynos5-is: Adds DT binding documentation
From: Shaik Ameer Basha shaik.am...@samsung.com
The patch adds the DT binding doc for exynos5 SoC camera
subsystem.
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../bindings/media/exynos5250-camera.txt | 126
1 file changed, 126 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/exynos5250-camera.txt
diff --git a/Documentation/devicetree/bindings/media/exynos5250-camera.txt
b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
new file mode 100644
index 000..09420ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
@@ -0,0 +1,126 @@
+Samsung EXYNOS5 SoC Camera Subsystem
+
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-device nodes are referenced using phandles in the common 'camera' node
+which also includes common properties of the whole subsystem not really
+specific to any single sub-device, like common camera port pins or the common
+camera bus clocks.
+
+Common 'camera' node
+
+
+Required properties:
+
+- compatible : must be samsung,exynos5250-fimc
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property
+- clock-names : must contain sclk_bayer entry
+- samsung,csis : list of phandles to the mipi-csis device nodes
+- samsung,fimc-lite: list of phandles to the fimc-lite device nodes
+- samsung,fimc-is : phandle to the fimc-is device node
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named default.
+
+'parallel-ports' node
+-
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A, camera B and RGB bay inputs.
+'reg' property in the port nodes specifies the input type:
+ 1 - parallel camport A
+ 2 - parallel camport B
+ 5 - RGB camera bay
+
+3, 4 are for MIPI CSI-2 bus and are already described in samsung-mipi-csis.txt
+
+Image sensor nodes
+--
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ aliases {
+ fimc-lite0 = fimc_lite_0
+ };
+
+ /* Parallel bus IF sensor */
+ i2c_0: i2c@1386 {
+ s5k6aa: sensor@3c {
+ compatible = samsung,s5k6aafx;
+ reg = 0x3c;
+ vddio-supply = ...;
+
+ clock-frequency = 2400;
+ clocks = ...;
+ clock-names = mclk;
+
+ port {
+ s5k6aa_ep: endpoint {
+ remote-endpoint = fimc0_ep;
+ bus-width = 8;
+ hsync-active = 0;
+ vsync-active = 1;
+ pclk-sample = 1;
+ };
+ };
+ };
+ };
+
+ /* MIPI CSI-2 bus IF sensor */
+ s5c73m3: sensor@1a {
+ compatible = samsung,s5c73m3;
+ reg = 0x1a;
+ vddio-supply = ...;
+
+ clock-frequency = 2400;
+ clocks = ...;
+ clock-names = mclk;
+
+ port {
+ s5c73m3_1: endpoint {
+ data-lanes = 1 2 3 4;
+ remote-endpoint = csis0_ep;
+ };
+ };
+ };
+
+ camera {
+ compatible = samsung,exynos5250-fimc;
+ #address-cells = 1;
+ #size-cells = 1;
+ status = okay;
+
+ pinctrl-names = default;
+ pinctrl-0 = cam_port_a_clk_active;
+
+ samsung,csis = csis_0, csis_1;
+ samsung,fimc-lite = fimc_lite_0, fimc_lite_1,
fimc_lite_2;
+ samsung,fimc-is = fimc_is;
+
+ /* parallel camera ports */
+ parallel-ports {
+ /* camera A input */
+ port@1 {
+ reg = 1;
+ camport_a_ep: endpoint {
+ remote-endpoint = s5k6aa_ep;
+ bus-width = 8;
+ hsync-active = 0;
+ vsync-active = 1;
+
[PATCH v11 2/2] [media] exynos5-is: Add media device driver for exynos5 SoCs camera subsystem
From: Shaik Ameer Basha shaik.am...@samsung.com
This patch adds a top level media device driver for the Exynos5 SoC series
camera subsystem. The driver currently supports processing pipelines
involving following IP blocks:
* MIPI-CSIS
MIPI CSI-2 bus front-end to the FIMC-LITE, image sensors with MIPI CSI-2
bus should be linked with FIMC-LITE through this sub-device.
* FIMC-LITE
Supports capture interface from device (Sensor, MIPI-CSIS) to memory.
Supports interconnection (through internal data FIFO links) between
devices like MIPI-CSIS and FIMC-IS.
* FIMC-IS
Camera ISP with multiple image processing and peripheral devices like
I2C or SPI bus controllers.
The G-Scaler IP is not yet supported.
The media device creates two kinds of pipelines for connecting the above
mentioned IP blocks.
The pipeline0 contains Sensor, MIPI-CSIS and FIMC-LITE devices and allows
to capture image data from external sensor to memory.
Pipeline1 uses FIMC-IS components for image processing operations on the
captured raw image data and provides scaled YUV image data at its output.
Pipeline0
++ +---+ +---+ ++
| Sensor | -- | MIPI-CSIS | -- | FIMC-LITE | -- | Memory |
++ +---+ +---+ ++
Pipeline1
++ +-+ +---+ +---+
| Memory | -- | ISP | -- |SCC| -- |SCP|
++ +-+ +---+ +---+
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
[s.nawro...@samsung.com: improved the commit description]
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/exynos5-mdev.c | 1211 ++
drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 +++
2 files changed, 1337 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
diff --git a/drivers/media/platform/exynos5-is/exynos5-mdev.c
b/drivers/media/platform/exynos5-is/exynos5-mdev.c
new file mode 100644
index 000..1621d94
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/exynos5-mdev.c
@@ -0,0 +1,1211 @@
+/*
+ * EXYNOS5 SoC series camera host interface media device driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Shaik Ameer Basha shaik.am...@samsung.com
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This driver is based on exynos4-is media device driver written by
+ * Sylwester Nawrocki s.nawro...@samsung.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include linux/bug.h
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/of_device.h
+#include linux/of_i2c.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/slab.h
+#include linux/types.h
+#include media/media-device.h
+#include media/s5p_fimc.h
+#include media/v4l2-async.h
+#include media/v4l2-ctrls.h
+#include media/v4l2-of.h
+
+#include exynos5-mdev.h
+#include fimc-is.h
+
+#define BAYER_CLK_NAME sclk_bayer
+
+/**
+ * fimc_pipeline_prepare - update pipeline information with subdevice pointers
+ * @me: media entity terminating the pipeline
+ *
+ * Caller holds the graph mutex.
+ */
+static void fimc_pipeline_prepare(struct fimc_pipeline *p,
+ struct media_entity *me)
+{
+ struct v4l2_subdev *sd;
+ int i;
+
+ for (i = 0; i IDX_MAX; i++)
+ p-subdevs[i] = NULL;
+
+ while (1) {
+ struct media_pad *pad = NULL;
+
+ /* Find remote source pad */
+ for (i = 0; i me-num_pads; i++) {
+ struct media_pad *spad = me-pads[i];
+ if (!(spad-flags MEDIA_PAD_FL_SINK))
+ continue;
+ pad = media_entity_remote_pad(spad);
+ if (pad)
+ break;
+ }
+
+ if (pad == NULL ||
+ media_entity_type(pad-entity) != MEDIA_ENT_T_V4L2_SUBDEV) {
+ break;
+ }
+ sd = media_entity_to_v4l2_subdev(pad-entity);
+
+ switch (sd-grp_id) {
+ case GRP_ID_FIMC_IS_SENSOR:
+ case GRP_ID_SENSOR:
+ p-subdevs[IDX_SENSOR] = sd;
+ break;
+ case GRP_ID_CSIS:
+ p-subdevs[IDX_CSIS] = sd;
+ break;
+
Re: [PATCH v11 02/12] [media] exynos5-fimc-is: Add driver core files
Hi Arun,
Thanks for the patch. A few comments below.
On Tue, Nov 05, 2013 at 11:42:33AM +0530, Arun Kumar K wrote:
This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-core.c | 410
++
drivers/media/platform/exynos5-is/fimc-is-core.h | 132 +++
2 files changed, 542 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..2b116d0
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,410 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/bug.h
+#include linux/ctype.h
+#include linux/device.h
+#include linux/debugfs.h
+#include linux/delay.h
+#include linux/errno.h
+#include linux/err.h
+#include linux/firmware.h
+#include linux/fs.h
+#include linux/gpio.h
+#include linux/interrupt.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include linux/of_irq.h
+#include linux/pinctrl/consumer.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/videodev2.h
+
+#include media/v4l2-device.h
+#include media/v4l2-ioctl.h
+#include media/v4l2-mem2mem.h
+#include media/v4l2-of.h
+#include media/videobuf2-core.h
+#include media/videobuf2-dma-contig.h
Do you really need all these headers?
+#include fimc-is.h
+#include fimc-is-i2c.h
+
+#define CLK_MCU_ISP_DIV0_FREQ(200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ(100 * 100)
+#define CLK_ISP_DIV0_FREQ(134 * 100)
+#define CLK_ISP_DIV1_FREQ(68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ (34 * 100)
+
+static const char * const fimc_is_clock_name[] = {
+ [IS_CLK_ISP]= isp,
+ [IS_CLK_MCU_ISP]= mcu_isp,
+ [IS_CLK_ISP_DIV0] = isp_div0,
+ [IS_CLK_ISP_DIV1] = isp_div1,
+ [IS_CLK_ISP_DIVMPWM]= isp_divmpwm,
+ [IS_CLK_MCU_ISP_DIV0] = mcu_isp_div0,
+ [IS_CLK_MCU_ISP_DIV1] = mcu_isp_div1,
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++) {
+ if (IS_ERR(is-clock[i]))
+ continue;
+ clk_unprepare(is-clock[i]);
+ clk_put(is-clock[i]);
+ is-clock[i] = ERR_PTR(-EINVAL);
+ }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+ struct device *dev = is-pdev-dev;
+ int i, ret;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++) {
+ is-clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+ if (IS_ERR(is-clock[i]))
+ goto err;
+ ret = clk_prepare(is-clock[i]);
+ if (ret 0) {
+ clk_put(is-clock[i]);
+ is-clock[i] = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ }
+ return 0;
+err:
+ fimc_is_put_clocks(is);
+ pr_err(Failed to get clock: %s\n, fimc_is_clock_name[i]);
How about dev_err() instead?
+ return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+ int i, ret;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++)
+ is-clock[i] = ERR_PTR(-EINVAL);
+
+ ret = fimc_is_get_clocks(is);
+ if (ret)
+ return ret;
+
+ /* Set rates */
+ ret = clk_set_rate(is-clock[IS_CLK_MCU_ISP_DIV0],
+ CLK_MCU_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_MCU_ISP_DIV1],
+ CLK_MCU_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIVMPWM],
+ CLK_ISP_DIVMPWM_FREQ);
+ return ret;
You can return the return value from clk_set_rate() directly here.
+}
+
+static void
Re: [PATCH v11 02/12] [media] exynos5-fimc-is: Add driver core files
Hi Sakari,
Thank you for the review.
Will make the required changes.
Thanks
Arun
On Tue, Nov 5, 2013 at 4:51 PM, Sakari Ailus sakari.ai...@iki.fi wrote:
Hi Arun,
Thanks for the patch. A few comments below.
On Tue, Nov 05, 2013 at 11:42:33AM +0530, Arun Kumar K wrote:
This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-core.c | 410
++
drivers/media/platform/exynos5-is/fimc-is-core.h | 132 +++
2 files changed, 542 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..2b116d0
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,410 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/bug.h
+#include linux/ctype.h
+#include linux/device.h
+#include linux/debugfs.h
+#include linux/delay.h
+#include linux/errno.h
+#include linux/err.h
+#include linux/firmware.h
+#include linux/fs.h
+#include linux/gpio.h
+#include linux/interrupt.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include linux/of_irq.h
+#include linux/pinctrl/consumer.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/videodev2.h
+
+#include media/v4l2-device.h
+#include media/v4l2-ioctl.h
+#include media/v4l2-mem2mem.h
+#include media/v4l2-of.h
+#include media/videobuf2-core.h
+#include media/videobuf2-dma-contig.h
Do you really need all these headers?
+#include fimc-is.h
+#include fimc-is-i2c.h
+
+#define CLK_MCU_ISP_DIV0_FREQ(200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ(100 * 100)
+#define CLK_ISP_DIV0_FREQ(134 * 100)
+#define CLK_ISP_DIV1_FREQ(68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ (34 * 100)
+
+static const char * const fimc_is_clock_name[] = {
+ [IS_CLK_ISP]= isp,
+ [IS_CLK_MCU_ISP]= mcu_isp,
+ [IS_CLK_ISP_DIV0] = isp_div0,
+ [IS_CLK_ISP_DIV1] = isp_div1,
+ [IS_CLK_ISP_DIVMPWM]= isp_divmpwm,
+ [IS_CLK_MCU_ISP_DIV0] = mcu_isp_div0,
+ [IS_CLK_MCU_ISP_DIV1] = mcu_isp_div1,
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++) {
+ if (IS_ERR(is-clock[i]))
+ continue;
+ clk_unprepare(is-clock[i]);
+ clk_put(is-clock[i]);
+ is-clock[i] = ERR_PTR(-EINVAL);
+ }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+ struct device *dev = is-pdev-dev;
+ int i, ret;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++) {
+ is-clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+ if (IS_ERR(is-clock[i]))
+ goto err;
+ ret = clk_prepare(is-clock[i]);
+ if (ret 0) {
+ clk_put(is-clock[i]);
+ is-clock[i] = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ }
+ return 0;
+err:
+ fimc_is_put_clocks(is);
+ pr_err(Failed to get clock: %s\n, fimc_is_clock_name[i]);
How about dev_err() instead?
+ return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+ int i, ret;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++)
+ is-clock[i] = ERR_PTR(-EINVAL);
+
+ ret = fimc_is_get_clocks(is);
+ if (ret)
+ return ret;
+
+ /* Set rates */
+ ret = clk_set_rate(is-clock[IS_CLK_MCU_ISP_DIV0],
+ CLK_MCU_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_MCU_ISP_DIV1],
+ CLK_MCU_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret =
[PATCH 1/1] ARM: dts: Add hs-i2c nodes to exynos5420
Added high speed I2C nodes to Exynos5420 DT file.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5420.dtsi | 98 +
1 file changed, 98 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9ce5f82..469769a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -34,6 +34,13 @@
i2c1 = i2c_1;
i2c2 = i2c_2;
i2c3 = i2c_3;
+ i2c4 = hsi2c_4;
+ i2c5 = hsi2c_5;
+ i2c6 = hsi2c_6;
+ i2c7 = hsi2c_7;
+ i2c8 = hsi2c_8;
+ i2c9 = hsi2c_9;
+ i2c10 = hsi2c_10;
gsc0 = gsc_0;
gsc1 = gsc_1;
};
@@ -339,6 +346,97 @@
status = disabled;
};
+ hsi2c_4: hsi2c@12CA {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12CA 0x1000;
+ interrupts = 0 60 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c4_hs_bus;
+ clocks = clock 265;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_5: hsi2c@12CB {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12CB 0x1000;
+ interrupts = 0 61 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c5_hs_bus;
+ clocks = clock 266;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_6: hsi2c@12CC {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12CC 0x1000;
+ interrupts = 0 62 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c6_hs_bus;
+ clocks = clock 267;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_7: hsi2c@12CD {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12CD 0x1000;
+ interrupts = 0 63 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c7_hs_bus;
+ clocks = clock 268;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_8: hsi2c@12E0 {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12E0 0x1000;
+ interrupts = 0 87 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c8_hs_bus;
+ clocks = clock 281;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_9: hsi2c@12E1 {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12E1 0x1000;
+ interrupts = 0 88 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c9_hs_bus;
+ clocks = clock 282;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_10: hsi2c@12E2 {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12E2 0x1000;
+ interrupts = 0 203 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = i2c10_hs_bus;
+ clocks = clock 283;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
hdmi@1453 {
compatible = samsung,exynos4212-hdmi;
reg = 0x1453 0x7;
--
1.7.9.5
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Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday, November 05, 2013 8:13 PM, Jingoo Han wrote: On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. In addition to this, Vivek's comment is also right. :-) A few minutes ago, I asked one of my USB S/W engineers. USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v12 05/12] [media] exynos5-fimc-is: Add isp subdev
fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-isp.c | 534 +++
drivers/media/platform/exynos5-is/fimc-is-isp.h | 90
2 files changed, 624 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..7bd603f
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,534 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include media/v4l2-ioctl.h
+#include media/videobuf2-dma-contig.h
+
+#include fimc-is.h
+
+#define ISP_DRV_NAME fimc-is-isp
+
+static const struct fimc_is_fmt formats[] = {
+ {
+ .name = Bayer GR-BG 8bits,
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .depth = { 8 },
+ .num_planes = 1,
+ },
+ {
+ .name = Bayer GR-BG 10bits,
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .depth = { 16 },
+ .num_planes = 1,
+ },
+ {
+ .name = Bayer GR-BG 12bits,
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .depth = { 16 },
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i NUM_FORMATS; i++)
+ if (formats[i].fourcc == f-fmt.pix_mp.pixelformat)
+ return formats[i];
+ return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ set_bit(STATE_RUNNING, isp-output_state);
+ return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ /* Release unused buffers */
+ while (!list_empty(isp-wait_queue)) {
+ buf = fimc_is_isp_wait_queue_get(isp);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(isp-run_queue)) {
+ buf = fimc_is_isp_run_queue_get(isp);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+
+ clear_bit(STATE_RUNNING, isp-output_state);
+ return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ const struct fimc_is_fmt *fmt = isp-fmt;
+ unsigned int wh, i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt-num_planes;
+ wh = isp-width * isp-height;
+
+ for (i = 0; i *num_planes; i++) {
+ allocators[i] = isp-alloc_ctx;
+ sizes[i] = (wh * fmt-depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+ buf-paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+ return 0;
+}
+
+static int isp_video_output_buffer_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb-vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ unsigned long size;
+
+ size = (isp-width * isp-height * isp-fmt-depth[0]) / 8;
+ if (vb2_plane_size(vb, 0) size) {
+ v4l2_err(isp-subdev, User buffer too small (%ld %ld)\n,
+vb2_plane_size(vb, 0), size);
+ return -EINVAL;
+ }
+ vb2_set_plane_payload(vb, 0, size);
+
+ return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb-vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+
[PATCH v12 01/12] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation
The patch adds the DT binding documentation for Samsung
Exynos5 SoC series imaging subsystem (FIMC-IS).
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Mark Rutland mark.rutl...@arm.com
---
.../devicetree/bindings/media/exynos5-fimc-is.txt | 113
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
new file mode 100644
index 000..658d4a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
@@ -0,0 +1,113 @@
+Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
+--
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but has a much improved version of FIMC-IS which can
+handle sensor controls and camera post-processing operations. The
+Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
+post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
+dedicated scalers (SCC and SCP).
+
+fimc-is node
+
+
+Required properties:
+
+- compatible: should contain samsung,exynos5250-fimc-is
+- reg : physical base address and size of the memory mapped
+ registers
+- interrupts: interrupt-specifier for the fimc-is interrupt
+- clocks: list of clock specifiers, corresponding to entries in
+ clock-names property
+- clock-names : must contain isp, mcu_isp, isp_div0, isp_div1,
+ isp_divmpwm, mcu_isp_div0, mcu_isp_div1 entries,
+ matching entries in the clocks property
+- samsung,pmu : phandle to the Power Management Unit (PMU) node
+
+i2c-isp (ISP I2C bus controller) nodes
+--
+The i2c-isp nodes should be children of the fimc-is node.
+
+Required properties:
+
+- compatible : must contain samsung,exynos4212-i2c-isp for Exynos4212,
+ Exynos4412 and Exynos5250 SoCs
+- reg : physical base address and length of the registers set
+- clocks : should contain gate clock specifier for this controller
+- clock-names : should contain i2c_isp for the gate clock
+- pinctrl-0: phandle of the pinctrl node for the i2c isp
+- pinctrl-names : must contain default
+
+ranges, #address-cells, and #size-cells should be present as appropriate.
+
+Device tree nodes of the image sensors controlled directly by the FIMC-IS
+firmware must be child nodes of their corresponding ISP I2C bus controller
node.
+The data link of these image sensors must be specified using the common video
+interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ fimc_is: fimc-is@1300 {
+ compatible = samsung,exynos5250-fimc-is;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ reg = 0x1300 0x20;
+ interrupt-parent = combiner;
+ interrupts = 19 1;
+ clocks = clock 346, clock 347, clock 512,
+ clock 513, clock 514, clock 515,
+ clock 516;
+ clock-names = isp, mcu_isp, isp_div0, isp_div1,
+ isp_divmpwm, mcu_isp_div0,
+ mcu_isp_div1;
+ samsung,pmu = pmu;
+
+ i2c0_isp: i2c-isp@1313 {
+ compatible = samsung,exynos4212-i2c-isp;
+ reg = 0x1313 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock 352;
+ clock-names = i2c_isp;
+ pinctrl-0 = cam_i2c0_bus;
+ pinctrl-names = default;
+ };
+
+ i2c1_isp: i2c-isp@1314 {
+ compatible = samsung,exynos4212-i2c-isp;
+ reg = 0x1314 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock 353;
+ clock-names = i2c_isp;
+ pinctrl-0 = cam_i2c1_bus;
+ pinctrl-names = default;
+ };
+ };
+
+In the board specific file the sensor nodes can be provided. For the sensor
+node documentation for s5k4e5, please refer to samsung-s5k4e5.txt
+
+ fimc-is@1300 {
+ status = okay;
+
+ i2c-isp@1313 {
+ s5k4e5@20 {
+ compatible = samsung,s5k4e5;
+ reg = 0x20;
+ reset-gpios = gpx1 2 1;
+
[PATCH v12 00/12] Exynos5 IS driver
The patch series adds support for exynos5 fimc-is driver and a new sensor s5k4e5. The media driver part is omitted form this series as it is already applied. Changes from v11 - Addressed review comments from Sakari Ailus http://www.mail-archive.com/linux-media@vger.kernel.org/msg68134.html Changes from v10 --- - Addressed DT binding review comments from Mark Rutland https://www.mail-archive.com/linux-media@vger.kernel.org/msg67806.html https://www.mail-archive.com/linux-media@vger.kernel.org/msg67808.html Changes from v9 --- - Addressed review comments from Hans and Sylwester http://www.mail-archive.com/linux-media@vger.kernel.org/msg67102.html http://www.mail-archive.com/linux-media@vger.kernel.org/msg67624.html http://www.mail-archive.com/linux-media@vger.kernel.org/msg67623.html - Skipped already applied media driver Changes from v8 --- - Moved i2c-isp device nodes into the fimc-is node as suggested by Sylwester - Addressed comments given by Sylwester and Philipp Zabel Changes from v7 --- - Addressed few DT related review comments from Sylwester http://www.mail-archive.com/linux-media@vger.kernel.org/msg66403.html - Few fixes added after some regression testing Changes from v6 --- - Addressed DT binding doc review comments from Sylwester http://www.mail-archive.com/linux-media@vger.kernel.org/msg65771.html http://www.mail-archive.com/linux-media@vger.kernel.org/msg65772.html Changes from v5 --- - Addressed review comments from Sylwester http://www.mail-archive.com/linux-media@vger.kernel.org/msg65578.html http://www.mail-archive.com/linux-media@vger.kernel.org/msg65605.html Changes from v4 --- - Addressed all review comments from Sylwester - Added separate PMU node as suggested by Stephen Warren - Added phandle based discovery of subdevs instead of node name Changes from v3 --- - Dropped the RFC tag - Addressed all review comments from Sylwester and Sachin - Removed clock provider for media dev - Added s5k4e5 sensor devicetree binding doc Changes from v2 --- - Added exynos5 media device driver from Shaik to this series - Added ISP pipeline support in media device driver - Based on Sylwester's latest exynos4-is development - Asynchronos registration of sensor subdevs - Made independent IS-sensor support - Add s5k4e5 sensor driver - Addressed review comments from Sylwester, Hans, Andrzej, Sachin Changes from v1 --- - Addressed all review comments from Sylwester - Made sensor subdevs as independent i2c devices - Lots of cleanup - Debugfs support added - Removed PMU global register access Arun Kumar K (12): [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation [media] exynos5-fimc-is: Add driver core files [media] exynos5-fimc-is: Add common driver header files [media] exynos5-fimc-is: Add register definition and context header [media] exynos5-fimc-is: Add isp subdev [media] exynos5-fimc-is: Add scaler subdev [media] exynos5-fimc-is: Add sensor interface [media] exynos5-fimc-is: Add the hardware pipeline control [media] exynos5-fimc-is: Add the hardware interface module [media] exynos5-is: Add Kconfig and Makefile V4L: Add DT binding doc for s5k4e5 image sensor V4L: Add s5k4e5 sensor driver .../devicetree/bindings/media/exynos5-fimc-is.txt | 113 ++ .../devicetree/bindings/media/samsung-s5k4e5.txt | 45 + drivers/media/i2c/Kconfig |8 + drivers/media/i2c/Makefile |1 + drivers/media/i2c/s5k4e5.c | 344 drivers/media/platform/Kconfig |1 + drivers/media/platform/Makefile|1 + drivers/media/platform/exynos5-is/Kconfig | 20 + drivers/media/platform/exynos5-is/Makefile |7 + drivers/media/platform/exynos5-is/fimc-is-cmd.h| 187 +++ drivers/media/platform/exynos5-is/fimc-is-core.c | 387 + drivers/media/platform/exynos5-is/fimc-is-core.h | 117 ++ drivers/media/platform/exynos5-is/fimc-is-err.h| 257 +++ .../media/platform/exynos5-is/fimc-is-interface.c | 810 ++ .../media/platform/exynos5-is/fimc-is-interface.h | 124 ++ drivers/media/platform/exynos5-is/fimc-is-isp.c| 534 ++ drivers/media/platform/exynos5-is/fimc-is-isp.h| 90 ++ .../media/platform/exynos5-is/fimc-is-metadata.h | 767 + drivers/media/platform/exynos5-is/fimc-is-param.h | 1159 + .../media/platform/exynos5-is/fimc-is-pipeline.c | 1699 .../media/platform/exynos5-is/fimc-is-pipeline.h | 129 ++ drivers/media/platform/exynos5-is/fimc-is-regs.h | 105 ++ drivers/media/platform/exynos5-is/fimc-is-scaler.c | 476 ++ drivers/media/platform/exynos5-is/fimc-is-scaler.h | 106 ++ drivers/media/platform/exynos5-is/fimc-is-sensor.c | 45 +
[PATCH v12 06/12] [media] exynos5-fimc-is: Add scaler subdev
FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-scaler.c | 476
drivers/media/platform/exynos5-is/fimc-is-scaler.h | 106 +
2 files changed, 582 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..029eb8b
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,476 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include media/v4l2-ioctl.h
+#include media/videobuf2-dma-contig.h
+
+#include fimc-is.h
+
+#define IS_SCALER_DRV_NAME fimc-is-scaler
+
+static const struct fimc_is_fmt formats[] = {
+ {
+ .name = YUV 4:2:0 3p MultiPlanar,
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .depth = {8, 2, 2},
+ .num_planes = 3,
+ },
+ {
+ .name = YUV 4:2:0 2p MultiPlanar,
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .depth = {8, 4},
+ .num_planes = 2,
+ },
+ {
+ .name = YUV 4:2:2 1p MultiPlanar,
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .depth = {16},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f-fmt.pix_mp.pixelformat)
+ return formats[i];
+ }
+ return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ ret = fimc_is_pipeline_scaler_start(ctx-pipeline,
+ ctx-scaler_id,
+ vq-num_buffers,
+ ctx-fmt-num_planes);
+ if (ret) {
+ v4l2_err(ctx-subdev, Scaler start failed.\n);
+ return -EINVAL;
+ }
+
+ set_bit(STATE_RUNNING, ctx-capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+ int ret;
+
+ ret = fimc_is_pipeline_scaler_stop(ctx-pipeline, ctx-scaler_id);
+ if (ret)
+ v4l2_info(ctx-subdev, Scaler already stopped.\n);
+
+ /* Release un-used buffers */
+ while (!list_empty(ctx-wait_queue)) {
+ buf = fimc_is_scaler_wait_queue_get(ctx);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(ctx-run_queue)) {
+ buf = fimc_is_scaler_run_queue_get(ctx);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+
+ clear_bit(STATE_RUNNING, ctx-capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ const struct fimc_is_fmt *fmt = ctx-fmt;
+ unsigned int wh;
+ int i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt-num_planes;
+ wh = ctx-width * ctx-height;
+
+ for (i = 0; i *num_planes; i++) {
+ allocators[i] = ctx-alloc_ctx;
+ sizes[i] = (wh * fmt-depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb-vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+ const struct fimc_is_fmt *fmt;
+ int i;
+
+ fmt = ctx-fmt;
+ for (i = 0; i fmt-num_planes; i++)
+ buf-paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+
[PATCH v12 08/12] [media] exynos5-fimc-is: Add the hardware pipeline control
This patch adds the crucial hardware pipeline control for the
fimc-is driver. All the subdev nodes will call this pipeline
interfaces to reach the hardware. Responsibilities of this module
involves configuring and maintaining the hardware pipeline involving
multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../media/platform/exynos5-is/fimc-is-pipeline.c | 1699
.../media/platform/exynos5-is/fimc-is-pipeline.h | 129 ++
2 files changed, 1828 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
new file mode 100644
index 000..25eaf24
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
@@ -0,0 +1,1699 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ * Kil-yeon Lim kilyeon...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include fimc-is.h
+#include fimc-is-pipeline.h
+#include fimc-is-metadata.h
+#include fimc-is-regs.h
+#include fimc-is-cmd.h
+#include media/videobuf2-dma-contig.h
+#include linux/delay.h
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH1280
+#define DEFAULT_PREVIEW_STILL_HEIGHT 720
+#define DEFAULT_CAPTURE_VIDEO_WIDTH1920
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT 1080
+#define DEFAULT_CAPTURE_STILL_WIDTH2560
+#define DEFAULT_CAPTURE_STILL_HEIGHT 1920
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH 2560
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT 1440
+#define DEFAULT_PREVIEW_VIDEO_WIDTH640
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT 480
+
+/* Init params for pipeline devices */
+static const struct sensor_param init_sensor_param = {
+ .frame_rate = {
+ .frame_rate = 30,
+ },
+};
+
+static const struct isp_param init_isp_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_DISABLE,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_BAYER,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .frametime_max = 3,
+ },
+ .dma1_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ },
+ .dma2_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ },
+ .aa = {
+ .cmd = ISP_AA_COMMAND_START,
+ },
+ .flash = {
+ .cmd = ISP_FLASH_COMMAND_DISABLE,
+ .redeye = ISP_FLASH_REDEYE_DISABLE,
+ },
+ .awb = {
+ .cmd = ISP_AWB_COMMAND_AUTO,
+ },
+ .effect = {
+ .cmd = ISP_IMAGE_EFFECT_DISABLE,
+ },
+ .iso = {
+ .cmd = ISP_ISO_COMMAND_AUTO,
+ },
+ .adjust = {
+ .cmd = ISP_ADJUST_COMMAND_AUTO,
+ },
+ .metering = {
+ .cmd = ISP_METERING_COMMAND_CENTER,
+ .win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ },
+ .afc = {
+ .cmd = ISP_AFC_COMMAND_AUTO,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ },
+ .dma1_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_INPUT_FORMAT_YUV444,
+ .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+ .plane = 1,
+ .order = DMA_INPUT_ORDER_YCBCR,
+ },
+ .dma2_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_OUTPUT_FORMAT_BAYER,
+ .bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
+ .plane = 1,
+ .order =
[PATCH v12 04/12] [media] exynos5-fimc-is: Add register definition and context header
This patch adds the register definition file for the fimc-is driver and also the header file containing the main context for the driver. Signed-off-by: Arun Kumar K arun...@samsung.com Signed-off-by: Kilyeon Im kilyeon...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com --- drivers/media/platform/exynos5-is/fimc-is-regs.h | 105 ++ drivers/media/platform/exynos5-is/fimc-is.h | 160 ++ 2 files changed, 265 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h new file mode 100644 index 000..06aa466 --- /dev/null +++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h @@ -0,0 +1,105 @@ +/* + * Samsung Exynos5 SoC series FIMC-IS driver + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd + * Arun Kumar K arun...@samsung.com + * Kil-yeon Lim kilyeon...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef FIMC_IS_REGS_H +#define FIMC_IS_REGS_H + +/* WDT_ISP register */ +#define WDT0x0017 +/* MCUCTL register */ +#define MCUCTL 0x0018 +/* MCU Controller Register */ +#define MCUCTLR(MCUCTL+0x00) +#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) 16) +#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) 12) +#define MCUCTLR_MSWRST (1 0) +/* Boot Base OFfset Address Register */ +#define BBOAR (MCUCTL+0x04) +#define BBOAR_BBOA(x) ((x) 0) + +/* Interrupt Generation Register 0 from Host CPU to VIC */ +#define INTGR0 (MCUCTL+0x08) +#define INTGR0_INTGC(n)(1 ((n) + 16)) +#define INTGR0_INTGD(n)(1 (n)) + +/* Interrupt Clear Register 0 from Host CPU to VIC */ +#define INTCR0 (MCUCTL+0x0c) +#define INTCR0_INTCC(n)(1 ((n) + 16)) +#define INTCR0_INTCD(n)(1 (n)) + +/* Interrupt Mask Register 0 from Host CPU to VIC */ +#define INTMR0 (MCUCTL+0x10) +#define INTMR0_INTMC(n)(1 ((n) + 16)) +#define INTMR0_INTMD(n)(1 (n)) + +/* Interrupt Status Register 0 from Host CPU to VIC */ +#define INTSR0 (MCUCTL+0x14) +#define INTSR0_GET_INTSD(n, x) (((x) (n)) 0x1) +#define INTSR0_GET_INTSC(n, x) (((x) ((n) + 16)) 0x1) + +/* Interrupt Mask Status Register 0 from Host CPU to VIC */ +#define INTMSR0(MCUCTL+0x18) +#define INTMSR0_GET_INTMSD(n, x) (((x) (n)) 0x1) +#define INTMSR0_GET_INTMSC(n, x) (((x) ((n) + 16)) 0x1) + +/* Interrupt Generation Register 1 from ISP CPU to Host IC */ +#define INTGR1 (MCUCTL+0x1c) +#define INTGR1_INTGC(n)(1 (n)) + +/* Interrupt Clear Register 1 from ISP CPU to Host IC */ +#define INTCR1 (MCUCTL+0x20) +#define INTCR1_INTCC(n)(1 (n)) + +/* Interrupt Mask Register 1 from ISP CPU to Host IC */ +#define INTMR1 (MCUCTL+0x24) +#define INTMR1_INTMC(n)(1 (n)) + +/* Interrupt Status Register 1 from ISP CPU to Host IC */ +#define INTSR1 (MCUCTL+0x28) +/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */ +#define INTMSR1(MCUCTL+0x2c) +/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */ +#define INTCR2 (MCUCTL+0x30) +#define INTCR2_INTCC(n)(1 (n)) + +/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */ +#define INTMR2 (MCUCTL+0x34) +#define INTMR2_INTMCIS(n) (1 (n)) + +/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */ +#define INTSR2 (MCUCTL+0x38) +/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */ +#define INTMSR2(MCUCTL+0x3c) +/* General Purpose Output Control Register (0~17) */ +#define GPOCTLR(MCUCTL+0x40) +#define GPOCTLR_GPOG(n, x) ((x) (n)) + +/* General Purpose Pad Output Enable Register (0~17) */ +#define GPOENCTLR (MCUCTL+0x44) +#define GPOENCTLR_GPOEN0(n, x) ((x) (n)) + +/* General Purpose Input Control Register (0~17) */ +#define GPICTLR(MCUCTL+0x48) + +/* IS Shared Registers between ISP CPU and HOST CPU */ +#define ISSR(n)(MCUCTL + 0x80 + (n)) + +/* PMU for FIMC-IS*/ +#define
[PATCH v12 07/12] [media] exynos5-fimc-is: Add sensor interface
Some sensors to be used with fimc-is are exclusively controlled
by the fimc-is firmware. This minimal sensor driver provides
the required info for the firmware to configure the sensors
sitting on I2C bus.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-sensor.c | 45 ++
drivers/media/platform/exynos5-is/fimc-is-sensor.h | 65
2 files changed, 110 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..475f1c3
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,45 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include fimc-is-sensor.h
+
+static const struct sensor_drv_data s5k6a3_drvdata = {
+ .id = FIMC_IS_SENSOR_ID_S5K6A3,
+ .open_timeout = S5K6A3_OPEN_TIMEOUT,
+ .setfile_name = exynos5_s5k6a3_setfile.bin,
+};
+
+static const struct sensor_drv_data s5k4e5_drvdata = {
+ .id = FIMC_IS_SENSOR_ID_S5K4E5,
+ .open_timeout = S5K4E5_OPEN_TIMEOUT,
+ .setfile_name = exynos5_s5k4e5_setfile.bin,
+};
+
+static const struct of_device_id fimc_is_sensor_of_ids[] = {
+ {
+ .compatible = samsung,s5k6a3,
+ .data = s5k6a3_drvdata,
+ },
+ {
+ .compatible = samsung,s5k4e5,
+ .data = s5k4e5_drvdata,
+ },
+ { }
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+ struct device_node *node)
+{
+ const struct of_device_id *of_id;
+
+ of_id = of_match_node(fimc_is_sensor_of_ids, node);
+ return of_id ? of_id-data : NULL;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h
b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 000..0ba5733
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,65 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include linux/of.h
+#include linux/types.h
+
+#define S5K6A3_OPEN_TIMEOUT2000 /* ms */
+#define S5K6A3_SENSOR_WIDTH1392
+#define S5K6A3_SENSOR_HEIGHT 1392
+
+#define S5K4E5_OPEN_TIMEOUT2000 /* ms */
+#define S5K4E5_SENSOR_WIDTH2560
+#define S5K4E5_SENSOR_HEIGHT 1920
+
+#define SENSOR_WIDTH_PADDING 16
+#define SENSOR_HEIGHT_PADDING 10
+
+enum fimc_is_sensor_id {
+ FIMC_IS_SENSOR_ID_S5K3H2 = 1,
+ FIMC_IS_SENSOR_ID_S5K6A3,
+ FIMC_IS_SENSOR_ID_S5K4E5,
+ FIMC_IS_SENSOR_ID_S5K3H7,
+ FIMC_IS_SENSOR_ID_CUSTOM,
+ FIMC_IS_SENSOR_ID_END
+};
+
+struct sensor_drv_data {
+ enum fimc_is_sensor_id id;
+ /* sensor open timeout in ms */
+ unsigned short open_timeout;
+ char *setfile_name;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor data structure
+ * @drvdata: a pointer to the sensor's parameters data structure
+ * @i2c_bus: ISP I2C bus index (0...1)
+ * @width: sensor active width
+ * @height: sensor active height
+ * @pixel_width: sensor effective pixel width (width + padding)
+ * @pixel_height: sensor effective pixel height (height + padding)
+ */
+struct fimc_is_sensor {
+ const struct sensor_drv_data *drvdata;
+ unsigned int i2c_bus;
+ unsigned int width;
+ unsigned int height;
+ unsigned int pixel_width;
+ unsigned int pixel_height;
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+ struct device_node *node);
+
+#endif /* FIMC_IS_SENSOR_H_ */
--
1.7.9.5
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[PATCH v12 09/12] [media] exynos5-fimc-is: Add the hardware interface module
The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../media/platform/exynos5-is/fimc-is-interface.c | 810
.../media/platform/exynos5-is/fimc-is-interface.h | 124 +++
2 files changed, 934 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..c5da6ff
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,810 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim kilyeon...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/debugfs.h
+#include linux/seq_file.h
+#include fimc-is.h
+#include fimc-is-cmd.h
+#include fimc-is-regs.h
+
+#define init_request_barrier(itf) mutex_init(itf-request_barrier)
+#define enter_request_barrier(itf) mutex_lock(itf-request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(itf-request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg, unsigned int index)
+{
+ struct is_common_reg __iomem *com_regs = itf-com_regs;
+
+ memset(msg, 0, sizeof(*msg));
+
+ switch (index) {
+ case INTR_GENERAL:
+ msg-command = com_regs-ihcmd;
+ msg-instance = com_regs-ihc_sensorid;
+ memcpy(msg-param, com_regs-ihc_param,
+ 4 * sizeof(msg-param[0]));
+ break;
+ case INTR_SCC_FDONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-scc_sensor_id;
+ memcpy(msg-param, com_regs-scc_param,
+ 3 * sizeof(msg-param[0]));
+ break;
+ case INTR_SCP_FDONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-scp_sensor_id;
+ memcpy(msg-param, com_regs-scp_param,
+ 3 * sizeof(msg-param[0]));
+ break;
+ case INTR_META_DONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-meta_sensor_id;
+ msg-param[0] = com_regs-meta_param1;
+ break;
+ case INTR_SHOT_DONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-shot_sensor_id;
+ memcpy(msg-param, com_regs-shot_param,
+ 2 * sizeof(msg-param[0]));
+ break;
+ default:
+ dev_err(itf-dev, %s Unknown command\n, __func__);
+ break;
+ }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+ unsigned int status;
+ struct is_common_reg __iomem *com_regs = itf-com_regs;
+
+ status = readl(itf-regs + INTMSR1) | com_regs-ihcmd_iflag |
+ com_regs-scc_iflag |
+ com_regs-scp_iflag |
+ com_regs-meta_iflag |
+ com_regs-shot_iflag;
+
+ return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(itf-slock_state, flags);
+ __set_bit(state, itf-state);
+ spin_unlock_irqrestore(itf-slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(itf-slock_state, flags);
+ __clear_bit(state, itf-state);
+ spin_unlock_irqrestore(itf-slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(itf-slock_state, flags);
+ ret = test_bit(state, itf-state);
+ spin_unlock_irqrestore(itf-slock_state, flags);
+ return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+ itf_set_state(itf, IS_IF_STATE_INIT);
+ wake_up(itf-irq_queue);
+}
+
+void itf_busy_wakeup(struct fimc_is_interface *itf)
+{
+ itf_clr_state(itf, IS_IF_STATE_BUSY);
+ wake_up(itf-irq_queue);
+}
+
+static int itf_wait_hw_ready(struct fimc_is_interface *itf)
+{
+ int t;
+ for (t = TRY_RECV_AWARE_COUNT; t = 0; t--) {
+ unsigned int cfg = readl(itf-regs + INTMSR0);
+
[PATCH v12 10/12] [media] exynos5-is: Add Kconfig and Makefile
Adds Kconfig and Makefile for exynos5-is driver files. Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com Signed-off-by: Arun Kumar K arun...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com --- drivers/media/platform/Kconfig |1 + drivers/media/platform/Makefile |1 + drivers/media/platform/exynos5-is/Kconfig| 20 drivers/media/platform/exynos5-is/Makefile |7 +++ drivers/media/platform/exynos5-is/fimc-is-core.c |1 + 5 files changed, 30 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/Kconfig create mode 100644 drivers/media/platform/exynos5-is/Makefile diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 08de865..4b0475e 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF source drivers/media/platform/soc_camera/Kconfig source drivers/media/platform/exynos4-is/Kconfig +source drivers/media/platform/exynos5-is/Kconfig source drivers/media/platform/s5p-tv/Kconfig endif # V4L_PLATFORM_DRIVERS diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index eee28dd..40bf09f 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)+= s5p-tv/ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)+= s5p-g2d/ obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/ +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos5-is/ obj-$(CONFIG_BLACKFIN) += blackfin/ diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig new file mode 100644 index 000..b67d11a --- /dev/null +++ b/drivers/media/platform/exynos5-is/Kconfig @@ -0,0 +1,20 @@ +config VIDEO_SAMSUNG_EXYNOS5_CAMERA + bool Samsung Exynos5 SoC Camera Media Device driver + depends on VIDEO_V4L2 VIDEO_V4L2_SUBDEV_API PM_RUNTIME + depends on VIDEO_SAMSUNG_EXYNOS4_IS + help + This is a V4L2 media device driver for Exynos5 SoC series + camera subsystem. + +if VIDEO_SAMSUNG_EXYNOS5_CAMERA + +config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS + tristate Samsung Exynos5 SoC FIMC-IS driver + depends on I2C OF + depends on VIDEO_EXYNOS4_FIMC_IS + select VIDEOBUF2_DMA_CONTIG + help + This is a V4L2 driver for Samsung Exynos5 SoC series Imaging + Subsystem known as FIMC-IS. + +endif #VIDEO_SAMSUNG_EXYNOS5_MDEV diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile new file mode 100644 index 000..6cdb037 --- /dev/null +++ b/drivers/media/platform/exynos5-is/Makefile @@ -0,0 +1,7 @@ +ccflags-y += -Idrivers/media/platform/exynos4-is +exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o +exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o +exynos-mdevice-objs := exynos5-mdev.o + +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos-mdevice.o diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c b/drivers/media/platform/exynos5-is/fimc-is-core.c index 136e3c1..0b391f2 100644 --- a/drivers/media/platform/exynos5-is/fimc-is-core.c +++ b/drivers/media/platform/exynos5-is/fimc-is-core.c @@ -12,6 +12,7 @@ #include linux/of.h #include linux/of_address.h #include linux/of_irq.h +#include linux/of_platform.h #include linux/videodev2.h #include media/v4l2-device.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v12 11/12] V4L: Add DT binding doc for s5k4e5 image sensor
S5K4E5 is a Samsung raw image sensor controlled via I2C.
This patch adds the DT binding documentation for the same.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Mark Rutland mark.rutl...@arm.com
---
.../devicetree/bindings/media/samsung-s5k4e5.txt | 45
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/samsung-s5k4e5.txt
diff --git a/Documentation/devicetree/bindings/media/samsung-s5k4e5.txt
b/Documentation/devicetree/bindings/media/samsung-s5k4e5.txt
new file mode 100644
index 000..fc37792
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/samsung-s5k4e5.txt
@@ -0,0 +1,45 @@
+* Samsung S5K4E5 Raw Image Sensor
+
+S5K4E5 is a raw image sensor with maximum resolution of 2560x1920
+pixels. Data transfer is carried out via MIPI CSI-2 port and controls
+via I2C bus.
+
+Required Properties:
+- compatible : should contain samsung,s5k4e5
+- reg : I2C device address
+- reset-gpios : specifier of a GPIO connected to the RESET pin
+- clocks : should refer to the clock named in clock-names, from
+ the common clock bindings
+- clock-names : should contain extclk entry
+- svdda-supply : core voltage supply
+- svddio-supply: I/O voltage supply
+
+Optional Properties:
+- clock-frequency : the frequency at which the extclk clock should be
+ configured to operate, in Hz; if this property is not
+ specified default 24 MHz value will be used
+
+The device node should be added to respective control bus controller
+(e.g. I2C0) nodes and linked to the csis port node, using the common
+video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ i2c-isp@1313 {
+ s5k4e5@20 {
+ compatible = samsung,s5k4e5;
+ reg = 0x20;
+ reset-gpios = gpx1 2 1;
+ clock-frequency = 2400;
+ clocks = clock 129;
+ clock-names = extclk
+ svdda-supply = ...;
+ svddio-supply = ...;
+ port {
+ is_s5k4e5_ep: endpoint {
+ data-lanes = 1 2 3 4;
+ remote-endpoint = csis0_ep;
+ };
+ };
+ };
+ };
--
1.7.9.5
--
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[PATCH v12 12/12] V4L: Add s5k4e5 sensor driver
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/i2c/Kconfig |8 ++
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 344
3 files changed, 353 insertions(+)
create mode 100644 drivers/media/i2c/s5k4e5.c
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index f7e9147..271028b 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -572,6 +572,14 @@ config VIDEO_S5K6A3
This is a V4L2 sensor-level driver for Samsung S5K6A3 raw
camera sensor.
+config VIDEO_S5K4E5
+ tristate Samsung S5K4E5 sensor support
+ depends on MEDIA_CAMERA_SUPPORT
+ depends on I2C VIDEO_V4L2 VIDEO_V4L2_SUBDEV_API OF
+ ---help---
+ This is a V4L2 sensor-level driver for Samsung S5K4E5 raw
+ camera sensor.
+
config VIDEO_S5K4ECGX
tristate Samsung S5K4ECGX sensor support
depends on I2C VIDEO_V4L2 VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index cf3cf03..0aeed8e 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
obj-$(CONFIG_VIDEO_NOON010PC30)+= noon010pc30.o
obj-$(CONFIG_VIDEO_S5K6AA) += s5k6aa.o
obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o
+obj-$(CONFIG_VIDEO_S5K4E5) += s5k4e5.o
obj-$(CONFIG_VIDEO_S5K4ECGX) += s5k4ecgx.o
obj-$(CONFIG_VIDEO_S5C73M3)+= s5c73m3/
obj-$(CONFIG_VIDEO_ADP1653)+= adp1653.o
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..5d4007e
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,344 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/pm_runtime.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/videodev2.h
+#include media/v4l2-async.h
+#include media/v4l2-subdev.h
+
+#define S5K4E5_SENSOR_MAX_WIDTH2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
+#define S5K4E5_SENSOR_MIN_WIDTH(32 + 16)
+#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
+
+#define S5K4E5_DEF_WIDTH 1296
+#define S5K4E5_DEF_HEIGHT 732
+
+#define S5K4E5_DRV_NAMES5K4E5
+#define S5K4E5_CLK_NAMEextclk
+
+#define S5K4E5_NUM_SUPPLIES2
+
+#define S5K4E5_DEF_CLK_FREQ2400
+
+/**
+ * struct s5k4e5 - s5k4e5 sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+ struct device *dev;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+ int gpio_reset;
+ struct mutex lock;
+ struct v4l2_mbus_framefmt format;
+ struct clk *clock;
+ u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
+
+static inline struct s5k4e5 *sd_to_s5k4e5(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct s5k4e5, subdev);
+}
+
+static const struct v4l2_mbus_framefmt s5k4e5_formats[] = {
+ {
+ .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .field = V4L2_FIELD_NONE,
+ }
+};
+
+static const struct v4l2_mbus_framefmt *find_sensor_format(
+ struct v4l2_mbus_framefmt *mf)
+{
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(s5k4e5_formats); i++)
+ if (mf-code == s5k4e5_formats[i].code)
+ return s5k4e5_formats[i];
+
+ return s5k4e5_formats[0];
+}
+
+static int s5k4e5_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+
Re: [PATCH v11 03/12] [media] exynos5-fimc-is: Add common driver header files
Hi Arun,
On Tue, Nov 05, 2013 at 11:42:34AM +0530, Arun Kumar K wrote:
This patch adds all the common header files used by the fimc-is
driver. It includes the commands for interfacing with the firmware
and error codes from IS firmware, metadata and command parameter
definitions.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-cmd.h| 187
drivers/media/platform/exynos5-is/fimc-is-err.h| 257 +
.../media/platform/exynos5-is/fimc-is-metadata.h | 767 +
drivers/media/platform/exynos5-is/fimc-is-param.h | 1159
4 files changed, 2370 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-cmd.h
b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
new file mode 100644
index 000..6250280
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
@@ -0,0 +1,187 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Kil-yeon Lim kilyeon...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CMD_H
+#define FIMC_IS_CMD_H
+
+#define IS_COMMAND_VER 122 /* IS COMMAND VERSION 1.22 */
+
+enum is_cmd {
+ /* HOST - IS */
+ HIC_PREVIEW_STILL = 0x1,
+ HIC_PREVIEW_VIDEO,
+ HIC_CAPTURE_STILL,
+ HIC_CAPTURE_VIDEO,
+ HIC_PROCESS_START,
+ HIC_PROCESS_STOP,
+ HIC_STREAM_ON,
+ HIC_STREAM_OFF,
+ HIC_SHOT,
+ HIC_GET_STATIC_METADATA,
+ HIC_SET_CAM_CONTROL,
+ HIC_GET_CAM_CONTROL,
+ HIC_SET_PARAMETER,
+ HIC_GET_PARAMETER,
+ HIC_SET_A5_MEM_ACCESS,
+ RESERVED2,
+ HIC_GET_STATUS,
+ /* SENSOR PART*/
+ HIC_OPEN_SENSOR,
+ HIC_CLOSE_SENSOR,
+ HIC_SIMMIAN_INIT,
+ HIC_SIMMIAN_WRITE,
+ HIC_SIMMIAN_READ,
+ HIC_POWER_DOWN,
+ HIC_GET_SET_FILE_ADDR,
+ HIC_LOAD_SET_FILE,
+ HIC_MSG_CONFIG,
+ HIC_MSG_TEST,
+ /* IS - HOST */
+ IHC_GET_SENSOR_NUMBER = 0x1000,
+ /* Parameter1 : Address of space to copy a setfile */
+ /* Parameter2 : Space szie */
+ IHC_SET_SHOT_MARK,
+ /* PARAM1 : a frame number */
+ /* PARAM2 : confidence level(smile 0~100) */
+ /* PARMA3 : confidence level(blink 0~100) */
+ IHC_SET_FACE_MARK,
+ /* PARAM1 : coordinate count */
+ /* PARAM2 : coordinate buffer address */
+ IHC_FRAME_DONE,
+ /* PARAM1 : frame start number */
+ /* PARAM2 : frame count */
+ IHC_AA_DONE,
+ IHC_NOT_READY,
+ IHC_FLASH_READY
+};
+
+enum is_reply {
+ ISR_DONE= 0x2000,
+ ISR_NDONE
+};
+
+enum is_scenario_id {
+ ISS_PREVIEW_STILL,
+ ISS_PREVIEW_VIDEO,
+ ISS_CAPTURE_STILL,
+ ISS_CAPTURE_VIDEO,
+ ISS_END
+};
+
+enum is_subscenario_id {
+ ISS_SUB_SCENARIO_STILL,
+ ISS_SUB_SCENARIO_VIDEO,
+ ISS_SUB_SCENARIO_SCENE1,
+ ISS_SUB_SCENARIO_SCENE2,
+ ISS_SUB_SCENARIO_SCENE3,
+ ISS_SUB_END
+};
+
+struct is_setfile_header_element {
+ u32 binary_addr;
+ u32 binary_size;
+};
+
+struct is_setfile_header {
+ struct is_setfile_header_element isp[ISS_END];
+ struct is_setfile_header_element drc[ISS_END];
+ struct is_setfile_header_element fd[ISS_END];
+};
+
+struct is_common_reg {
+ u32 hicmd;
+ u32 hic_sensorid;
+ u32 hic_param[4];
+
+ u32 reserved1[3];
+
+ u32 ihcmd_iflag;
+ u32 ihcmd;
+ u32 ihc_sensorid;
+ u32 ihc_param[4];
+
+ u32 reserved2[3];
+
+ u32 isp_bayer_iflag;
+ u32 isp_bayer_sensor_id;
+ u32 isp_bayer_param[2];
+
+ u32 reserved3[4];
+
+ u32 scc_iflag;
+ u32 scc_sensor_id;
+ u32 scc_param[3];
+
+ u32 reserved4[3];
+
+ u32 dnr_iflag;
+ u32 dnr_sensor_id;
+ u32 dnr_param[2];
+
+ u32 reserved5[4];
+
+ u32 scp_iflag;
+ u32 scp_sensor_id;
+ u32 scp_param[3];
+
+ u32 reserved6[1];
+
+ u32 isp_yuv_iflag;
+ u32 isp_yuv_sensor_id;
+ u32 isp_yuv_param[2];
+
+ u32 reserved7[1];
+
+ u32 shot_iflag;
+ u32 shot_sensor_id;
+ u32 shot_param[2];
+
+ u32 reserved8[1];
+
+ u32 meta_iflag;
+ u32 meta_sensor_id;
+ u32 meta_param1;
+
+ u32 reserved9[1];
+
+ u32 fcount;
If these structs define an interface that's not used by the driver only it
might be a good idea to use
Re: [PATCH v11 03/12] [media] exynos5-fimc-is: Add common driver header files
Hi Sakari,
Thank you for the review.
On Tue, Nov 5, 2013 at 6:21 PM, Sakari Ailus sakari.ai...@iki.fi wrote:
Hi Arun,
On Tue, Nov 05, 2013 at 11:42:34AM +0530, Arun Kumar K wrote:
This patch adds all the common header files used by the fimc-is
driver. It includes the commands for interfacing with the firmware
and error codes from IS firmware, metadata and command parameter
definitions.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-cmd.h| 187
drivers/media/platform/exynos5-is/fimc-is-err.h| 257 +
.../media/platform/exynos5-is/fimc-is-metadata.h | 767 +
drivers/media/platform/exynos5-is/fimc-is-param.h | 1159
4 files changed, 2370 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-cmd.h
b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
new file mode 100644
index 000..6250280
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
@@ -0,0 +1,187 @@
+/*
[snip]
+struct is_common_reg {
+ u32 hicmd;
+ u32 hic_sensorid;
+ u32 hic_param[4];
+
+ u32 reserved1[3];
+
+ u32 ihcmd_iflag;
+ u32 ihcmd;
+ u32 ihc_sensorid;
+ u32 ihc_param[4];
+
+ u32 reserved2[3];
+
+ u32 isp_bayer_iflag;
+ u32 isp_bayer_sensor_id;
+ u32 isp_bayer_param[2];
+
+ u32 reserved3[4];
+
+ u32 scc_iflag;
+ u32 scc_sensor_id;
+ u32 scc_param[3];
+
+ u32 reserved4[3];
+
+ u32 dnr_iflag;
+ u32 dnr_sensor_id;
+ u32 dnr_param[2];
+
+ u32 reserved5[4];
+
+ u32 scp_iflag;
+ u32 scp_sensor_id;
+ u32 scp_param[3];
+
+ u32 reserved6[1];
+
+ u32 isp_yuv_iflag;
+ u32 isp_yuv_sensor_id;
+ u32 isp_yuv_param[2];
+
+ u32 reserved7[1];
+
+ u32 shot_iflag;
+ u32 shot_sensor_id;
+ u32 shot_param[2];
+
+ u32 reserved8[1];
+
+ u32 meta_iflag;
+ u32 meta_sensor_id;
+ u32 meta_param1;
+
+ u32 reserved9[1];
+
+ u32 fcount;
If these structs define an interface that's not used by the driver only it
might be a good idea to use __packed to ensure no padding is added.
The same structure is used as is in the firmware code and so it is retained
in the driver.
+};
+
+struct is_mcuctl_reg {
+ u32 mcuctl;
+ u32 bboar;
+
+ u32 intgr0;
+ u32 intcr0;
+ u32 intmr0;
+ u32 intsr0;
+ u32 intmsr0;
+
+ u32 intgr1;
+ u32 intcr1;
+ u32 intmr1;
+ u32 intsr1;
+ u32 intmsr1;
+
+ u32 intcr2;
+ u32 intmr2;
+ u32 intsr2;
+ u32 intmsr2;
+
+ u32 gpoctrl;
+ u32 cpoenctlr;
+ u32 gpictlr;
+
+ u32 pad[0xD];
+
+ struct is_common_reg common_reg;
+};
+#endif
...
diff --git a/drivers/media/platform/exynos5-is/fimc-is-metadata.h
b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
new file mode 100644
index 000..02367c4
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
@@ -0,0 +1,767 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim kilyeon...@samsung.com
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_METADATA_H_
+#define FIMC_IS_METADATA_H_
+
+struct rational {
+ uint32_t num;
+ uint32_t den;
+};
+
+#define CAMERA2_MAX_AVAILABLE_MODE 21
+#define CAMERA2_MAX_FACES16
+
+/*
+ * Controls/dynamic metadata
+ */
+
+enum metadata_mode {
+ METADATA_MODE_NONE,
+ METADATA_MODE_FULL
+};
+
+struct camera2_request_ctl {
+ uint32_tid;
+ enum metadata_mode metadatamode;
+ uint8_t outputstreams[16];
+ uint32_tframecount;
+};
+
+struct camera2_request_dm {
+ uint32_tid;
+ enum metadata_mode metadatamode;
+ uint32_tframecount;
+};
+
+
+
+enum optical_stabilization_mode {
+ OPTICAL_STABILIZATION_MODE_OFF,
+ OPTICAL_STABILIZATION_MODE_ON
+};
+
+enum lens_facing {
+ LENS_FACING_BACK,
+ LENS_FACING_FRONT
+};
+
+struct camera2_lens_ctl {
+ uint32_tfocus_distance;
+ float aperture;
Floating point numbers? Really? :-)
Yes as
[PATCH v3 0/3] phy: Add new Exynos USB 2.0 PHY driver
Hi, This is the third version of the patchset adding the new Exynos USB 2.0 PHY driver, which uses the Generic PHY Framework. It contains numerous fixes and cleanups, which are the results of the feedback to the second version. Best wishes, Kamil Debski Changes from v2: - rebase all patches to the usb-next branch - fixes in the documentation file - remove wrong entries in the phy node (ranges, and #address- #size-cells) - add clocks and clock-names as required properites - rephrase a few sentences - fixes in the ehci-exynos.c file - move phy_name variable next to phy in exynos_ehci_hcd - remove otg from exynos_ehci_hcd as it was no longer used - move devm_phy_get after the Exynos5440 skip_phy check - fixes in the s3c-hsotg.c file - cosmetic fixes (remove empty line that was wrongfully added) - fixes in the main driver - remove cpu_type in favour for a boolean flag matched with the compatible value - rename files, structures, variables and Kconfig entires - change from simple uphy to usb2_phy - fix multiline comments style - simplify #ifdefs in of_device_id - fix Kconfig description - change dev_info to dev_dbg where reasonable - cosmetic changes (remove wrongful blank lines) - remove unnecessary reference counting Changes from v1: - the changes include minor fixes of the hardware initialization of the PHY module - some other minor fixes were introduced -- Original cover letter: Hi, This patch adds a new drive for USB PHYs for Samsung SoCs. The driver is using the Generic PHY Framework created by Kishon Vijay Abrahan I. It can be found here https://lkml.org/lkml/2013/8/21/29. This patch adds support to Exynos4 family of SoCs. Support for Exynos3 and Exynos5 is planned to be added in the near future. I welcome your comments. -- [1] https://lkml.org/lkml/2013/8/21/29 *** BLURB HERE *** Kamil Debski (3): phy: Add new Exynos USB PHY driver usb: ehci-s5p: Change to use phy provided by the generic phy framework usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework .../devicetree/bindings/phy/samsung-usbphy.txt | 52 drivers/phy/Kconfig| 23 +- drivers/phy/Makefile |4 + drivers/phy/phy-exynos-usb2.c | 234 ++ drivers/phy/phy-exynos-usb2.h | 87 ++ drivers/phy/phy-exynos4210-usb2.c | 272 drivers/phy/phy-exynos4212-usb2.c | 324 drivers/usb/gadget/s3c-hsotg.c | 12 +- drivers/usb/host/ehci-exynos.c | 34 +- 9 files changed, 1013 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt create mode 100644 drivers/phy/phy-exynos-usb2.c create mode 100644 drivers/phy/phy-exynos-usb2.h create mode 100644 drivers/phy/phy-exynos4210-usb2.c create mode 100644 drivers/phy/phy-exynos4212-usb2.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/3] phy: Add new Exynos USB PHY driver
Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/phy/samsung-usbphy.txt | 52
drivers/phy/Kconfig| 23 +-
drivers/phy/Makefile |4 +
drivers/phy/phy-exynos-usb2.c | 234 ++
drivers/phy/phy-exynos-usb2.h | 87 ++
drivers/phy/phy-exynos4210-usb2.c | 272
drivers/phy/phy-exynos4212-usb2.c | 324
7 files changed, 995 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt
create mode 100644 drivers/phy/phy-exynos-usb2.c
create mode 100644 drivers/phy/phy-exynos-usb2.h
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4212-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
new file mode 100644
index 000..c8fbc70
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
@@ -0,0 +1,52 @@
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usbphy
+ - samsung,exynos4212-usbphy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+ - second and also required is the location of isolation registers
+ (isolation registers control the physical connection between the in
+ SoC modules and outside of the SoC, this also can be called enable
+ control in the documentation of the SoC)
+ - third is the location of the mode switch register, this only applies
+ to SoCs that have such a feature; mode switching enables to have
+ both host and device used the same SoC pins and is commonly used
+ when OTG is supported
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clocks is required by the phy module
+ - other clocks are associated by name with their respective phys and
+ are used to determine the value of the clock settings register
+
+The second cell in the PHY specifier identifies the PHY, its meaning is
+compatible dependent. For the currently supported SoCs (Exynos 4210 and
+Exynos 4212) it is as follows:
+ 0 - USB device,
+ 1 - USB host,
+ 2 - HSIC0,
+ 3 - HSIC1,
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+exynos_usbphy: exynos-usbphy@125B {
+ compatible = samsung,exynos4212-usbphy;
+ reg = 0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4;
+ clocks = clock 305, clock 2, clock 2, clock 2,
+ clock 2;
+ clock-names = phy, device, host, hsic0, hsic1;
+ status = okay;
+ #phy-cells = 1;
+};
+
+Then the PHY can be used in other nodes such as:
+
+ehci@1258 {
+ status = okay;
+ phys = exynos_usbphy 2;
+ phy-names = hsic0;
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..bdf0fab 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -14,7 +14,7 @@ config GENERIC_PHY
API by which phy drivers can create PHY using the phy framework and
phy users can obtain reference to the PHY. All the users of this
framework should select this config.
-
+
config PHY_EXYNOS_MIPI_VIDEO
tristate S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver
help
@@ -51,4 +51,25 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_EXYNOS_USB2
+ tristate Samsung USB 2.0 PHY driver
+ help
+ Enable this to support Samsung USB phy helper driver for Samsung SoCs.
+ This driver provides common interface to interact, for Samsung
+ USB 2.0 PHY driver.
+
+config PHY_EXYNOS4210_USB2
+ bool Support for Exynos 4210
+ depends on PHY_EXYNOS_USB2
+ depends on CPU_EXYNOS4210
+ help
+ Enable USB PHY support for Exynos 4210
+
+config PHY_EXYNOS4212_USB2
+ bool Support for Exynos 4212
+ depends on PHY_EXYNOS_USB2
+ depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+ help
+ Enable USB PHY support for Exynos 4212
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..c87bc65 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,3 +7,7 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+=
[PATCH v3 2/3] usb: ehci-s5p: Change to use phy provided by the generic phy framework
Change the phy provider used from the old usb phy specific to a new one
using the generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/usb/host/ehci-exynos.c | 34 +++---
1 file changed, 11 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 8898c01..974001b 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -19,12 +19,12 @@
#include linux/module.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/phy/phy.h
#include linux/platform_device.h
#include linux/usb/phy.h
#include linux/usb/samsung_usb_phy.h
#include linux/usb.h
#include linux/usb/hcd.h
-#include linux/usb/otg.h
#include ehci.h
@@ -44,8 +44,7 @@ static struct hc_driver __read_mostly exynos_ehci_hc_driver;
struct exynos_ehci_hcd {
struct clk *clk;
- struct usb_phy *phy;
- struct usb_otg *otg;
+ struct phy *phy;
};
#define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)-priv)
@@ -75,7 +74,8 @@ static int exynos_ehci_probe(struct platform_device *pdev)
struct usb_hcd *hcd;
struct ehci_hcd *ehci;
struct resource *res;
- struct usb_phy *phy;
+ struct phy *phy;
+ const char *phy_name;
int irq;
int err;
@@ -98,12 +98,12 @@ static int exynos_ehci_probe(struct platform_device *pdev)
return -ENOMEM;
}
exynos_ehci = to_exynos_ehci(hcd);
-
if (of_device_is_compatible(pdev-dev.of_node,
samsung,exynos5440-ehci))
goto skip_phy;
- phy = devm_usb_get_phy(pdev-dev, USB_PHY_TYPE_USB2);
+ phy_name = of_get_property(pdev-dev.of_node, phy-names, NULL);
+ phy = devm_phy_get(pdev-dev, phy_name);
if (IS_ERR(phy)) {
usb_put_hcd(hcd);
dev_warn(pdev-dev, no platform data or transceiver
defined\n);
@@ -149,11 +149,8 @@ skip_phy:
goto fail_io;
}
- if (exynos_ehci-otg)
- exynos_ehci-otg-set_host(exynos_ehci-otg, hcd-self);
-
if (exynos_ehci-phy)
- usb_phy_init(exynos_ehci-phy);
+ phy_power_on(exynos_ehci-phy);
ehci = hcd_to_ehci(hcd);
ehci-caps = hcd-regs;
@@ -173,7 +170,7 @@ skip_phy:
fail_add_hcd:
if (exynos_ehci-phy)
- usb_phy_shutdown(exynos_ehci-phy);
+ phy_power_off(exynos_ehci-phy);
fail_io:
clk_disable_unprepare(exynos_ehci-clk);
fail_clk:
@@ -188,11 +185,8 @@ static int exynos_ehci_remove(struct platform_device *pdev)
usb_remove_hcd(hcd);
- if (exynos_ehci-otg)
- exynos_ehci-otg-set_host(exynos_ehci-otg, hcd-self);
-
if (exynos_ehci-phy)
- usb_phy_shutdown(exynos_ehci-phy);
+ phy_power_off(exynos_ehci-phy);
clk_disable_unprepare(exynos_ehci-clk);
@@ -212,11 +206,8 @@ static int exynos_ehci_suspend(struct device *dev)
rc = ehci_suspend(hcd, do_wakeup);
- if (exynos_ehci-otg)
- exynos_ehci-otg-set_host(exynos_ehci-otg, hcd-self);
-
if (exynos_ehci-phy)
- usb_phy_shutdown(exynos_ehci-phy);
+ phy_power_off(exynos_ehci-phy);
clk_disable_unprepare(exynos_ehci-clk);
@@ -230,11 +221,8 @@ static int exynos_ehci_resume(struct device *dev)
clk_prepare_enable(exynos_ehci-clk);
- if (exynos_ehci-otg)
- exynos_ehci-otg-set_host(exynos_ehci-otg, hcd-self);
-
if (exynos_ehci-phy)
- usb_phy_init(exynos_ehci-phy);
+ phy_power_on(exynos_ehci-phy);
/* DMA burst Enable */
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd-regs));
--
1.7.9.5
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[PATCH v3 3/3] usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework
Change the used phy driver to the new Exynos USB phy driver that uses the
generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/usb/gadget/s3c-hsotg.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index bb31262..dc7f20c 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -31,6 +31,7 @@
#include linux/regulator/consumer.h
#include linux/of.h
#include linux/of_platform.h
+#include linux/phy/phy.h
#include linux/usb/ch9.h
#include linux/usb/gadget.h
@@ -162,7 +163,7 @@ struct s3c_hsotg_ep {
struct s3c_hsotg {
struct device*dev;
struct usb_gadget_driver *driver;
- struct usb_phy *phy;
+ struct phy *phy;
struct s3c_hsotg_plat*plat;
spinlock_t lock;
@@ -2905,9 +2906,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
dev_dbg(hsotg-dev, pdev 0x%p\n, pdev);
if (hsotg-phy)
- usb_phy_init(hsotg-phy);
+ phy_power_on(hsotg-phy);
else if (hsotg-plat-phy_init)
hsotg-plat-phy_init(pdev, hsotg-plat-phy_type);
+
}
/**
@@ -2922,7 +2924,7 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
struct platform_device *pdev = to_platform_device(hsotg-dev);
if (hsotg-phy)
- usb_phy_shutdown(hsotg-phy);
+ phy_power_off(hsotg-phy);
else if (hsotg-plat-phy_exit)
hsotg-plat-phy_exit(pdev, hsotg-plat-phy_type);
}
@@ -3529,7 +3531,7 @@ static void s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg)
static int s3c_hsotg_probe(struct platform_device *pdev)
{
struct s3c_hsotg_plat *plat = dev_get_platdata(pdev-dev);
- struct usb_phy *phy;
+ struct phy *phy;
struct device *dev = pdev-dev;
struct s3c_hsotg_ep *eps;
struct s3c_hsotg *hsotg;
@@ -3544,7 +3546,7 @@ static int s3c_hsotg_probe(struct platform_device *pdev)
return -ENOMEM;
}
- phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ phy = devm_phy_get(pdev-dev, device);
if (IS_ERR(phy)) {
/* Fallback for pdata */
plat = dev_get_platdata(pdev-dev);
--
1.7.9.5
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Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kamil, On Tue, Nov 5, 2013 at 3:06 PM, Kamil Debski k.deb...@samsung.com wrote: Hi, From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] Sent: Tuesday, November 05, 2013 8:20 AM To: Kishon Vijay Abraham I Cc: Kamil Debski; Vivek Gautam; Linux USB Mailing List; linux-samsung- s...@vger.kernel.org; linux-ker...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-...@vger.kernel.org; Greg KH; Kukjin Kim; Sylwester Nawrocki; Tomasz Figa; Felipe Balbi; Julius Werner; Jingoo Han Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? Yes, this PHY driver supports both Host as well as device type of operations of DWC3 controller. This driver is a straight port from older driver available at drivers/usb/phy/phy-samsung-usb3.c which also had been tested for host as well as device operation of DWC3. [snip] Best wishes, Kamil Debski -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: On Tuesday, November 05, 2013 8:13 PM, Jingoo Han wrote: On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. Thank you for clarifying this. This was really kind of you to help in making things clear. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. In addition to this, Vivek's comment is also right. :-) A few minutes ago, I asked one of my USB S/W engineers. USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is ofcourse the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Best regards, Jingoo Han -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/3] phy: Add new Exynos USB PHY driver
On Wednesday, November 06, 2013 1:13 AM, Kamil Debski wrote: Add a new driver for the Exynos USB PHY. The new driver uses the generic PHY framework. The driver includes support for the Exynos 4x10 and 4x12 SoC families. Signed-off-by: Kamil Debski k.deb...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/phy/samsung-usbphy.txt | 52 drivers/phy/Kconfig| 23 +- drivers/phy/Makefile |4 + drivers/phy/phy-exynos-usb2.c | 234 ++ drivers/phy/phy-exynos-usb2.h | 87 ++ drivers/phy/phy-exynos4210-usb2.c | 272 drivers/phy/phy-exynos4212-usb2.c | 324 7 files changed, 995 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt create mode 100644 drivers/phy/phy-exynos-usb2.c create mode 100644 drivers/phy/phy-exynos-usb2.h create mode 100644 drivers/phy/phy-exynos4210-usb2.c create mode 100644 drivers/phy/phy-exynos4212-usb2.c [] diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..c87bc65 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,7 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5250_USB) += phy-exynos5250-usb.o Hi Kamil, Would you add 'phy-exynos5250-usb.c' file? :-) Now, I am testing Exynos5250 USB HOST with your patchset. However, it makes error because there is no PHY driver for Exynos5250. WARNING: CPU: 0 PID: 18 at drivers/phy/phy-core.c:366 phy_get+0x1e8/0x224() Device: exynos-ehci missing string . Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/3] usb: ehci-s5p: Change to use phy provided by the generic phy framework
On Wednesday, November 06, 2013 1:13 AM, Kamil Debski wrote:
Change the phy provider used from the old usb phy specific to a new one
using the generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/usb/host/ehci-exynos.c | 34 +++---
1 file changed, 11 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 8898c01..974001b 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
[.]
@@ -98,12 +98,12 @@ static int exynos_ehci_probe(struct platform_device *pdev)
return -ENOMEM;
}
exynos_ehci = to_exynos_ehci(hcd);
-
if (of_device_is_compatible(pdev-dev.of_node,
samsung,exynos5440-ehci))
goto skip_phy;
- phy = devm_usb_get_phy(pdev-dev, USB_PHY_TYPE_USB2);
+ phy_name = of_get_property(pdev-dev.of_node, phy-names, NULL);
+ phy = devm_phy_get(pdev-dev, phy_name);
if (IS_ERR(phy)) {
usb_put_hcd(hcd);
dev_warn(pdev-dev, no platform data or transceiver
defined\n);
Hi Kamil,
The following build error happens.
drivers/usb/host/ehci-exynos.c: In function 'exynos_ehci_probe'
drivers/usb/host/ehci-exynos.c:113:14: error: 'struct exynos_ehci_hcd' has no
member named 'otg'
drivers/usb/host/ehci-exynos.c:113:25: error: 'struct phy' has no member named
'otg'
Would you add the following to this patch?
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -110,7 +110,6 @@ static int exynos_ehci_probe(struct platform_device *pdev)
return -EPROBE_DEFER;
} else {
exynos_ehci-phy = phy;
- exynos_ehci-otg = phy-otg;
}
Best regards,
Jingoo Han
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[PATCH] usb: ohci-exynos: Change to use phy provided by the generic phy framework
Change the phy provider used from the old usb phy specific to a new one
using the generic phy framework.
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Kamil Debski k.deb...@samsung.com
---
Exynos OHCI driver also uses Exynos USB2.0 PHY. Thus, I make this
patch based-on Kamil Debski's patchset for adding Exynos USB 2.0 PHY
driver.
(http://www.spinics.net/lists/linux-samsung-soc/msg24104.html)
drivers/usb/host/ohci-exynos.c | 28
1 file changed, 8 insertions(+), 20 deletions(-)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index a87baed..76eb4d3 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -17,12 +17,12 @@
#include linux/kernel.h
#include linux/module.h
#include linux/of.h
+#include linux/phy/phy.h
#include linux/platform_device.h
#include linux/usb/phy.h
#include linux/usb/samsung_usb_phy.h
#include linux/usb.h
#include linux/usb/hcd.h
-#include linux/usb/otg.h
#include ohci.h
@@ -35,8 +35,7 @@ static struct hc_driver __read_mostly exynos_ohci_hc_driver;
struct exynos_ohci_hcd {
struct clk *clk;
- struct usb_phy *phy;
- struct usb_otg *otg;
+ struct phy *phy;
};
static void exynos_ohci_phy_enable(struct platform_device *pdev)
@@ -45,7 +44,7 @@ static void exynos_ohci_phy_enable(struct platform_device
*pdev)
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
if (exynos_ohci-phy)
- usb_phy_init(exynos_ohci-phy);
+ phy_power_on(exynos_ohci-phy);
}
static void exynos_ohci_phy_disable(struct platform_device *pdev)
@@ -54,7 +53,7 @@ static void exynos_ohci_phy_disable(struct platform_device
*pdev)
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
if (exynos_ohci-phy)
- usb_phy_shutdown(exynos_ohci-phy);
+ phy_power_off(exynos_ohci-phy);
}
static int exynos_ohci_probe(struct platform_device *pdev)
@@ -62,7 +61,8 @@ static int exynos_ohci_probe(struct platform_device *pdev)
struct exynos_ohci_hcd *exynos_ohci;
struct usb_hcd *hcd;
struct resource *res;
- struct usb_phy *phy;
+ struct phy *phy;
+ const char *phy_name;
int irq;
int err;
@@ -89,14 +89,14 @@ static int exynos_ohci_probe(struct platform_device *pdev)
samsung,exynos5440-ohci))
goto skip_phy;
- phy = devm_usb_get_phy(pdev-dev, USB_PHY_TYPE_USB2);
+ phy_name = of_get_property(pdev-dev.of_node, phy-names, NULL);
+ phy = devm_phy_get(pdev-dev, phy_name);
if (IS_ERR(phy)) {
usb_put_hcd(hcd);
dev_warn(pdev-dev, no platform data or transceiver
defined\n);
return -EPROBE_DEFER;
} else {
exynos_ohci-phy = phy;
- exynos_ohci-otg = phy-otg;
}
skip_phy:
@@ -135,9 +135,6 @@ skip_phy:
goto fail_io;
}
- if (exynos_ohci-otg)
- exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
-
platform_set_drvdata(pdev, hcd);
exynos_ohci_phy_enable(pdev);
@@ -165,9 +162,6 @@ static int exynos_ohci_remove(struct platform_device *pdev)
usb_remove_hcd(hcd);
- if (exynos_ohci-otg)
- exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
-
exynos_ohci_phy_disable(pdev);
clk_disable_unprepare(exynos_ohci-clk);
@@ -210,9 +204,6 @@ static int exynos_ohci_suspend(struct device *dev)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, hcd-flags);
- if (exynos_ohci-otg)
- exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
-
exynos_ohci_phy_disable(pdev);
clk_disable_unprepare(exynos_ohci-clk);
@@ -231,9 +222,6 @@ static int exynos_ohci_resume(struct device *dev)
clk_prepare_enable(exynos_ohci-clk);
- if (exynos_ohci-otg)
- exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
-
exynos_ohci_phy_enable(pdev);
ohci_resume(hcd, false);
--
1.7.10.4
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Re: [PATCH V4] spi: s3c64xx: Enable Word transfer
Hi Tomasz, On Thu, Oct 31, 2013 at 6:07 PM, Tomasz Figa t.f...@samsung.com wrote: Hi Rajeshwari, On Thursday 31 of October 2013 16:17:15 Rajeshwari Birje wrote: Hi Mark Brown , On Wed, Oct 30, 2013 at 10:36 PM, Tomasz Figa t.f...@samsung.com wrote: On Wednesday 30 of October 2013 10:00:29 Mark Brown wrote: On Wed, Oct 30, 2013 at 11:52:54AM +0530, Rajeshwari Birje wrote: The following patch already sets bits_per_word_mask for drivers/spi/spi-s3c64xx.c in s3c64xx_spi_probe, hence I had a doubt do I need to set the same again. OK, so how did this work before then? You're just adding new code but the driver was previously claiming to support different bits per word (and now I look at the code there is some handling for that in code). Is this a bug fix? No idea if it worked before, but now if I try to do 16 bit transfer without my patch, I get following error. Xfer length(1) not a multiple of word size(2) I guess we can consider this as a bug fix then for word transfer. That's a good question. Rajeshwari, what SPI device did you test this patch with? Does it have a driver in mainline kernel? @Tomasz: I tested it for W25Q32DW Winbond device which is already has a driver in mainline Kernel The driver as of today's linux-next does not seem to support word transfers. Do you have some additional, out of tree patches that add such support? Yes I set the bits_per_word to 32/16 in drivers/mtd/devices/m25p80.c m25p_probe function and the call spi_setup(spi). Best regards, Tomasz -- Regards, Rajeshwari Shinde -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
