Re: [GIT PULL 3/4] Samsung PM updates for v3.15
On Thursday 20 March 2014, Kukjin Kim wrote: > Samsung PM related 2nd updates for v3.15 > > From Tomasz Figa : > Current Samsung PM code is heavily unprepared for multiplatform > systems. The design implies accessing functions and global > variables defined in particular mach- subdirectory from common > code in plat-, which is not allowed when building ARCH_MULTIPLATFORM. > In addition there is a lot of forced code unification, which makes > common function handle any possible quirks of all supported SoCs. > In the end this design turned out to not work too well, ending with > a lot of empty functions exported from mach-, just because code in > common pm.c calls them. Moreover, recent trend of moving lower level > suspend/resume code to proper drivers, like pinctrl or clk, made a > lot of code there redundant, especially on DT-only platforms like > Exynos. > > Note that this branch is based on previous tags/samsung-pm-1 and merge > tags/samsung-cleanup-2 because of fix build error from recent changes > of > Merged into next/cleanup3, thanks Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 4/4] Samsung Exynos cleanup/consolidate for v3.15
On Thursday 20 March 2014, Kukjin Kim wrote: > Exynos cleanup for v3.15 > > - reorganize code for > - add support reserve memory for mfc-v7 > - consolidate exynos4 and exynos5 machine codes > - add generic compatible strings for exynos4 and exynos5 > - update DT with generic compatible strings > - move clk related dt-binding header file in dt-bindings/clock Merged into next/cleanup3, thanks Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 2/4] Samsung 3rd DT updates for v3.15
On Thursday 20 March 2014, Kukjin Kim wrote: > Samsung 3rd DT updates for v3.15 > > - Arndale Octa board updates: >LDO3 and LDO23 enabled for soft-reset >LDO9 enabled for USB operation >MDMA1 disabled to avoid imprecise external abort > > Note that this is based on previous tags/samsung-dt-2 Merged into next/cleanup3, thanks Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 1/4] Samsung 3rd cleanup for v3.15
On Thursday 20 March 2014, Kukjin Kim wrote: > > Samsung 3rd cleanup for v3.15 > > - Remove in mach-exynos > - Remove invalid code from in mach-s3c24xx > > Note that this is based on previous tags/samsung-cleanup-2 > merged into next/cleanup3, thanks! Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 2/2] Samsung 2nd DT updates for v3.15
On Tuesday 18 March 2014, Kukjin Kim wrote:
> The following changes since commit 86feafebbec2b510daf36ffbdbe10228ed890b00:
>
>ARM: dts: use macros in clock bindings for exynos5440 (2014-02-26
> 09:53:31 +0900)
>
> are available in the git repository at:
>
>git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> tags/samsung-dt-2
>
> for you to fetch changes up to ba0d7ed391b7b3fb5ca98d9cf4d067b7f5ed956b:
>
>ARM: dts: enable ahci sata and sata phy for exynos5250 (2014-03-18
> 07:49:14 +0900)
>
>
> Samsung 2nd DT updates for v3.15
> - add DT entry for AHCI SATA and SATA PHY with using generic
>PHY framework for exynos5250 and arndale, smdk5250 boards.
> - add SSS DT node for exynos5420 and exynos5250
> - remove leftover spi0 node for smdk5250 board
> - add ADC and thermistor nodes for exynos4412-trats2 board
> - move common irq-combiner node for exynos4x12 from exynos4212
>and exynos4412
> - add ADC, PMU and GPS_ALIVE power domain nodes for exynos4x12
>
> Note that based on previous tags/samsung-dt and tags/exynos-clk
>
>
> Chanwoo Choi (5):
>ARM: dts: Add ADC's dt data to read raw data for exynos4x12
>ARM: dts: Add PMU dt data to support PMU for exynos4x12
>ARM: dts: Add GPS_ALIVE power domain for exynos4x12
>ARM: dts: Move common dt data for interrupt combiner controller
> for exynos4x12
>ARM: dts: Add ADC and themistor nodes for exynos4412-trats2
>
> Mark Brown (1):
>ARM: dts: Remove leftover spi0 node for smdk5250
>
> Naveen Krishna Chatradhi (1):
>ARM: dts: add dt node for sss module for exynos5250/5420
>
> Yuvaraj Kumar C D (1):
>ARM: dts: enable ahci sata and sata phy for exynos5250
>
> .../devicetree/bindings/ata/exynos-sata-phy.txt| 14 -
> .../devicetree/bindings/ata/exynos-sata.txt| 25 +--
> .../devicetree/bindings/phy/samsung-phy.txt| 36
> ++
Looking through the branch contents, I noticed that the examples in the
bindings contain mandatory properties that are not documented.
I have merged your branch into next/cleanup3 of the arm-soc tree,
but I also applied a patch on top to document the missing strings
and properties. It is currently the top commit on the branch, so
if anyone spots a mistake, we can probably rectify it.
Please be more careful with binding documentation in the future.
Was this actually reviewed on the devicetree-discuss mailing list?
Arnd
9<-
>From 9dfbff16b422a4bac7ad309847c7bc5d65653392 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann
Date: Sat, 29 Mar 2014 02:15:43 +0100
Subject: [PATCH] devicetree: fix newly added exynos sata bindings
Commit ba0d7ed391b7b "ARM: dts: enable ahci sata and sata phy for
exynos5250" added a new binding document for the sata phy device,
and changed the sata controller binding. However, in both cases
significant aspects of the binding remained undocumented.
This attempts to reconstruct the actual binding from the usage.
Signed-off-by: Arnd Bergmann
Cc: Yuvaraj Kumar C D
Cc: Kishon Vijay Abraham I
Cc: Kukjin Kim
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt
b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index b2adb1f..cb48448 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -8,8 +8,14 @@ Required properties:
- interrupts :
- reg :
- samsung,sata-freq:
-- phys : as mentioned in phy-bindings.txt
-- phy-names: as mentioned in phy-bindings.txt
+- phys : Must contain exactly one entry as specified
+ in phy-bindings.txt
+- phy-names: Must be "sata-phy"
+
+Optional properties:
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Shall be "sata" for the external SATA bus clock,
+ and "sclk_sata" for the internal controller clock.
Example:
sata@122f {
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index a937f75..67d38b3 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -30,7 +30,11 @@ Each SATA PHY controller should have its own node.
Required properties:
- compatible: compatible list, contains "samsung,exynos5250-sata-phy"
- reg : offset and length of the SATA PHY register set;
-- #phy-cells : from the generic phy bindings;
+- #phy-cells : must be zero
+- clocks : must be exactly one entry
+- clock-names : must be "sata_phyctrl"
+- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no
arguments
+- samsung,syscon-phandle : a phandle to t
Re: [GIT PULL 1/2] Samsung 2nd cleanup for v3.15
On Tuesday 18 March 2014, Kukjin Kim wrote: > The following changes since commit d9671ca923445aa870ecc34df3db01dd602d87fc: > >ARM: EXYNOS: Remove uncompress.h (2014-02-24 09:39:18 +0900) > > are available in the git repository at: > >git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git > tags/samsung-cleanup-2 > > for you to fetch changes up to 19a964644f1e655c3f67d539c1e99a9fbcc4588c: > >ARM: SAMSUNG: remove all custom uncompress.h (2014-03-11 22:05:18 +0900) > > > Samsung cleanup-2 for v3.15 > - use generic uncompress.h and remove all custom >uncompress.h in mach-s3c24xx, s3c64xx, s5p64x0, >s5pc100, s5pv210 and plat-samsung directories. > > Note that based on previous tags/samsung-cleanup I've started a new next/cleanup3 branch for this one and the following five samsung branches. I found one small issue with one of the branches, if we all agree on a solution for that, I expect we can just send out the cleanup3 branch together with cleanup2. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 5/6] Samsung PM updates for v3.15
On Friday 28 March 2014, Kukjin Kim wrote: > Kukjin Kim wrote: > > > > On 03/19/14 13:01, Mike Turquette wrote: > > > > > Thanks :-) > > > > > Acked-by: Mike Turquette > > > > > It's time. Please pull this [5/6] and "[GIT PULL 6/6] Samsung > > clk-s3c24xx updates for v3.15". > > > Hi Arnd, Olof and Mike, > > Still I cannot see this in arm-soc. Any problems? > Sorry, I didn't have this one on my radar any more, merged into next/drivers now. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 49/75] ARM: l2c: fix register naming
* Russell King - ARM Linux [140328 14:06]: > On Fri, Mar 28, 2014 at 09:00:48AM -0700, Tony Lindgren wrote: > > * Russell King [140328 08:22]: > > > We have a mixture of different devices with different register layouts, > > > but we group all the bits together in an opaque mess. Split them out > > > into those which are L2C-310 specific and ones which refer to earlier > > > devices. Provide full auxiliary control register definitions. > > > > > > Signed-off-by: Russell King > > > > Acked-by: Tony Lindgren > > > > > --- a/arch/arm/mach-omap2/omap4-common.c > > > +++ b/arch/arm/mach-omap2/omap4-common.c > > > @@ -212,15 +212,15 @@ static int __init omap_l2_cache_init(void) > > > return -ENOMEM; > > > > > > /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ > > > - aux_ctrl = (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | > > > - (0x1 << 25) | > > > - (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | > > > - (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)) | > > > - (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | > > > - (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | > > > - (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | > > > - (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | > > > - (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT); > > > + aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 | > > > +L310_AUX_CTRL_CACHE_REPLACE_RR | > > > +L310_AUX_CTRL_NS_LOCKDOWN | > > > +L310_AUX_CTRL_NS_INT_CTRL | > > > +L2C_AUX_CTRL_WAY_SIZE(3) | > > > +L2C_AUX_CTRL_SHARED_OVERRIDE | > > > +L310_AUX_CTRL_DATA_PREFETCH | > > > +L310_AUX_CTRL_INSTR_PREFETCH | > > > +L310_AUX_CTRL_EARLY_BRESP; > > > > I guess eventually we can set up some common configuration mask > > define for these kind of things? > > The idea is that eventually platforms should just specify no changes to > the auxctl configuration. You will notice later patches remove a number > of the above flags. OK thanks great! Tony -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 49/75] ARM: l2c: fix register naming
On Fri, Mar 28, 2014 at 09:00:48AM -0700, Tony Lindgren wrote: > * Russell King [140328 08:22]: > > We have a mixture of different devices with different register layouts, > > but we group all the bits together in an opaque mess. Split them out > > into those which are L2C-310 specific and ones which refer to earlier > > devices. Provide full auxiliary control register definitions. > > > > Signed-off-by: Russell King > > Acked-by: Tony Lindgren > > > --- a/arch/arm/mach-omap2/omap4-common.c > > +++ b/arch/arm/mach-omap2/omap4-common.c > > @@ -212,15 +212,15 @@ static int __init omap_l2_cache_init(void) > > return -ENOMEM; > > > > /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ > > - aux_ctrl = (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | > > - (0x1 << 25) | > > - (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | > > - (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)) | > > - (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | > > - (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | > > - (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | > > - (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | > > - (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT); > > + aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 | > > + L310_AUX_CTRL_CACHE_REPLACE_RR | > > + L310_AUX_CTRL_NS_LOCKDOWN | > > + L310_AUX_CTRL_NS_INT_CTRL | > > + L2C_AUX_CTRL_WAY_SIZE(3) | > > + L2C_AUX_CTRL_SHARED_OVERRIDE | > > + L310_AUX_CTRL_DATA_PREFETCH | > > + L310_AUX_CTRL_INSTR_PREFETCH | > > + L310_AUX_CTRL_EARLY_BRESP; > > I guess eventually we can set up some common configuration mask > define for these kind of things? The idea is that eventually platforms should just specify no changes to the auxctl configuration. You will notice later patches remove a number of the above flags. -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 49/75] ARM: l2c: fix register naming
On Fri, Mar 28, 2014 at 4:18 PM, Russell King wrote: > We have a mixture of different devices with different register layouts, > but we group all the bits together in an opaque mess. Split them out > into those which are L2C-310 specific and ones which refer to earlier > devices. Provide full auxiliary control register definitions. > > Signed-off-by: Russell King Acked-by: Linus Walleij For ux500. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [STLinux Kernel] [PATCH 49/75] ARM: l2c: fix register naming
Thanks Russel, On 03/28/2014 04:18 PM, Russell King wrote: We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Signed-off-by: Russell King --- arch/arm/include/asm/hardware/cache-l2x0.h | 73 -- arch/arm/mach-cns3xxx/core.c | 8 ++-- arch/arm/mach-imx/system.c | 8 ++-- arch/arm/mach-omap2/omap-mpuss-lowpower.c | 2 +- arch/arm/mach-omap2/omap4-common.c | 18 arch/arm/mach-prima2/l2x0.c| 5 +- arch/arm/mach-realview/realview_pbx.c | 4 +- arch/arm/mach-spear/spear13xx.c| 6 +-- arch/arm/mach-sti/board-dt.c | 8 ++-- arch/arm/mach-tegra/sleep.h| 8 ++-- arch/arm/mach-ux500/cache-l2x0.c | 4 +- arch/arm/mach-vexpress/ct-ca9x4.c | 4 +- arch/arm/mm/cache-l2x0.c | 57 +++ arch/arm/plat-samsung/s5p-sleep.S | 8 ++-- 14 files changed, 118 insertions(+), 95 deletions(-) For the mach-sti part: Acked-by: Maxime Coquelin Thanks, Maxime -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH net-next] net: sxgbe: fix sparse warnings about static declaration
From: Byungho An Date: Fri, 28 Mar 2014 10:57:36 -0700 > From: Byungho An > > This fixes followings: > > sparse warnings: (new ones prefixed by >>) > >>> drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c:197:5: > sparse: symbol 'sxgbe_platform_freeze' was not declared. Should it be static? >>> drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c:204:5: > sparse: symbol 'sxgbe_platform_restore' was not declared. Should it be static? >>> drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c:228:24: > sparse: symbol 'sxgbe_platform_driver' was not declared. Should it be static? > >>> drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c:1795:6: > sparse: symbol 'sxgbe_get_ops' was not declared. Should it be static? > > Reported-by: kbuild test robot > Signed-off-by: Byungho An Applied. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH net-next] net: sxgbe: fix potential null dereference
From: Byungho An Date: Fri, 28 Mar 2014 10:57:44 -0700 > From: Byungho An > > This fixes following: > > drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c:1828 sxgbe_hw_init() > error: potential null dereference 'priv->hw'. (kmalloc returns null) > > Reported-by: kbuild test robot > Signed-off-by: Byungho An Applied. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH net-next] net: sxgbe: fix sparse warnings about static declaration
From: Byungho An
This fixes followings:
sparse warnings: (new ones prefixed by >>)
>> drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c:197:5:
sparse: symbol 'sxgbe_platform_freeze' was not declared. Should it be static?
>> drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c:204:5:
sparse: symbol 'sxgbe_platform_restore' was not declared. Should it be static?
>> drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c:228:24:
sparse: symbol 'sxgbe_platform_driver' was not declared. Should it be static?
>> drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c:1795:6:
sparse: symbol 'sxgbe_get_ops' was not declared. Should it be static?
Reported-by: kbuild test robot
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c |2 +-
drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
b/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
index 1869d4c6..ee1fd3c 100644
--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
@@ -2013,7 +2013,7 @@ static const struct net_device_ops sxgbe_netdev_ops = {
};
/* Get the hardware ops */
-void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
+static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
{
ops_ptr->mac= sxgbe_get_core_ops();
ops_ptr->desc = sxgbe_get_desc_ops();
diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c
b/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c
index 94c2cd7..b147d46 100644
--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c
+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c
@@ -200,14 +200,14 @@ static int sxgbe_platform_resume(struct device *dev)
return sxgbe_resume(ndev);
}
-int sxgbe_platform_freeze(struct device *dev)
+static int sxgbe_platform_freeze(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
return sxgbe_freeze(ndev);
}
-int sxgbe_platform_restore(struct device *dev)
+static int sxgbe_platform_restore(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
@@ -231,7 +231,7 @@ static const struct of_device_id sxgbe_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, sxgbe_dt_ids);
-struct platform_driver sxgbe_platform_driver = {
+static struct platform_driver sxgbe_platform_driver = {
.probe = sxgbe_platform_probe,
.remove = sxgbe_platform_remove,
.driver = {
--
1.7.10.4
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[PATCH net-next] net: sxgbe: fix potential null dereference
From: Byungho An
This fixes following:
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c:1828 sxgbe_hw_init()
error: potential null dereference 'priv->hw'. (kmalloc returns null)
Reported-by: kbuild test robot
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
b/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
index ee1fd3c..a72688e 100644
--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
@@ -2039,11 +2039,13 @@ static void sxgbe_get_ops(struct sxgbe_ops * const
ops_ptr)
* Description: this function checks the HW capability
* (if supported) and sets the driver's features.
*/
-static void sxgbe_hw_init(struct sxgbe_priv_data * const priv)
+static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
{
u32 ctrl_ids;
priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL);
+ if(!priv->hw)
+ return -ENOMEM;
/* get the hardware ops */
sxgbe_get_ops(priv->hw);
@@ -2064,6 +2066,8 @@ static void sxgbe_hw_init(struct sxgbe_priv_data * const
priv)
if (priv->hw_cap.rx_csum_offload)
pr_info("RX Checksum offload supported\n");
+
+ return 0;
}
/**
@@ -2102,7 +2106,9 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device
*device,
sxgbe_verify_args();
/* Init MAC and get the capabilities */
- sxgbe_hw_init(priv);
+ ret = sxgbe_hw_init(priv);
+ if (ret)
+ goto error_free_netdev;
/* allocate memory resources for Descriptor rings */
ret = txring_mem_alloc(priv);
--
1.7.10.4
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Re: [PATCH 49/75] ARM: l2c: fix register naming
* Russell King [140328 08:22]: > We have a mixture of different devices with different register layouts, > but we group all the bits together in an opaque mess. Split them out > into those which are L2C-310 specific and ones which refer to earlier > devices. Provide full auxiliary control register definitions. > > Signed-off-by: Russell King Acked-by: Tony Lindgren > --- a/arch/arm/mach-omap2/omap4-common.c > +++ b/arch/arm/mach-omap2/omap4-common.c > @@ -212,15 +212,15 @@ static int __init omap_l2_cache_init(void) > return -ENOMEM; > > /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ > - aux_ctrl = (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | > - (0x1 << 25) | > - (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | > - (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)) | > - (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | > - (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | > - (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | > - (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | > - (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT); > + aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 | > +L310_AUX_CTRL_CACHE_REPLACE_RR | > +L310_AUX_CTRL_NS_LOCKDOWN | > +L310_AUX_CTRL_NS_INT_CTRL | > +L2C_AUX_CTRL_WAY_SIZE(3) | > +L2C_AUX_CTRL_SHARED_OVERRIDE | > +L310_AUX_CTRL_DATA_PREFETCH | > +L310_AUX_CTRL_INSTR_PREFETCH | > +L310_AUX_CTRL_EARLY_BRESP; I guess eventually we can set up some common configuration mask define for these kind of things? Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/8] i.MX6 PCIe binding change and MSI support
While working on MSI support for the i.MX6 PCIe host driver it has been discovered that the binding for this host controller is broken in many ways (refer to the patch descriptions for more info) and was introduced without proper discussion about what should/should not be in the binding. This series fixes this and minimizes the difference of the i.MX6 binding to the common designware PCIe binding. I'm aware that this is a quite radical change, but I think it's justified to do this as long as there aren't many user of the old binding (most of the optional properties in the binding aren't even implemented). Looking forward to your feedback. Lucas Stach (8): ARM: imx6q-clk: parent lvds_gate from lvds_sel PCI: designware: split Exynos and i.MX bindings ARM: dts: imx6: update pcie to bring in line with new binding PCI: imx6: use new clock names PCI: imx6: drop old irq mapping PCI: imx6: rip out optional (and unused) irqs PCI: designware: make MSI isr shared irq aware PCI: imx6: add support for MSI .../devicetree/bindings/pci/designware-pcie.txt| 74 +-- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 38 ++ .../bindings/pci/samsung,exynos5440-pcie.txt | 65 + arch/arm/boot/dts/imx6qdl.dtsi | 7 +- arch/arm/mach-imx/clk-imx6q.c | 4 +- drivers/pci/host/pci-exynos.c | 4 +- drivers/pci/host/pci-imx6.c| 145 - drivers/pci/host/pcie-designware.c | 6 +- drivers/pci/host/pcie-designware.h | 2 +- 9 files changed, 176 insertions(+), 169 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 49/75] ARM: l2c: fix register naming
We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Signed-off-by: Russell King --- arch/arm/include/asm/hardware/cache-l2x0.h | 73 -- arch/arm/mach-cns3xxx/core.c | 8 ++-- arch/arm/mach-imx/system.c | 8 ++-- arch/arm/mach-omap2/omap-mpuss-lowpower.c | 2 +- arch/arm/mach-omap2/omap4-common.c | 18 arch/arm/mach-prima2/l2x0.c| 5 +- arch/arm/mach-realview/realview_pbx.c | 4 +- arch/arm/mach-spear/spear13xx.c| 6 +-- arch/arm/mach-sti/board-dt.c | 8 ++-- arch/arm/mach-tegra/sleep.h| 8 ++-- arch/arm/mach-ux500/cache-l2x0.c | 4 +- arch/arm/mach-vexpress/ct-ca9x4.c | 4 +- arch/arm/mm/cache-l2x0.c | 57 +++ arch/arm/plat-samsung/s5p-sleep.S | 8 ++-- 14 files changed, 118 insertions(+), 95 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 94fbcec216ae..e52584539743 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -26,8 +26,8 @@ #define L2X0_CACHE_TYPE0x004 #define L2X0_CTRL 0x100 #define L2X0_AUX_CTRL 0x104 -#define L2X0_TAG_LATENCY_CTRL 0x108 -#define L2X0_DATA_LATENCY_CTRL 0x10C +#define L310_TAG_LATENCY_CTRL 0x108 +#define L310_DATA_LATENCY_CTRL 0x10C #define L2X0_EVENT_CNT_CTRL0x200 #define L2X0_EVENT_CNT1_CFG0x204 #define L2X0_EVENT_CNT0_CFG0x208 @@ -54,16 +54,16 @@ #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 #define L2X0_LOCKDOWN_STRIDE 0x08 -#define L2X0_ADDR_FILTER_START 0xC00 -#define L2X0_ADDR_FILTER_END 0xC04 +#define L310_ADDR_FILTER_START 0xC00 +#define L310_ADDR_FILTER_END 0xC04 #define L2X0_TEST_OPERATION0xF00 #define L2X0_LINE_DATA 0xF10 #define L2X0_LINE_TAG 0xF30 #define L2X0_DEBUG_CTRL0xF40 -#define L2X0_PREFETCH_CTRL 0xF60 -#define L2X0_POWER_CTRL0xF80 -#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) -#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L310_PREFETCH_CTRL 0xF60 +#define L310_POWER_CTRL0xF80 +#define L310_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L310_STNDBY_MODE_EN (1 << 0) /* Registers shifts and masks */ #define L2X0_CACHE_ID_PART_MASK(0xf << 6) @@ -88,29 +88,52 @@ #define L310_CACHE_ID_RTL_R3P3 0x09 #define L2X0_AUX_CTRL_MASK 0xcfff +/* L2C auxiliary control register - bits common to L2C-210/220/310 */ +#define L2C_AUX_CTRL_WAY_SIZE_SHIFT17 +#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17) +#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17) +#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20) +#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21) +#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22) +/* L2C-210/220 common bits */ #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT0 -#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 +#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0) #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT3 -#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) +#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3) #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT6 -#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) +#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6) #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 -#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) -#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 -#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 -#define L2X0_AUX_CTRL_WAY_SIZE_MASK(0x7 << 17) -#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 -#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT26 -#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT27 -#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 -#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 -#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT30 +#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) +#define L2X0_AUX_CTRL_ASSOC_SHIFT 13 +#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) +/* L2C-210 specific bits */ +#define L210_AUX_CTRL_WRAP_DISABLE BIT(12) +#define L210_AUX_CTRL_WA_OVERRIDE BIT(23) +#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24) +/* L2C-220 specific bits */ +#define L220_AUX_CTRL_EXCLUSIVE_
[PATCH 51/75] ARM: l2c: remove platforms/SoCs setting early BRESP
Since we now automatically enable early BRESP in core L2C-310 code when we detect a Cortex-A9, we don't need platforms/SoCs to set this bit explicitly. Instead, they should seek to preserve the value of bit 30 in the auxiliary control register. Signed-off-by: Russell King --- arch/arm/mach-berlin/berlin.c| 2 +- arch/arm/mach-exynos/common.c| 4 ++-- arch/arm/mach-omap2/omap4-common.c | 3 +-- arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 4 ++-- arch/arm/mach-shmobile/board-armadillo800eva.c | 4 ++-- arch/arm/mach-shmobile/board-kzm9g-reference.c | 4 ++-- arch/arm/mach-shmobile/board-kzm9g.c | 4 ++-- arch/arm/mach-shmobile/setup-r8a7778.c | 4 ++-- arch/arm/mach-shmobile/setup-r8a7779.c | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- arch/arm/mach-tegra/tegra.c | 4 ++-- 11 files changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-berlin/berlin.c b/arch/arm/mach-berlin/berlin.c index 025bcb5473eb..6709d2a6bec8 100644 --- a/arch/arm/mach-berlin/berlin.c +++ b/arch/arm/mach-berlin/berlin.c @@ -24,7 +24,7 @@ static void __init berlin_init_machine(void) * with DT probing for L2CCs, berlin_init_machine can be removed. * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc */ - l2x0_of_init(0x70c0, 0xfeff); + l2x0_of_init(0x30c0, 0xfeff); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index f18be40e5b21..cd53b72449a0 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -45,8 +45,8 @@ #include "common.h" #include "regs-pmu.h" -#define L2_AUX_VAL 0x7C470001 -#define L2_AUX_MASK 0xC200 +#define L2_AUX_VAL 0x3c470001 +#define L2_AUX_MASK 0xc200 static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 84e097f5fdf4..ce2fad84a43c 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -219,8 +219,7 @@ static int __init omap_l2_cache_init(void) L2C_AUX_CTRL_WAY_SIZE(3) | L2C_AUX_CTRL_SHARED_OVERRIDE | L310_AUX_CTRL_DATA_PREFETCH | - L310_AUX_CTRL_INSTR_PREFETCH | - L310_AUX_CTRL_EARLY_BRESP; + L310_AUX_CTRL_INSTR_PREFETCH; outer_cache.write_sec = omap4_l2c310_write_sec; if (of_have_populated_dt()) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c index 57d1a78367b6..34e7f3c17dd2 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c @@ -164,8 +164,8 @@ static void __init eva_init(void) r8a7740_meram_workaround(); #ifdef CONFIG_CACHE_L2X0 - /* Early BRESP enable, Shared attribute override enable, 32K*8way */ - l2x0_init(IOMEM(0xf0002000), 0x4044, 0x82000fff); + /* Shared attribute override enable, 32K*8way */ + l2x0_init(IOMEM(0xf0002000), 0x0044, 0xc2000fff); #endif r8a7740_add_standard_devices_dt(); diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 93533e2710a8..69ec71038ec7 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -1270,8 +1270,8 @@ static void __init eva_init(void) #ifdef CONFIG_CACHE_L2X0 - /* Early BRESP enable, Shared attribute override enable, 32K*8way */ - l2x0_init(IOMEM(0xf0002000), 0x4044, 0x82000fff); + /* Shared attribute override enable, 32K*8way */ + l2x0_init(IOMEM(0xf0002000), 0x0044, 0xc2000fff); #endif i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index 598e32488410..85873f186d77 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -36,8 +36,8 @@ static void __init kzm_init(void) sh73a0_add_standard_devices_dt(); #ifdef CONFIG_CACHE_L2X0 - /* Early BRESP enable, Shared attribute override enable, 64K*8way */ - l2x0_init(IOMEM(0xf010), 0x4046, 0x82000fff); + /* Shared attribute override enable, 64K*8way */ + l2x0_init(IOMEM(0xf010), 0x0046, 0xc2000fff); #endif } diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index bc40b853ffd3..bd9931f223ae 100644 --- a/arch/arm/mach-shmobile/boar
[PATCH 7/8] PCI: designware: make MSI isr shared irq aware
On i.MX6 the host controller MSI irq is shared
with PCI legacy INTD. Make sure we don't bail too
early from the irq handler.
The issue is fairly theoretical as it would require
a system setup with a PCIe switch where one connected
device is using legacy INTD and another one using
MSI, but better fix it now.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-exynos.c | 4 +---
drivers/pci/host/pcie-designware.c | 6 +-
drivers/pci/host/pcie-designware.h | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 3de6bfbbe8e9..b616d34922d8 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -415,9 +415,7 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq,
void *arg)
{
struct pcie_port *pp = arg;
- dw_handle_msi_irq(pp);
-
- return IRQ_HANDLED;
+ return dw_handle_msi_irq(pp);
}
static void exynos_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 98c118e04dba..cbce9b04b13d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -156,15 +156,17 @@ static struct irq_chip dw_msi_irq_chip = {
};
/* MSI int handler */
-void dw_handle_msi_irq(struct pcie_port *pp)
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
{
unsigned long val;
int i, pos, irq;
+ irqreturn_t ret = IRQ_NONE;
for (i = 0; i < MAX_MSI_CTRLS; i++) {
dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
(u32 *)&val);
if (val) {
+ ret = IRQ_HANDLED;
pos = 0;
while ((pos = find_next_bit(&val, 32, pos)) != 32) {
irq = irq_find_mapping(pp->irq_domain,
@@ -177,6 +179,8 @@ void dw_handle_msi_irq(struct pcie_port *pp)
}
}
}
+
+ return ret;
}
void dw_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.h
b/drivers/pci/host/pcie-designware.h
index 3063b3594d88..a169d22d517e 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -68,7 +68,7 @@ struct pcie_host_ops {
int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
-void dw_handle_msi_irq(struct pcie_port *pp);
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
--
1.9.0
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[PATCH 1/8] ARM: imx6q-clk: parent lvds_gate from lvds_sel
Allows fror proper refcounting of the parent clocks
when enabling the clock output on CLK1/2 pads.
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/clk-imx6q.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index af2e582d2b74..f98a6bb98145 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
* the "output_enable" bit as a gate, even though it's really just
* enabling clock output.
*/
- clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
- clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
+ clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160,
10);
+ clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160,
11);
/*name parent_name
reg idx */
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",
base + 0x100, 0);
--
1.9.0
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[PATCH 5/8] PCI: imx6: drop old irq mapping
We don't need this anymore. The irqs are now
properly mapped through the DT.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-imx6.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 71730bbcd9a2..259a73687526 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -483,12 +483,6 @@ static int imx6_add_pcie_port(struct pcie_port *pp,
{
int ret;
- pp->irq = platform_get_irq(pdev, 0);
- if (!pp->irq) {
- dev_err(&pdev->dev, "failed to get irq\n");
- return -ENODEV;
- }
-
pp->root_bus_nr = -1;
pp->ops = &imx6_pcie_host_ops;
--
1.9.0
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[PATCH 3/8] ARM: dts: imx6: update pcie to bring in line with new binding
The new bindings drops one clock, renames the others and drops the old interrupt mapping. Signed-off-by: Lucas Stach --- arch/arm/boot/dts/imx6qdl.dtsi | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index c1c06d25decc..1ea1adb6d8c6 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -128,15 +128,16 @@ 0x8100 0 0 0x01f8 0 0x0001 /* downstream I/O */ 0x8200 0 0x0100 0x0100 0 0x00f0>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = <0 123 0x04>; + interrupts = ; + interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + clocks = <&clks 144>, <&clks 206>, <&clks 189>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; status = "disabled"; }; -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/8] PCI: imx6: add support for MSI
This patch adds support for Message Signaled Interrupts in the
imx6-pcie driver.
Signed-off-by: Harro Haan
Signed-off-by: Juergen Beisert
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-imx6.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 4c20fc4795e5..41008b7804f9 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "pcie-designware.h"
@@ -314,6 +315,13 @@ static int imx6_pcie_wait_for_link(struct pcie_port *pp)
return 0;
}
+static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+
+ return dw_handle_msi_irq(pp);
+}
+
static int imx6_pcie_start_link(struct pcie_port *pp)
{
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
@@ -388,6 +396,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
dw_pcie_setup_rc(pp);
imx6_pcie_start_link(pp);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ dw_pcie_msi_init(pp);
}
static void imx6_pcie_reset_phy(struct pcie_port *pp)
@@ -477,6 +488,22 @@ static int imx6_add_pcie_port(struct pcie_port *pp,
{
int ret;
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
+ if (pp->msi_irq <= 0) {
+ dev_err(&pdev->dev, "failed to get MSI irq\n");
+ return -ENODEV;
+ }
+
+ ret = devm_request_irq(&pdev->dev, pp->msi_irq,
+ imx6_pcie_msi_handler,
+ IRQF_SHARED, "mx6-pcie-msi", pp);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request MSI irq\n");
+ return -ENODEV;
+ }
+ }
+
pp->root_bus_nr = -1;
pp->ops = &imx6_pcie_host_ops;
--
1.9.0
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[PATCH 6/8] PCI: imx6: rip out optional (and unused) irqs
They are dropped with the new binding.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-imx6.c | 42 --
1 file changed, 42 deletions(-)
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 259a73687526..4c20fc4795e5 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -32,9 +32,6 @@
struct imx6_pcie {
int reset_gpio;
- int power_on_gpio;
- int wake_up_gpio;
- int disable_gpio;
struct clk *pcie_bus;
struct clk *pcie_phy;
struct clk *pcie;
@@ -230,9 +227,6 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port
*pp)
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
int ret;
- if (gpio_is_valid(imx6_pcie->power_on_gpio))
- gpio_set_value(imx6_pcie->power_on_gpio, 1);
-
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
@@ -531,42 +525,6 @@ static int __init imx6_pcie_probe(struct platform_device
*pdev)
}
}
- imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
- if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
- ret = devm_gpio_request_one(&pdev->dev,
- imx6_pcie->power_on_gpio,
- GPIOF_OUT_INIT_LOW,
- "PCIe power enable");
- if (ret) {
- dev_err(&pdev->dev, "unable to get power-on gpio\n");
- return ret;
- }
- }
-
- imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
- if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
- ret = devm_gpio_request_one(&pdev->dev,
- imx6_pcie->wake_up_gpio,
- GPIOF_IN,
- "PCIe wake up");
- if (ret) {
- dev_err(&pdev->dev, "unable to get wake-up gpio\n");
- return ret;
- }
- }
-
- imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
- if (gpio_is_valid(imx6_pcie->disable_gpio)) {
- ret = devm_gpio_request_one(&pdev->dev,
- imx6_pcie->disable_gpio,
- GPIOF_OUT_INIT_HIGH,
- "PCIe disable endpoint");
- if (ret) {
- dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
- return ret;
- }
- }
-
/* Fetch clocks */
imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
if (IS_ERR(imx6_pcie->pcie_phy)) {
--
1.9.0
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[PATCH 2/8] PCI: designware: split Exynos and i.MX bindings
The glue around the core designware IP is significantly
different between the Exynos and i.MX implementation,
which is reflected in the DT bindings.
This changes the i.MX6 binding to reuse as much as
possible from the common designware binding and
removes old cruft.
I removed the optional GPIOs with the following reasoning:
- disable-gpio: endpoint specific GPIO, not currently
wired up in any code. Should be handled by the PCI device
driver, not the host controller driver.
- wake-up-gpio: same as above.
- power-on-gpio: No user in any upstream DT. This should
be handled by a regulator which shouldn't be controlled
by the host driver, but rather by the PCI device driver.
Signed-off-by: Lucas Stach
---
.../devicetree/bindings/pci/designware-pcie.txt| 74 ++
.../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 38 +++
.../bindings/pci/samsung,exynos5440-pcie.txt | 65 +++
3 files changed, 109 insertions(+), 68 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
create mode 100644
Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13ff062..228b37684305 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -1,15 +1,7 @@
* Synopsys Designware PCIe interface
Required properties:
-- compatible: should contain "snps,dw-pcie" to identify the
- core, plus an identifier for the specific instance, such
- as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
-- reg: base addresses and lengths of the pcie controller,
- the phy controller, additional register for the phy controller.
-- interrupts: interrupt values for level interrupt,
- pulse interrupt, special interrupt.
-- clocks: from common clock binding: handle to pci clock.
-- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
+- compatible: should contain "snps,dw-pcie" to identify the core.
- #address-cells: set to <3>
- #size-cells: set to <2>
- device_type: set to "pci"
@@ -19,65 +11,11 @@ Required properties:
to define the mapping of the PCIe interface to interrupt
numbers.
- num-lanes: number of lanes to use
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - "pcie"
+ - "pcie_bus"
Optional properties:
- reset-gpio: gpio pin number of power good signal
-
-Optional properties for fsl,imx6q-pcie
-- power-on-gpio: gpio pin number of power-enable signal
-- wake-up-gpio: gpio pin number of incoming wakeup signal
-- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
-
-Example:
-
-SoC specific DT Entry:
-
- pcie@29 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x29 0x1000
- 0x27 0x1000
- 0x271000 0x40>;
- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x0800 0 0x4000 0x4000 0 0x1000 /*
configuration space */
- 0x8100 0 0 0x40001000 0 0x0001 /*
downstream I/O */
- 0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /*
non-prefetchable memory */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 53>;
- num-lanes = <4>;
- };
-
- pcie@2a {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a 0x1000
- 0x272000 0x1000
- 0x271040 0x40>;
- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
- clocks = <&clock 29>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x0800 0 0x6000 0x6000 0 0x1000 /*
configuration space */
- 0x8100 0 0 0x60001000 0 0x0001 /*
downstream I/O */
- 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /*
non-prefetchable memory */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 56>;
- num-lanes = <4>;
- };
-
-Board specific DT Entry:
-
- pcie@29 {
- reset-gpio = <&pin_ct
[PATCH 4/8] PCI: imx6: use new clock names
As defined in the new binding.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-imx6.c | 74 ++---
1 file changed, 29 insertions(+), 45 deletions(-)
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index ee082509b0ba..71730bbcd9a2 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -35,10 +35,9 @@ struct imx6_pcie {
int power_on_gpio;
int wake_up_gpio;
int disable_gpio;
- struct clk *lvds_gate;
- struct clk *sata_ref_100m;
- struct clk *pcie_ref_125m;
- struct clk *pcie_axi;
+ struct clk *pcie_bus;
+ struct clk *pcie_phy;
+ struct clk *pcie;
struct pcie_portpp;
struct regmap *iomuxc_gpr;
void __iomem*mem_base;
@@ -239,28 +238,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port
*pp)
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
- ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
+ ret = clk_prepare_enable(imx6_pcie->pcie_phy);
if (ret) {
- dev_err(pp->dev, "unable to enable sata_ref_100m\n");
- goto err_sata_ref;
+ dev_err(pp->dev, "unable to enable pcie_phy clock\n");
+ goto err_pcie_phy;
}
- ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
+ ret = clk_prepare_enable(imx6_pcie->pcie_bus);
if (ret) {
- dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
- goto err_pcie_ref;
+ dev_err(pp->dev, "unable to enable pcie_bus clock\n");
+ goto err_pcie_bus;
}
- ret = clk_prepare_enable(imx6_pcie->lvds_gate);
+ ret = clk_prepare_enable(imx6_pcie->pcie);
if (ret) {
- dev_err(pp->dev, "unable to enable lvds_gate\n");
- goto err_lvds_gate;
- }
-
- ret = clk_prepare_enable(imx6_pcie->pcie_axi);
- if (ret) {
- dev_err(pp->dev, "unable to enable pcie_axi\n");
- goto err_pcie_axi;
+ dev_err(pp->dev, "unable to enable pcie clock\n");
+ goto err_pcie;
}
/* allow the clocks to stabilize */
@@ -274,13 +267,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port
*pp)
}
return 0;
-err_pcie_axi:
- clk_disable_unprepare(imx6_pcie->lvds_gate);
-err_lvds_gate:
- clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
-err_pcie_ref:
- clk_disable_unprepare(imx6_pcie->sata_ref_100m);
-err_sata_ref:
+err_pcie:
+ clk_disable_unprepare(imx6_pcie->pcie_bus);
+err_pcie_bus:
+ clk_disable_unprepare(imx6_pcie->pcie_phy);
+err_pcie_phy:
return ret;
}
@@ -583,32 +574,25 @@ static int __init imx6_pcie_probe(struct platform_device
*pdev)
}
/* Fetch clocks */
- imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
- if (IS_ERR(imx6_pcie->lvds_gate)) {
- dev_err(&pdev->dev,
- "lvds_gate clock select missing or invalid\n");
- return PTR_ERR(imx6_pcie->lvds_gate);
- }
-
- imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
- if (IS_ERR(imx6_pcie->sata_ref_100m)) {
+ imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
+ if (IS_ERR(imx6_pcie->pcie_phy)) {
dev_err(&pdev->dev,
- "sata_ref_100m clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->sata_ref_100m);
+ "pcie_phy clock source missing or invalid\n");
+ return PTR_ERR(imx6_pcie->pcie_phy);
}
- imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
- if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
+ imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
+ if (IS_ERR(imx6_pcie->pcie_bus)) {
dev_err(&pdev->dev,
- "pcie_ref_125m clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_ref_125m);
+ "pcie_bus clock source missing or invalid\n");
+ return PTR_ERR(imx6_pcie->pcie_bus);
}
- imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
- if (IS_ERR(imx6_pcie->pcie_axi)) {
+ imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
+ if (IS_ERR(imx6_pcie->pcie)) {
dev_err(&pdev->dev,
- "pcie_axi clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_axi);
+ "pcie clock source missing or invalid\n");
+ return PTR_ERR(imx6_pcie->pcie);
}
Re: [PATCH v2 0/6] PCI irq mapping fixes and cleanups
Friendly ping. Bjorn could you please pick the patches labeled "PCI: ..." up? Both the Tegra and i.MX dts changes are already queued up for 3.15 and I think all patches gathered enough acks and tested-bys for this to be low risk. Regards, Lucas Am Mittwoch, den 05.03.2014, 14:25 +0100 schrieb Lucas Stach: > This series cleans up the PCI irq mapping for all > the ARM PCI host drivers, so they handle it in the > way defined in the common PCI bindings. > > I've worked in all the feedback I received on the first > round of this series and left out the i.MX pcie driver > changes, as these need more work includig breaking > of the existing binding, which I'll send as a separate > series. > > Lucas Stach (6): > ARM: dts: tegra: add PCIe interrupt mapping properties > PCI: tegra: use new OF interrupt mapping when possible > PCI: rcar: use new OF interrupt mapping when possible > ARM: dts: exynos5440: fix PCIe interrupt mapping > ARM: dts: imx6: add PCIe interrupt mapping properties > PCI: designware: use new OF interrupt mapping when possible > > .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 8 > arch/arm/boot/dts/exynos5440.dtsi| 6 -- > arch/arm/boot/dts/imx6qdl.dtsi | 8 > arch/arm/boot/dts/tegra20.dtsi | 4 > arch/arm/boot/dts/tegra30.dtsi | 4 > drivers/pci/host/pci-rcar-gen2.c | 12 > +--- > drivers/pci/host/pci-tegra.c | 7 ++- > drivers/pci/host/pcie-designware.c | 12 > +--- > 8 files changed, 52 insertions(+), 9 deletions(-) > -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 49/75] ARM: l2c: fix register naming
* Russell King [140328 08:22]: > We have a mixture of different devices with different register layouts, > but we group all the bits together in an opaque mess. Split them out > into those which are L2C-310 specific and ones which refer to earlier > devices. Provide full auxiliary control register definitions. > > Signed-off-by: Russell King Acked-by: Tony Lindgren -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 51/75] ARM: l2c: remove platforms/SoCs setting early BRESP
* Russell King [140328 08:22]: > Since we now automatically enable early BRESP in core L2C-310 code when > we detect a Cortex-A9, we don't need platforms/SoCs to set this bit > explicitly. Instead, they should seek to preserve the value of bit 30 > in the auxiliary control register. > > Signed-off-by: Russell King Acked-by: Tony Lindgren -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 56/75] ARM: l2c: exynos: remove cache size override
Signed-off-by: Russell King
---
arch/arm/mach-exynos/common.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index cd53b72449a0..0d19a1b0444e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -45,9 +45,6 @@
#include "common.h"
#include "regs-pmu.h"
-#define L2_AUX_VAL 0x3c470001
-#define L2_AUX_MASK 0xc200
-
static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
@@ -400,7 +397,7 @@ static int __init exynos4_l2x0_cache_init(void)
{
int ret;
- ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
+ ret = l2x0_of_init(0x3c41, 0xc20f);
if (ret)
return ret;
--
1.8.3.1
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[PATCH 2/3] clocksource: exynos_mct: Change exynos4_mct_tick_clear return type to void
Return value of exynos4_mct_tick_clear() was never checked so it can
be safely changed to void.
Signed-off-by: Krzysztof Kozlowski
---
drivers/clocksource/exynos_mct.c |8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 0b49b09dd1a9..2ac7d228743a 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -376,15 +376,11 @@ static inline void exynos4_tick_set_mode(enum
clock_event_mode mode,
}
}
-static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
/* Clear the MCT tick interrupt */
- if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
- return 1;
- }
-
- return 0;
}
static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
--
1.7.9.5
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[PATCH 3/3] clocksource: exynos_mct: Fix too early ISR fire up on wrong CPU
After hotplugging CPU1 the first call of interrupt handler for CPU1
oneshot timer was called on CPU0 because it fired up before setting IRQ
affinity. Affected are SoCs where Multi Core Timer interrupts are shared
(SPI), e.g. Exynos 4210.
During setup of the MCT timers the clock event device should be
registered after setting the affinity for interrupt. This will prevent
starting the timer too early.
Additionally, if clock event device has interrupt set up, the
clockevents_config_and_register() will also set the affinity for it.
Signed-off-by: Krzysztof Kozlowski
Cc:
---
drivers/clocksource/exynos_mct.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 2ac7d228743a..f9c9a1d41f2a 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -418,8 +418,6 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
evt->set_mode = exynos4_tick_set_mode;
evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
evt->rating = 450;
- clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
- 0xf, 0x7fff);
exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
@@ -435,6 +433,8 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
} else {
enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
+ clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
+ 0xf, 0x7fff);
return 0;
}
--
1.7.9.5
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[PATCH 1/3] clocksource: exynos_mct: Fix stall after CPU hotplugging
Fix stall after hotplugging CPU1. Affected are SoCs where Multi Core Timer
interrupts are shared (SPI), e.g. Exynos 4210. The stall was a result of
starting the CPU1 local timer not in L1 timer but in L0 (which is used
by CPU0).
Trigger:
$ echo 0 > /sys/bus/cpu/devices/cpu1/online && echo 1 >
/sys/bus/cpu/devices/cpu1/online
Stall information:
[ 530.045259] INFO: rcu_preempt detected stalls on CPUs/tasks:
[ 530.045618] 1: (6 GPs behind) idle=6d0/0/0 softirq=369/369
[ 530.050987] (detected by 0, t=6589 jiffies, g=33, c=32, q=0)
[ 530.056721] Task dump for CPU 1:
[ 530.059928] swapper/1 R running 0 0 1 0x1000
[ 530.066377] [] (__schedule+0x414/0x9b4) from []
(rcu_idle_enter+0x18/0x38)
[ 530.074955] [] (rcu_idle_enter+0x18/0x38) from []
(cpu_startup_entry+0x60/0x3bc)
[ 530.084069] [] (cpu_startup_entry+0x60/0x3bc) from []
(secondary_start_kernel+0x164/0x1a0)
[ 530.094029] [] (secondary_start_kernel+0x164/0x1a0) from
[<40517244>] (0x40517244)
The timers for CPU1 were missed:
[ 591.668436] cpu: 1
[ 591.670430] clock 0:
[ 591.672691] .base: c0ab7750
[ 591.676160] .index: 0
[ 591.679025] .resolution: 1 nsecs
[ 591.682404] .get_time: ktime_get
[ 591.685970] .offset: 0 nsecs
[ 591.689349] active timers:
[ 591.692045] #0: , hrtimer_wakeup, S:01
[ 591.696759] # expires at 454687834257-454687884257 nsecs [in -136770537232
to -136770487232 nsecs]
And the event_handler for next event was wrong:
[ 591.917120] Tick Device: mode: 1
[ 591.920676] Per CPU device: 0
[ 591.923621] Clock Event Device: mct_tick0
[ 591.927623] max_delta_ns: 178956969027
[ 591.931613] min_delta_ns: 1249
[ 591.934913] mult: 51539608
[ 591.938557] shift: 32
[ 591.941681] mode: 3
[ 591.944724] next_event: 59502500 nsecs
[ 591.949227] set_next_event: exynos4_tick_set_next_event
[ 591.954522] set_mode: exynos4_tick_set_mode
[ 591.959296] event_handler: hrtimer_interrupt
[ 591.963730] retries:0
[ 591.966761]
[ 591.968245] Tick Device: mode: 0
[ 591.971801] Per CPU device: 1
[ 591.974746] Clock Event Device: mct_tick1
[ 591.978750] max_delta_ns: 178956969027
[ 591.982739] min_delta_ns: 1249
[ 591.986037] mult: 51539608
[ 591.989681] shift: 32
[ 591.992806] mode: 3
[ 591.995848] next_event: 45368500 nsecs
[ 592.000353] set_next_event: exynos4_tick_set_next_event
[ 592.005648] set_mode: exynos4_tick_set_mode
[ 592.010421] event_handler: tick_handle_periodic
[ 592.015115] retries:0
[ 592.018145]
After turning off the CPU1, the MCT L1 local timer was disabled but the
interrupt was not cleared. Turning on the CPU1 enabled the IRQ
with setup_irq() but, before setting affinity to CPU1, the pending L1 timer
interrupt was processed by CPU0 in exynos4_mct_tick_isr().
The ISR then called event handler which set up the next timer event for
current CPU (CPU0). Therefore the MCT L1 timer wasn't actually started.
Fix the stall by:
1. Setting next timer event not on current CPU but on the CPU indicated
by cpumask in 'clock_event_device'.
2. Clearing the timer interrupt upon stopping the local timer.
The patch also moves around the call to exynos4_mct_tick_stop() but this
is done only for the code readability as it is not essential for the fix.
Signed-off-by: Krzysztof Kozlowski
Cc:
---
drivers/clocksource/exynos_mct.c | 33 -
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 48f76bc05da0..0b49b09dd1a9 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -339,7 +339,14 @@ static void exynos4_mct_tick_start(unsigned long cycles,
static int exynos4_tick_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
- struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
+ /*
+* In case of hotplugging non-boot CPU, the set_next_event could be
+* called on CPU0 by ISR before IRQ affinity is set to proper CPU.
+* Thus for accessing proper MCT Lx timer, 'per_cpu' for cpumask
+* in event must be used instead of 'this_cpu_ptr'.
+*/
+ struct mct_clock_event_device *mevt = &per_cpu(percpu_mct_tick,
+ cpumask_first(evt->cpumask));
exynos4_mct_tick_start(cycles, mevt);
@@ -371,23 +378,13 @@ static inline void exynos4_tick_set_mode(enum
clock_event_mode mode,
static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
- struct clock_event_device *evt = &mevt->evt;
-
- /*
-* This is for supporting oneshot mode.
-* Mct would generate interrupt periodically
-* without explicit stopping.
-*/
- if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
- exy
[PATCH v3 12/12] ARM: dts: exynos4412-trats2: enable exynos/fimd node
The patch changes fimd node status to OK.
Signed-off-by: Andrzej Hajda
---
arch/arm/boot/dts/exynos4412-trats2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index f7070e9..53c717b 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -577,6 +577,10 @@
};
};
+ fimd@11c0 {
+ status = "okay";
+ };
+
camera {
pinctrl-0 = <&cam_port_b_clk_active>;
pinctrl-names = "default";
--
1.8.3.2
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[PATCH v3 08/12] ARM: dts: exynos4: add MIPI DSI Master node
This is a common part of DSI node for all Exynos4 boards.
Signed-off-by: Andrzej Hajda
---
arch/arm/boot/dts/exynos4.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 08452e1..3d14cdb 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -104,6 +104,20 @@
reg = <0x1001 0x400>;
};
+ dsi_0: dsi@11C8 {
+ compatible = "samsung,exynos4210-mipi-dsi";
+ reg = <0x11C8 0x1>;
+ interrupts = <0 79 0>;
+ samsung,power-domain = <&pd_lcd0>;
+ phys = <&mipi_phy 1>;
+ phy-names = "dsim";
+ clocks = <&clock 286>, <&clock 143>;
+ clock-names = "bus_clk", "pll_clk";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
camera {
compatible = "samsung,fimc", "simple-bus";
status = "disabled";
--
1.8.3.2
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[PATCH v3 01/12] drm/mipi_dsi: add flags to DSI messages
This patch adds flags field to mipi_dsi_msg structure and two flags:
- MIPI_DSI_MSG_REQ_ACK - request ACK from peripheral for given message,
- MIPI_DSI_MSG_USE_LPM - use Low Power Mode to transmit message.
The first flag is usually helpful during DSI diagnostic, the second
flag is required by some peripherals during configuration phase.
Signed-off-by: Andrzej Hajda
---
include/drm/drm_mipi_dsi.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index d32628a..7209df1 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -17,6 +17,11 @@
struct mipi_dsi_host;
struct mipi_dsi_device;
+/* request ACK from peripheral */
+#define MIPI_DSI_MSG_REQ_ACK BIT(0)
+/* use Low Power Mode to transmit message */
+#define MIPI_DSI_MSG_USE_LPM BIT(1)
+
/**
* struct mipi_dsi_msg - read/write DSI buffer
* @channel: virtual channel id
@@ -29,6 +34,7 @@ struct mipi_dsi_device;
struct mipi_dsi_msg {
u8 channel;
u8 type;
+ u16 flags;
size_t tx_len;
const void *tx_buf;
--
1.8.3.2
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[PATCH v3 11/12] ARM: dts: exynos4210-trats: enable exynos/fimd node
The patch changes fimd node status to OK.
Signed-off-by: Andrzej Hajda
---
arch/arm/boot/dts/exynos4210-trats.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 996c7e3..02c6768 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -410,6 +410,10 @@
};
};
+ fimd@11c0 {
+ status = "okay";
+ };
+
camera {
pinctrl-names = "default";
pinctrl-0 = <>;
--
1.8.3.2
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[PATCH v3 06/12] panel/s6e8aa0: add DT bindings
The patch adds bindings for s6e8aa0 panel.
Bindings describes panel resources, boot delays,
display timings, orientation and physical size.
Signed-off-by: Andrzej Hajda
---
v2
- removed samsung prefix from panel physical size props,
- renamed file to follow convention of panel bindings
v3
- reset-gpio renamed to reset-gpios
- added video interfaces bindings
---
.../devicetree/bindings/panel/samsung,s6e8aa0.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt
b/Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt
new file mode 100644
index 000..e7ee988
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt
@@ -0,0 +1,56 @@
+Samsung S6E8AA0 AMOLED LCD 5.3 inch panel
+
+Required properties:
+ - compatible: "samsung,s6e8aa0"
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin
+ - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+ - power-on-delay: delay after turning regulators on [ms]
+ - reset-delay: delay after reset sequence [ms]
+ - init-delay: delay after initialization sequence [ms]
+ - panel-width-mm: physical panel width [mm]
+ - panel-height-mm: physical panel height [mm]
+ - flip-horizontal: boolean to flip image horizontally
+ - flip-vertical: boolean to flip image vertically
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [2]. This
+node should describe panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel {
+ compatible = "samsung,s6e8aa0";
+ reg = <0>;
+ vdd3-supply = <&vcclcd_reg>;
+ vci-supply = <&vlcd_reg>;
+ reset-gpios = <&gpy4 5 0>;
+ power-on-delay= <50>;
+ reset-delay = <100>;
+ init-delay = <100>;
+ panel-width-mm = <58>;
+ panel-height-mm = <103>;
+ flip-horizontal;
+ flip-vertical;
+
+ display-timings {
+ timing0: timing-0 {
+ clock-frequency = <57153600>;
+ hactive = <720>;
+ vactive = <1280>;
+ hfront-porch = <5>;
+ hback-porch = <5>;
+ hsync-len = <5>;
+ vfront-porch = <13>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+ };
--
1.8.3.2
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[PATCH v3 09/12] ARM: dts: exynos4210-trats: add panel node
The patch adds s6e8aa0 panel node for trats.
It adds also trats specific properties for DSI.
Signed-off-by: Andrzej Hajda
---
arch/arm/boot/dts/exynos4210-trats.dts | 57 ++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 63cc571..996c7e3 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -353,6 +353,63 @@
};
};
+ dsi_0: dsi@11C8 {
+ vddcore-supply = <&vusb_reg>;
+ vddio-supply = <&vmipi_reg>;
+ samsung,pll-clock-frequency = <2400>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ samsung,burst-clock-frequency =
<5>;
+ samsung,esc-clock-frequency =
<2000>;
+ };
+ };
+ };
+
+ panel@0 {
+ reg = <0>;
+ compatible = "samsung,s6e8aa0";
+ vdd3-supply = <&vcclcd_reg>;
+ vci-supply = <&vlcd_reg>;
+ reset-gpios = <&gpy4 5 0>;
+ power-on-delay= <50>;
+ reset-delay = <100>;
+ init-delay = <100>;
+ flip-horizontal;
+ flip-vertical;
+ panel-width-mm = <58>;
+ panel-height-mm = <103>;
+
+ display-timings {
+ timing-0 {
+ clock-frequency = <57153600>;
+ hactive = <720>;
+ vactive = <1280>;
+ hfront-porch = <5>;
+ hback-porch = <5>;
+ hsync-len = <5>;
+ vfront-porch = <13>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+
+ port {
+ dsi_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+
camera {
pinctrl-names = "default";
pinctrl-0 = <>;
--
1.8.3.2
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[PATCH v3 02/12] drm/mipi_dsi: create dsi devices only for nodes with reg property
MIPI DSI host node can contain child nodes which are not DSI devices.
Checking for existence of reg property can be used to distinguish such nodes.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/drm_mipi_dsi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index b155ee2..09821f4 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -142,8 +142,12 @@ int mipi_dsi_host_register(struct mipi_dsi_host *host)
{
struct device_node *node;
- for_each_available_child_of_node(host->dev->of_node, node)
+ for_each_available_child_of_node(host->dev->of_node, node) {
+ /* skip nodes without reg property */
+ if (!of_find_property(node, "reg", NULL))
+ continue;
of_mipi_dsi_device_add(host, node);
+ }
return 0;
}
--
1.8.3.2
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[PATCH v3 07/12] drm/panel: add S6E8AA0 driver
The patch adds MIPI-DSI based S6E8AA0 AMOLED LCD panel driver.
Driver uses mipi_dsi bus to communicate with panel and exposes drm_panel
interface.
Signed-off-by: Andrzej Hajda
---
v2
- added bus error handling,
- set maxmimum DSI packet size on init,
- removed unsupported brightness drm_panel callbacks,
- minor improvements
v3
- switched to gpiod framework,
- minor fixes in error handling
---
drivers/gpu/drm/panel/Kconfig |7 +
drivers/gpu/drm/panel/Makefile|1 +
drivers/gpu/drm/panel/panel-s6e8aa0.c | 1069 +
3 files changed, 1077 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e8aa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index f0fcb62..4ec874d 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -23,4 +23,11 @@ config DRM_PANEL_LD9040
select SPI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E8AA0
+ tristate "S6E8AA0 DSI video mode panel"
+ depends on DRM && DRM_PANEL
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4f7dfce..8b92921 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
+obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e8aa0.c
b/drivers/gpu/drm/panel/panel-s6e8aa0.c
new file mode 100644
index 000..35941d2
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e8aa0.c
@@ -0,0 +1,1069 @@
+/*
+ * MIPI-DSI based s6e8aa0 AMOLED LCD 5.3 inch panel driver.
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ *
+ * Inki Dae,
+ * Donghwa Lee,
+ * Joongmock Shin
+ * Eunchul Kim
+ * Tomasz Figa
+ * Andrzej Hajda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+#define LDI_MTP_LENGTH 24
+#define GAMMA_LEVEL_NUM25
+#define GAMMA_TABLE_LEN26
+
+#define PANELCTL_SS_MASK (1 << 5)
+#define PANELCTL_SS_1_800 (0 << 5)
+#define PANELCTL_SS_800_1 (1 << 5)
+#define PANELCTL_GTCON_MASK(7 << 2)
+#define PANELCTL_GTCON_110 (6 << 2)
+#define PANELCTL_GTCON_111 (7 << 2)
+
+#define PANELCTL_CLK1_CON_MASK (7 << 3)
+#define PANELCTL_CLK1_000 (0 << 3)
+#define PANELCTL_CLK1_001 (1 << 3)
+#define PANELCTL_CLK2_CON_MASK (7 << 0)
+#define PANELCTL_CLK2_000 (0 << 0)
+#define PANELCTL_CLK2_001 (1 << 0)
+
+#define PANELCTL_INT1_CON_MASK (7 << 3)
+#define PANELCTL_INT1_000 (0 << 3)
+#define PANELCTL_INT1_001 (1 << 3)
+#define PANELCTL_INT2_CON_MASK (7 << 0)
+#define PANELCTL_INT2_000 (0 << 0)
+#define PANELCTL_INT2_001 (1 << 0)
+
+#define PANELCTL_BICTL_CON_MASK(7 << 3)
+#define PANELCTL_BICTL_000 (0 << 3)
+#define PANELCTL_BICTL_001 (1 << 3)
+#define PANELCTL_BICTLB_CON_MASK (7 << 0)
+#define PANELCTL_BICTLB_000(0 << 0)
+#define PANELCTL_BICTLB_001(1 << 0)
+
+#define PANELCTL_EM_CLK1_CON_MASK (7 << 3)
+#define PANELCTL_EM_CLK1_110 (6 << 3)
+#define PANELCTL_EM_CLK1_111 (7 << 3)
+#define PANELCTL_EM_CLK1B_CON_MASK (7 << 0)
+#define PANELCTL_EM_CLK1B_110 (6 << 0)
+#define PANELCTL_EM_CLK1B_111 (7 << 0)
+
+#define PANELCTL_EM_CLK2_CON_MASK (7 << 3)
+#define PANELCTL_EM_CLK2_110 (6 << 3)
+#define PANELCTL_EM_CLK2_111 (7 << 3)
+#define PANELCTL_EM_CLK2B_CON_MASK (7 << 0)
+#define PANELCTL_EM_CLK2B_110 (6 << 0)
+#define PANELCTL_EM_CLK2B_111 (7 << 0)
+
+#define PANELCTL_EM_INT1_CON_MASK (7 << 3)
+#define PANELCTL_EM_INT1_000 (0 << 3)
+#define PANELCTL_EM_INT1_001 (1 << 3)
+#define PANELCTL_EM_INT2_CON_MASK (7 << 0)
+#define PANELCTL_EM_INT2_000 (0 << 0)
+#define PANELCTL_EM_INT2_001 (1 << 0)
+
+#define AID_DISABLE(0x4)
+#define AID_1 (0x5)
+#define AID_2 (0x6)
+#define AID_3 (0x7)
+
+typedef u8 s6e8aa0_gamma_table[GAMMA_TABLE_LEN];
+
+struct s6e8aa0_variant {
+ u8 version;
+ const s6e8aa0_gamma_table *gamma_tables;
+};
+
+struct s6e8aa0 {
+ struct device *dev;
+ struct drm_panel panel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc *reset_gpio;
+ u32 power_on_delay;
+
[PATCH v3 03/12] drm/exynos: disallow fbdev initialization if no device is connected
This patch adds explicit check if there is a connector with
connected status before fbdev initialization. It prevents creation
of default fbdev 1024x768 which is unusable on panels with bigger resolutions.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index e7c2f2d..e09449a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -237,6 +237,24 @@ static struct drm_fb_helper_funcs
exynos_drm_fb_helper_funcs = {
.fb_probe = exynos_drm_fbdev_create,
};
+bool exynos_drm_fbdev_is_anything_connected(struct drm_device *dev)
+{
+ struct drm_connector *connector;
+ bool ret = false;
+
+ mutex_lock(&dev->mode_config.mutex);
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ if (connector->status != connector_status_connected)
+ continue;
+
+ ret = true;
+ break;
+ }
+ mutex_unlock(&dev->mode_config.mutex);
+
+ return ret;
+}
+
int exynos_drm_fbdev_init(struct drm_device *dev)
{
struct exynos_drm_fbdev *fbdev;
@@ -248,6 +266,9 @@ int exynos_drm_fbdev_init(struct drm_device *dev)
if (!dev->mode_config.num_crtc || !dev->mode_config.num_connector)
return 0;
+ if (!exynos_drm_fbdev_is_anything_connected(dev))
+ return 0;
+
fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
if (!fbdev)
return -ENOMEM;
--
1.8.3.2
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[PATCH v3 10/12] ARM: dts: exynos4412-trats2: add panel node
The patch adds s6e8aa0 panel node for trats2.
It adds also trats2 specific properties for DSI
and regulator required by panel.
Signed-off-by: Andrzej Hajda
---
arch/arm/boot/dts/exynos4412-trats2.dts | 66 +
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 4f851cc..f7070e9 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -71,6 +71,15 @@
enable-active-high;
};
+ lcd_vdd3_reg: voltage-regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_VDD_2.2V";
+ regulator-min-microvolt = <220>;
+ regulator-max-microvolt = <220>;
+ gpio = <&gpc0 1 0>;
+ enable-active-high;
+ };
+
/* More to come */
};
@@ -511,6 +520,63 @@
};
};
+ dsi_0: dsi@11C8 {
+ vddcore-supply = <&ldo8_reg>;
+ vddio-supply = <&ldo10_reg>;
+ samsung,pll-clock-frequency = <2400>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ samsung,burst-clock-frequency =
<5>;
+ samsung,esc-clock-frequency =
<2000>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "samsung,s6e8aa0";
+ reg = <0>;
+ vdd3-supply = <&lcd_vdd3_reg>;
+ vci-supply = <&ldo25_reg>;
+ reset-gpios = <&gpy4 5 0>;
+ power-on-delay= <50>;
+ reset-delay = <100>;
+ init-delay = <100>;
+ flip-horizontal;
+ flip-vertical;
+ panel-width-mm = <58>;
+ panel-height-mm = <103>;
+
+ display-timings {
+ timing-0 {
+ clock-frequency = <0>;
+ hactive = <720>;
+ vactive = <1280>;
+ hfront-porch = <5>;
+ hback-porch = <5>;
+ hsync-len = <5>;
+ vfront-porch = <13>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+
+ port {
+ dsi_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+
camera {
pinctrl-0 = <&cam_port_b_clk_active>;
pinctrl-names = "default";
--
1.8.3.2
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[PATCH v3 05/12] drm/exynos: add DSIM driver
The patch adds driver for Exynos DSI master (DSIM). It is a platform driver
which is registered as exynos_drm_display sub-driver of exynos_drm framework
and implements DRM encoder/connector pair.
It is also MIPI-DSI host driver and provides DSI bus for panels.
It interacts with its panel(s) using drm_panel framework.
Signed-off-by: Andrzej Hajda
---
v2:
- add support for DSI message flags,
- add support for new DT properties,
- remove brightness DRM property,
- corrected PM handlers,
- minor fixes/improvements
v3:
- panel attach/detach moved to connector detect callback,
- improved error handling,
- removed exynos_drm_initialize callback,
- added video interface handling,
- moved dsi clock properties to dsi endpoint
---
drivers/gpu/drm/exynos/Kconfig |9 +
drivers/gpu/drm/exynos/Makefile |1 +
drivers/gpu/drm/exynos/exynos_drm_drv.c | 15 +
drivers/gpu/drm/exynos/exynos_drm_drv.h |1 +
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1525 +++
5 files changed, 1551 insertions(+)
create mode 100644 drivers/gpu/drm/exynos/exynos_drm_dsi.c
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 56f9581..5bf5bca 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -39,6 +39,15 @@ config DRM_EXYNOS_DPI
help
This enables support for Exynos parallel output.
+config DRM_EXYNOS_DSI
+ bool "EXYNOS DRM MIPI-DSI driver support"
+ depends on DRM_EXYNOS
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ default n
+ help
+ This enables support for Exynos MIPI-DSI device.
+
config DRM_EXYNOS_DP
bool "EXYNOS DRM DP driver support"
depends on DRM_EXYNOS && ARCH_EXYNOS
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index babcd52..33ae365 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -12,6 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DMABUF) += exynos_drm_dmabuf.o
exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o
exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)+= exynos_hdmi.o exynos_mixer.o
exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)+= exynos_drm_vidi.o
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 771c87e..2d27ba2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -450,6 +450,12 @@ static int __init exynos_drm_init(void)
goto out_dp;
#endif
+#ifdef CONFIG_DRM_EXYNOS_DSI
+ ret = platform_driver_register(&dsi_driver);
+ if (ret < 0)
+ goto out_dsi;
+#endif
+
#ifdef CONFIG_DRM_EXYNOS_FIMD
ret = platform_driver_register(&fimd_driver);
if (ret < 0)
@@ -566,6 +572,11 @@ out_hdmi:
out_fimd:
#endif
+#ifdef CONFIG_DRM_EXYNOS_DSI
+ platform_driver_unregister(&dsi_driver);
+out_dsi:
+#endif
+
#ifdef CONFIG_DRM_EXYNOS_DP
platform_driver_unregister(&dp_driver);
out_dp:
@@ -613,6 +624,10 @@ static void __exit exynos_drm_exit(void)
platform_driver_unregister(&fimd_driver);
#endif
+#ifdef CONFIG_DRM_EXYNOS_DSI
+ platform_driver_unregister(&dsi_driver);
+#endif
+
#ifdef CONFIG_DRM_EXYNOS_DP
platform_driver_unregister(&dp_driver);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 2d892f3..4c5cf68 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -370,6 +370,7 @@ static inline int exynos_dpi_remove(struct device *dev) {
return 0; }
#endif
extern struct platform_driver dp_driver;
+extern struct platform_driver dsi_driver;
extern struct platform_driver fimd_driver;
extern struct platform_driver hdmi_driver;
extern struct platform_driver mixer_driver;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
new file mode 100644
index 000..697228e
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -0,0 +1,1525 @@
+/*
+ * Samsung SoC MIPI DSI Master driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * Contacts: Tomasz Figa
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "exynos_drm_drv.h"
+
+/* returns true iff both arguments logically differs */
+#define NEQV(a, b) (!(a) ^ !(b))
+
+#define DSIM_STATUS_REG0x0 /* Status register */
+#define DSIM_SWRST_R
[PATCH v3 04/12] exynos/dsim: add DT bindings
The patch adds DT bindings for Exynos DSI Master. DSIM follows rules
for DSI bus host bindings [1].
Properties describes its resources: memory, interrupt, clocks,
phy, regulators, frequencies of clocks and video interfaces.
[1]: Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
Signed-off-by: Andrzej Hajda
---
v2
- added burst and esc clock frequency properties
- add samsung prefix to all frequency props
v3
- reset-gpio changed to reset-gpios property
- added video interface bindings
- properties related to video interface moved to endpoint node
dsim bindings
---
.../devicetree/bindings/video/exynos_dsim.txt | 80 ++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/exynos_dsim.txt
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
new file mode 100644
index 000..33b5730
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -0,0 +1,80 @@
+Exynos MIPI DSI Master
+
+Required properties:
+ - compatible: "samsung,exynos4210-mipi-dsi"
+ - reg: physical base address and length of the registers set for the device
+ - interrupts: should contain DSI interrupt
+ - clocks: list of clock specifiers, must contain an entry for each required
+entry in clock-names
+ - clock-names: should include "bus_clk"and "pll_clk" entries
+ - phys: list of phy specifiers, must contain an entry for each required
+entry in phy-names
+ - phy-names: should include "dsim" entry
+ - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
+ - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
+ - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
+ - #address-cells, #size-cells: should be set respectively to <1> and <0>
+according to DSI host bindings (see MIPI DSI bindings [1])
+
+Optional properties:
+ - samsung,power-domain: a phandle to DSIM power domain node
+
+Child nodes:
+ Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
+
+Video interfaces:
+ Device node can contain video interface port nodes according to [2].
+ The following are properties specific to those nodes:
+
+ port node:
+- reg: (required) can be 0 for input RGB/I80 port or 1 for DSI port;
+
+ endpoint node of DSI port (reg = 1):
+- samsung,burst-clock-frequency: specifies DSI frequency in high-speed
burst
+ mode
+- samsung,esc-clock-frequency: specifies DSI frequency in escape mode
+
+[1]: Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ dsi@11C8 {
+ compatible = "samsung,exynos4210-mipi-dsi";
+ reg = <0x11C8 0x1>;
+ interrupts = <0 79 0>;
+ clocks = <&clock 286>, <&clock 143>;
+ clock-names = "bus_clk", "pll_clk";
+ phys = <&mipi_phy 1>;
+ phy-names = "dsim";
+ vddcore-supply = <&vusb_reg>;
+ vddio-supply = <&vmipi_reg>;
+ samsung,power-domain = <&pd_lcd0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,pll-clock-frequency = <2400>;
+
+ panel@1 {
+ reg = <0>;
+ ...
+ port {
+ panel_ep: endpoint {
+ remote-endpoint = <&dsi_ep>;
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ dsi_ep: endpoint {
+ reg = <0>;
+ samsung,burst-clock-frequency =
<5>;
+ samsung,esc-clock-frequency =
<2000>;
+ remote-endpoint = <&panel_ep>;
+ };
+ };
+ };
+ };
--
1.8.3.2
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[PATCH v3 00/12] Add DSI display support for Exynos based boards
Hi, This patchset adds drivers and bindings to the following devices: - Exynos DSI master, - S6E8AA0 DSI panel, It adds also display support in DTS files for the following boards: - Exynos4210/Trats, - Exynos4412/Trats2. The patchset is based on exynos_drm_next branch. It is the 3rd iteration of the patches, main changes: - based on exynos_drm_next branch, - added video interface bindings between DSI host and slave, it seems to me to be redundand, and I hope when video interface bindings will be stabilized it can become optional, - GPIOs implemented using gpiod framework, - removed controversial stuff (toshiba bridge implementation and arndale support), it will be send in another set of patches Other changes are described in individual patches. Regards Andrzej Andrzej Hajda (12): drm/mipi_dsi: add flags to DSI messages drm/mipi_dsi: create dsi devices only for nodes with reg property drm/exynos: disallow fbdev initialization if no device is connected exynos/dsim: add DT bindings drm/exynos: add DSIM driver panel/s6e8aa0: add DT bindings drm/panel: add S6E8AA0 driver ARM: dts: exynos4: add MIPI DSI Master node ARM: dts: exynos4210-trats: add panel node ARM: dts: exynos4412-trats2: add panel node ARM: dts: exynos4210-trats: enable exynos/fimd node ARM: dts: exynos4412-trats2: enable exynos/fimd node .../devicetree/bindings/panel/samsung,s6e8aa0.txt | 56 + .../devicetree/bindings/video/exynos_dsim.txt | 80 + arch/arm/boot/dts/exynos4.dtsi | 14 + arch/arm/boot/dts/exynos4210-trats.dts | 61 + arch/arm/boot/dts/exynos4412-trats2.dts| 70 + drivers/gpu/drm/drm_mipi_dsi.c |6 +- drivers/gpu/drm/exynos/Kconfig |9 + drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_drv.c| 15 + drivers/gpu/drm/exynos/exynos_drm_drv.h|1 + drivers/gpu/drm/exynos/exynos_drm_dsi.c| 1525 drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 21 + drivers/gpu/drm/panel/Kconfig |7 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-s6e8aa0.c | 1069 ++ include/drm/drm_mipi_dsi.h |6 + 16 files changed, 2941 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt create mode 100644 Documentation/devicetree/bindings/video/exynos_dsim.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_dsi.c create mode 100644 drivers/gpu/drm/panel/panel-s6e8aa0.c -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Enabling uart 3 in arndale
Dear Tomasz,
On 16-Mar-2014, at 6:23 pm, Tomasz Figa wrote:
> Hi,
>
> On 14.03.2014 09:04, armdev wrote:
>> Hi,
>>
>> We are trying to enable the UART3 on COM18 pins of arndale board. The UART3
>> RXD and TXD are on pins 2 and 4 which as per the base board specification is
>> connected as
>>
>> XuRXD3 : UART_3_RXD/GPA1[4] : 2
>> XuTXD3 : UART_3_TXD/GPA1[5] : 4
>>
>> As per the public reference manual of exynos 5250, there is a register
>> GPACON (0x1140_)
>> Setting GPACON |= 0x0010_ should enable the pins, but I am not able to
>> see any output on UART3.
>>
>> Can you please suggest what is the right procedure
>
> The register is GPA1CON and its GPA1CON[4] and [5] bit fields need both to be
> set to 0x2 - see Pad Control chapter of Exynos5250 public datasheet. Also
> GPA1PUD should be reconfigured to disable default pull-down on both pins,
> again you can find details of the register in the datasheet.
>
> Best regards,
> Tomasz
Based on the steps provided, we are still not able to get some output on UART3
simultaneously with UART2.
Can you please help us find out what we are missing.
On the current u-boot, Following was the observation and steps to enable UART3
on arndale
Observations / Questions
——
a) The board has the default UART set to UART2 which is at 0x12c2, while
the include/configs/arndale.h has the UART_OFFSET set to 0x01.
Shouldn’t it be set to 0x2 ?
b) board_uart_init in board/samsung/arndale/arndale.c is configuring all the
uarts,
Clocks would be set properly for all 4 uarts ?
Steps / Code Modified
——
a) GPAICON[4] and [5] set to 0x2 in board/samsung/arndale/arndale.c
b) GPA1PUD [4] and [5] set to 0.
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 9efc355..4fb291e 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -102,12 +102,18 @@ static int board_uart_init(void)
int board_early_init_f(void)
{
int err;
-
+ volatile unsigned int *gpa1con = (volatile unsigned int *)0x11400020;
+ volatile unsigned int *gpa1pud = (volatile unsigned int *)0x11400028;
err = board_uart_init();
if (err) {
debug("UART init failed\n");
return err;
}
+ serial_init_dev(2);
+ serial_setbrg_dev(2);
+ *gpa1con |= 0x0022;
+ *gpa1pud &= 0xf0ff;
+
return err;
}
#endif
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RE: [PATCH v4 1/3] arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Kukjin Kim wrote:
>
>
> Signed-off-by: Kukjin Kim
> Reviewed-by: Thomas Abraham
> Cc: Mark Rutland
> Cc: Catalin Marinas
> ---
>
> Changes since v3:
> - addressed comments from Mark
> : updated reserved memory
> : fixed interrupt trigger for pmu and serial
> - removing 'gh7-pmu' from PMU compatible string
>
> Since the patch 2nd and 3rd are same with previous version I'm not re-
> posting.
>
> arch/arm64/boot/dts/samsung-gh7.dtsi | 134
> ++
> arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 ++
> 2 files changed, 160 insertions(+)
> create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi
> create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dts
>
> diff --git a/arch/arm64/boot/dts/samsung-gh7.dtsi
> b/arch/arm64/boot/dts/samsung-gh7.dtsi
> new file mode 100644
> index 000..d3ab914
> --- /dev/null
> +++ b/arch/arm64/boot/dts/samsung-gh7.dtsi
> @@ -0,0 +1,134 @@
> +/*
> + * SAMSUNG GH7 SoC device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/memreserve/ 0x8000 0x0001;
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = "/amba/uart@12c0";
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x000>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@001 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x001>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@002 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x002>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@003 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x003>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x102>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x103>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + };
> + };
> +
> + gic: interrupt-controller@1C00 {
> + compatible = "arm,cortex-a15-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1C001000 0 0x1000>,/* GIC Dist */
> + <0x0 0x1C002000 0 0x1000>,/* GIC CPU */
> + <0x0 0x1C004000 0 0x2000>,/* GIC VCPU Control
*/
> + <0x0 0x1C006000 0 0x2000>;/* GIC VCPU */
> + interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 13 0xff01>, /* Secure Phys IRQ */
> + <1 14 0xff01>, /* Non-secure Phys IRQ */
> + <1 11 0xff01>, /* Virt IRQ */
> + <1 10 0xff01>; /* Hyp IRQ */
> + };
> +
> + pmu {
> + compatible = "armv8-pmuv3";
> + interrupts
RE: [GIT PULL 1/4] Samsung 3rd cleanup for v3.15
Kukjin Kim wrote: > > The following changes since commit > 19a964644f1e655c3f67d539c1e99a9fbcc4588c: > >ARM: SAMSUNG: remove all custom uncompress.h (2014-03-11 22:05:18 +0900) > > are available in the git repository at: > >git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git > tags/samsung-cleanup-3 > > for you to fetch changes up to 1aa9c483d1be13831bc4e516ce4848d32ac3e944: > >ARM: EXYNOS: Remove hardware.h file (2014-03-21 04:49:03 +0900) > > > Samsung 3rd cleanup for v3.15 > > - Remove in mach-exynos > - Remove invalid code from in mach-s3c24xx > > Note that this is based on previous tags/samsung-cleanup-2 > > > Sachin Kamat (3): >ARM: S3C24XX: Remove invalid code from hardware.h >ARM: SAMSUNG: Remove hardware.h inclusion >ARM: EXYNOS: Remove hardware.h file > > arch/arm/mach-exynos/include/mach/hardware.h | 18 -- > arch/arm/mach-exynos/platsmp.c| 2 -- > arch/arm/mach-s3c24xx/include/mach/hardware.h | 14 +- > arch/arm/plat-samsung/clock.c | 1 - > arch/arm/plat-samsung/devs.c | 2 +- > arch/arm/plat-samsung/init.c | 2 -- > arch/arm/plat-samsung/pm.c| 1 - > arch/arm/plat-samsung/s5p-dev-uart.c | 1 - > 8 files changed, 2 insertions(+), 39 deletions(-) > delete mode 100644 arch/arm/mach-exynos/include/mach/hardware.h Hi, Gentle reminder again ;-) - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 1/2] Samsung 2nd cleanup for v3.15
Kukjin Kim wrote: > > The following changes since commit > d9671ca923445aa870ecc34df3db01dd602d87fc: > >ARM: EXYNOS: Remove uncompress.h (2014-02-24 09:39:18 +0900) > > are available in the git repository at: > >git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git > tags/samsung-cleanup-2 > > for you to fetch changes up to 19a964644f1e655c3f67d539c1e99a9fbcc4588c: > >ARM: SAMSUNG: remove all custom uncompress.h (2014-03-11 22:05:18 +0900) > > > Samsung cleanup-2 for v3.15 > - use generic uncompress.h and remove all custom >uncompress.h in mach-s3c24xx, s3c64xx, s5p64x0, >s5pc100, s5pv210 and plat-samsung directories. > > Note that based on previous tags/samsung-cleanup > > > Heiko Stuebner (2): >ARM: SAMSUNG: use generic uncompress.h >ARM: SAMSUNG: remove all custom uncompress.h > > arch/arm/Kconfig.debug | 4 +- > arch/arm/mach-s3c24xx/include/mach/uncompress.h | 57 > arch/arm/mach-s3c64xx/include/mach/uncompress.h | 31 - > arch/arm/mach-s5p64x0/include/mach/uncompress.h | 34 - > arch/arm/mach-s5pc100/include/mach/uncompress.h | 30 > arch/arm/mach-s5pv210/include/mach/uncompress.h | 28 > arch/arm/plat-samsung/include/plat/uncompress.h | 175 > > 7 files changed, 2 insertions(+), 357 deletions(-) > delete mode 100644 arch/arm/mach-s3c24xx/include/mach/uncompress.h > delete mode 100644 arch/arm/mach-s3c64xx/include/mach/uncompress.h > delete mode 100644 arch/arm/mach-s5p64x0/include/mach/uncompress.h > delete mode 100644 arch/arm/mach-s5pc100/include/mach/uncompress.h > delete mode 100644 arch/arm/mach-s5pv210/include/mach/uncompress.h > delete mode 100644 arch/arm/plat-samsung/include/plat/uncompress.h Hi, Gentle reminder ;-) - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 5/6] Samsung PM updates for v3.15
Kukjin Kim wrote: > > On 03/19/14 13:01, Mike Turquette wrote: > > Quoting Olof Johansson (2014-03-10 19:52:01) > >> On Mon, Mar 10, 2014 at 6:50 PM, Kukjin Kim > wrote: > >>> Olof Johansson wrote: > > >> Hi, > >> > >> I don't see a single cc or acked-by line from Mike Turquette here. > I'll > >> hold > >> off until he's had a chance to take a look at these ones; I suspect > >> they'll be > >> fine since it's mostly code refactoring though. > > > > > > I guess I should have ACKed them too, but it felt kind of strange to > ACK > my > > own patches. ;) > > > > Anyway, for all samsung-clk patches: > > > > Acked-by: Tomasz Figa > > Yeah, self-acking doesn't make much sense. :) > > I'm mostly worried about patches touching other subsystems without > the > other maintainer being aware of it or having reviewed them. As I said, > these mostly look like refactorings but it's still good habit. > > >>> OK, agreed, I think Mike knew about that though. Let's wait for Mike's > >>> response. > >>> > >>> BTW, should I sort out the branch again if Mike gives ack on that? > >> > >> If I hear from Mike that he's OK with it then I can merge it, no need > to rebase. > > > Thanks :-) > > > Acked-by: Mike Turquette > > > It's time. Please pull this [5/6] and "[GIT PULL 6/6] Samsung > clk-s3c24xx updates for v3.15". > Hi Arnd, Olof and Mike, Still I cannot see this in arm-soc. Any problems? - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/17] i2c: deprecate class based instantiation for embedded I2C drivers
On Mon, Feb 10, 2014 at 11:03:54AM +0100, Wolfram Sang wrote: > With I2C, class based instantiation means if a master driver has e.g. > I2C_CLASS_HWMON set, all slave drivers with this class will try to probe a > device using an array of possible addresses and some heuristics. That creates > traffic and needs time, even when nothing is connected. This mechanism is > needed when you do not have another method to describe the slaves. Embedded > I2C > drivers do not need class based instantiation, since there is i2c_board_info > or > devicetree description. Some drivers have the class flags set, though, and it > has spread further over the years. We can't remove the flags directly, because > there might be users out there relying on this feature. So, we add a > deprecation warning if a device is instantiated via class attributes. After > giving some time to switch over, we can then finally remove the class flags > and > gain boot time. > > Patch 1 adds some missing documentation. Patch 2 adds the deprecation feature. > Patches 3+4 are tested on hardware I need. Patches 5-17 are suggestions for > drivers I think could benefit from that. For those, acks are needed before I > will apply them to my tree. If you use a different driver which can also > benefit from this, just send a patch adding the new DEPRECATED flag. > > The series can also be found here: > > git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git > i2c/deprecated_class > > Thanks, > >Wolfram > > > Wolfram Sang (17): > Documentation: i2c: describe devicetree method for instantiating > devices > i2c: add deprecation warning for class based instantiation > i2c: i2c-omap: deprecate class based instantiation > i2c: i2c-at91: deprecate class based instantiation > i2c: i2c-bcm2835: deprecate class based instantiation > i2c: i2c-bfin-twi: deprecate class based instantiation > i2c: i2c-davinci: deprecate class based instantiation > i2c: i2c-designware-platdrv: deprecate class based instantiation > i2c: i2c-mv64xxx: deprecate class based instantiation > i2c: i2c-nomadik: deprecate class based instantiation > i2c: i2c-ocores: deprecate class based instantiation > i2c: i2c-rcar: deprecate class based instantiation > i2c: i2c-s3c2410: deprecate class based instantiation > i2c: i2c-sirf: deprecate class based instantiation > i2c: i2c-stu300: deprecate class based instantiation > i2c: i2c-tegra: deprecate class based instantiation > i2c: i2c-xiic: deprecate class based instantiation I reconsidered and have now applied all patches. That way, all these drivers can be converted to no class based instantiation in one go after some grace period. If it turns out, one driver actually needs it, there is still the grace period left to remove the DEPRECATED flag again. signature.asc Description: Digital signature
