[PATCH 1/5] ARM: dts: Enable RTC node on Origen boards
Enabled RTC node on Origen 4210 and 4412 boards.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts |4
arch/arm/boot/dts/exynos4412-origen.dts |4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 72fb11f7ea21..95efb1189cf0 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -48,6 +48,10 @@
};
};
+ rtc@1007 {
+ status = okay;
+ };
+
tmu@100C {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index e2c0dcab4d81..934fe7ecca7e 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -48,6 +48,10 @@
};
};
+ rtc@1007 {
+ status = okay;
+ };
+
pinctrl@1100 {
keypad_rows: keypad-rows {
samsung,pins = gpx2-0, gpx2-1, gpx2-2;
--
1.7.9.5
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[PATCH 2/5] ARM: dts: Enable watchdog node on Origen boards
Enabled watchdog nodes on Origen 4210 and 4412 boards.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts |4
arch/arm/boot/dts/exynos4412-origen.dts |4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 95efb1189cf0..f018e2149168 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -48,6 +48,10 @@
};
};
+ watchdog@1006 {
+ status = okay;
+ };
+
rtc@1007 {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index 934fe7ecca7e..bd3985b767c4 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -48,6 +48,10 @@
};
};
+ watchdog@1006 {
+ status = okay;
+ };
+
rtc@1007 {
status = okay;
};
--
1.7.9.5
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[PATCH 5/5] ARM: dts: Update watchdog node name in exynos5440.dtsi
Made it as per DT node naming convention name@reg_addr.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5440.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 84f77c2fe4d4..ae3a17c791f6 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -176,7 +176,7 @@
clock-names = i2c;
};
- watchdog {
+ watchdog@11 {
compatible = samsung,s3c2410-wdt;
reg = 0x11 0x1000;
interrupts = 0 1 0;
--
1.7.9.5
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[PATCH 3/5] ARM: dts: Replace numbers with key code macros on Origen boards
Key code macros improve readability.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts | 11 ++-
arch/arm/boot/dts/exynos4412-origen.dts | 13 +++--
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f018e2149168..f767c425d0b5 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -16,6 +16,7 @@
/dts-v1/;
#include exynos4210.dtsi
+#include dt-bindings/input/input.h
/ {
model = Insignal Origen evaluation board based on Exynos4210;
@@ -259,35 +260,35 @@
up {
label = Up;
gpios = gpx2 0 1;
- linux,code = 103;
+ linux,code = KEY_UP;
gpio-key,wakeup;
};
down {
label = Down;
gpios = gpx2 1 1;
- linux,code = 108;
+ linux,code = KEY_DOWN;
gpio-key,wakeup;
};
back {
label = Back;
gpios = gpx1 7 1;
- linux,code = 158;
+ linux,code = KEY_BACK;
gpio-key,wakeup;
};
home {
label = Home;
gpios = gpx1 6 1;
- linux,code = 102;
+ linux,code = KEY_HOME;
gpio-key,wakeup;
};
menu {
label = Menu;
gpios = gpx1 5 1;
- linux,code = 139;
+ linux,code = KEY_MENU;
gpio-key,wakeup;
};
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index bd3985b767c4..e925c9fbfb07 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -14,6 +14,7 @@
/dts-v1/;
#include exynos4412.dtsi
+#include dt-bindings/input/input.h
/ {
model = Insignal Origen evaluation board based on Exynos4412;
@@ -84,37 +85,37 @@
key_home {
keypad,row = 0;
keypad,column = 0;
- linux,code = 102;
+ linux,code = KEY_HOME;
};
key_down {
keypad,row = 0;
keypad,column = 1;
- linux,code = 108;
+ linux,code = KEY_DOWN;
};
key_up {
keypad,row = 1;
keypad,column = 0;
- linux,code = 103;
+ linux,code = KEY_UP;
};
key_menu {
keypad,row = 1;
keypad,column = 1;
- linux,code = 139;
+ linux,code = KEY_MENU;
};
key_back {
keypad,row = 2;
keypad,column = 0;
- linux,code = 158;
+ linux,code = KEY_BACK;
};
key_enter {
keypad,row = 2;
keypad,column = 1;
- linux,code = 28;
+ linux,code = KEY_ENTER;
};
};
--
1.7.9.5
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[PATCH 4/5] ARM: dts: Replace numbers with key code macros on Arndale board
Key code macros improve readability.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5250-arndale.dts | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cde19c818667..d0de1f50d15b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -12,6 +12,7 @@
/dts-v1/;
#include exynos5250.dtsi
#include dt-bindings/interrupt-controller/irq.h
+#include dt-bindings/input/input.h
/ {
model = Insignal Arndale evaluation board based on EXYNOS5250;
@@ -445,42 +446,42 @@
menu {
label = SW-TACT2;
gpios = gpx1 4 1;
- linux,code = 139;
+ linux,code = KEY_MENU;
gpio-key,wakeup;
};
home {
label = SW-TACT3;
gpios = gpx1 5 1;
- linux,code = 102;
+ linux,code = KEY_HOME;
gpio-key,wakeup;
};
up {
label = SW-TACT4;
gpios = gpx1 6 1;
- linux,code = 103;
+ linux,code = KEY_UP;
gpio-key,wakeup;
};
down {
label = SW-TACT5;
gpios = gpx1 7 1;
- linux,code = 108;
+ linux,code = KEY_DOWN;
gpio-key,wakeup;
};
back {
label = SW-TACT6;
gpios = gpx2 0 1;
- linux,code = 158;
+ linux,code = KEY_BACK;
gpio-key,wakeup;
};
wakeup {
label = SW-TACT7;
gpios = gpx2 1 1;
- linux,code = 143;
+ linux,code = KEY_WAKEUP;
gpio-key,wakeup;
};
};
--
1.7.9.5
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Re: [PATCH] ARM: EXYNOS: Use wfi macro in platform_do_lowpower
Hi Kgene, On Fri, May 23, 2014 at 12:31 AM, Daniel Lezcano daniel.lezc...@linaro.org wrote: On 05/22/2014 09:57 AM, Leela Krishna Amudala wrote: This patch is originally based on commit b3377d186572 (ARM: 7064/1: vexpress: Use wfi macro in platform_do_lowpower.) Current Exynos CPU hotplug code includes a hardcoded WFI instruction, in ARM encoding. When the kernel is compiled in Thumb-2 mode, this is invalid and causes the machine to hang hard when a CPU is offlined. Use wfi macro instead of the hardcoded WFI instruction. Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org Acked-by: Daniel Lezcano daniel.lezc...@linaro.org Can you please take action on this patch. Best Regards, Leela Krishna. -- http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro Facebook | http://twitter.com/#!/linaroorg Twitter | http://www.linaro.org/linaro-blog/ Blog -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] ARM: dts: Update watchdog node name in exynos5440.dtsi
On Friday, May 23, 2014 3:09 PM, Sachin Kamat wrote:
Made it as per DT node naming convention name@reg_addr.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Reviewed-by: Jingoo Han jg1@samsung.com
Best regards,
Jingoo Han
---
arch/arm/boot/dts/exynos5440.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 84f77c2fe4d4..ae3a17c791f6 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -176,7 +176,7 @@
clock-names = i2c;
};
- watchdog {
+ watchdog@11 {
compatible = samsung,s3c2410-wdt;
reg = 0x11 0x1000;
interrupts = 0 1 0;
--
1.7.9.5
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[PATCH] ARM: EXYNOS: Add 5800 SoC support
Exynos5800 is an octa core SoC which is based on the 5420 platform. This patch adds the basic support for it in the mach-exynos. Signed-off-by: Arun Kumar K arun...@samsung.com --- arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/platsmp.c |2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4663417..c5423da 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -99,6 +99,11 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config SOC_EXYNOS5800 + bool SAMSUNG EXYNOS5800 + default y + depends on SOC_EXYNOS5420 + endmenu config EXYNOS5420_MCPM diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ae5f648..8fbc55b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -23,6 +23,7 @@ #define EXYNOS5250_SOC_ID 0x4352 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 +#define EXYNOS5800_SOC_ID 0xE5422000 #define EXYNOS5_SOC_MASK 0xF000 extern unsigned long samsung_cpu_id; @@ -39,6 +40,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() @@ -80,9 +82,16 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5440() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5800) +# define soc_is_exynos5800() is_samsung_exynos5800() +#else +# define soc_is_exynos5800() 0 +#endif + #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ + soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 9c16da2..112bc66 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -70,7 +70,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) return ERR_PTR(-ENODEV); if (soc_is_exynos4412()) boot_reg += 4*cpu; - else if (soc_is_exynos5420()) + else if (soc_is_exynos5420() || soc_is_exynos5800()) boot_reg += 4; return boot_reg; } -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4] drm/exynos: enable fimd clocks in probe before accessing fimd registers
Hi Rahul,
On 05/23/2014 04:19 AM, Rahul Sharma wrote:
From: Rahul Sharma rahul.sha...@samsung.com
Fimd probe is accessing fimd Registers without enabling the fimd
gate clocks. If FIMD clocks are kept disabled in Uboot or disbaled
during kernel boottime, the system hangs during boottime.
This issue got surfaced when verifying with sysmmu enabled. Probe of
fimd Sysmmu enables the master clock before accessing sysmmu regs and
then disables. Later fimd probe tries to read the register without
enabling the clock which is wrong and hangs the system.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
v4:
1) Added clk_disable for prev clock when clk_enable fails.
v3:
1) Added checks for clk_enable.
v2:
Rebase.
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bd30d0c..30ccd67 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -898,16 +898,32 @@ static int fimd_bind(struct device *dev, struct device
*master, void *data)
{
struct fimd_context *ctx = fimd_manager.ctx;
struct drm_device *drm_dev = data;
- int win;
+ int win, ret;
fimd_mgr_initialize(fimd_manager, drm_dev);
exynos_drm_crtc_create(fimd_manager);
if (ctx-display)
exynos_drm_create_enc_conn(drm_dev, ctx-display);
+ ret = clk_prepare_enable(ctx-bus_clk);
+ if (ret) {
+ dev_err(dev, bus clock enable failed.\n);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(ctx-lcd_clk);
+ if (ret) {
+ dev_err(dev, lcd clock enable failed.\n);
+ clk_disable_unprepare(ctx-bus_clk);
+ return ret;
+ }
+
for (win = 0; win WINDOWS_NR; win++)
fimd_clear_win(ctx, win);
+ clk_disable_unprepare(ctx-lcd_clk);
+ clk_disable_unprepare(ctx-bus_clk);
+
return 0;
If you want to access fimd registers I guess pm_runtime_get_sync should
be called as well, to wake up display pm domain.
Regards
Andrzej
}
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Re: [PATCH 2/2] ASoC: samsung: Add machine driver for odroidx2
On 22/05/14 20:53, Mark Brown wrote:
On Thu, May 22, 2014 at 01:55:08PM +0200, Sylwester Nawrocki wrote:
From: Chen Zhen zhen1.c...@samsung.com
This machine driver primary defines the audio path, the supported
data formats and sample frequency.
I guess it can't yet, it would have been good to explain that in the
changelog for the bindings (and include the binding in this patch...).
Thanks for the review, I'm still rather inexperienced in the ASoC stuff,
I've obviously overlooked there is actually no routing handling. I'd rather
add those bits.
As for the DT binding documentation patch, I thought we're supposed to keep
documentation in separate patches, so processes of separating it from the
kernel is easier ?
+ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+| SND_SOC_DAIFMT_NB_NF
+| SND_SOC_DAIFMT_CBM_CFM);
+if (ret 0)
+return ret;
+
+ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+| SND_SOC_DAIFMT_NB_NF
+| SND_SOC_DAIFMT_CBM_CFM);
+if (ret 0)
+return ret;
These are constant, set these in the dai_link.
+
+ret = snd_soc_dai_set_sysclk(codec_dai, 3, MAX98090_MCLK_FREQ,
+ SND_SOC_CLOCK_IN);
+if (ret 0) {
+dev_err(codec_dai-dev,
+Unable to switch to FLL1: %d\n, ret);
+return ret;
+}
So's this - also what is 3? Set it on init.
OK, will move it. I'm not sure why 3, it seems to be ignored by the codec
anyway. Chen, can you confirm the second argument is actually a don't care
value ?
+ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK,
+0, MOD_OPCLK_PCLK);
Similarly for the rest of the function.
+return snd_soc_register_card(card);
devm_snd_soc_register_card().
Thanks for the suggestions, I'll amend that.
--
Regards,
Sylwester
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[PATCH] clk: samsung: Make of_device_id array const
Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 2 +-
drivers/clk/samsung/clk-exynos5250.c | 2 +-
drivers/clk/samsung/clk-exynos5420.c | 2 +-
drivers/clk/samsung/clk-exynos5440.c | 2 +-
drivers/clk/samsung/clk.c| 2 +-
drivers/clk/samsung/clk.h| 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index b4f967210175..3463535dcc25 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1070,7 +1070,7 @@ static void __init exynos4_clk_register_finpll(void)
}
-static struct of_device_id ext_clk_match[] __initdata = {
+static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ .compatible = samsung,clock-xusbxti, .data = (void *)1, },
{},
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index e7ee4420da81..0d97c69fde29 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -678,7 +678,7 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
-static struct of_device_id ext_clk_match[] __initdata = {
+static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
};
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 60b26819bed5..904881493b32 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -770,7 +770,7 @@ static struct samsung_pll_clock exynos5420_plls[nr_plls]
__initdata = {
KPLL_CON0, NULL),
};
-static struct of_device_id ext_clk_match[] __initdata = {
+static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,exynos5420-oscclk, .data = (void *)0, },
{ },
};
diff --git a/drivers/clk/samsung/clk-exynos5440.c
b/drivers/clk/samsung/clk-exynos5440.c
index 2bfad5a993d0..ff70bfed5ef8 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -84,7 +84,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[]
__initdata = {
GATE(CLK_CS250_O, cs250_o, cs250, CLKEN_OV_VAL, 19, 0, 0),
};
-static struct of_device_id ext_clk_match[] __initdata = {
+static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xtal, .data = (void *)0, },
{},
};
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 91bec3ebdc8f..f9914a8b02ae 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -269,7 +269,7 @@ void __init samsung_clk_register_gate(struct
samsung_gate_clock *list,
void __init samsung_clk_of_register_fixed_ext(
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
- struct of_device_id *clk_matches)
+ const struct of_device_id *clk_matches)
{
const struct of_device_id *match;
struct device_node *np;
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index c7141ba826e0..dc8f2cc6f486 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -317,7 +317,7 @@ extern void __init samsung_clk_init(struct device_node *np,
void __iomem *base,
extern void __init samsung_clk_of_register_fixed_ext(
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
- struct of_device_id *clk_matches);
+ const struct of_device_id *clk_matches);
extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
--
1.9.1
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Re: [PATCH 1/2] doc: dt bindings: Document Odroid X2/U3 audio subsystem bindings
On 22/05/14 20:46, Mark Brown wrote:
On Thu, May 22, 2014 at 01:55:07PM +0200, Sylwester Nawrocki wrote:
+sound {
+compatible = samsung,odroidx2-audio;
+samsung,i2s-controller = i2s0;
+samsung,audio-codec = max98090;
+};
Can this not use simple-card?
I dug into that and it seems it almost could, but there is one
thing I'm not sure how to cover with the simple-card DT bindings
and the related driver.
There are these two calls:
+ ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK,
+ 0, MOD_OPCLK_PCLK);
+ /* Set the cpu DAI configuration in order to use CDCLK */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK,
+ 0, SND_SOC_CLOCK_OUT);
This changes clocks routing so that the CPU DAI in slave mode generates
master clock for the codec, on the SoC's CDCLK pin. Then this is
a reference clock for the codec's PLL, which is a source of the I2S
interface clocks.
It's done this way to avoid changing at runtime frequency of the EPLL
clock, which may be parent of other clocks than the sound subsystem,
e.g. MMC.
simple-card just calls set_sysclk once for the CPU DAI and CODEC with
the second and last argument set to 0.
I'll try and see again if there is some way to use simple-card.
--
Thanks,
Sylwester
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[PATCH 0/3] mmc: fixed the mmc_of_parse for dwmmc
This patch-set is fixed the dw-mmc controller problem. dw-mmc controller have the slot, but mmc_of_parse didn't parse the slot sub-node. So dw-mmc controller didn't work correctly. Jaehoon Chung (2): mmc: dw_mmc: use the __mmc_of_parse to parse the slot node ARM: dts: replace the broken-cd property into slot node for dwmmc. Ludovic Desroches (1): mmc: host: add slot argument to mmc_of_parse arch/arm/boot/dts/exynos4412-odroidx.dts |2 +- arch/arm/boot/dts/exynos4412-origen.dts |2 +- arch/arm/boot/dts/exynos4412-trats2.dts |4 ++-- arch/arm/boot/dts/exynos5250-arndale.dts |2 +- arch/arm/boot/dts/exynos5250-cros-common.dtsi |4 ++-- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- arch/arm/boot/dts/exynos5420-arndale-octa.dts |2 +- arch/arm/boot/dts/rk3066a-bqcurie2.dts|2 +- arch/arm/boot/dts/socfpga_arria5.dtsi |2 +- arch/arm/boot/dts/socfpga_cyclone5.dtsi |2 +- arch/arm/boot/dts/socfpga_vt.dts |2 +- drivers/mmc/core/host.c | 13 + drivers/mmc/host/dw_mmc.c | 25 ++--- include/linux/mmc/host.h | 10 +- 14 files changed, 37 insertions(+), 37 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM: dts: replace the broken-cd property into slot node for dwmmc.
dw-mmc controller can be support the multiple slot.
So each slot's property can be difference.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
arch/arm/boot/dts/exynos4412-odroidx.dts |2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts |2 +-
arch/arm/boot/dts/exynos5250-cros-common.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5420-arndale-octa.dts |2 +-
arch/arm/boot/dts/rk3066a-bqcurie2.dts|2 +-
arch/arm/boot/dts/socfpga_arria5.dtsi |2 +-
arch/arm/boot/dts/socfpga_cyclone5.dtsi |2 +-
arch/arm/boot/dts/socfpga_vt.dts |2 +-
11 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..24ec351 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -46,7 +46,6 @@
num-slots = 1;
supports-highspeed;
- broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -55,6 +54,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+ broken-cd;
};
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index e2c0dca..ed712a6 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -129,7 +129,6 @@
num-slots = 1;
supports-highspeed;
- broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -138,6 +137,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+ broken-cd;
};
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 9583563..294a586 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -460,8 +460,6 @@
mmc@1255 {
num-slots = 1;
supports-highspeed;
- broken-cd;
- non-removable;
card-detect-delay = 200;
vmmc-supply = vemmc_reg;
clock-frequency = 4;
@@ -475,6 +473,8 @@
slot@0 {
reg = 0;
bus-width = 8;
+ non-removable;
+ broken-cd;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 090f983..0c9a7da 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -400,7 +400,6 @@
status = okay;
num-slots = 1;
supports-highspeed;
- broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -412,6 +411,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+ broken-cd;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 2c1560d..7ab3b94 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -249,7 +249,6 @@
mmc@1220 {
num-slots = 1;
supports-highspeed;
- broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -260,6 +259,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+ broken-cd;
};
};
@@ -283,7 +283,6 @@
mmc@1223 {
num-slots = 1;
supports-highspeed;
- broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -293,6 +292,7 @@
slot@0 {
reg = 0;
bus-width = 4;
+ broken-cd;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..feffe24 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -283,7 +283,6 @@
status =
[PATCH 2/3] mmc: dw_mmc: use the __mmc_of_parse to parse the slot node
dw-mmc controller have the multiple slot.
Then it needs to parse the property for each slot.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
drivers/mmc/host/dw_mmc.c | 25 ++---
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..d4800f8 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1015,12 +1015,11 @@ static int dw_mci_get_cd(struct mmc_host *mmc)
{
int present;
struct dw_mci_slot *slot = mmc_priv(mmc);
- struct dw_mci_board *brd = slot-host-pdata;
struct dw_mci *host = slot-host;
int gpio_cd = mmc_gpio_get_cd(mmc);
/* Use platform get_cd function, else try onboard card detect */
- if (brd-quirks DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
+ if (slot-quirks DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
present = 1;
else if (!IS_ERR_VALUE(gpio_cd))
present = gpio_cd;
@@ -2010,6 +2009,9 @@ static struct dw_mci_of_slot_quirks {
{
.quirk = disable-wp,
.id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
+ }, {
+ .quirk = broken-cd,
+ .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
},
};
@@ -2088,7 +2090,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned
int id)
if (host-pdata-caps2)
mmc-caps2 = host-pdata-caps2;
- mmc_of_parse(mmc);
+ __mmc_of_parse(mmc, dw_mci_of_find_slot_node(host-dev, slot-id));
if (host-pdata-blk_settings) {
mmc-max_segs = host-pdata-blk_settings-max_segs;
@@ -2231,23 +2233,13 @@ static inline bool dw_mci_ctrl_all_reset(struct dw_mci
*host)
}
#ifdef CONFIG_OF
-static struct dw_mci_of_quirks {
- char *quirk;
- int id;
-} of_quirks[] = {
- {
- .quirk = broken-cd,
- .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
- },
-};
-
static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
{
struct dw_mci_board *pdata;
struct device *dev = host-dev;
struct device_node *np = dev-of_node;
const struct dw_mci_drv_data *drv_data = host-drv_data;
- int idx, ret;
+ int ret;
u32 clock_frequency;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
@@ -2264,11 +2256,6 @@ static struct dw_mci_board *dw_mci_parse_dt(struct
dw_mci *host)
pdata-num_slots = 1;
}
- /* get quirks */
- for (idx = 0; idx ARRAY_SIZE(of_quirks); idx++)
- if (of_get_property(np, of_quirks[idx].quirk, NULL))
- pdata-quirks |= of_quirks[idx].id;
-
if (of_property_read_u32(np, fifo-depth, pdata-fifo_depth))
dev_info(dev, fifo-depth property not found, using
value of FIFOTH register as default\n);
--
1.7.9.5
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[PATCH 1/3] mmc: host: add slot argument to mmc_of_parse
From: Ludovic Desroches ludovic.desroc...@atmel.com
Some hosts manage several slots. In these case information such as the
bus width, chi detect and others are into the slot node. So we have to
parse child node. If not NULL, slot node will be used instead of the
device node.
Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
drivers/mmc/core/host.c | 13 +
include/linux/mmc/host.h | 10 +-
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 95cceae..0f677b3 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct
mmc_host *host)
#endif
/**
- * mmc_of_parse() - parse host's device-tree node
+ * __mmc_of_parse() - parse host's device-tree node
* @host: host whose node should be parsed.
+ * @slot : some device provide several slots so the node to parse
+ * is not the host one.
*
* To keep the rest of the MMC subsystem unaware of whether DT has been
* used to to instantiate and configure this host instance or not, we
* parse the properties and set respective generic mmc-host flags and
* parameters.
*/
-int mmc_of_parse(struct mmc_host *host)
+int __mmc_of_parse(struct mmc_host *host, struct device_node *slot)
{
struct device_node *np;
u32 bus_width;
@@ -317,7 +319,10 @@ int mmc_of_parse(struct mmc_host *host)
if (!host-parent || !host-parent-of_node)
return 0;
- np = host-parent-of_node;
+ if (slot)
+ np = slot;
+ else
+ np = host-parent-of_node;
/* bus-width is translated to MMC_CAP_*_BIT_DATA flags */
if (of_property_read_u32(np, bus-width, bus_width) 0) {
@@ -459,7 +464,7 @@ out:
return ret;
}
-EXPORT_SYMBOL(mmc_of_parse);
+EXPORT_SYMBOL(__mmc_of_parse);
/**
* mmc_alloc_host - initialise the per-host structure.
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 7960424..c62af91 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -372,7 +372,15 @@ struct mmc_host *mmc_alloc_host(int extra, struct device
*);
int mmc_add_host(struct mmc_host *);
void mmc_remove_host(struct mmc_host *);
void mmc_free_host(struct mmc_host *);
-int mmc_of_parse(struct mmc_host *host);
+int __mmc_of_parse(struct mmc_host *host, struct device_node *slot);
+/*
+ * mmc_of_parse - parse host's device-tree node
+ * @host: host whose node should be parsed.
+ */
+static inline int mmc_of_parse(struct mmc_host *host)
+{
+ return __mmc_of_parse(host, NULL);
+}
static inline void *mmc_priv(struct mmc_host *host)
{
--
1.7.9.5
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[PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 82
arch/arm/boot/dts/exynos5410.dtsi | 206 +
3 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410,
samsung,exynos5;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ firmware@02037000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x02037000 0x1000;
+ };
+
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+};
+
+uart0 {
+ status = okay;
+};
+
+uart1 {
+ status = okay;
+};
+
+uart2 {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include skeleton.dtsi
+#include dt-bindings/clock/exynos5410.h
+
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+ interrupt-parent = gic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x0;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x1;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x2;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x3;
+ };
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ combiner:
[PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/mach-exynos/Kconfig|8 arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/firmware.c |2 +- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abc..79a3e85 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,14 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5410 + bool SAMSUNG EXYNOS5410 + default y + depends on ARCH_EXYNOS5 + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Enable EXYNOS5410 SoC support + config SOC_EXYNOS5420 bool SAMSUNG EXYNOS5420 default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e2d0954..d64c6de 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -21,6 +21,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5_SOC_MASK 0xF000 @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 19307a0 Merge branch 'v3.16-next/dt-samsung-2' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) Many thanks for reviewing to Tomasz Figa. Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 82 arch/arm/boot/dts/exynos5410.dtsi | 206 +++ arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/common.h | 11 +- arch/arm/mach-exynos/firmware.c|2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 10 files changed, 602 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] mmc: host: add slot argument to mmc_of_parse
On 23 May 2014 15:55, Jaehoon Chung jh80.ch...@samsung.com wrote: From: Ludovic Desroches ludovic.desroc...@atmel.com Some hosts manage several slots. In these case information such as the bus width, chi detect and others are into the slot node. So we have to parse child node. If not NULL, slot node will be used instead of the device node. Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com --- drivers/mmc/core/host.c | 13 + include/linux/mmc/host.h | 10 +- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 95cceae..0f677b3 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host) #endif /** - * mmc_of_parse() - parse host's device-tree node + * __mmc_of_parse() - parse host's device-tree node IMO it would be better to rename this function, something like mmc_of_parse_slot(). -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] drm/exynos: remove redundant mutex_unlock
The patch fixes unlocking in exynos_drm_component_del.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Hi Inki,
This patch is based on exynos_drm_next branch.
Regards
Andrzej
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 4cef88f..c5a401ae 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -417,7 +417,6 @@ void exynos_drm_component_del(struct device *dev,
if (dev == cdev-dev) {
list_del(cdev-list);
kfree(cdev);
- mutex_unlock(drm_component_lock);
break;
}
}
--
1.9.1
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[PATCH] drm/exynos/fimd: allow multiplatform configuration
The patch removes dependency on !ARCH_MULTIPLATFORM. This dependency seems to be not longer valid. Signed-off-by: Andrzej Hajda a.ha...@samsung.com --- drivers/gpu/drm/exynos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index c8c9510..e0d73fb 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -26,7 +26,7 @@ config DRM_EXYNOS_DMABUF config DRM_EXYNOS_FIMD bool Exynos DRM FIMD - depends on DRM_EXYNOS !FB_S3C !ARCH_MULTIPLATFORM + depends on DRM_EXYNOS !FB_S3C select FB_MODE_HELPERS help Choose this option if you want to use Exynos FIMD for DRM. -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] drm/exynos: add fimd dependency to fimd related encoders
DPI, DSI and DP drivers will not work without FIMD. The patch adds appropriate dependencies in Kconfig. Signed-off-by: Andrzej Hajda a.ha...@samsung.com --- drivers/gpu/drm/exynos/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index e0d73fb..178d2a9 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -33,7 +33,7 @@ config DRM_EXYNOS_FIMD config DRM_EXYNOS_DPI bool EXYNOS DRM parallel output support - depends on DRM_EXYNOS + depends on DRM_EXYNOS_FIMD select DRM_PANEL default n help @@ -41,7 +41,7 @@ config DRM_EXYNOS_DPI config DRM_EXYNOS_DSI bool EXYNOS DRM MIPI-DSI driver support - depends on DRM_EXYNOS + depends on DRM_EXYNOS_FIMD select DRM_MIPI_DSI select DRM_PANEL default n @@ -50,7 +50,7 @@ config DRM_EXYNOS_DSI config DRM_EXYNOS_DP bool EXYNOS DRM DP driver support - depends on DRM_EXYNOS ARCH_EXYNOS (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) + depends on DRM_EXYNOS_FIMD ARCH_EXYNOS (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) default DRM_EXYNOS help This enables support for DP device. -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] drm/exynos/fimd: allow multiplatform configuration
On 23 May 2014 16:28, Andrzej Hajda a.ha...@samsung.com wrote: The patch removes dependency on !ARCH_MULTIPLATFORM. This dependency seems to be not longer valid. Signed-off-by: Andrzej Hajda a.ha...@samsung.com Reviewed-by: Sachin Kamat sachin.ka...@linaro.org -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] drm/exynos: remove redundant mutex_unlock
Hi Andrzej,
On 23 May 2014 16:27, Andrzej Hajda a.ha...@samsung.com wrote:
The patch fixes unlocking in exynos_drm_component_del.
This patch actually removes multiple unlocking issue.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Hi Inki,
This patch is based on exynos_drm_next branch.
Regards
Andrzej
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 4cef88f..c5a401ae 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -417,7 +417,6 @@ void exynos_drm_component_del(struct device *dev,
if (dev == cdev-dev) {
list_del(cdev-list);
kfree(cdev);
- mutex_unlock(drm_component_lock);
break;
}
}
--
1.9.1
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--
With warm regards,
Sachin
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Re: [PATCH 2/2] ASoC: samsung: Add machine driver for odroidx2
On Fri, May 23, 2014 at 10:44:56AM +0200, Sylwester Nawrocki wrote:
On 22/05/14 20:53, Mark Brown wrote:
As for the DT binding documentation patch, I thought we're supposed to keep
documentation in separate patches, so processes of separating it from the
kernel is easier ?
I'm not sure what the current theory is - they should definitely be
separate if they're part of a multi-patch series but for a single patch
I don't remember what the current taste is. If you're sending to the
same recipients anyway splitting isn't going to accomplish much, the
idea was to only send the DT binding to the DT maintainers and list and
not the code.
+ ret = snd_soc_dai_set_sysclk(codec_dai, 3, MAX98090_MCLK_FREQ,
+ SND_SOC_CLOCK_IN);
+ if (ret 0) {
+ dev_err(codec_dai-dev,
+ Unable to switch to FLL1: %d\n, ret);
+ return ret;
+ }
So's this - also what is 3? Set it on init.
OK, will move it. I'm not sure why 3, it seems to be ignored by the codec
anyway. Chen, can you confirm the second argument is actually a don't care
value ?
If it's don't care supply 0 instead.
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Description: Digital signature
Re: Re: [PATCH 2/2] ASoC: samsung: Add machine driver for odroidx2
On Fri, May 23, 2014 at 02:18:39AM +, Zhen Chen wrote: HTML xmlns:o = urn:schemas-microsoft-com:office:officeHEADTITLESamsung Enterprise Portal mySingle/TITLE META content=IE=5 http-equiv=X-UA-Compatible META content=text/html; charset=windows-1252 http-equiv=Content-Type Please fix your mail configuration to send in plain text, I can't read this - it's not even got a multipart/alternative plain text bit. signature.asc Description: Digital signature
Re: [PATCH v4] drm/exynos: enable fimd clocks in probe before accessing fimd registers
Hi Andrej, On 23 May 2014 13:13, Andrzej Hajda a.ha...@samsung.com wrote: Hi Rahul, [snip] + clk_disable_unprepare(ctx-lcd_clk); + clk_disable_unprepare(ctx-bus_clk); + return 0; If you want to access fimd registers I guess pm_runtime_get_sync should be called as well, to wake up display pm domain. You are right. I have added pm runtime get sync and put sync. Regards, Rahul Sharma. Regards Andrzej } -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5] drm/exynos: enable fimd clocks in probe before accessing fimd registers
From: Rahul Sharma rahul.sha...@samsung.com
Fimd probe is accessing fimd Registers without enabling the fimd
gate clocks. If FIMD clocks are kept disabled in Uboot or disbaled
during kernel boottime, the system hangs during boottime.
This issue got surfaced when verifying with sysmmu enabled. Probe of
fimd Sysmmu enables the master clock before accessing sysmmu regs and
then disables. Later fimd probe tries to read the register without
enabling the clock which is wrong and hangs the system.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
v5:
1) Added pm_runtime_get_sync to enable the Display power domain.
v4:
1) Added clk_disable for prev clock when clk_enable fails.
v3:
1) Added checks for clk_enable.
v2:
Rebase.
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 35 +-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bd30d0c..6a30415 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -898,18 +898,51 @@ static int fimd_bind(struct device *dev, struct device
*master, void *data)
{
struct fimd_context *ctx = fimd_manager.ctx;
struct drm_device *drm_dev = data;
- int win;
+ int win, ret;
fimd_mgr_initialize(fimd_manager, drm_dev);
exynos_drm_crtc_create(fimd_manager);
if (ctx-display)
exynos_drm_create_enc_conn(drm_dev, ctx-display);
+ ret = pm_runtime_get_sync(ctx-dev);
+ if (ret) {
+ dev_err(dev, pm runtime get has failed.\n);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(ctx-bus_clk);
+ if (ret) {
+ dev_err(dev, bus clock enable failed.\n);
+ goto bus_clk_err;
+ }
+
+ ret = clk_prepare_enable(ctx-lcd_clk);
+ if (ret) {
+ dev_err(dev, lcd clock enable failed.\n);
+ goto lcd_clk_err;
+ }
+
for (win = 0; win WINDOWS_NR; win++)
fimd_clear_win(ctx, win);
+ clk_disable_unprepare(ctx-lcd_clk);
+ clk_disable_unprepare(ctx-bus_clk);
+
+ ret = pm_runtime_put_sync(ctx-dev);
+ if (ret) {
+ dev_err(dev, pm runtime put has failed.\n);
+ goto pm_put_err;
+ }
+
return 0;
+lcd_clk_err:
+ clk_disable_unprepare(ctx-bus_clk);
+bus_clk_err:
+ pm_runtime_put_sync(ctx-dev);
+pm_put_err:
+ return ret;
}
static void fimd_unbind(struct device *dev, struct device *master,
--
1.7.9.5
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[PATCH] ASoC: samsung: Use params_width()
commit 8c5178fca4ce (ALSA: Add params_width() helpers) introduces
a helper to get the sample width. Updating Samsung related sound
drivers to use this helper.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/i2s.c |8
sound/soc/samsung/pcm.c |4 ++--
sound/soc/samsung/s3c-i2s-v2.c |8
sound/soc/samsung/s3c2412-i2s.c |6 +++---
sound/soc/samsung/s3c24xx-i2s.c |6 +++---
sound/soc/samsung/smdk_wm8580.c |8 +++-
sound/soc/samsung/smdk_wm8994.c |2 +-
sound/soc/samsung/spdif.c |4 ++--
8 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 07ff3e7..6b96168 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -672,8 +672,8 @@ static int i2s_hw_params(struct snd_pcm_substream
*substream,
if (is_manager(i2s))
mod = ~MOD_BLC_MASK;
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
if (is_secondary(i2s))
mod |= MOD_BLCS_8BIT;
else
@@ -681,7 +681,7 @@ static int i2s_hw_params(struct snd_pcm_substream
*substream,
if (is_manager(i2s))
mod |= MOD_BLC_8BIT;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
if (is_secondary(i2s))
mod |= MOD_BLCS_16BIT;
else
@@ -689,7 +689,7 @@ static int i2s_hw_params(struct snd_pcm_substream
*substream,
if (is_manager(i2s))
mod |= MOD_BLC_16BIT;
break;
- case SNDRV_PCM_FORMAT_S24_LE:
+ case 24:
if (is_secondary(i2s))
mod |= MOD_BLCS_24BIT;
else
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index a3c9c9c..4c5f97f 100644
--- a/sound/soc/samsung/pcm.c
+++ b/sound/soc/samsung/pcm.c
@@ -283,8 +283,8 @@ static int s3c_pcm_hw_params(struct snd_pcm_substream
*substream,
dev_dbg(pcm-dev, Entered %s\n, __func__);
/* Strictly check for sample size */
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S16_LE:
+ switch (params_width(params)) {
+ case 16:
break;
default:
return -EINVAL;
diff --git a/sound/soc/samsung/s3c-i2s-v2.c b/sound/soc/samsung/s3c-i2s-v2.c
index 77a2ae5..0ff4bbe 100644
--- a/sound/soc/samsung/s3c-i2s-v2.c
+++ b/sound/soc/samsung/s3c-i2s-v2.c
@@ -322,13 +322,13 @@ static int s3c_i2sv2_hw_params(struct snd_pcm_substream
*substream,
iismod = ~S3C64XX_IISMOD_BLC_MASK;
/* Sample size */
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
iismod |= S3C64XX_IISMOD_BLC_8BIT;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
break;
- case SNDRV_PCM_FORMAT_S24_LE:
+ case 24:
iismod |= S3C64XX_IISMOD_BLC_24BIT;
break;
}
diff --git a/sound/soc/samsung/s3c2412-i2s.c b/sound/soc/samsung/s3c2412-i2s.c
index 843f315..08c059b 100644
--- a/sound/soc/samsung/s3c2412-i2s.c
+++ b/sound/soc/samsung/s3c2412-i2s.c
@@ -120,11 +120,11 @@ static int s3c2412_i2s_hw_params(struct snd_pcm_substream
*substream,
iismod = readl(i2s-regs + S3C2412_IISMOD);
pr_debug(%s: r: IISMOD: %x\n, __func__, iismod);
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
iismod |= S3C2412_IISMOD_8BIT;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
iismod = ~S3C2412_IISMOD_8BIT;
break;
}
diff --git a/sound/soc/samsung/s3c24xx-i2s.c b/sound/soc/samsung/s3c24xx-i2s.c
index 4a6d206..9aba9fb 100644
--- a/sound/soc/samsung/s3c24xx-i2s.c
+++ b/sound/soc/samsung/s3c24xx-i2s.c
@@ -248,12 +248,12 @@ static int s3c24xx_i2s_hw_params(struct snd_pcm_substream
*substream,
iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
pr_debug(hw_params r: IISMOD: %x\n, iismod);
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
iismod = ~S3C2410_IISMOD_16BIT;
dma_data-dma_size = 1;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
iismod |= S3C2410_IISMOD_16BIT;
dma_data-dma_size = 2;
break;
diff --git a/sound/soc/samsung/smdk_wm8580.c b/sound/soc/samsung/smdk_wm8580.c
index 7a16b32..b1a519f 100644
--- a/sound/soc/samsung/smdk_wm8580.c
+++ b/sound/soc/samsung/smdk_wm8580.c
@@ -37,13 +37,11 @@ static int smdk_hw_params(struct snd_pcm_substream
*substream,
Crash during S2R on Arndale if CONFIG_SAMSUNG_PM_CHECK enabled
Hi, I notice that if CONFIG_SAMSUNG_PM_CHECK is enabled, we get a crash in function crc32_le(), as below. wanted to know, if anyone of you came across this. Tested on Arndale5250 on kgene's 'for-next' branch 19307a0b41ef10a20712827430e1f2074efab3c4 Merge branch 'v3.16-next/dt-samsung-2' into for-next 3c8977f17796f0b8816a1a283b0b80b71c83d416 ARM: dts: enable usb nodes for exynos4412-trats2 ef14d94cdc41c0af1c2713e1ddced903d9d68768 ARM: dts: add hsotg device node for exynos4 26bbd41fe1b3b75bb075eaddf26571c7573c4c01 ARM: dts: add exynos_usbphy node for exynos4 7b9613aca42a5522d269f89496fef7df10934335 ARM: dts: add PMU syscon node for exynos4 e8af308549178271bccaa7886f429a7c0b1d8514 ARM: dts: enable usb nodes for exynos4412-trats2 -- / $ echo mem /sys/power/state [9.874440] PM: Syncing filesystems ... [ 10.518085] random: nonblocking pool is initialized [ 10.645255] done. [ 10.646561] Freezing user space processes ... (elapsed 0.000 seconds) done. [ 10.652642] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 10.713454] wake enabled for irq 187 [ 10.715575] wake enabled for irq 188 [ 10.719117] wake enabled for irq 189 [ 10.722686] wake enabled for irq 190 [ 10.726244] wake enabled for irq 191 [ 10.729793] wake enabled for irq 192 [ 10.745154] PM: suspend of devices complete after 83.460 msecs [ 10.751576] PM: late suspend of devices complete after 2.051 msecs [ 10.758449] PM: noirq suspend of devices complete after 2.155 msecs [ 10.763253] Disabling non-boot CPUs ... [ 10.767496] IRQ153 no longer affine to CPU1 [ 10.767623] CPU1: shutdown [ 10.774637] Unable to handle kernel paging request at virtual address f0001000 [ 10.774637] pgd = edb18000 [ 10.774637] [f0001000] *pgd=6e006811, *pte=, *ppte= [ 10.774637] Internal error: Oops: 7 [#1] PREEMPT SMP ARM [ 10.774637] Modules linked in: [ 10.774637] CPU: 0 PID: 1 Comm: sh Not tainted 3.15.0-rc4-00197-g0cb752a #43 [ 10.774637] task: ee00e800 ti: ee078000 task.ti: ee078000 [ 10.774637] PC is at crc32_le+0x2c/0x13c [ 10.774637] LR is at 0x1e00 [ 10.774637] pc : [c01cb3a0]lr : [1e00]psr: 2093 [ 10.774637] sp : ee079e6c ip : 700de3b6 fp : efa06222 [ 10.774637] r10: 840510ee r9 : r8 : 2000 [ 10.774637] r7 : c05086ac r6 : r5 : 9e16d8c3 r4 : fffc [ 10.774637] r3 : c05083c0 r2 : r1 : effc r0 : 20706046 [ 10.774637] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user [ 10.774637] Control: 10c5387d Table: 6db1806a DAC: 0015 [ 10.774637] Process sh (pid: 1, stack limit = 0xee078240) [ 10.774637] Stack: (0xee079e6c to 0xee07a000) [ 10.774637] 9e60:7000 ed9cba00 ef7fccc0 c050f036 [ 10.774637] 9e80: ee3ca60c beb7da40 c001a8c8 ef7fccc0 ed9cba00 c001a894 c001a880 [ 10.774637] 9ea0: c05128a0 ed9c c001a894 c001a850 c05125f0 c05439bc 0003 c001a0ec [ 10.774637] 9ec0: c05439bc c0057044 beb7da40 c03841a4 c044e1d0 ee079eec ee079eec [ 10.774637] 9ee0: 0003 0003 c038f360 0003 ed899d40 0004 c00572a0 [ 10.774637] 9f00: 006d 0003 c04465bc c00562c4 0004 ee079f80 [ 10.774637] 9f20: ed899d40 0004 ee3ca600 c0110534 ee203900 b6f3b000 [ 10.774637] 9f40: ee079f80 0004 0004 b6f3b000 c00b7ca0 ee00e800 c00d1570 [ 10.774637] 9f60: 0001 ee203900 ee203900 0004 b6f3b000 c00b8284 [ 10.774637] 9f80: ee203900 0004 b6f3b000 b6e265f8 0004 c000e4e4 [ 10.774637] 9fa0: ee078000 c000e360 0004 b6f3b000 0001 b6f3b000 0004 [ 10.774637] 9fc0: 0004 b6f3b000 b6e265f8 0004 0004 000ad848 0974 beb7da40 [ 10.774637] 9fe0: b6f3b000 beb7d7c0 b6d6d124 b6dba43c 6010 0001 [ 10.774637] [c01cb3a0] (crc32_le) from [c001a8c8] (s3c_pm_makecheck+0x34/0x54) [ 10.774637] [c001a8c8] (s3c_pm_makecheck) from [c001a880] (s3c_pm_run_res+0x6c/0x80) [ 10.774637] [c001a880] (s3c_pm_run_res) from [c001a850] (s3c_pm_run_res+0x3c/0x80) [ 10.774637] [c001a850] (s3c_pm_run_res) from [c001a0ec] (exynos_suspend_enter+0xa8/0x144) [ 10.774637] [c001a0ec] (exynos_suspend_enter) from [c0057044] (suspend_devices_and_enter+0x25c/0x304) [ 10.774637] [c0057044] (suspend_devices_and_enter) from [c00572a0] (pm_suspend+0x1b4/0x214) [ 10.774637] [c00572a0] (pm_suspend) from [c00562c4] (state_store+0x68/0xb8) [ 10.774637] [c00562c4] (state_store) from [c0110534] (kernfs_fop_write+0xc0/0x180) [ 10.774637] [c0110534] (kernfs_fop_write) from [c00b7ca0] (vfs_write+0xac/0x188) [ 10.774637] [c00b7ca0] (vfs_write) from [c00b8284] (SyS_write+0x40/0x94) [ 10.774637] [c00b8284] (SyS_write) from [c000e360] (ret_fast_syscall+0x0/0x30) [ 10.774637]
[PATCH v4 0/2] cpufreq: opp: Add device tree based lookup of boost mode frequency
Changes since v3: - Minor changes as suggested in the last version. Changes since v2: - Reworked based on the PM / OPP: move cpufreq specific helpers out of OPP layer patch series posted by Nishanth Menon n...@ti.com. Changes since v1: - Boost mode frequencies are specfied as a set of frequencies instead of specifying them as OPPs. Thanks to Nishanth, Lukasz and Rob for the feedback. Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds support for CPU boost mode for CPUfreq drivers. To use the new boost mode, CPUfreq drivers have to specify the boost mode frequency and voltage within the CPUfreq driver, which is the case for Exynos4x12 CPUfreq driver. But for CPUfreq drivers which obtain the OPPs from cpus node, this patch series adds support to specify boost mode frequencies in the cpu device tree node. This requirement came up when Lukasz pointed out the regression caused by the Exynos CPUfreq driver consolidation patches. Thomas Abraham (2): cpufreq / OPP: Allow boost frequency to be looked up from device tree Documentation: devicetree: Add boost-frequency binding to list boost mode frequency .../devicetree/bindings/cpufreq/cpufreq-boost.txt | 38 + drivers/cpufreq/cpufreq_opp.c | 44 2 files changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/2] Documentation: devicetree: Add boost-frequency binding to list boost mode frequency
From: Thomas Abraham thomas...@samsung.com
Add a new optional boost-frequency binding for specifying the frequencies
usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
.../devicetree/bindings/cpufreq/cpufreq-boost.txt | 38
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
b/Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
new file mode 100644
index 000..63ed0fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
@@ -0,0 +1,38 @@
+* Device tree binding for CPU boost frequency (aka over-clocking)
+
+Certain CPU's can be operated in optional 'boost' mode (or sometimes referred
as
+overclocking) in which the CPU can operate at frequencies which are not
+specified by the manufacturer as CPU's operating frequency.
+
+Optional Properties:
+- boost-frequencies: list of frequencies in KHz to be used only in boost mode.
+ This list should be a subset of frequencies listed in operating-points
+ property. Refer to Documentation/devicetree/bindings/power/opp.txt for
+ details about operating-points property.
+
+Example:
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
+
+ operating-points =
+ 150 135
+ 140 1287500
+ 130 125
+ 120 1187500
+ 110 1137500
+ 100 1087500
+ ;
+ boost-frequencies = 150 140;
+ };
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
+ };
+ };
--
1.7.9.5
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[PATCH v4 1/2] cpufreq / OPP: Allow boost frequency to be looked up from device tree
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost frequencies from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/cpufreq/cpufreq_opp.c | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/cpufreq/cpufreq_opp.c b/drivers/cpufreq/cpufreq_opp.c
index c0c6f4a..2b3905b 100644
--- a/drivers/cpufreq/cpufreq_opp.c
+++ b/drivers/cpufreq/cpufreq_opp.c
@@ -19,6 +19,7 @@
#include linux/pm_opp.h
#include linux/rcupdate.h
#include linux/slab.h
+#include linux/of.h
/**
* dev_pm_opp_init_cpufreq_table() - create a cpufreq table for a device
@@ -51,6 +52,10 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev,
struct cpufreq_frequency_table *freq_table = NULL;
int i, max_opps, ret = 0;
unsigned long rate;
+#ifdef CONFIG_CPU_FREQ_BOOST_SW
+ int j, len;
+ u32 *boost_freqs = NULL;
+#endif
rcu_read_lock();
@@ -82,6 +87,45 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev,
*table = freq_table[0];
+#ifdef CONFIG_CPU_FREQ_BOOST_SW
+ if (of_find_property(dev-of_node, boost-frequencies, len)) {
+ struct cpufreq_frequency_table *ft;
+
+ if (len == 0 || (len (sizeof(u32) - 1)) != 0) {
+ dev_err(dev, %s: invalid boost frequency\n, __func__);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ boost_freqs = kzalloc(len, GFP_KERNEL);
+ if (!boost_freqs) {
+ dev_warn(dev, %s: no memory for boost freq table\n,
+ __func__);
+ ret = -ENOMEM;
+ goto out;
+ }
+ of_property_read_u32_array(dev-of_node, boost-frequencies,
+ boost_freqs, len / sizeof(u32));
+
+ for (j = 0; j len / sizeof(u32); j++) {
+ ft = *table;
+ for (i = 0; ft-frequency != CPUFREQ_TABLE_END; i++) {
+ if (boost_freqs[j] == ft-frequency) {
+ ft-flags |= CPUFREQ_BOOST_FREQ;
+ break;
+ }
+ ft++;
+ }
+
+ if (ft-frequency == CPUFREQ_TABLE_END)
+ pr_err(%s: invalid boost frequency %d\n,
+ __func__, boost_freqs[j]);
+ }
+ }
+
+ kfree(boost_freqs);
+#endif
+
out:
rcu_read_unlock();
if (ret)
--
1.7.9.5
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Re: [PATCH] drm/exynos: add fimd dependency to fimd related encoders
On 2014년 05월 23일 19:59, Andrzej Hajda wrote: DPI, DSI and DP drivers will not work without FIMD. The patch adds appropriate dependencies in Kconfig. Applied. Thanks, Inki Dae Signed-off-by: Andrzej Hajda a.ha...@samsung.com --- drivers/gpu/drm/exynos/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index e0d73fb..178d2a9 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -33,7 +33,7 @@ config DRM_EXYNOS_FIMD config DRM_EXYNOS_DPI bool EXYNOS DRM parallel output support - depends on DRM_EXYNOS + depends on DRM_EXYNOS_FIMD select DRM_PANEL default n help @@ -41,7 +41,7 @@ config DRM_EXYNOS_DPI config DRM_EXYNOS_DSI bool EXYNOS DRM MIPI-DSI driver support - depends on DRM_EXYNOS + depends on DRM_EXYNOS_FIMD select DRM_MIPI_DSI select DRM_PANEL default n @@ -50,7 +50,7 @@ config DRM_EXYNOS_DSI config DRM_EXYNOS_DP bool EXYNOS DRM DP driver support - depends on DRM_EXYNOS ARCH_EXYNOS (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) + depends on DRM_EXYNOS_FIMD ARCH_EXYNOS (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) default DRM_EXYNOS help This enables support for DP device. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms
Changes since v4: - Various changes in clock code suggested by Tomasz Figa t.f...@samsung.com - This series depends on mutiple other patches [a] patch that introduces read-only attribute for clock dividers. - http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/259264.html [b] the series PM / OPP: move cpufreq specific helpers out of OPP layer - https://www.mail-archive.com/linux-omap@vger.kernel.org/msg104610.html [c] the series cpufreq: opp: Add device tree based lookup of boost mode frequency - http://www.spinics.net/lists/arm-kernel/msg334336.html Changes since v3: - Addressed comments from Tomasz Figa t.f...@samsung.com [http://www.spinics.net/lists/cpufreq/msg09290.html] - Rebased to v3.15-rc4 Changes since v2: - Safe operating voltage is not required while switching APLL frequency since the temporary parent's clock is divided down to keep armclk within permissible limits. Thanks to Heiko Stuebner he...@sntech.de for suggesting this. - Rob had suggested to use max frequency for each of the divider clock outputs instead of divider values. But due to certain SoC specific characteristics, the divider values corresponding to the input clock frequency for the CMU_CPU clock blocks have to be used. Changes since v1: - Removes Exynos4x12 and Exynos5250 cpufreq driver also. - Device tree based clock configuration lookup as suggested by Lukasz Majewski and Tomasz Figa. - safe operating point binding reworked as suggested by Shawn Guo. The patch series removes the use of Exynos specific cpufreq driver and enables the use of cpufreq-cpu0 driver for Exynos4210, Exynos4x12 and Exynos5250 based platforms. This is being done for few reasons. (a) The Exynos cpufreq driver reads/writes clock controller registers bypassing the Exynos CCF driver which is sort of problematic. (b) Removes the need for having clock controller register definitions in the cpufreq driver and also removes the need for statically io-remapping clock controller address space (helps in moving towards multiplatform kernel). Thomas Abraham (7): cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies clk: samsung: add infrastructure to register cpu clocks Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq-cpu0 driver cpufreq: exynos: remove all exynos specific cpufreq driver support .../devicetree/bindings/clock/exynos4-clock.txt| 37 ++ .../devicetree/bindings/clock/exynos5250-clock.txt | 36 ++ .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt |2 + arch/arm/boot/dts/exynos4210-origen.dts|6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts|6 + arch/arm/boot/dts/exynos4210.dtsi | 35 ++ arch/arm/boot/dts/exynos4212.dtsi | 18 + arch/arm/boot/dts/exynos4412-odroidx.dts |6 + arch/arm/boot/dts/exynos4412-origen.dts|6 + arch/arm/boot/dts/exynos4412-trats2.dts|6 + arch/arm/boot/dts/exynos4412.dtsi | 31 ++ arch/arm/boot/dts/exynos4x12.dtsi | 36 ++ arch/arm/boot/dts/exynos5250-arndale.dts |6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 41 ++ arch/arm/mach-exynos/exynos.c |4 +- drivers/clk/samsung/Makefile |2 +- drivers/clk/samsung/clk-cpu.c | 448 drivers/clk/samsung/clk-exynos4.c | 25 +- drivers/clk/samsung/clk-exynos5250.c | 16 +- drivers/clk/samsung/clk.h |4 + drivers/cpufreq/Kconfig|1 + drivers/cpufreq/Kconfig.arm| 52 --- drivers/cpufreq/Makefile |4 - drivers/cpufreq/cpufreq-cpu0.c |3 + drivers/cpufreq/exynos-cpufreq.c | 218 -- drivers/cpufreq/exynos-cpufreq.h | 99 - drivers/cpufreq/exynos4210-cpufreq.c | 157 --- drivers/cpufreq/exynos4x12-cpufreq.c | 208 - drivers/cpufreq/exynos5250-cpufreq.c | 183 include/dt-bindings/clock/exynos5250.h |1 + 33 files changed, 779 insertions(+), 936 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c delete mode 100644 drivers/cpufreq/exynos-cpufreq.c delete mode 100644 drivers/cpufreq/exynos-cpufreq.h delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c
Re: [PATCH] drm/exynos: remove redundant mutex_unlock
On 2014년 05월 23일 19:57, Andrzej Hajda wrote:
The patch fixes unlocking in exynos_drm_component_del.
Applied.
Thanks,
Inki Dae
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Hi Inki,
This patch is based on exynos_drm_next branch.
Regards
Andrzej
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 4cef88f..c5a401ae 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -417,7 +417,6 @@ void exynos_drm_component_del(struct device *dev,
if (dev == cdev-dev) {
list_del(cdev-list);
kfree(cdev);
- mutex_unlock(drm_component_lock);
break;
}
}
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[PATCH v5 4/7] clk: exynos: use cpu-clock provider type to represent arm clock
From: Thomas Abraham thomas...@samsung.com
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type and the independent
clock blocks that made up the arm clock can be removed.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 25 +
drivers/clk/samsung/clk-exynos5250.c | 16 +++-
include/dt-bindings/clock/exynos5250.h |1 +
3 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index c4df294..fd235e4 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -471,7 +471,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4210, SRC_CAM, 4, 4),
@@ -530,7 +531,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
MUX(0, mout_jpeg, mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_DMC, 12, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, mout_vpll_p, SRC_TOP0, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4x12, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4x12, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, mout_fimc2, group1_p4x12, SRC_CAM, 8, 4),
@@ -572,8 +574,10 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_core2, div_core, DIV_CPU0, 28, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
DIV(0, div_fimc1, mout_fimc1, DIV_CAM, 4, 4),
DIV(0, div_fimc2, mout_fimc2, DIV_CAM, 8, 4),
@@ -619,8 +623,10 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1005,7 +1011,6 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
static struct samsung_clock_alias exynos4_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
- ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
};
@@ -1244,6 +1249,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_gate_clks));
samsung_clk_register_alias(ctx, exynos4210_aliases,
ARRAY_SIZE(exynos4210_aliases));
+ exynos_register_arm_clock(ctx, CLK_ARM_CLK, mout_core_p4210[0],
+ mout_core_p4210[1], np);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1253,6 +1260,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4x12_gate_clks));
samsung_clk_register_alias(ctx, exynos4x12_aliases,
ARRAY_SIZE(exynos4x12_aliases));
+ exynos_register_arm_clock(ctx, CLK_ARM_CLK, mout_core_p4x12[0],
+ mout_core_p4x12[1], np);
}
samsung_clk_register_alias(ctx, exynos4_aliases,
@@ -1265,7
[PATCH v5 3/7] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5
From: Thomas Abraham thomas...@samsung.com The clock blocks within the CMU_CPU clock domain are put together into a new composite clock type called the cpu clock. This clock type requires configuration data that will be atomically programmed in the multiple clock blocks encapsulated within the cpu clock type when the parent clock frequency is changed. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Tomasz Figa t.f...@samsung.com Cc: Rob Herring robh...@kernel.org Cc: Pawel Moll pawel.m...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: devicet...@vger.kernel.org Signed-off-by: Thomas Abraham thomas...@samsung.com --- .../devicetree/bindings/clock/exynos4-clock.txt| 37 .../devicetree/bindings/clock/exynos5250-clock.txt | 36 +++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19..0934e02 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,35 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock parent frequency + cell #2 ~ cell 9#: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio. + + - for Exynos4412 based platforms: + cell #1: expected arm clock parent frequency + cell #2 ~ cell #10: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, cores_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + + - for Exynos4210 and Exynos4212: the value should be 9. + - for Exynos4412: the value should be 10. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -28,6 +57,14 @@ Example 1: An example of a clock controller node is listed below. compatible = samsung,exynos4210-clock; reg = 0x1003 0x2; #clock-cells = 1; + + samsung,armclk-cells = 9; + samsung,armclk-divider-table = 120 3 7 3 4 1 7 5 0, + 100 3 7 3 4 1 7 4 0, + 80 3 7 3 3 1 7 3 0, + 50 3 7 3 3 1 7 3 0, + 40 3 7 3 3 1 7 3 0, + 20 1 3 1 1 1 0 3 0; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd..3d63d09 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,24 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #9: value of clock divider in the following order + cpud_ratio, acp_ratio,
[PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies
From: Thomas Abraham thomas...@samsung.com
Lookup for the optional boost-frequency property in cpu0 node and if
available, enable support for boost mode frequencies. The frequencies
usable in boost mode are determined while preparing the cpufreq table
from the list of operating points available.
Cc: Shawn Guo shawn@linaro.org
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
.../devicetree/bindings/cpufreq/cpufreq-cpu0.txt |2 ++
drivers/cpufreq/Kconfig|1 +
drivers/cpufreq/cpufreq-cpu0.c |3 +++
3 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
index f055515..60f321a 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
@@ -19,6 +19,8 @@ Optional properties:
- cooling-min-level:
- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
+- boost-frequency:
+ Please refer to
Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
Examples:
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 1fbe11f..52741b9 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -187,6 +187,7 @@ config GENERIC_CPUFREQ_CPU0
tristate Generic CPU0 cpufreq driver
depends on HAVE_CLK REGULATOR OF THERMAL CPU_THERMAL
select PM_OPP
+ select CPU_FREQ_BOOST_SW
help
This adds a generic cpufreq driver for CPU0 frequency management.
It supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
index 1bf6bba..93d3d6d 100644
--- a/drivers/cpufreq/cpufreq-cpu0.c
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -194,6 +194,9 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev)
transition_latency += ret * 1000;
}
+ if (of_find_property(cpu_dev-of_node, boost-frequencies, NULL))
+ cpu0_cpufreq_driver.boost_supported = true;
+
ret = cpufreq_register_driver(cpu0_cpufreq_driver);
if (ret) {
pr_err(failed register driver: %d\n, ret);
--
1.7.9.5
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[PATCH v5 2/7] clk: samsung: add infrastructure to register cpu clocks
From: Thomas Abraham thomas...@samsung.com
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 448 +
drivers/clk/samsung/clk.h |4 +
3 files changed, 453 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..83620a1 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..13fa4c5
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the CPU clocks
+ * for Samsung platforms.
+*/
+
+#include linux/errno.h
+#include clk.h
+
+#define SRC_CPU0x0
+#define STAT_CPU 0x200
+#define DIV_CPU0 0x300
+#define DIV_CPU1 0x304
+#define DIV_STAT_CPU0 0x400
+#define DIV_STAT_CPU1 0x404
+
+#define DIV_CPU0_RATIO0_MASK 0x7
+
+#define MAX_DIV8
+
+#define EXYNOS4210_ARM_DIV1(div) ((div 0x7) + 1)
+#define EXYNOS4210_ARM_DIV2(div) (((div 28) 0x7) + 1)
+
+#define EXYNOS4210_DIV_CPU0(d5, d4, d3, d2, d1, d0)\
+ (((d5) 24) | ((d4) 20) | ((d3) 16) | ((d2) 12) | \
+((d1) 8) | ((d0) 4))
+#define EXYNOS4210_DIV_CPU1(d2, d1, d0)
\
+ (((d2) 8) | ((d1) 4) | ((d0) 0))
+
+#define EXYNOS4210_DIV1_HPM_MASK ((0x7 0) | (0x7 4))
+#define EXYNOS4210_MUX_HPM_MASK(1 20)
+
+/**
+ * struct exynos4210_armclk_data: config data to setup exynos4210 cpu clocks.
+ * @prate: frequency of the parent clock.
+ * @div0: value to be programmed in the div_cpu0 register.
+ * @div1: value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for divider clocks
+ * belonging to the CMU_CPU clock domain. The parent frequency at which these
+ * divider values are valid is specified in @prate.
+ */
+struct exynos4210_armclk_data {
+ unsigned long prate;
+ unsigned intdiv0;
+ unsigned intdiv1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw:handle between CCF and CPU clock.
+ * @alt_parent:alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @offset:offset from the ctrl_base address where the CPU clock div/mux
+ * registers can be accessed.
+ * @clk_nb:clock notifier registered for changes in clock speed of the
+ * primary parent clock.
+ * @lock: register access lock.
+ * @data: optional data which the actual instantiation of this clock
+ * can use.
+ */
+struct exynos_cpuclk {
+ struct clk_hw hw;
+ struct clk *alt_parent;
+ void __iomem*ctrl_base;
+ unsigned long offset;
+ struct notifier_block clk_nb;
+ spinlock_t *lock;
+ void*data;
+};
+
+#define to_exynos_cpuclk_hw(hw) container_of(hw, struct exynos_cpuclk, hw)
+#define to_exynos_cpuclk_nb(nb) container_of(nb, struct exynos_cpuclk, clk_nb)
+
+/**
+ * struct exynos_cpuclk_soc_data: soc specific data for cpu clocks.
+ * @parser:pointer to a function that can parse SoC specific data.
+ * @ops: clock operations to be used for this clock.
+ * @offset:optional offset from base of clock controller register base, to
+ * be used when accessing clock controller registers related to the
+ * CPU clock.
+ * @clk_cb:the clock notifier callback to be called for
[PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support
From: Thomas Abraham thomas...@samsung.com Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched over to use cpufreq-cpu0 driver for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed. Signed-off-by: Thomas Abraham thomas...@samsung.com --- drivers/cpufreq/Kconfig.arm | 52 drivers/cpufreq/Makefile |4 - drivers/cpufreq/exynos-cpufreq.c | 218 -- drivers/cpufreq/exynos-cpufreq.h | 99 --- drivers/cpufreq/exynos4210-cpufreq.c | 157 drivers/cpufreq/exynos4x12-cpufreq.c | 208 drivers/cpufreq/exynos5250-cpufreq.c | 183 7 files changed, 921 deletions(-) delete mode 100644 drivers/cpufreq/exynos-cpufreq.c delete mode 100644 drivers/cpufreq/exynos-cpufreq.h delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 5805035..9721674 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -24,43 +24,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ This add the CPUfreq driver support for Versatile Express big.LITTLE platforms using SPC for power management. - -config ARM_EXYNOS_CPUFREQ - bool - -config ARM_EXYNOS4210_CPUFREQ - bool SAMSUNG EXYNOS4210 - depends on CPU_EXYNOS4210 !ARCH_MULTIPLATFORM - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4210 - SoC (S5PV310 or S5PC210). - - If in doubt, say N. - -config ARM_EXYNOS4X12_CPUFREQ - bool SAMSUNG EXYNOS4x12 - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) !ARCH_MULTIPLATFORM - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4X12 - SoC (EXYNOS4212 or EXYNOS4412). - - If in doubt, say N. - -config ARM_EXYNOS5250_CPUFREQ - bool SAMSUNG EXYNOS5250 - depends on SOC_EXYNOS5250 !ARCH_MULTIPLATFORM - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS5250 - SoC. - - If in doubt, say N. - config ARM_EXYNOS5440_CPUFREQ bool SAMSUNG EXYNOS5440 depends on SOC_EXYNOS5440 @@ -75,21 +38,6 @@ config ARM_EXYNOS5440_CPUFREQ If in doubt, say N. -config ARM_EXYNOS_CPU_FREQ_BOOST_SW - bool EXYNOS Frequency Overclocking - Software - depends on ARM_EXYNOS_CPUFREQ - select CPU_FREQ_BOOST_SW - select EXYNOS_THERMAL - help - This driver supports software managed overclocking (BOOST). - It allows usage of special frequencies for Samsung Exynos - processors if thermal conditions are appropriate. - - It reguires, for safe operation, thermal framework with properly - defined trip points. - - If in doubt, say N. - config ARM_HIGHBANK_CPUFREQ tristate Calxeda Highbank-based depends on ARCH_HIGHBANK GENERIC_CPUFREQ_CPU0 REGULATOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 738c8b7..8a75419 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -51,10 +51,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += davinci-cpufreq.o obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c deleted file mode 100644 index e8a4a7e..000 --- a/drivers/cpufreq/exynos-cpufreq.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - CPU frequency scaling support for EXYNOS series - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include linux/kernel.h -#include linux/err.h -#include linux/clk.h -#include linux/io.h -#include linux/slab.h -#include linux/regulator/consumer.h -#include linux/cpufreq.h -#include linux/platform_device.h -#include linux/of.h - -#include plat/cpu.h - -#include exynos-cpufreq.h - -static struct exynos_dvfs_info *exynos_info;
[PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver
From: Thomas Abraham thomas...@samsung.com
Remove the platform device instantiation for Exynos specific cpufreq
driver and add the platform device for cpufreq-cpu0 driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/mach-exynos/exynos.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 93507ee..2193061 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -184,7 +184,9 @@ void __init exynos_cpuidle_init(void)
void __init exynos_cpufreq_init(void)
{
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ if (!(of_machine_is_compatible(samsung,exynos5420))
+ !(of_machine_is_compatible(samsung,exynos5440)))
+ platform_device_register_simple(cpufreq-cpu0, -1, NULL, 0);
}
void __init exynos_init_late(void)
--
1.7.9.5
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[PATCH] ARM: dts: exynos4: Fix reg sizes of GIC
This patch fixes reg entry sizes in GIC node that were not large enough
to cover whole regions.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8ece4b..fbaf426 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -113,7 +113,7 @@
compatible = arm,cortex-a9-gic;
#interrupt-cells = 3;
interrupt-controller;
- reg = 0x1049 0x1000, 0x1048 0x100;
+ reg = 0x1049 0x1, 0x1048 0x1;
};
combiner: interrupt-controller@1044 {
--
1.9.3
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Re: [PATCH v4 3/8] clk: samsung: add infrastructure to register cpu clocks
Hi Tomasz,
On Fri, May 16, 2014 at 10:47 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Thomas,
On 14.05.2014 03:11, Thomas Abraham wrote:
From: Thomas Abraham thomas...@samsung.com
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 458
+
drivers/clk/samsung/clk.h |5 +
3 files changed, 464 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..e2b453f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..6a40862
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the cpu clocks
+ * for samsung platforms.
s/cpu/CPU/
s/samsung/Samsung/
+*/
+
+#include linux/errno.h
+#include clk.h
+
+#define SRC_CPU 0x0
+#define STAT_CPU 0x200
+#define DIV_CPU0 0x300
+#define DIV_CPU1 0x304
+#define DIV_STAT_CPU00x400
+#define DIV_STAT_CPU10x404
+
+#define MAX_DIV 8
+
+#define EXYNOS4210_ARM_DIV1(div) ((div 0x7) + 1)
+#define EXYNOS4210_ARM_DIV2(div) (((div 28) 0x7) + 1)
+
+#define EXYNOS4210_DIV_CPU0(d5, d4, d3, d2, d1, d0) \
+ ((d5 24) | (d4 20) | (d3 16) | (d2 12) |\
+ (d1 8) | (d0 4))
+#define EXYNOS4210_DIV_CPU1(d2, d1, d0)
\
+ ((d2 8) | (d1 4) | (d0 0))
Macro arguments should be put into parentheses to make sure that whole
argument is subject to further arithmetic operations.
+
+#define EXYNOS4210_DIV1_HPM_MASK ((0x7 0) | (0x7 4))
+#define EXYNOS4210_MUX_HPM_MASK (1 20)
+
+/**
+ * struct exynos4210_armclk_data: config data to setup exynos4210 cpu
clocks.
+ * @prate: frequency of the parent clock.
+ * @div0:value to be programmed in the div_cpu0 register.
+ * @div1:value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for divider clocks
+ * belonging to the CMU_CPU clock domain. The parent frequency at which
these
+ * divider values are vaild is specified in @prate.
s/vaild/valid/
+ */
+struct exynos4210_armclk_data {
+ unsigned long prate;
+ unsigned intdiv0;
+ unsigned intdiv1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw: handle between ccf and cpu clock.
s/ccf/CCF/
s/cpu/CPU/
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @offset: offset from the ctrl_base address where the cpu clock div/mux
s/cpu/CPU/
+ * registers can be accessed.
+ * @clk_nb: clock notifier registered for changes in clock speed of the
+ * primary parent clock.
+ * @lock:register access lock.
+ * @data:optional data which the acutal instantiation of this clock
+ * can use.
s/acutal/actual/
+ */
+struct exynos_cpuclk {
+ struct clk_hw hw;
+ struct clk *alt_parent;
+ void __iomem*ctrl_base;
+ unsigned long offset;
+ struct notifier_block clk_nb;
+ spinlock_t *lock;
+ void*data;
+};
+
+#define to_exynos_cpuclk_hw(hw) container_of(hw, struct exynos_cpuclk, hw)
+#define to_exynos_cpuclk_nb(nb) container_of(nb, struct exynos_cpuclk,
clk_nb)
+
+/**
+ * struct exynos_cpuclk_soc_data: soc specific data for cpu
Re: [PATCH v4 3/8] clk: samsung: add infrastructure to register cpu clocks
Hi Thomas, On 23.05.2014 16:41, Thomas Abraham wrote: [snip] Thanks for your detailed review. I have made all the changes that you have suggested. Unfortunately it seems like you have missed quite a lot of my comments, especially those regarding patch 4/8, which adds DT binding. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: EXYNOS: Fix core ID used by platsmp and hotplug code
When CPU topology is specified in device tree, cpu_logical_map() does
not return core ID anymore, but rather full MPIDR value. This breaks
existing calculation of PMU register offsets on Exynos SoCs.
This patch fixes the problem by adjusting the code to use only core ID
bits of the value returned by cpu_logical_map() to allow CPU topology to
be specified in device tree on Exynos SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/hotplug.c | 10 ++
arch/arm/mach-exynos/platsmp.c | 34 +++---
2 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 69fa483..5644dac 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -40,11 +40,13 @@ static inline void cpu_leave_lowpower(void)
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
+ u32 mpidr = cpu_logical_map(cpu);
+ u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
for (;;) {
- /* make cpu1 to be turned off at next WFI command */
- if (cpu == 1)
- exynos_cpu_power_down(cpu);
+ /* Turn the CPU off on next WFI instruction. */
+ exynos_cpu_power_down(core_id);
/*
* here's the WFI
@@ -54,7 +56,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int
*spurious)
:
: memory, cc);
- if (pen_release == cpu_logical_map(cpu)) {
+ if (pen_release == core_id) {
/*
* OK, proper wakeup, we're done
*/
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 9c16da2..8429c0e 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -112,7 +112,8 @@ static void exynos_secondary_init(unsigned int cpu)
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
- unsigned long phys_cpu = cpu_logical_map(cpu);
+ u32 mpidr = cpu_logical_map(cpu);
+ u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
int ret = -ENOSYS;
/*
@@ -126,17 +127,18 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
-* Note that pen_release is the hardware CPU ID, whereas
+* Note that pen_release is the hardware CPU core ID, whereas
* cpu is Linux's internal ID.
*/
- write_pen_release(phys_cpu);
+ write_pen_release(core_id);
- if (!exynos_cpu_power_state(cpu)) {
- exynos_cpu_power_up(cpu);
+ if (!exynos_cpu_power_state(core_id)) {
+ exynos_cpu_power_up(core_id);
timeout = 10;
/* wait max 10 ms until cpu1 is on */
- while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
+ while (exynos_cpu_power_state(core_id)
+ != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -167,20 +169,20 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
* Try to set boot address using firmware first
* and fall back to boot register if it fails.
*/
- ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
+ ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
if (ret ret != -ENOSYS)
goto fail;
if (ret == -ENOSYS) {
- void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
+ void __iomem *boot_reg = cpu_boot_reg(core_id);
if (IS_ERR(boot_reg)) {
ret = PTR_ERR(boot_reg);
goto fail;
}
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+ __raw_writel(boot_addr, cpu_boot_reg(core_id));
}
- call_firmware_op(cpu_boot, phys_cpu);
+ call_firmware_op(cpu_boot, core_id);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -249,22 +251,24 @@ static void __init exynos_smp_prepare_cpus(unsigned int
max_cpus)
* boot register if it fails.
*/
for (i = 1; i max_cpus; ++i) {
- unsigned long phys_cpu;
unsigned long boot_addr;
+ u32 mpidr;
+ u32 core_id;
int ret;
- phys_cpu = cpu_logical_map(i);
+ mpidr = cpu_logical_map(i);
+ core_id =
[PATCH v2 1/3] ARM: EXYNOS: Consolidate Kconfig entries
Instead of repeating the Kconfig entries for every SoC, move them under ARCH_EXYNOS4 and 5 and move the entries common to both 4 and 5 under ARCH_EXYNOS. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- No changes since v1 --- arch/arm/Kconfig | 10 ++ arch/arm/mach-exynos/Kconfig | 45 -- 2 files changed, 14 insertions(+), 41 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eae853bb7ee5..b8d47ca91406 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -832,18 +832,28 @@ config ARCH_S5PV210 config ARCH_EXYNOS bool Samsung EXYNOS + select ARCH_HAS_BANDGAP select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE + select ARM_AMBA select ARM_GIC + select CLKSRC_OF select COMMON_CLK_SAMSUNG select CPU_V7 select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS + select HAVE_SMP select NEED_MACH_MEMORY_H + select PINCTRL + select PINCTRL_EXYNOS + select PM_GENERIC_DOMAINS if PM_RUNTIME + select S5P_DEV_MFC + select SAMSUNG_DMADEV select SPARSE_IRQ select SRAM select USE_OF diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abce6ec0..138070e42aa9 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -14,30 +14,20 @@ menu SAMSUNG EXYNOS SoCs Support config ARCH_EXYNOS4 bool SAMSUNG EXYNOS4 default y - select ARM_AMBA - select CLKSRC_OF + select ARM_CPU_SUSPEND if PM_SLEEP select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select GIC_NON_BANKED select KEYBOARD_SAMSUNG if INPUT_KEYBOARD - select HAVE_ARM_SCU if SMP - select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select PINCTRL - select PM_GENERIC_DOMAINS if PM_RUNTIME - select S5P_DEV_MFC help - Samsung EXYNOS4 SoCs based systems + Samsung EXYNOS4 (Cortex-A9) SoC based systems config ARCH_EXYNOS5 bool SAMSUNG EXYNOS5 - select ARM_AMBA - select CLKSRC_OF - select HAVE_ARM_SCU if SMP - select HAVE_SMP - select PINCTRL + default y help - Samsung EXYNOS5 (Cortex-A15) SoC based systems + Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems comment EXYNOS SoCs @@ -45,59 +35,32 @@ config CPU_EXYNOS4210 bool SAMSUNG EXYNOS4210 default y depends on ARCH_EXYNOS4 - select ARCH_HAS_BANDGAP - select ARM_CPU_SUSPEND if PM_SLEEP - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS4210 CPU support config SOC_EXYNOS4212 bool SAMSUNG EXYNOS4212 default y depends on ARCH_EXYNOS4 - select ARCH_HAS_BANDGAP - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS4212 SoC support config SOC_EXYNOS4412 bool SAMSUNG EXYNOS4412 default y depends on ARCH_EXYNOS4 - select ARCH_HAS_BANDGAP - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS4412 SoC support config SOC_EXYNOS5250 bool SAMSUNG EXYNOS5250 default y depends on ARCH_EXYNOS5 - select ARCH_HAS_BANDGAP - select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM_RUNTIME - select S5P_DEV_MFC - select SAMSUNG_DMADEV - help - Enable EXYNOS5250 SoC support config SOC_EXYNOS5420 bool SAMSUNG EXYNOS5420 default y depends on ARCH_EXYNOS5 - select PM_GENERIC_DOMAINS if PM_RUNTIME - help - Enable EXYNOS5420 SoC support config SOC_EXYNOS5440 bool SAMSUNG EXYNOS5440 default y depends on ARCH_EXYNOS5 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE - select ARCH_HAS_BANDGAP select ARCH_HAS_OPP select HAVE_ARM_ARCH_TIMER select AUTO_ZRELADDR -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/3] Exynos multi-platform support
The patches in this series were earlier sent as part of other series. Now that the other patches have been merged, re-sending these after rebasing them on linux-next (20140523). Tested on Exynos4210, 4412, 5250 and 5420 based boards. A particular change in this series is the removal of single platform support for Exynos as suggested by Arnd and Olof (patch 2/3). With this change certain features (drivers) which are not yet multi-platform aware like cpufreq, devfreq and DRM based gscaler will not be available now. Changes since v1: Patch 2/3: Dropped some duplicated config symbols as suggested by Arnd. Arnd Bergmann (1): ARM: EXYNOS: Enable multi-platform build support Sachin Kamat (2): ARM: EXYNOS: Consolidate Kconfig entries ARM: multi_v7_defconfig: Enable Exynos platform arch/arm/Kconfig| 20 --- arch/arm/configs/multi_v7_defconfig | 12 +++ arch/arm/mach-exynos/Kconfig| 66 +-- arch/arm/mach-exynos/Makefile |2 ++ arch/arm/plat-samsung/Makefile |3 ++ 5 files changed, 42 insertions(+), 61 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/3] ARM: EXYNOS: Enable multi-platform build support
From: Arnd Bergmann a...@arndb.de This makes it possible to enable the Exynos platform as part of a multiplatform kernel. Signed-off-by: Arnd Bergmann a...@arndb.de Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- Changes since v1: Dropped duplicate config symbols as suggested by Arnd. Updated commit log. --- arch/arm/Kconfig | 30 -- arch/arm/mach-exynos/Kconfig | 21 + arch/arm/mach-exynos/Makefile |2 ++ arch/arm/plat-samsung/Makefile |3 +++ 4 files changed, 26 insertions(+), 30 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b8d47ca91406..a2a0153c94e7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -830,36 +830,6 @@ config ARCH_S5PV210 help Samsung S5PV210/S5PC110 series based systems -config ARCH_EXYNOS - bool Samsung EXYNOS - select ARCH_HAS_BANDGAP - select ARCH_HAS_CPUFREQ - select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_REQUIRE_GPIOLIB - select ARCH_SPARSEMEM_ENABLE - select ARM_AMBA - select ARM_GIC - select CLKSRC_OF - select COMMON_CLK_SAMSUNG - select CPU_V7 - select GENERIC_CLOCKEVENTS - select HAVE_ARM_SCU if SMP - select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG - select HAVE_S3C_RTC if RTC_CLASS - select HAVE_SMP - select NEED_MACH_MEMORY_H - select PINCTRL - select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM_RUNTIME - select S5P_DEV_MFC - select SAMSUNG_DMADEV - select SPARSE_IRQ - select SRAM - select USE_OF - help - Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) - config ARCH_DAVINCI bool TI DaVinci select ARCH_HAS_HOLES_MEMORYMODEL diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 138070e42aa9..7035131a1c99 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -7,6 +7,27 @@ # Configuration options for the EXYNOS4 +config ARCH_EXYNOS + bool Samsung EXYNOS if ARCH_MULTI_V7 + select ARCH_HAS_BANDGAP + select ARCH_HAS_CPUFREQ + select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_GIC + select COMMON_CLK_SAMSUNG + select HAVE_ARM_SCU if SMP + select HAVE_S3C2410_I2C if I2C + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + select PM_GENERIC_DOMAINS if PM_RUNTIME + select S5P_DEV_MFC + select SRAM + help + Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) + if ARCH_EXYNOS menu SAMSUNG EXYNOS SoCs Support diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index df809039b017..6f3608602bfa 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -5,6 +5,8 @@ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include + obj-y := obj-m := obj-n := diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 25c826ed3b65..5e5beaa9ae15 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -4,6 +4,9 @@ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include +ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include + obj-y := obj-m := obj-n := dummy.o -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/3] ARM: multi_v7_defconfig: Enable Exynos platform
Enable Exynos platform and its related IPs. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- No changes since v1. --- arch/arm/configs/multi_v7_defconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 6a27f90ab7bc..bbdcadf642b6 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -48,6 +48,7 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y CONFIG_ARCH_STI=y +CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_SIRF=y CONFIG_ARCH_TEGRA=y @@ -72,6 +73,7 @@ CONFIG_PCI_MSI=y CONFIG_PCI_MVEBU=y CONFIG_PCI_TEGRA=y CONFIG_SMP=y +CONFIG_NR_CPUS=8 CONFIG_HIGHPTE=y CONFIG_CMA=y CONFIG_ARM_APPENDED_DTB=y @@ -160,6 +162,8 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_SIRFSOC=y CONFIG_SERIAL_SIRFSOC_CONSOLE=y CONFIG_SERIAL_TEGRA=y @@ -183,6 +187,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_EXYNOS5=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_SIRF=y CONFIG_I2C_TEGRA=y @@ -218,6 +223,7 @@ CONFIG_MFD_AS3722=y CONFIG_MFD_CROS_EC=y CONFIG_MFD_CROS_EC_SPI=y CONFIG_MFD_MAX8907=y +CONFIG_MFD_SEC_CORE=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS6586X=y @@ -228,6 +234,8 @@ CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS51632=y CONFIG_REGULATOR_TPS62360=y CONFIG_REGULATOR_TPS65090=y @@ -284,12 +292,16 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_PXAV3=y CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_SDHCI_S3C=y CONFIG_MMC_SDHCI_DOVE=y CONFIG_MMC_SDHCI_SPEAR=y +CONFIG_MMC_SDHCI_S3C_DMA=y CONFIG_MMC_SDHCI_BCM_KONA=y CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y CONFIG_MMC_MVSDIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_HIGHBANK_MC=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
Currently Exynos cpufreq drivers rely on globally mapped clock
controller registers to configure frequency of CPU cores. This is
obviously wrong and will be removed in near future, but to enable
support for multi-platform builds without introducing a regression it
needs to be worked around.
This patch hacks the code to look for clock controller node in device
tree and map its registers using of_iomap(), instead of relying on
global mapping, so dependencies on platform headers are removed and the
driver can compile again with multiplatform support.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 6 ++---
drivers/cpufreq/exynos-cpufreq.c | 2 --
drivers/cpufreq/exynos-cpufreq.h | 30 -
drivers/cpufreq/exynos4210-cpufreq.c | 39 +++-
drivers/cpufreq/exynos4x12-cpufreq.c | 40 -
drivers/cpufreq/exynos5250-cpufreq.c | 43 +---
6 files changed, 119 insertions(+), 41 deletions(-)
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 6a7dd3e..36d20d0 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -31,7 +31,7 @@ config ARM_EXYNOS_CPUFREQ
config ARM_EXYNOS4210_CPUFREQ
bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210 !ARCH_MULTIPLATFORM
+ depends on CPU_EXYNOS4210
default y
select ARM_EXYNOS_CPUFREQ
help
@@ -42,7 +42,7 @@ config ARM_EXYNOS4210_CPUFREQ
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
- depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) !ARCH_MULTIPLATFORM
+ depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
default y
select ARM_EXYNOS_CPUFREQ
help
@@ -53,7 +53,7 @@ config ARM_EXYNOS4X12_CPUFREQ
config ARM_EXYNOS5250_CPUFREQ
bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250 !ARCH_MULTIPLATFORM
+ depends on SOC_EXYNOS5250
default y
select ARM_EXYNOS_CPUFREQ
help
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 7c2a096..1e0ec57 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -19,8 +19,6 @@
#include linux/platform_device.h
#include linux/of.h
-#include plat/cpu.h
-
#include exynos-cpufreq.h
static struct exynos_dvfs_info *exynos_info;
diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h
index a28ee9d..8dfebac 100644
--- a/drivers/cpufreq/exynos-cpufreq.h
+++ b/drivers/cpufreq/exynos-cpufreq.h
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
struct cpufreq_frequency_table *freq_table;
void (*set_freq)(unsigned int, unsigned int);
bool (*need_apll_change)(unsigned int, unsigned int);
+ void __iomem*cmu_regs;
};
#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
@@ -77,24 +78,21 @@ static inline int exynos5250_cpufreq_init(struct
exynos_dvfs_info *info)
}
#endif
-#include plat/cpu.h
-#include mach/map.h
+#define EXYNOS4_CLKSRC_CPU 0x14200
+#define EXYNOS4_CLKMUX_STATCPU 0x14400
-#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200)
-#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400)
-
-#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500)
-#define EXYNOS4_CLKDIV_CPU1(S5P_VA_CMU + 0x14504)
-#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1(S5P_VA_CMU + 0x14604)
+#define EXYNOS4_CLKDIV_CPU 0x14500
+#define EXYNOS4_CLKDIV_CPU10x14504
+#define EXYNOS4_CLKDIV_STATCPU 0x14600
+#define EXYNOS4_CLKDIV_STATCPU10x14604
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK(0x7
EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
-#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x0)
-#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100)
-#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400)
-#define EXYNOS5_CLKDIV_CPU0(S5P_VA_CMU + 0x00500)
-#define EXYNOS5_CLKDIV_CPU1(S5P_VA_CMU + 0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0(S5P_VA_CMU + 0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1(S5P_VA_CMU + 0x00604)
+#define EXYNOS5_APLL_LOCK 0x0
+#define EXYNOS5_APLL_CON0 0x00100
+#define EXYNOS5_CLKMUX_STATCPU 0x00400
+#define EXYNOS5_CLKDIV_CPU00x00500
+#define EXYNOS5_CLKDIV_CPU10x00504
+#define EXYNOS5_CLKDIV_STATCPU00x00600
+#define EXYNOS5_CLKDIV_STATCPU10x00604
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index
Re: [PATCH V5 00/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle
On 05/22/2014 08:35 PM, Kukjin Kim wrote: On 04/26/14 20:05, Kukjin Kim wrote: Tomasz Figa wrote: On 14.04.2014 11:01, Daniel Lezcano wrote: Hi Kukjin, I believe I addressed all the comments. Is it possible to take this patchset for next ? Sure ;-) +1. Also when applying you might add Reviewed-by: Tomasz Figat.f...@samsung.com to any patches that don't have it yet. Tomasz, thanks for your review. I will take this series, moving exynos-cpuidle into drivers/cpuidle into samsung tree if Rafael is OK on that. Daniel, Can you please check/test the functionality your series with using my for-next because there were merge conflicts with mcpm-exynos stuff...? Hi Kukjin, I tested the latest tree. Unfortunately it panics when unplugging cpu1: [3.124189] Unable to handle kernel paging request at virtual address f8400024 [3.129950] pgd = c0004000 [3.132626] [f8400024] *pgd=6f7f7841, *pte=, *ppte= [3.138877] Internal error: Oops: 827 [#1] PREEMPT SMP ARM [3.192782] r3 : f8400024 r2 : f8180800 r1 : ee836e44 r0 : f8400024 [3.199293] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [3.206673] Control: 10c5387d Table: 6e37c04a DAC: 0015 [3.212398] Process swapper/0 (pid: 0, stack limit = 0xc0510240) [3.218388] Stack: (0xc0511ef4 to 0xc0512000) [3.222728] 1ee0: 0030 c02b20f8 ee836e40 [3.230894] 1f00: c001234c 6e88 c0511f34 40018a80 0015 [3.239053] 1f20: 4000404a 10c5387d 0041 00f0 c02b20e4 edc4a540 [3.247212] 1f40: c038dacc eefc5cf8 c050ecf0 c0543210 c0012460 0001 c0543210 [3.255371] 1f60: eefc5cf8 c02b2148 b9f92927 c054326c c02b0968 b9f92927 [3.263530] 1f80: c051 c0518480 c038dacc c051 c051 c0518480 c038dacc eefc5cf8 [3.271689] 1fa0: c0543210 c004e990 c0511fb4 c03873b8 c04f90c8 c04d4b18 [3.279848] 1fc0: c04d457c c04f90c8 10c5387d [3.288007] 1fe0: c0518410 c04f90c4 c051bd5c 4000406a 40008074 [3.296184] [c0019c5c] (exynos_enter_aftr) from [c02b20f8] (idle_finisher+0x14/0x20) [3.304247] [c02b20f8] (idle_finisher) from [c001234c] (cpu_suspend_abort+0x0/0x14) [3.312226] [c001234c] (cpu_suspend_abort) from [] ( (null)) [3.318994] Code: e34f3840 e3500010 11a2 01a3 (e5804000) [3.325069] ---[ end trace fca911f75a18c040 ]--- After git bisecting I falls on this commit: commit b3205dea8fbf6db9b1e46a0dad19a0712fdff44f Author: Sachin Kamat sachin.ka...@linaro.org Date: Tue May 13 07:13:44 2014 +0900 ARM: EXYNOS: Map SYSRAM through generic DT bindings Instead of hardcoding the SYSRAM details for each SoC, pass this information through device tree (DT) and make the code SoC agnostic. Generic DT SRAM bindings are used for achieving this. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Heiko Stuebner he...@sntech.de Reviewed-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com ... which is before my series is applied. So I am not able to tell yet if my series is correctly rebased or not. And before someone asks me, yes I updated the dtb :) -- http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro Facebook | http://twitter.com/#!/linaroorg Twitter | http://www.linaro.org/linaro-blog/ Blog -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
2014-05-23 12:35 GMT+02:00 Tarek Dakhran t.dakh...@samsung.com:
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 82
arch/arm/boot/dts/exynos5410.dtsi | 206
+
3 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410,
samsung,exynos5;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ firmware@02037000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x02037000 0x1000;
+ };
+
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+};
+
+uart0 {
+ status = okay;
+};
+
+uart1 {
+ status = okay;
+};
+
+uart2 {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include skeleton.dtsi
+#include dt-bindings/clock/exynos5410.h
+
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+ interrupt-parent = gic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x0;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x1;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x2;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+
Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
Quoting Tarek Dakhran (2014-05-23 03:35:42)
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Quick glance over it. Looks good to me.
Regards,
Mike
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 294 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be samsung,exynos5410-oscclk
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the
clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..69e8177 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c9505ab
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
Re: [PATCH v2 0/3] Exynos multi-platform support
On Friday 23 May 2014, Sachin Kamat wrote: The patches in this series were earlier sent as part of other series. Now that the other patches have been merged, re-sending these after rebasing them on linux-next (20140523). Tested on Exynos4210, 4412, 5250 and 5420 based boards. A particular change in this series is the removal of single platform support for Exynos as suggested by Arnd and Olof (patch 2/3). With this change certain features (drivers) which are not yet multi-platform aware like cpufreq, devfreq and DRM based gscaler will not be available now. Acked-by: Arnd Bergmann a...@arndb.de -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] Samsung 2nd fixes for 3.15
Hi, Here is 2nd samsung fixes for 3.15, actually it happened before 3.14 but would be better if this could be merged into 3.15. Thanks, Kukjin The following changes since commit c9eaa447e77efe77b7fa4c953bd62de8297fd6c5: Linux 3.15-rc1 (2014-04-13 14:18:35 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-fixes-2nd-tag for you to fetch changes up to 68d0e40298f064a5cff40670caded0480274d4b2: ARM: dts: Keep LDO4 always ON for exynos5250-arndale board (2014-05-20 01:15:46 +0900) Samsung-fixes-2 for 3.15 - keep LD04 always on for exynos5250-arndale - fix spi interrupt numbers for exynos5420 - fix ak8975 compatible for exynos4412-trats2 Beomho Seo (1): ARM: dts: fix incorrect ak8975 compatible for exynos4412-trats2 board Sachin Kamat (2): ARM: dts: Fix SPI interrupt numbers for exynos5420 ARM: dts: Keep LDO4 always ON for exynos5250-arndale board arch/arm/boot/dts/exynos4412-trats2.dts | 2 +- arch/arm/boot/dts/exynos5250-arndale.dts | 1 + arch/arm/boot/dts/exynos5420.dtsi| 6 +++--- 3 files changed, 5 insertions(+), 4 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/3] Exynos multi-platform support
On 05/24/14 04:17, Arnd Bergmann wrote: On Friday 23 May 2014, Sachin Kamat wrote: The patches in this series were earlier sent as part of other series. Now that the other patches have been merged, re-sending these after rebasing them on linux-next (20140523). Tested on Exynos4210, 4412, 5250 and 5420 based boards. A particular change in this series is the removal of single platform support for Exynos as suggested by Arnd and Olof (patch 2/3). With this change certain features (drivers) which are not yet multi-platform aware like cpufreq, devfreq and DRM based gscaler will not be available now. Acked-by: Arnd Bergmanna...@arndb.de Yes, it's time to move on exynos multiplatform and we can't wait for more perfect something. Anyway if any problems, let's fix them after this. Will apply this whole series. Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Add 5800 SoC support
On 05/23/14 16:34, Arun Kumar K wrote: Exynos5800 is an octa core SoC which is based on the 5420 platform. This patch adds the basic support for it in the mach-exynos. Signed-off-by: Arun Kumar Karun...@samsung.com --- arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/platsmp.c |2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4663417..c5423da 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -99,6 +99,11 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config SOC_EXYNOS5800 + bool SAMSUNG EXYNOS5800 + default y + depends on SOC_EXYNOS5420 + endmenu config EXYNOS5420_MCPM diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ae5f648..8fbc55b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -23,6 +23,7 @@ #define EXYNOS5250_SOC_ID 0x4352 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 +#define EXYNOS5800_SOC_ID 0xE5422000 #define EXYNOS5_SOC_MASK 0xF000 extern unsigned long samsung_cpu_id; @@ -39,6 +40,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() @@ -80,9 +82,16 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5440() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5800) +# define soc_is_exynos5800() is_samsung_exynos5800() +#else +# define soc_is_exynos5800() 0 +#endif + #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ + soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 9c16da2..112bc66 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -70,7 +70,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) return ERR_PTR(-ENODEV); if (soc_is_exynos4412()) boot_reg += 4*cpu; - else if (soc_is_exynos5420()) + else if (soc_is_exynos5420() || soc_is_exynos5800()) boot_reg += 4; return boot_reg; } + Arnd, Olof Hmm...yeah, 5800 doesn't boot without this and 3250 is also same situation. In this time, soc_is_exynos() is required and I think, we need to sort it out next time. Let's do one by one...;) Arnd, Olof how do you think about this? I agree with Olof's suggestion that we need to add only dt for new SoC but we need more time... Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Add 5800 SoC support
On Fri, May 23, 2014 at 1:05 PM, Kukjin Kim kgene@samsung.com wrote: On 05/23/14 16:34, Arun Kumar K wrote: Exynos5800 is an octa core SoC which is based on the 5420 platform. This patch adds the basic support for it in the mach-exynos. Signed-off-by: Arun Kumar Karun...@samsung.com --- arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/platsmp.c |2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4663417..c5423da 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -99,6 +99,11 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config SOC_EXYNOS5800 + bool SAMSUNG EXYNOS5800 + default y + depends on SOC_EXYNOS5420 + endmenu config EXYNOS5420_MCPM diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ae5f648..8fbc55b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -23,6 +23,7 @@ #define EXYNOS5250_SOC_ID 0x4352 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 +#define EXYNOS5800_SOC_ID 0xE5422000 #define EXYNOS5_SOC_MASK 0xF000 extern unsigned long samsung_cpu_id; @@ -39,6 +40,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() @@ -80,9 +82,16 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5440() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5800) +# define soc_is_exynos5800() is_samsung_exynos5800() +#else +# define soc_is_exynos5800() 0 +#endif + #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ + soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 9c16da2..112bc66 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -70,7 +70,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) return ERR_PTR(-ENODEV); if (soc_is_exynos4412()) boot_reg += 4*cpu; - else if (soc_is_exynos5420()) + else if (soc_is_exynos5420() || soc_is_exynos5800()) boot_reg += 4; return boot_reg; } + Arnd, Olof Hmm...yeah, 5800 doesn't boot without this and 3250 is also same situation. In this time, soc_is_exynos() is required and I think, we need to sort it out next time. Let's do one by one...;) Arnd, Olof how do you think about this? I agree with Olof's suggestion that we need to add only dt for new SoC but we need more time... As long as you follow through on the cleanups I'm ok with it. In the past, that has not always been the case. I'm willing to give you one more (last) chance. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] devicetree: Add generic IOMMU device tree bindings
From: Thierry Reding tred...@nvidia.com This commit introduces a generic device tree binding for IOMMU devices. Only a very minimal subset is described here, but it is enough to cover the requirements of both the Exynos System MMU and Tegra SMMU as discussed here: https://lkml.org/lkml/2014/4/27/346 Signed-off-by: Thierry Reding tred...@nvidia.com --- Apologies for the noise, but apparently I mistyped one of the email addresses, should be fixed now. Changes in v2: - add notes about dma-ranges property (drop note from commit message) - document priorities of iommus property vs. dma-ranges property - drop #iommu-cells in favour of #address-cells and #size-cells - remove multiple-master device example Documentation/devicetree/bindings/iommu/iommu.txt | 167 ++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt new file mode 100644 index ..6ce759afcc94 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/iommu.txt @@ -0,0 +1,167 @@ +This document describes the generic device tree binding for IOMMUs and their +master(s). + + +IOMMU device node: +== + +An IOMMU can provide the following services: + +* Remap address space to allow devices to access physical memory ranges that + they otherwise wouldn't be capable of accessing. + + Example: 32-bit DMA to 64-bit physical addresses + +* Implement scatter-gather at page level granularity so that the device does + not have to. + +* Provide system protection against rogue DMA by forcing all accesses to go + through the IOMMU and faulting when encountering accesses to unmapped + address regions. + +* Provide address space isolation between multiple contexts. + + Example: Virtualization + +Device nodes compatible with this binding represent hardware with some of the +above capabilities. + +IOMMUs can be single-master or multiple-master. Single-master IOMMU devices +typically have a fixed association to the master device, whereas multiple- +master IOMMU devices can translate accesses from more than one master. + +The device tree node of the IOMMU device's parent bus must contain a valid +dma-ranges property that describes how the physical address space of the +IOMMU maps to memory. An empty dma-ranges property means that there is a +1:1 mapping from IOMMU to memory. + +Required properties: + +- #address-cells: The number of cells in an IOMMU specifier needed to encode + an address. +- #size-cells: The number of cells in an IOMMU specifier needed to represent + the length of an address range. + +Typical values for the above include: +- #address-cells = 0, size-cells = 0: Single master IOMMU devices are not + configurable and therefore no additional information needs to be encoded in + the specifier. This may also apply to multiple master IOMMU devices that do + not allow the association of masters to be configured. +- #address-cells = 1, size-cells = 0: Multiple master IOMMU devices may + need to be configured in order to enable translation for a given master. In + such cases the single address cell corresponds to the master device's ID. +- #address-cells = 2, size-cells = 2: Some IOMMU devices allow the DMA + window for masters to be configured. The first cell of the address in this + may contain the master device's ID for example, while the second cell could + contain the start of the DMA window for the given device. The length of the + DMA window is specified by two additional cells. + + +IOMMU master node: +== + +Devices that access memory through an IOMMU are called masters. A device can +have multiple master interfaces (to one or more IOMMU devices). + +Required properties: + +- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU + master interfaces of the device. One entry in the list describes one master + interface of the device. + +When an iommus property is specified in a device tree node, the IOMMU will +be used for address translation. If a dma-ranges property exists in the +device's parent node it will be ignored. An exception to this rule is if the +referenced IOMMU is disabled, in which case the dma-ranges property of the +parent shall take effect. + +Optional properties: + +- iommu-names: A list of names identifying each entry in the iommus + property. + + +Notes: +== + +One possible extension to the above is to use an iommus property along with +a dma-ranges property in a bus device node (such as PCI host bridges). This +can be useful to describe how children on the bus relate to the IOMMU if they +are not explicitly listed in the device tree (e.g. PCI devices). However, the +requirements of that use-case haven't been fully determined yet. Implementing +this is therefore not recommended without further
Re: [PATCH v2 0/3] Exynos multi-platform support
Hi Kukjin, On 23.05.2014 21:48, Kukjin Kim wrote: On 05/24/14 04:17, Arnd Bergmann wrote: On Friday 23 May 2014, Sachin Kamat wrote: The patches in this series were earlier sent as part of other series. Now that the other patches have been merged, re-sending these after rebasing them on linux-next (20140523). Tested on Exynos4210, 4412, 5250 and 5420 based boards. A particular change in this series is the removal of single platform support for Exynos as suggested by Arnd and Olof (patch 2/3). With this change certain features (drivers) which are not yet multi-platform aware like cpufreq, devfreq and DRM based gscaler will not be available now. Acked-by: Arnd Bergmanna...@arndb.de Yes, it's time to move on exynos multiplatform and we can't wait for more perfect something. Anyway if any problems, let's fix them after this. Will apply this whole series. I have tested v1 of this series on Exynos4210-TRATS and Exynos4412-TRATS2 boards and they seemed to work fine with added two patches that are already on the ML: - [PATCH v2] cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM, - [PATCH] drm/exynos/fimd: allow multiplatform configuration. Not tested too extensively, but primary features (boot, display, USB gadget, cpufreq) seem to work at first glance with the above patches. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Add 5800 SoC support
Hi Arun, On 23.05.2014 09:34, Arun Kumar K wrote: Exynos5800 is an octa core SoC which is based on the 5420 platform. This patch adds the basic support for it in the mach-exynos. Signed-off-by: Arun Kumar K arun...@samsung.com --- arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/platsmp.c |2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4663417..c5423da 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -99,6 +99,11 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config SOC_EXYNOS5800 + bool SAMSUNG EXYNOS5800 + default y + depends on SOC_EXYNOS5420 + endmenu config EXYNOS5420_MCPM diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ae5f648..8fbc55b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -23,6 +23,7 @@ #define EXYNOS5250_SOC_ID0x4352 #define EXYNOS5420_SOC_ID0xE542 #define EXYNOS5440_SOC_ID0xE544 +#define EXYNOS5800_SOC_ID0xE5422000 #define EXYNOS5_SOC_MASK 0xF000 extern unsigned long samsung_cpu_id; @@ -39,6 +40,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() @@ -80,9 +82,16 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5440() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5800) +# define soc_is_exynos5800() is_samsung_exynos5800() +#else +# define soc_is_exynos5800() 0 +#endif + #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ + soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 9c16da2..112bc66 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -70,7 +70,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) return ERR_PTR(-ENODEV); if (soc_is_exynos4412()) boot_reg += 4*cpu; - else if (soc_is_exynos5420()) + else if (soc_is_exynos5420() || soc_is_exynos5800()) boot_reg += 4; return boot_reg; } Isn't this SoC a multi-cluster one? Shouldn't it rather use MCPM SMP ops and so the code being changed here be ignored completely? Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/mach-exynos/Kconfig|8 arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/firmware.c |2 +- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abc..79a3e85 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,14 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5410 + bool SAMSUNG EXYNOS5410 + default y + depends on ARCH_EXYNOS5 + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Enable EXYNOS5410 SoC support + config SOC_EXYNOS5420 bool SAMSUNG EXYNOS5420 default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e2d0954..d64c6de 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -21,6 +21,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID0x4352 +#define EXYNOS5410_SOC_ID0xE541 #define EXYNOS5420_SOC_ID0xE542 #define EXYNOS5440_SOC_ID0xE544 #define EXYNOS5_SOC_MASK 0xF000 @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Hi Tarek, On 23.05.2014 12:35, Tarek Dakhran wrote: Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/boot/dts/Makefile|1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 82 arch/arm/boot/dts/exynos5410.dtsi | 206 + 3 files changed, 289 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi Looks good. Hopefully we can have this patch applied soon, so it won't get outdated again. Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
Hi Tarek,
Thanks for keeping up with addressing my comments. See below.
On 23.05.2014 12:35, Tarek Dakhran wrote:
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 294 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
The driver itself looks good, but binding documentation seems to be
outdated. The part about external clocks, more specifically.
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be samsung,exynos5410-oscclk
^
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
^
Best regards,
Tomasz
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Re: [PATCH 1/3] ARM: EXYNOS: Add support for clock handling in power domain
Hi,
On 23.05.2014 07:08, Arun Kumar K wrote:
From: Prathyush K prathyus...@samsung.com
While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
(aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on a
domain everytime.
This patch adds the framework for getting the required mux and parent clocks
through a power domain device node. With this patch, while powering off
a domain, parent is set to oscclk and while powering back on, its re-set
to the correct parent which is as per the recommended pd on/off
sequence.
Signed-off-by: Prathyush K prathyus...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../bindings/arm/exynos/power_domain.txt | 18 +++
arch/arm/mach-exynos/pm_domains.c | 56
+++-
2 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b41..168a191 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,16 @@ Required Properties:
- reg: physical base address of the controller and length of memory mapped
region.
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+ devices in this power domain are set to oscclk before power gating and
+ restored back after powering on a domain. This is required for all domains
+ which are powered on and off and not required for unused domains.
I'd keep it required to all domains that exhibit this behavior, as
device tree should expose complete information about the hardware
whenever possible.
+ The following clocks can be specified:
+ - oscclk: oscillator clock.
+ - clk(n): input clock to the devices in this power domain
s/clk(n)/clkN/
+ - pclk(n): parent clock of input clock to the devices in this power domain
s/pclk(n)/pclkN/
The meaning of N should be described and the relation between clkN and
pclkN with the same value of N.
Also shouldn't this rather be a description of clock-names property?
+
Node of a device using power domains must have a samsung,power-domain
property
defined with a phandle to respective power domain.
@@ -19,6 +29,14 @@ Example:
reg = 0x10023C00 0x10;
};
+ mfc_pd: power-domain@10044060 {
+ compatible = samsung,exynos4210-pd;
+ reg = 0x10044060 0x20;
+ clocks = clock CLK_FIN_PLL, clock CLK_MOUT_SW_ACLK333,
+ clock CLK_MOUT_USER_ACLK333;
+ clock-names = oscclk, pclk0, clk0;
+ };
+
Example of the node using power domain:
node {
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index fe6570e..e5fe76d 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -17,6 +17,7 @@
#include linux/err.h
#include linux/slab.h
#include linux/pm_domain.h
+#include linux/clk.h
#include linux/delay.h
#include linux/of_address.h
#include linux/of_platform.h
@@ -24,6 +25,8 @@
#include regs-pmu.h
+#define MAX_CLK_PER_DOMAIN 4
+
/*
* Exynos specific wrapper around the generic power domain
*/
@@ -32,6 +35,9 @@ struct exynos_pm_domain {
char const *name;
bool is_off;
struct generic_pm_domain pd;
+ struct clk *oscclk;
+ struct clk *clk[MAX_CLK_PER_DOMAIN];
+ struct clk *pclk[MAX_CLK_PER_DOMAIN];
};
static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -44,6 +50,18 @@ static int exynos_pd_power(struct generic_pm_domain
*domain, bool power_on)
pd = container_of(domain, struct exynos_pm_domain, pd);
base = pd-base;
+ /* Set oscclk before powering off a domain*/
+ if (!power_on) {
+ int i;
+ for (i = 0; i MAX_CLK_PER_DOMAIN; i++) {
+ if (!pd-clk[i])
+ break;
Clock handles should be checked for validity using IS_ERR() macro (as
most of opaque handles, which should not be considered pointers, even if
they have a pointer type).
+ if (clk_set_parent(pd-clk[i], pd-oscclk))
+ pr_info(%s: error setting oscclk as parent to
clock %d\n,
+ pd-name, i);
pr_err()?
+ }
+ }
+
pwr =
Re: [PATCH 2/3] clk: exynos5420: Add IDs for clocks used in PD mfc
Hi Arun,
On 23.05.2014 07:08, Arun Kumar K wrote:
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K arun...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c |6 --
include/dt-bindings/clock/exynos5420.h |2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7ee..c899dbe 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP4, 16, 1),
MUX(0, mout_user_aclk266, mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, mout_user_aclk166, mout_user_aclk166_p, SRC_TOP4, 24, 1),
- MUX(0, mout_user_aclk333, mout_user_aclk333_p, SRC_TOP4, 28, 1),
+ MUX(CLK_MOUT_USER_ACLK333, mout_user_aclk333, mout_user_aclk333_p,
+ SRC_TOP4, 28, 1),
Please keep the indentation consistent. As you can see below, just two
extra tabs are used on wrapped lines.
MUX(0, mout_user_aclk400_disp1, mout_user_aclk400_disp1_p,
SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP11, 12, 1),
MUX(0, mout_sw_aclk266, mout_sw_aclk266_p, SRC_TOP11, 20, 1),
MUX(0, mout_sw_aclk166, mout_sw_aclk166_p, SRC_TOP11, 24, 1),
- MUX(0, mout_sw_aclk333, mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+ MUX(CLK_MOUT_SW_ACLK333, mout_sw_aclk333, mout_sw_aclk333_p,
+ SRC_TOP11, 28, 1),
Ditto.
Best regards,
Tomasz
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Re: [PATCH 3/3] ARM: dts: Add clock property for mfc_pd in 5420
On 23.05.2014 07:08, Arun Kumar K wrote:
Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: Arun Kumar K arun...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 5a85896..890bdac 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -260,6 +260,9 @@
mfc_pd: power-domain@10044060 {
compatible = samsung,exynos4210-pd;
reg = 0x10044060 0x20;
+ clocks = clock CLK_FIN_PLL, clock CLK_MOUT_SW_ACLK333,
+ clock CLK_MOUT_USER_ACLK333,;
+ clock-names = oscclk, pclk0, clk0;
};
disp_pd: power-domain@100440C0 {
Reviewed-by: Tomasz Figa t.f...@samsung.com
Best regards,
Tomasz
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Re: [GIT PULL] Samsung 2nd fixes for 3.15
On Friday 23 May 2014, Kukjin Kim wrote: Hi, Here is 2nd samsung fixes for 3.15, actually it happened before 3.14 but would be better if this could be merged into 3.15. Thanks, Kukjin The following changes since commit c9eaa447e77efe77b7fa4c953bd62de8297fd6c5: Linux 3.15-rc1 (2014-04-13 14:18:35 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-fixes-2nd-tag for you to fetch changes up to 68d0e40298f064a5cff40670caded0480274d4b2: ARM: dts: Keep LDO4 always ON for exynos5250-arndale board (2014-05-20 01:15:46 +0900) Samsung-fixes-2 for 3.15 - keep LD04 always on for exynos5250-arndale - fix spi interrupt numbers for exynos5420 - fix ak8975 compatible for exynos4412-trats2 Pulled into fixes branch. Should these have been marked 'Cc: stable'? Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Hi Tomazs, On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: [snip] diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); I need to define SoC type to set correct bootreg in firmware, otherwise only one cpu can be booted. So, this stuff is needed. Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
On 24.05.2014 00:44, Tarek Dakhran wrote: Hi Tomazs, On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: [snip] diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); I need to define SoC type to set correct bootreg in firmware, otherwise only one cpu can be booted. So, this stuff is needed. The patch I referred to in my previous reply changes this condition from !soc_is_exynos4212() to soc_is_exynos4412(), which makes the 4*cpu offset being added only in case of Exynos4412 (and so not being added for Exynos5410). What else is needed? Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Sorry, only now catch it! I agree, this patch is not needed anymore, except Kconfig option. config SOC_EXYNOS5410 is needed to build clock stuff. What is your opinion, Tomasz? On Sat, May 24, 2014 at 2:44 AM, Tarek Dakhran t.dakh...@gmail.com wrote: Hi Tomazs, On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: [snip] diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); I need to define SoC type to set correct bootreg in firmware, otherwise only one cpu can be booted. So, this stuff is needed. Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/3] clk: s2mps11: Fixes and add support for S2MPS14 clocks
Quoting Krzysztof Kozlowski (2014-05-21 04:22:58) Hi, This is actually a resend of previous patches, rebased on latest 3.15-rc5. There are no changes, beside rebasing. The first two fixes were posted previously as separate patches and they didn't get review [1]. I am attaching them here. The last patch adds support for S2MPS14 device and already was reviewed/acked [2]. Mike, could you pick them up or should they go through MFD tree? Applied to clk-next. Regards, Mike [1] https://lkml.org/lkml/2014/4/7/42 [2] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/28039/focus=310279 Changes since v3: = 1. Add Mike's acked-by (see [2]). 2. Rebase patch 3/3 on the fixes (patches 1 and 2). 3. Rebase on v3.15-rc5-157-g60b5f90d0fac Changes since v2: = 1. Patch 2/3: Remove MFD cells of_compatible which aren't used by child drivers and are not documented. 2. Added Tomasz's Review-by. Changes since v1: = 1. Patch 1/3: Update driver description in Kconfig. 2. Patch 2/3: Add of_compatible to all MFD cells. 3. Add Yadwinder's Review-by. Best regards, Krzysztof Krzysztof Kozlowski (3): clk: s2mps11: Add missing of_node_put and of_clk_del_provider clk: s2mps11: Remove useless check for clk_table clk: s2mps11: Add support for S2MPS14 clocks drivers/clk/Kconfig | 8 ++--- drivers/clk/clk-s2mps11.c | 88 +-- 2 files changed, 66 insertions(+), 30 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
This is just my inattention. Will be corrected until Monday. On Sat, May 24, 2014 at 1:19 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, Thanks for keeping up with addressing my comments. See below. On 23.05.2014 12:35, Tarek Dakhran wrote: The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 4 files changed, 294 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h The driver itself looks good, but binding documentation seems to be outdated. The part about external clocks, more specifically. diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt new file mode 100644 index 000..82337c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt @@ -0,0 +1,51 @@ +* Samsung Exynos5410 Clock Controller + +The Exynos5410 clock controller generates and supplies clock to various +controllers within the Exynos5410 SoC. + +Required Properties: + +- compatible: should be samsung,exynos5410-clock + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5410.h header and can be used in device +tree sources. + +External clock: +There is clock that is generated outside the SoC. It is expected +that it is defined using standard clock bindings with following + - compatible: should be samsung,exynos5410-oscclk ^ Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
On 24.05.2014 00:48, Tarek Dakhran wrote: Sorry, only now catch it! I agree, this patch is not needed anymore, except Kconfig option. config SOC_EXYNOS5410 is needed to build clock stuff. Right, I missed this. What is your opinion, Tomasz? I'd suggest re-spinning this series once more, removing changes that are not needed anymore, but keeping the Kconfig entry. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode
On 20 May 2014 09:20, Tushar Behera tushar.beh...@linaro.org wrote: From: Sachin Kamat sachin.ka...@linaro.org Almost all Exynos-series of SoCs that run in secure mode don't need additional offset for every CPU, with Exynos4412 being the only exception. Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420). While at it, fix the coding style (space around *). Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Tushar Behera tushar.beh...@linaro.org --- Changes for V2: * Changed the condition statement as per review comment * Fixed coding style arch/arm/mach-exynos/firmware.c |9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..7d18103 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,8 +50,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) - boot_reg += 4*cpu; + /* +* Almost all Exynos-series of SoCs that run in secure mode don't need +* additional offset for every CPU, with Exynos4412 being the only +* exception. +*/ + if (soc_is_exynos4412()) + boot_reg += 4 * cpu; __raw_writel(boot_addr, boot_reg); return 0; -- 1.7.9.5 Kukjin, This series is required for properly booting A15 cores on Arndale octa. Please apply them. -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V5 00/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle
On 24 May 2014 03:01, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Daniel, On 23.05.2014 17:32, Daniel Lezcano wrote: On 05/22/2014 08:35 PM, Kukjin Kim wrote: On 04/26/14 20:05, Kukjin Kim wrote: Tomasz Figa wrote: On 14.04.2014 11:01, Daniel Lezcano wrote: Hi Kukjin, I believe I addressed all the comments. Is it possible to take this patchset for next ? Sure ;-) +1. Also when applying you might add Reviewed-by: Tomasz Figat.f...@samsung.com to any patches that don't have it yet. Tomasz, thanks for your review. I will take this series, moving exynos-cpuidle into drivers/cpuidle into samsung tree if Rafael is OK on that. Daniel, Can you please check/test the functionality your series with using my for-next because there were merge conflicts with mcpm-exynos stuff...? Hi Kukjin, I tested the latest tree. Unfortunately it panics when unplugging cpu1: [3.124189] Unable to handle kernel paging request at virtual address f8400024 [3.129950] pgd = c0004000 [3.132626] [f8400024] *pgd=6f7f7841, *pte=, *ppte= [3.138877] Internal error: Oops: 827 [#1] PREEMPT SMP ARM [3.192782] r3 : f8400024 r2 : f8180800 r1 : ee836e44 r0 : f8400024 [3.199293] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [3.206673] Control: 10c5387d Table: 6e37c04a DAC: 0015 [3.212398] Process swapper/0 (pid: 0, stack limit = 0xc0510240) [3.218388] Stack: (0xc0511ef4 to 0xc0512000) [3.222728] 1ee0: 0030 c02b20f8 ee836e40 [3.230894] 1f00: c001234c 6e88 c0511f34 40018a80 0015 [3.239053] 1f20: 4000404a 10c5387d 0041 00f0 c02b20e4 edc4a540 [3.247212] 1f40: c038dacc eefc5cf8 c050ecf0 c0543210 c0012460 0001 c0543210 [3.255371] 1f60: eefc5cf8 c02b2148 b9f92927 c054326c c02b0968 b9f92927 [3.263530] 1f80: c051 c0518480 c038dacc c051 c051 c0518480 c038dacc eefc5cf8 [3.271689] 1fa0: c0543210 c004e990 c0511fb4 c03873b8 c04f90c8 c04d4b18 [3.279848] 1fc0: c04d457c c04f90c8 10c5387d [3.288007] 1fe0: c0518410 c04f90c4 c051bd5c 4000406a 40008074 [3.296184] [c0019c5c] (exynos_enter_aftr) from [c02b20f8] (idle_finisher+0x14/0x20) [3.304247] [c02b20f8] (idle_finisher) from [c001234c] (cpu_suspend_abort+0x0/0x14) [3.312226] [c001234c] (cpu_suspend_abort) from [] ( (null)) [3.318994] Code: e34f3840 e3500010 11a2 01a3 (e5804000) [3.325069] ---[ end trace fca911f75a18c040 ]--- After git bisecting I falls on this commit: commit b3205dea8fbf6db9b1e46a0dad19a0712fdff44f Author: Sachin Kamat sachin.ka...@linaro.org Date: Tue May 13 07:13:44 2014 +0900 ARM: EXYNOS: Map SYSRAM through generic DT bindings Instead of hardcoding the SYSRAM details for each SoC, pass this information through device tree (DT) and make the code SoC agnostic. Generic DT SRAM bindings are used for achieving this. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Heiko Stuebner he...@sntech.de Reviewed-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com ... which is before my series is applied. So I am not able to tell yet if my series is correctly rebased or not. And before someone asks me, yes I updated the dtb :) The driver seemed to be working fine for me on Exynos4210-TRATS board (with right bootloader, which supports AFTR). Still, a quick look at the code reveals use of S5P_VA_SYSRAM macro, in case of certain SoC revisions, which is not valid any longer, after SYSRAM started to be mapped dynamically. As you can see in platsmp.c, the new dynamic mapping is stored in sysram_base_addr variable, which is static right now. My proposed fix would be to make it non-static, declare it in one of existing private headers (common.h probably) and use it in pm.c instead of S5P_VA_SYSRAM. Yes, that is right. Just like the way it is done for sysram_ns_base_addr in common.h -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
