Re: [PATCH v4 4/8] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5

[Thomas Abraham]

Hi Tomasz,

Thanks for your comments. Please see inline reply.

On Sat, May 17, 2014 at 4:54 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Thomas,

 Please see my comments inline.

 On 14.05.2014 03:11, Thomas Abraham wrote:
 From; Thomas Abraham thomas...@samsung.com

 The clock blocks within the CMU_CPU clock domain are put together into a
 new composite clock type called the cpu clock. This clock type requires
 configuration data that will be atomically programmed in the multiple
 clock blocks encapsulated within the cpu clock type when the parent clock
 frequency is changed. This configuration data is held in the clock controller
 node. Update clock binding documentation about this configuration data format
 for Samsung Exynos4 and Exynos5 platforms.

 Cc: Tomasz Figa t.f...@samsung.com
 Cc: Rob Herring robh...@kernel.org
 Cc: Pawel Moll pawel.m...@arm.com
 Cc: Mark Rutland mark.rutl...@arm.com
 Cc: Ian Campbell ijc+devicet...@hellion.org.uk
 Cc: Kumar Gala ga...@codeaurora.org
 Cc: devicet...@vger.kernel.org
 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  .../devicetree/bindings/clock/exynos4-clock.txt|   37 
 
  .../devicetree/bindings/clock/exynos5250-clock.txt |   36 
 +++
  2 files changed, 73 insertions(+), 0 deletions(-)

 diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt 
 b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
 index f5a5b19..0934e02 100644
 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
 +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
 @@ -15,6 +15,35 @@ Required Properties:

  - #clock-cells: should be 1.

 +- samsung,armclk-divider-table: when the frequency of the APLL is changed
 +  the divider clocks in CMU_CPU clock domain also need to be updated. These
 +  divider clocks have SoC specific divider clock output requirements for a
 +  specific APLL clock speeds. When APLL clock rate is changed, these divider
 +  clocks are reprogrammed with pre-determined values in order to maintain 
 the
 +  SoC specific divider clock outputs. This property lists the divider values
 +  for divider clocks in the CMU_CPU block for supported APLL clock speeds.
 +  The format of each entry included in the arm-frequency-table should be
 +  as defined below

 As far as I understand, the relation is not between the APLL frequency
 and particular clocks in CPU domain, but rather between the latter and
 input clock to CPU domain, which is _after_ the two dividers (called
 DIV_CORE and DIV_CORE2 or ARM_DIV1 and ARM_DIV2), which is also exactly
 the output frequency of ARMCLK.

 +
 +  - for Exynos4210 and Exynos4212 based platforms:
 +  cell #1: arm clock parent frequency

 Considering my comment above, this should be rather ARMCLK frequency.

The clocks SCLK_APLL, SCLK_HPM, ATCLK and PCLK_DBG have no relation to
the ARMCLK frequency. These clocks are directly derived from the PLL
clock and so it would not be correct to have them related to ARMCLK.

So, I see two solutions to this, first being preferred solution.

[A] Cell #1 should define PLL (parent of armclk) clock speed. Cell #2
and Cell #3  should define divider values for ARMCLK clock speed. The
hardware does support PLL frequency != ARMCLK frequency and so DT
binding should allow that (even though implementation in the linux
kernel does not use this feature). BTW, this was what was done in v2
of this series.

[B] Embedded this data with the code and don't get this from DT. The
reason for doing this is, these are SoC specific values and not board
specific. And when we are clear about what we want to put in DT, have
a provision to lookup DT first and if DT values are not found,
fallback on data embedded with the code.

Thanks,
Thomas.


 +  cell #2 ~ cell 9#: value of clock divider in the following order
 + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio,
 + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio.
 +
 +  - for Exynos4412 based platforms:
 +  cell #1: expected arm clock parent frequency

 Ditto.

 +  cell #2 ~ cell #10: value of clock divider in the following order
 +corem0_ratio, corem1_ratio, periph_ratio, atb_ratio,
 +   pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, 
 cores_ratio
 +
 +- samsung,armclk-cells: defines the number of cells in
 +  samsung,armclk-divider-table property. The value of this property depends 
 on
 +  the SoC type.

 To follow conventions used by all other bindings with variable number of
 cells, the property should be called #samsung,armclk-cells. AFAIK the
 # should be interpreted as number of and so accents the meaning of
 the property.

 +
 +  - for Exynos4210 and Exynos4212: the value should be 9.
 +  - for Exynos4412: the value should be 10.
 +
  Each clock is assigned an identifier and client nodes can use this 
 identifier
  to specify the clock which they consume.

 @@ -28,6 +57,14 @@ Example 1: An example of a clock 

Re: [PATCH v4 2/2] Documentation: devicetree: Add boost-frequency binding to list boost mode frequency

[Viresh Kumar]

On 23 May 2014 19:07, Thomas Abraham thomas...@samsung.com wrote:
 From: Thomas Abraham thomas...@samsung.com

 Add a new optional boost-frequency binding for specifying the frequencies
 usable in boost mode.

 Cc: Nishanth Menon n...@ti.com
 Cc: Lukasz Majewski l.majew...@samsung.com
 Cc: Rob Herring robh...@kernel.org
 Cc: Pawel Moll pawel.m...@arm.com
 Cc: Mark Rutland mark.rutl...@arm.com
 Cc: Ian Campbell ijc+devicet...@hellion.org.uk
 Cc: Kumar Gala ga...@codeaurora.org
 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  .../devicetree/bindings/cpufreq/cpufreq-boost.txt  |   38 
 
  1 file changed, 38 insertions(+)
  create mode 100644 
 Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt

 diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt 
 b/Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
 new file mode 100644
 index 000..63ed0fc
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt
 @@ -0,0 +1,38 @@
 +* Device tree binding for CPU boost frequency (aka over-clocking)
 +
 +Certain CPU's can be operated in optional 'boost' mode (or sometimes 
 referred as
 +overclocking) in which the CPU can operate at frequencies which are not
 +specified by the manufacturer as CPU's operating frequency.
 +
 +Optional Properties:
 +- boost-frequencies: list of frequencies in KHz to be used only in boost 
 mode.
 +  This list should be a subset of frequencies listed in operating-points
 +  property. Refer to Documentation/devicetree/bindings/power/opp.txt for
 +  details about operating-points property.
 +
 +Example:
 +
 +   cpus {
 +   #address-cells = 1;
 +   #size-cells = 0;
 +   cpu@0 {
 +   device_type = cpu;
 +   compatible = arm,cortex-a9;
 +   reg = 0;
 +
 +   operating-points = 
 +   150 135
 +   140 1287500
 +   130 125
 +   120 1187500
 +   110 1137500
 +   100 1087500
 +   ;
 +   boost-frequencies = 150 140;
 +   };
 +   cpu@1 {
 +   device_type = cpu;
 +   compatible = arm,cortex-a9;
 +   reg = 1;
 +   };
 +   };

Acked-by: Viresh Kumar viresh.ku...@linaro.org
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Re: [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies

[Viresh Kumar]

On 23 May 2014 19:57, Thomas Abraham thomas...@samsung.com wrote:
 From: Thomas Abraham thomas...@samsung.com

 Lookup for the optional boost-frequency property in cpu0 node and if
 available, enable support for boost mode frequencies. The frequencies
 usable in boost mode are determined while preparing the cpufreq table
 from the list of operating points available.

 Cc: Shawn Guo shawn@linaro.org
 Cc: Lukasz Majewski l.majew...@samsung.com
 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt   |2 ++
  drivers/cpufreq/Kconfig|1 +
  drivers/cpufreq/cpufreq-cpu0.c |3 +++
  3 files changed, 6 insertions(+)

 diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt 
 b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 index f055515..60f321a 100644
 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 @@ -19,6 +19,8 @@ Optional properties:
  - cooling-min-level:
  - cooling-max-level:
   Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
 +- boost-frequency:
 + Please refer to 
 Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt

  Examples:

 diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
 index 1fbe11f..52741b9 100644
 --- a/drivers/cpufreq/Kconfig
 +++ b/drivers/cpufreq/Kconfig
 @@ -187,6 +187,7 @@ config GENERIC_CPUFREQ_CPU0
 tristate Generic CPU0 cpufreq driver
 depends on HAVE_CLK  REGULATOR  OF  THERMAL  CPU_THERMAL
 select PM_OPP
 +   select CPU_FREQ_BOOST_SW

Drop this. Select it from your platform driver if you want.

 help
   This adds a generic cpufreq driver for CPU0 frequency management.
   It supports both uniprocessor (UP) and symmetric multiprocessor 
 (SMP)
 diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
 index 1bf6bba..93d3d6d 100644
 --- a/drivers/cpufreq/cpufreq-cpu0.c
 +++ b/drivers/cpufreq/cpufreq-cpu0.c
 @@ -194,6 +194,9 @@ static int cpu0_cpufreq_probe(struct platform_device 
 *pdev)
 transition_latency += ret * 1000;
 }

 +   if (of_find_property(cpu_dev-of_node, boost-frequencies, NULL))
 +   cpu0_cpufreq_driver.boost_supported = true;
 +
 ret = cpufreq_register_driver(cpu0_cpufreq_driver);
 if (ret) {
 pr_err(failed register driver: %d\n, ret);
 --
 1.7.9.5

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Re: [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver

[Viresh Kumar]

On 23 May 2014 19:57, Thomas Abraham thomas...@samsung.com wrote:
 From: Thomas Abraham thomas...@samsung.com

 Remove the platform device instantiation for Exynos specific cpufreq
 driver and add the platform device for cpufreq-cpu0 driver.

 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  arch/arm/mach-exynos/exynos.c |4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

Acked-by: Viresh Kumar viresh.ku...@linaro.org
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Re: [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support

[Viresh Kumar]

On 23 May 2014 19:57, Thomas Abraham thomas...@samsung.com wrote:
 From: Thomas Abraham thomas...@samsung.com

 Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched over
 to use cpufreq-cpu0 driver for cpufreq functionality. So the Exynos
 specific cpufreq drivers for these platforms can be removed.

 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  drivers/cpufreq/Kconfig.arm  |   52 
  drivers/cpufreq/Makefile |4 -
  drivers/cpufreq/exynos-cpufreq.c |  218 
 --
  drivers/cpufreq/exynos-cpufreq.h |   99 ---
  drivers/cpufreq/exynos4210-cpufreq.c |  157 
  drivers/cpufreq/exynos4x12-cpufreq.c |  208 
  drivers/cpufreq/exynos5250-cpufreq.c |  183 
  7 files changed, 921 deletions(-)
  delete mode 100644 drivers/cpufreq/exynos-cpufreq.c
  delete mode 100644 drivers/cpufreq/exynos-cpufreq.h
  delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
  delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c
  delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c

Acked-by: Viresh Kumar viresh.ku...@linaro.org
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[PATCH] ARM: dts: Add pmu sysreg node to Exynos3250

[Chanwoo Choi]

This patch add pmusysreg node for Exynos3250 to access PMU (Power Management 
Unit)
register in a centralized way using syscon driver.

Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
 Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 +
 arch/arm/boot/dts/exynos3250.dtsi | 5 +
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt 
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index b562634..2a4ab04 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -2,6 +2,7 @@ SAMSUNG Exynos SoC series PMU Registers
 
 Properties:
  - compatible : should contain two values. First value must be one from 
following list:
+  - samsung,exynos3250-pmu - for Exynos3250 SoC,
   - samsung,exynos4210-pmu - for Exynos4210 SoC,
   - samsung,exynos4212-pmu - for Exynos4212 SoC,
   - samsung,exynos4412-pmu - for Exynos4412 SoC,
diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index ca28eac..3e678fa 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -125,6 +125,11 @@
reg = 0x1001 0x400;
};
 
+   pmu_system_controller: system-controller@1002 {
+   compatible = samsung,exynos3250-pmu, syscon;
+   reg = 0x1002 0x4000;
+   };
+
pd_cam: cam-power-domain@10023C00 {
compatible = samsung,exynos4210-pd;
reg = 0x10023C00 0x20;
-- 
1.8.0

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Re: [PATCH] arm: exynos: Fix allmodconfig build errors in mcpm and hotplug

[Sachin Kamat]

Thanks Abhilash.

On 26 May 2014 11:24, Abhilash Kesavan a.kesa...@samsung.com wrote:
 This fixes the following build errors:

 /tmp/ccRbZlaA.s: Assembler messages:
 /tmp/ccRbZlaA.s:69: Error: selected processor does not support ARM mode `isb '
 /tmp/ccRbZlaA.s:75: Error: selected processor does not support ARM mode `isb '
 /tmp/ccRbZlaA.s:76: Error: selected processor does not support ARM mode `dsb '
 make[1]: *** [arch/arm/mach-exynos/hotplug.o] Error 1

 /tmp/ccJEg4jw.s: Assembler messages:
 /tmp/ccJEg4jw.s:454: Error: selected processor does not support ARM mode `isb'
 /tmp/ccJEg4jw.s:455: Error: selected processor does not support ARM mode `dsb'
 /tmp/ccJEg4jw.s:465: Error: selected processor does not support ARM mode `isb'
 /tmp/ccJEg4jw.s:474: Error: selected processor does not support ARM mode `isb'
 /tmp/ccJEg4jw.s:475: Error: selected processor does not support ARM mode `dsb'
 /tmp/ccJEg4jw.s:516: Error: selected processor does not support ARM mode `isb'
 /tmp/ccJEg4jw.s:525: Error: selected processor does not support ARM mode `isb'
 /tmp/ccJEg4jw.s:526: Error: selected processor does not support ARM mode `dsb'
 make[1]: *** [arch/arm/mach-exynos/mcpm-exynos.o] Error 1

 Reported-by: Sachin Kamat sachin.ka...@linaro.org
 Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com

This patch fixes the above reported issues.

Tested-by: Sachin Kamat sachin.ka...@linaro.org

-- 
With warm regards,
Sachin
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Re: [PATCH v5] drm/exynos: enable fimd clocks in probe before accessing fimd registers

[Rahul Sharma]

Hi Inki,

Please review this patch.

Regards,
Rahul Sharma

On 23 May 2014 17:17, Rahul Sharma rahul.sha...@samsung.com wrote:
 From: Rahul Sharma rahul.sha...@samsung.com

 Fimd probe is accessing fimd Registers without enabling the fimd
 gate clocks. If FIMD clocks are kept disabled in Uboot or disbaled
 during kernel boottime, the system hangs during boottime.

 This issue got surfaced when verifying with sysmmu enabled. Probe of
 fimd Sysmmu enables the master clock before accessing sysmmu regs and
 then disables. Later fimd probe tries to read the register without
 enabling the clock which is wrong and hangs the system.

 Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
 ---
 v5:
 1) Added pm_runtime_get_sync to enable the Display power domain.
 v4:
 1) Added clk_disable for prev clock when clk_enable fails.
 v3:
 1) Added checks for clk_enable.
 v2:
 Rebase.
  drivers/gpu/drm/exynos/exynos_drm_fimd.c |   35 
 +-
  1 file changed, 34 insertions(+), 1 deletion(-)

 diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
 b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
 index bd30d0c..6a30415 100644
 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
 +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
 @@ -898,18 +898,51 @@ static int fimd_bind(struct device *dev, struct device 
 *master, void *data)
  {
 struct fimd_context *ctx = fimd_manager.ctx;
 struct drm_device *drm_dev = data;
 -   int win;
 +   int win, ret;

 fimd_mgr_initialize(fimd_manager, drm_dev);
 exynos_drm_crtc_create(fimd_manager);
 if (ctx-display)
 exynos_drm_create_enc_conn(drm_dev, ctx-display);

 +   ret = pm_runtime_get_sync(ctx-dev);
 +   if (ret) {
 +   dev_err(dev, pm runtime get has failed.\n);
 +   return ret;
 +   }
 +
 +   ret = clk_prepare_enable(ctx-bus_clk);
 +   if (ret) {
 +   dev_err(dev, bus clock enable failed.\n);
 +   goto bus_clk_err;
 +   }
 +
 +   ret = clk_prepare_enable(ctx-lcd_clk);
 +   if (ret) {
 +   dev_err(dev, lcd clock enable failed.\n);
 +   goto lcd_clk_err;
 +   }
 +
 for (win = 0; win  WINDOWS_NR; win++)
 fimd_clear_win(ctx, win);

 +   clk_disable_unprepare(ctx-lcd_clk);
 +   clk_disable_unprepare(ctx-bus_clk);
 +
 +   ret = pm_runtime_put_sync(ctx-dev);
 +   if (ret) {
 +   dev_err(dev, pm runtime put has failed.\n);
 +   goto pm_put_err;
 +   }
 +
 return 0;

 +lcd_clk_err:
 +   clk_disable_unprepare(ctx-bus_clk);
 +bus_clk_err:
 +   pm_runtime_put_sync(ctx-dev);
 +pm_put_err:
 +   return ret;
  }

  static void fimd_unbind(struct device *dev, struct device *master,
 --
 1.7.9.5

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Re: [PATCH v5] drm/exynos: enable fimd clocks in probe before accessing fimd registers

[Daniel Kurtz]

On Mon, May 26, 2014 at 2:59 PM, Rahul Sharma rahul.sha...@samsung.com wrote:

 Hi Inki,

 Please review this patch.

 Regards,
 Rahul Sharma

 On 23 May 2014 17:17, Rahul Sharma rahul.sha...@samsung.com wrote:
  From: Rahul Sharma rahul.sha...@samsung.com
 
  Fimd probe is accessing fimd Registers without enabling the fimd
  gate clocks. If FIMD clocks are kept disabled in Uboot or disbaled
  during kernel boottime, the system hangs during boottime.
 
  This issue got surfaced when verifying with sysmmu enabled. Probe of
  fimd Sysmmu enables the master clock before accessing sysmmu regs and
  then disables. Later fimd probe tries to read the register without
  enabling the clock which is wrong and hangs the system.
 
  Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
  ---
  v5:
  1) Added pm_runtime_get_sync to enable the Display power domain.
  v4:
  1) Added clk_disable for prev clock when clk_enable fails.
  v3:
  1) Added checks for clk_enable.
  v2:
  Rebase.
   drivers/gpu/drm/exynos/exynos_drm_fimd.c |   35 
  +-
   1 file changed, 34 insertions(+), 1 deletion(-)
 
  diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
  b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
  index bd30d0c..6a30415 100644
  --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
  +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
  @@ -898,18 +898,51 @@ static int fimd_bind(struct device *dev, struct 
  device *master, void *data)
   {
  struct fimd_context *ctx = fimd_manager.ctx;
  struct drm_device *drm_dev = data;
  -   int win;
  +   int win, ret;
 
  fimd_mgr_initialize(fimd_manager, drm_dev);
  exynos_drm_crtc_create(fimd_manager);
  if (ctx-display)
  exynos_drm_create_enc_conn(drm_dev, ctx-display);
 
  +   ret = pm_runtime_get_sync(ctx-dev);
  +   if (ret) {
  +   dev_err(dev, pm runtime get has failed.\n);
  +   return ret;
  +   }
  +
  +   ret = clk_prepare_enable(ctx-bus_clk);
  +   if (ret) {
  +   dev_err(dev, bus clock enable failed.\n);
  +   goto bus_clk_err;
  +   }
  +
  +   ret = clk_prepare_enable(ctx-lcd_clk);

Hi Rahul,

Can you explain why exactly we are clearing windows here in probe(), anyway?

IIUC, bus_clk is the clock that enables FIMD register access, and
lcd_clk clocks the scan out engine.
Therefore, if we only need to read/write some registers, we only need
the bus_clk, not lcd_clk, right?

However, fimd_clear_win() actually clears per-window registers.
Writes to per-window registers typically do not take effect until the
next vblank.
Therefore we do would need to enable lcd_clk to ensure that these
changes take effect.
Furthermore, to ensure the window clear completes during probe(), we
would also need to synchronously wait for the next vblank here - but
only if FIMD scanout is actually enabled already, otherwise there will
never be a next scanout, so we must check for that first.
Lastly, waiting around for a vblank could take a while.  Doing so in
probe() is not very friendly to boot up time, so the waiting should
probably be moved out of the main probe() thread into some sort of
asynchronous handler, which could then signal back when the clear is
complete.

Do you agree, or am I missing something?

Thanks,
-djk


  +   if (ret) {
  +   dev_err(dev, lcd clock enable failed.\n);
  +   goto lcd_clk_err;
  +   }
  +
  for (win = 0; win  WINDOWS_NR; win++)
  fimd_clear_win(ctx, win);
 
  +   clk_disable_unprepare(ctx-lcd_clk);
  +   clk_disable_unprepare(ctx-bus_clk);
  +
  +   ret = pm_runtime_put_sync(ctx-dev);
  +   if (ret) {
  +   dev_err(dev, pm runtime put has failed.\n);
  +   goto pm_put_err;
  +   }
  +
  return 0;
 
  +lcd_clk_err:
  +   clk_disable_unprepare(ctx-bus_clk);
  +bus_clk_err:
  +   pm_runtime_put_sync(ctx-dev);
  +pm_put_err:
  +   return ret;
   }
 
   static void fimd_unbind(struct device *dev, struct device *master,
  --
  1.7.9.5
 
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Re: [PATCH 1/3] mmc: host: add slot argument to mmc_of_parse

[Ludovic Desroches]

On Fri, May 23, 2014 at 07:25:19PM +0900, Jaehoon Chung wrote:
 From: Ludovic Desroches ludovic.desroc...@atmel.com
 
 Some hosts manage several slots. In these case information such as the
 bus width, chi detect and others are into the slot node. So we have to

/s/chi detect/chip detect

 parse child node. If not NULL, slot node will be used instead of the
 device node.
 
 Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 ---
  drivers/mmc/core/host.c  |   13 +
  include/linux/mmc/host.h |   10 +-
  2 files changed, 18 insertions(+), 5 deletions(-)
 
 diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
 index 95cceae..0f677b3 100644
 --- a/drivers/mmc/core/host.c
 +++ b/drivers/mmc/core/host.c
 @@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct 
 mmc_host *host)
  #endif
  
  /**
 - *   mmc_of_parse() - parse host's device-tree node
 + *   __mmc_of_parse() - parse host's device-tree node
   *   @host: host whose node should be parsed.
 + *   @slot : some device provide several slots so the node to parse
 + *   is not the host one.
   *
   * To keep the rest of the MMC subsystem unaware of whether DT has been
   * used to to instantiate and configure this host instance or not, we
   * parse the properties and set respective generic mmc-host flags and
   * parameters.
   */
 -int mmc_of_parse(struct mmc_host *host)
 +int __mmc_of_parse(struct mmc_host *host, struct device_node *slot)
  {
   struct device_node *np;
   u32 bus_width;
 @@ -317,7 +319,10 @@ int mmc_of_parse(struct mmc_host *host)
   if (!host-parent || !host-parent-of_node)
   return 0;
  
 - np = host-parent-of_node;
 + if (slot)
 + np = slot;
 + else
 + np = host-parent-of_node;
  
   /* bus-width is translated to MMC_CAP_*_BIT_DATA flags */
   if (of_property_read_u32(np, bus-width, bus_width)  0) {
 @@ -459,7 +464,7 @@ out:
   return ret;
  }
  
 -EXPORT_SYMBOL(mmc_of_parse);
 +EXPORT_SYMBOL(__mmc_of_parse);
  
  /**
   *   mmc_alloc_host - initialise the per-host structure.
 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
 index 7960424..c62af91 100644
 --- a/include/linux/mmc/host.h
 +++ b/include/linux/mmc/host.h
 @@ -372,7 +372,15 @@ struct mmc_host *mmc_alloc_host(int extra, struct device 
 *);
  int mmc_add_host(struct mmc_host *);
  void mmc_remove_host(struct mmc_host *);
  void mmc_free_host(struct mmc_host *);
 -int mmc_of_parse(struct mmc_host *host);
 +int __mmc_of_parse(struct mmc_host *host, struct device_node *slot);
 +/*
 + * mmc_of_parse - parse host's device-tree node
 + *   @host: host whose node should be parsed.
 + */
 +static inline int mmc_of_parse(struct mmc_host *host)
 +{
 + return __mmc_of_parse(host, NULL);
 +}
  
  static inline void *mmc_priv(struct mmc_host *host)
  {
 -- 
 1.7.9.5
 
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Re: [PATCH] ARM: dts: Add mclk entry for Snow/Peach-pit boards

[Tushar Behera]

On 20 May 2014 10:19, Tushar Behera tushar.beh...@linaro.org wrote:
 On Snow/Peach-pit boards, XCLKOUT provides master clock (mclk) to codec.

 Signed-off-by: Tushar Behera tushar.beh...@linaro.org
 ---

This patch is obsolete now because the proposed clock bindings for
XCLKOUT is now different (change in #clock-cells). Updated patch will
be sent once the XCLKOUT drivers are accepted.

 Dependency:
 1. Driver side changes have been posted here.
 https://lkml.org/lkml/2014/5/20/4

 2. XCLKOUT clock driver support
 https://lkml.org/lkml/2014/5/15/530

  arch/arm/boot/dts/exynos5250-snow.dts  |3 +++
  arch/arm/boot/dts/exynos5420-peach-pit.dts |3 +++
  2 files changed, 6 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos5250-snow.dts 
 b/arch/arm/boot/dts/exynos5250-snow.dts
 index 67391b9..1014ce0 100644
 --- a/arch/arm/boot/dts/exynos5250-snow.dts
 +++ b/arch/arm/boot/dts/exynos5250-snow.dts
 @@ -346,6 +346,9 @@

 samsung,i2s-controller = i2s0;
 samsung,audio-codec = max98095;
 +
 +   clocks = pmu_system_controller;
 +   clock-names = mclk;
 };

 usb@1211 {
 diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts 
 b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 index f4b2a16..c0664e9 100644
 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
 +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 @@ -64,6 +64,9 @@

 samsung,i2s-controller = i2s0;
 samsung,audio-codec = max98090;
 +
 +   clocks = pmu_system_controller;
 +   clock-names = mclk;
 };
  };

 --
 1.7.9.5




-- 
Tushar Behera
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[PATCH 0/9] drm/exynos/ipp: image post processing improvements, part deux

[Andrzej Hajda]

This is the next part of ipp improvement patches, this time made
by YoungJun Cho, I am posting them as he is on leave.

The patchset is based on drm-exynos/exynos-drm-next branch.

Regards
Andrzej


Andrzej Hajda (1):
  drm/exynos: ipp: remove description of non-existing field

YoungJun Cho (8):
  drm/exynos: ipp: remove usless list_empty() functions
  drm/exynos: ipp: remove duplicated setting
  drm/exynos: ipp: rename cmd_lock to lock
  drm/exynos: ipp: add cmd_lock for cmd_list
  drm/exynos: ipp: add ipp_remove_id()
  drm/exynos: ipp: rearrange c_node-mem_lock using routines
  drm/exynos: ipp: rearrange c_node-event_lock using routine
  drm/exynos: ipp: update comment for struct drm_ipp_buf_info

 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 242 
 drivers/gpu/drm/exynos/exynos_drm_ipp.h |   9 +-
 2 files changed, 129 insertions(+), 122 deletions(-)

-- 
1.9.1

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[PATCH 8/9] drm/exynos: ipp: update comment for struct drm_ipp_buf_info

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

The attribute gem_objs in struct drm_exynos_ipp_buf_info was
changed to handles. So the comment needs to be updated also.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
index 09cb5a2..e06c41e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
@@ -83,7 +83,7 @@ struct drm_exynos_ipp_cmd_node {
 /*
  * A structure of buffer information.
  *
- * @gem_objs: Y, Cb, Cr each gem object.
+ * @handles: Y, Cb, Cr each gem object handle.
  * @base: Y, Cb, Cr each planar address.
  */
 struct drm_exynos_ipp_buf_info {
-- 
1.9.1

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[PATCH 6/9] drm/exynos: ipp: rearrange c_node-mem_lock using routines

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

The c_node-mem_list[] should be protected with
c_node-mem_lock.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 86 ++---
 1 file changed, 48 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index f1c51b4..4b5afd3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -584,8 +584,6 @@ static int ipp_check_mem_list(struct 
drm_exynos_ipp_cmd_node *c_node)
struct list_head *head;
int ret, i, count[EXYNOS_DRM_OPS_MAX] = { 0, };
 
-   mutex_lock(c_node-mem_lock);
-
for_each_ipp_ops(i) {
/* source/destination memory list */
head = c_node-mem_list[i];
@@ -614,8 +612,6 @@ static int ipp_check_mem_list(struct 
drm_exynos_ipp_cmd_node *c_node)
ret = max(count[EXYNOS_DRM_OPS_SRC],
count[EXYNOS_DRM_OPS_DST]);
 
-   mutex_unlock(c_node-mem_lock);
-
return ret;
 }
 
@@ -658,16 +654,13 @@ static int ipp_set_mem_node(struct exynos_drm_ippdrv 
*ippdrv,
return -EFAULT;
}
 
-   mutex_lock(c_node-mem_lock);
-
DRM_DEBUG_KMS(ops_id[%d]\n, m_node-ops_id);
 
/* get operations callback */
ops = ippdrv-ops[m_node-ops_id];
if (!ops) {
DRM_ERROR(not support ops.\n);
-   ret = -EFAULT;
-   goto err_unlock;
+   return -EFAULT;
}
 
/* set address and enable irq */
@@ -676,12 +669,10 @@ static int ipp_set_mem_node(struct exynos_drm_ippdrv 
*ippdrv,
m_node-buf_id, IPP_BUF_ENQUEUE);
if (ret) {
DRM_ERROR(failed to set addr.\n);
-   goto err_unlock;
+   return ret;
}
}
 
-err_unlock:
-   mutex_unlock(c_node-mem_lock);
return ret;
 }
 
@@ -696,11 +687,9 @@ static struct drm_exynos_ipp_mem_node
void *addr;
int i;
 
-   mutex_lock(c_node-mem_lock);
-
m_node = kzalloc(sizeof(*m_node), GFP_KERNEL);
if (!m_node)
-   goto err_unlock;
+   return ERR_PTR(-ENOMEM);
 
/* clear base address for error handling */
memset(buf_info, 0x0, sizeof(buf_info));
@@ -734,15 +723,14 @@ static struct drm_exynos_ipp_mem_node
 
m_node-filp = file;
m_node-buf_info = buf_info;
+   mutex_lock(c_node-mem_lock);
list_add_tail(m_node-list, c_node-mem_list[qbuf-ops_id]);
-
mutex_unlock(c_node-mem_lock);
+
return m_node;
 
 err_clear:
kfree(m_node);
-err_unlock:
-   mutex_unlock(c_node-mem_lock);
return ERR_PTR(-EFAULT);
 }
 
@@ -759,13 +747,6 @@ static int ipp_put_mem_node(struct drm_device *drm_dev,
return -EFAULT;
}
 
-   if (list_empty(m_node-list)) {
-   DRM_ERROR(empty memory node.\n);
-   return -ENOMEM;
-   }
-
-   mutex_lock(c_node-mem_lock);
-
DRM_DEBUG_KMS(ops_id[%d]\n, m_node-ops_id);
 
/* put gem buffer */
@@ -780,8 +761,6 @@ static int ipp_put_mem_node(struct drm_device *drm_dev,
list_del(m_node-list);
kfree(m_node);
 
-   mutex_unlock(c_node-mem_lock);
-
return 0;
 }
 
@@ -894,7 +873,9 @@ static int ipp_queue_buf_with_run(struct device *dev,
return 0;
}
 
+   mutex_lock(c_node-mem_lock);
if (!ipp_check_mem_list(c_node)) {
+   mutex_unlock(c_node-mem_lock);
DRM_DEBUG_KMS(empty memory.\n);
return 0;
}
@@ -911,10 +892,12 @@ static int ipp_queue_buf_with_run(struct device *dev,
} else {
ret = ipp_set_mem_node(ippdrv, c_node, m_node);
if (ret) {
+   mutex_unlock(c_node-mem_lock);
DRM_ERROR(failed to set m node.\n);
return ret;
}
}
+   mutex_unlock(c_node-mem_lock);
 
return 0;
 }
@@ -926,12 +909,14 @@ static void ipp_clean_queue_buf(struct drm_device 
*drm_dev,
struct drm_exynos_ipp_mem_node *m_node, *tm_node;
 
/* delete list */
+   mutex_lock(c_node-mem_lock);
list_for_each_entry_safe(m_node, tm_node,
c_node-mem_list[qbuf-ops_id], list) {
if (m_node-buf_id == qbuf-buf_id 
m_node-ops_id == qbuf-ops_id)
ipp_put_mem_node(drm_dev, c_node, m_node);
}
+   mutex_unlock(c_node-mem_lock);
 }
 
 int exynos_drm_ipp_queue_buf(struct drm_device *drm_dev, void *data,
@@ -1267,9 +1252,11 @@ static int ipp_start_property(struct exynos_drm_ippdrv 

[PATCH 5/9] drm/exynos: ipp: add ipp_remove_id()

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

This patch adds ipp_remove_id() for idr resource free.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 42 -
 1 file changed, 31 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index b60ae54..f1c51b4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -167,6 +167,13 @@ static int ipp_create_id(struct idr *id_idr, struct mutex 
*lock, void *obj,
return 0;
 }
 
+static void ipp_remove_id(struct idr *id_idr, struct mutex *lock, u32 id)
+{
+   mutex_lock(lock);
+   idr_remove(id_idr, id);
+   mutex_unlock(lock);
+}
+
 static void *ipp_find_obj(struct idr *id_idr, struct mutex *lock, u32 id)
 {
void *obj;
@@ -501,7 +508,7 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, 
void *data,
c_node-start_work = ipp_create_cmd_work();
if (IS_ERR(c_node-start_work)) {
DRM_ERROR(failed to create start work.\n);
-   goto err_clear;
+   goto err_remove_id;
}
 
c_node-stop_work = ipp_create_cmd_work();
@@ -542,16 +549,22 @@ err_free_stop:
kfree(c_node-stop_work);
 err_free_start:
kfree(c_node-start_work);
+err_remove_id:
+   ipp_remove_id(ctx-prop_idr, ctx-prop_lock, property-prop_id);
 err_clear:
kfree(c_node);
return ret;
 }
 
-static void ipp_clean_cmd_node(struct drm_exynos_ipp_cmd_node *c_node)
+static void ipp_clean_cmd_node(struct ipp_context *ctx,
+   struct drm_exynos_ipp_cmd_node *c_node)
 {
/* delete list */
list_del(c_node-list);
 
+   ipp_remove_id(ctx-prop_idr, ctx-prop_lock,
+   c_node-property.prop_id);
+
/* destroy mutex */
mutex_destroy(c_node-lock);
mutex_destroy(c_node-mem_lock);
@@ -1122,7 +1135,7 @@ int exynos_drm_ipp_cmd_ctrl(struct drm_device *drm_dev, 
void *data,
c_node-state = IPP_STATE_STOP;
ippdrv-dedicated = false;
mutex_lock(ippdrv-cmd_lock);
-   ipp_clean_cmd_node(c_node);
+   ipp_clean_cmd_node(ctx, c_node);
 
if (list_empty(ippdrv-cmd_list))
pm_runtime_put_sync(ippdrv-dev);
@@ -1686,7 +1699,7 @@ static int ipp_subdrv_probe(struct drm_device *drm_dev, 
struct device *dev)
ipp_id);
if (ret || ipp_id == 0) {
DRM_ERROR(failed to create id.\n);
-   goto err_idr;
+   goto err;
}
 
DRM_DEBUG_KMS(count[%d]ippdrv[0x%x]ipp_id[%d]\n,
@@ -1707,34 +1720,40 @@ static int ipp_subdrv_probe(struct drm_device *drm_dev, 
struct device *dev)
ret = drm_iommu_attach_device(drm_dev, ippdrv-dev);
if (ret) {
DRM_ERROR(failed to activate iommu\n);
-   goto err_iommu;
+   goto err;
}
}
}
 
return 0;
 
-err_iommu:
+err:
/* get ipp driver entry */
-   list_for_each_entry_reverse(ippdrv, exynos_drm_ippdrv_list, drv_list)
+   list_for_each_entry_continue_reverse(ippdrv, exynos_drm_ippdrv_list,
+   drv_list) {
if (is_drm_iommu_supported(drm_dev))
drm_iommu_detach_device(drm_dev, ippdrv-dev);
 
-err_idr:
-   idr_destroy(ctx-ipp_idr);
-   idr_destroy(ctx-prop_idr);
+   ipp_remove_id(ctx-ipp_idr, ctx-ipp_lock,
+   ippdrv-prop_list.ipp_id);
+   }
+
return ret;
 }
 
 static void ipp_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
 {
struct exynos_drm_ippdrv *ippdrv;
+   struct ipp_context *ctx = get_ipp_context(dev);
 
/* get ipp driver entry */
list_for_each_entry(ippdrv, exynos_drm_ippdrv_list, drv_list) {
if (is_drm_iommu_supported(drm_dev))
drm_iommu_detach_device(drm_dev, ippdrv-dev);
 
+   ipp_remove_id(ctx-ipp_idr, ctx-ipp_lock,
+   ippdrv-prop_list.ipp_id);
+
ippdrv-drm_dev = NULL;
exynos_drm_ippdrv_unregister(ippdrv);
}
@@ -1765,6 +1784,7 @@ static void ipp_subdrv_close(struct drm_device *drm_dev, 
struct device *dev,
struct drm_exynos_file_private *file_priv = file-driver_priv;
struct exynos_drm_ipp_private *priv = file_priv-ipp_priv;
struct exynos_drm_ippdrv *ippdrv = NULL;
+   struct ipp_context *ctx = 

[PATCH 7/9] drm/exynos: ipp: rearrange c_node-event_lock using routine

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

The c_node-event_list should be protected with
c_node-event_lock.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 25 ++---
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 4b5afd3..603a796 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -796,7 +796,9 @@ static int ipp_get_event(struct drm_device *drm_dev,
e-base.event = e-event.base;
e-base.file_priv = file;
e-base.destroy = ipp_free_event;
+   mutex_lock(c_node-event_lock);
list_add_tail(e-base.link, c_node-event_list);
+   mutex_unlock(c_node-event_lock);
 
return 0;
 }
@@ -807,6 +809,7 @@ static void ipp_put_event(struct drm_exynos_ipp_cmd_node 
*c_node,
struct drm_exynos_ipp_send_event *e, *te;
int count = 0;
 
+   mutex_lock(c_node-event_lock);
list_for_each_entry_safe(e, te, c_node-event_list, base.link) {
DRM_DEBUG_KMS(count[%d]e[0x%x]\n, count++, (int)e);
 
@@ -827,9 +830,13 @@ static void ipp_put_event(struct drm_exynos_ipp_cmd_node 
*c_node,
/* delete list */
list_del(e-base.link);
kfree(e);
-   return;
+   goto out_unlock;
}
}
+
+out_unlock:
+   mutex_unlock(c_node-event_lock);
+   return;
 }
 
 static void ipp_handle_cmd_work(struct device *dev,
@@ -1515,9 +1522,11 @@ static int ipp_send_event(struct exynos_drm_ippdrv 
*ippdrv,
return -EINVAL;
}
 
+   mutex_lock(c_node-event_lock);
if (list_empty(c_node-event_list)) {
DRM_DEBUG_KMS(event list is empty.\n);
-   return 0;
+   ret = 0;
+   goto err_event_unlock;
}
 
mutex_lock(c_node-mem_lock);
@@ -1609,11 +1618,6 @@ static int ipp_send_event(struct exynos_drm_ippdrv 
*ippdrv,
e = list_first_entry(c_node-event_list,
struct drm_exynos_ipp_send_event, base.link);
 
-   if (!e) {
-   DRM_ERROR(empty event.\n);
-   return -EINVAL;
-   }
-
do_gettimeofday(now);
DRM_DEBUG_KMS(tv_sec[%ld]tv_usec[%ld]\n, now.tv_sec, now.tv_usec);
e-event.tv_sec = now.tv_sec;
@@ -1628,6 +1632,7 @@ static int ipp_send_event(struct exynos_drm_ippdrv 
*ippdrv,
list_move_tail(e-base.link, e-base.file_priv-event_list);
wake_up_interruptible(e-base.file_priv-event_wait);
spin_unlock_irqrestore(drm_dev-event_lock, flags);
+   mutex_unlock(c_node-event_lock);
 
DRM_DEBUG_KMS(done cmd[%d]prop_id[%d]buf_id[%d]\n,
property-cmd, property-prop_id, tbuf_id[EXYNOS_DRM_OPS_DST]);
@@ -1636,6 +1641,8 @@ static int ipp_send_event(struct exynos_drm_ippdrv 
*ippdrv,
 
 err_mem_unlock:
mutex_unlock(c_node-mem_lock);
+err_event_unlock:
+   mutex_unlock(c_node-event_lock);
return ret;
 }
 
@@ -1678,8 +1685,6 @@ void ipp_sched_event(struct work_struct *work)
goto err_completion;
}
 
-   mutex_lock(c_node-event_lock);
-
ret = ipp_send_event(ippdrv, c_node, event_work-buf_id);
if (ret) {
DRM_ERROR(failed to send event.\n);
@@ -1689,8 +1694,6 @@ void ipp_sched_event(struct work_struct *work)
 err_completion:
if (ipp_is_m2m_cmd(c_node-property.cmd))
complete(c_node-start_complete);
-
-   mutex_unlock(c_node-event_lock);
 }
 
 static int ipp_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
-- 
1.9.1

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[PATCH 9/9] drm/exynos: ipp: remove description of non-existing field

[Andrzej Hajda]

ipp_id field is removed from exynos_drm_ippdrv struct.
The patch removes its description as well.

Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
index e06c41e..7aaeaae 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
@@ -142,7 +142,6 @@ struct exynos_drm_ipp_ops {
  * @parent_dev: parent device information.
  * @dev: platform device.
  * @drm_dev: drm device.
- * @ipp_id: id of ipp driver.
  * @dedicated: dedicated ipp device.
  * @ops: source, destination operations.
  * @event_workq: event work queue.
-- 
1.9.1

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[PATCH 1/9] drm/exynos: ipp: remove usless list_empty() functions

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

list_for_each_entry() handles empty lists, so there is no
need to check whether the list is empty first.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 61 +
 1 file changed, 9 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index bf71d97..c8cfa24 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -276,11 +276,6 @@ static struct exynos_drm_ippdrv 
*ipp_find_drv_by_handle(u32 prop_id)
 
DRM_DEBUG_KMS(prop_id[%d]\n, prop_id);
 
-   if (list_empty(exynos_drm_ippdrv_list)) {
-   DRM_DEBUG_KMS(ippdrv_list is empty.\n);
-   return ERR_PTR(-ENODEV);
-   }
-
/*
 * This case is search ipp driver by prop_id handle.
 * sometimes, ipp subsystem find driver by prop_id.
@@ -289,11 +284,9 @@ static struct exynos_drm_ippdrv 
*ipp_find_drv_by_handle(u32 prop_id)
list_for_each_entry(ippdrv, exynos_drm_ippdrv_list, drv_list) {
DRM_DEBUG_KMS(count[%d]ippdrv[0x%x]\n, count++, (int)ippdrv);
 
-   if (!list_empty(ippdrv-cmd_list)) {
-   list_for_each_entry(c_node, ippdrv-cmd_list, list)
-   if (c_node-property.prop_id == prop_id)
-   return ippdrv;
-   }
+   list_for_each_entry(c_node, ippdrv-cmd_list, list)
+   if (c_node-property.prop_id == prop_id)
+   return ippdrv;
}
 
return ERR_PTR(-ENODEV);
@@ -573,11 +566,6 @@ static int ipp_check_mem_list(struct 
drm_exynos_ipp_cmd_node *c_node)
/* source/destination memory list */
head = c_node-mem_list[i];
 
-   if (list_empty(head)) {
-   DRM_DEBUG_KMS(%s memory empty.\n, i ? dst : src);
-   continue;
-   }
-
/* find memory node entry */
list_for_each_entry(m_node, head, list) {
DRM_DEBUG_KMS(%s,count[%d]m_node[0x%x]\n,
@@ -816,11 +804,6 @@ static void ipp_put_event(struct drm_exynos_ipp_cmd_node 
*c_node,
struct drm_exynos_ipp_send_event *e, *te;
int count = 0;
 
-   if (list_empty(c_node-event_list)) {
-   DRM_DEBUG_KMS(event_list is empty.\n);
-   return;
-   }
-
list_for_each_entry_safe(e, te, c_node-event_list, base.link) {
DRM_DEBUG_KMS(count[%d]e[0x%x]\n, count++, (int)e);
 
@@ -918,14 +901,12 @@ static void ipp_clean_queue_buf(struct drm_device 
*drm_dev,
 {
struct drm_exynos_ipp_mem_node *m_node, *tm_node;
 
-   if (!list_empty(c_node-mem_list[qbuf-ops_id])) {
-   /* delete list */
-   list_for_each_entry_safe(m_node, tm_node,
-   c_node-mem_list[qbuf-ops_id], list) {
-   if (m_node-buf_id == qbuf-buf_id 
-   m_node-ops_id == qbuf-ops_id)
-   ipp_put_mem_node(drm_dev, c_node, m_node);
-   }
+   /* delete list */
+   list_for_each_entry_safe(m_node, tm_node,
+   c_node-mem_list[qbuf-ops_id], list) {
+   if (m_node-buf_id == qbuf-buf_id 
+   m_node-ops_id == qbuf-ops_id)
+   ipp_put_mem_node(drm_dev, c_node, m_node);
}
 }
 
@@ -1361,11 +1342,6 @@ static int ipp_stop_property(struct drm_device *drm_dev,
/* source/destination memory list */
head = c_node-mem_list[i];
 
-   if (list_empty(head)) {
-   DRM_DEBUG_KMS(mem_list is empty.\n);
-   break;
-   }
-
list_for_each_entry_safe(m_node, tm_node,
head, list) {
ret = ipp_put_mem_node(drm_dev, c_node,
@@ -1381,11 +1357,6 @@ static int ipp_stop_property(struct drm_device *drm_dev,
/* destination memory list */
head = c_node-mem_list[EXYNOS_DRM_OPS_DST];
 
-   if (list_empty(head)) {
-   DRM_DEBUG_KMS(mem_list is empty.\n);
-   break;
-   }
-
list_for_each_entry_safe(m_node, tm_node, head, list) {
ret = ipp_put_mem_node(drm_dev, c_node, m_node);
if (ret) {
@@ -1398,11 +1369,6 @@ static int ipp_stop_property(struct drm_device *drm_dev,
/* source memory list */
head = c_node-mem_list[EXYNOS_DRM_OPS_SRC];
 
-   if 

[PATCH 4/9] drm/exynos: ipp: add cmd_lock for cmd_list

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

This patch adds cmd_lock for cmd_list synchronization.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 20 ++--
 drivers/gpu/drm/exynos/exynos_drm_ipp.h |  2 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 0d85433..b60ae54 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -284,9 +284,14 @@ static struct exynos_drm_ippdrv 
*ipp_find_drv_by_handle(u32 prop_id)
list_for_each_entry(ippdrv, exynos_drm_ippdrv_list, drv_list) {
DRM_DEBUG_KMS(count[%d]ippdrv[0x%x]\n, count++, (int)ippdrv);
 
-   list_for_each_entry(c_node, ippdrv-cmd_list, list)
-   if (c_node-property.prop_id == prop_id)
+   mutex_lock(ippdrv-cmd_lock);
+   list_for_each_entry(c_node, ippdrv-cmd_list, list) {
+   if (c_node-property.prop_id == prop_id) {
+   mutex_unlock(ippdrv-cmd_lock);
return ippdrv;
+   }
+   }
+   mutex_unlock(ippdrv-cmd_lock);
}
 
return ERR_PTR(-ENODEV);
@@ -318,6 +323,7 @@ int exynos_drm_ipp_get_property(struct drm_device *drm_dev, 
void *data,
if (!prop_list-ipp_id) {
list_for_each_entry(ippdrv, exynos_drm_ippdrv_list, drv_list)
count++;
+
/*
 * Supports ippdrv list count for user application.
 * First step user application getting ippdrv count.
@@ -379,9 +385,11 @@ static int ipp_find_and_set_property(struct 
drm_exynos_ipp_property *property)
 * when we find this command no using prop_id.
 * return property information set in this command node.
 */
+   mutex_lock(ippdrv-cmd_lock);
list_for_each_entry(c_node, ippdrv-cmd_list, list) {
if ((c_node-property.prop_id == prop_id) 
(c_node-state == IPP_STATE_STOP)) {
+   mutex_unlock(ippdrv-cmd_lock);
DRM_DEBUG_KMS(found cmd[%d]ippdrv[0x%x]\n,
property-cmd, (int)ippdrv);
 
@@ -389,6 +397,7 @@ static int ipp_find_and_set_property(struct 
drm_exynos_ipp_property *property)
return 0;
}
}
+   mutex_unlock(ippdrv-cmd_lock);
 
DRM_ERROR(failed to search property.\n);
 
@@ -519,7 +528,9 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, 
void *data,
 
INIT_LIST_HEAD(c_node-event_list);
list_splice_init(priv-event_list, c_node-event_list);
+   mutex_lock(ippdrv-cmd_lock);
list_add_tail(c_node-list, ippdrv-cmd_list);
+   mutex_unlock(ippdrv-cmd_lock);
 
/* make dedicated state without m2m */
if (!ipp_is_m2m_cmd(property-cmd))
@@ -1110,10 +1121,12 @@ int exynos_drm_ipp_cmd_ctrl(struct drm_device *drm_dev, 
void *data,
 
c_node-state = IPP_STATE_STOP;
ippdrv-dedicated = false;
+   mutex_lock(ippdrv-cmd_lock);
ipp_clean_cmd_node(c_node);
 
if (list_empty(ippdrv-cmd_list))
pm_runtime_put_sync(ippdrv-dev);
+   mutex_unlock(ippdrv-cmd_lock);
break;
case IPP_CTRL_PAUSE:
cmd_work = c_node-stop_work;
@@ -1688,6 +1701,7 @@ static int ipp_subdrv_probe(struct drm_device *drm_dev, 
struct device *dev)
ippdrv-event_workq = ctx-event_workq;
ippdrv-sched_event = ipp_sched_event;
INIT_LIST_HEAD(ippdrv-cmd_list);
+   mutex_init(ippdrv-cmd_lock);
 
if (is_drm_iommu_supported(drm_dev)) {
ret = drm_iommu_attach_device(drm_dev, ippdrv-dev);
@@ -1757,6 +1771,7 @@ static void ipp_subdrv_close(struct drm_device *drm_dev, 
struct device *dev,
DRM_DEBUG_KMS(for priv[0x%x]\n, (int)priv);
 
list_for_each_entry(ippdrv, exynos_drm_ippdrv_list, drv_list) {
+   mutex_lock(ippdrv-cmd_lock);
list_for_each_entry_safe(c_node, tc_node,
ippdrv-cmd_list, list) {
DRM_DEBUG_KMS(count[%d]ippdrv[0x%x]\n,
@@ -1781,6 +1796,7 @@ static void ipp_subdrv_close(struct drm_device *drm_dev, 
struct device *dev,
pm_runtime_put_sync(ippdrv-dev);
}
}
+   mutex_unlock(ippdrv-cmd_lock);
}
 
kfree(priv);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
index fbb80ac..09cb5a2 

[PATCH 2/9] drm/exynos: ipp: remove duplicated setting

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

This patch removes duplicated setting.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index c8cfa24..0968777 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -1090,12 +1090,12 @@ int exynos_drm_ipp_cmd_ctrl(struct drm_device *drm_dev, 
void *data,
case IPP_CTRL_PLAY:
if (pm_runtime_suspended(ippdrv-dev))
pm_runtime_get_sync(ippdrv-dev);
+
c_node-state = IPP_STATE_START;
 
cmd_work = c_node-start_work;
cmd_work-ctrl = cmd_ctrl-ctrl;
ipp_handle_cmd_work(dev, ippdrv, cmd_work, c_node);
-   c_node-state = IPP_STATE_START;
break;
case IPP_CTRL_STOP:
cmd_work = c_node-stop_work;
-- 
1.9.1

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[PATCH 3/9] drm/exynos: ipp: rename cmd_lock to lock

[Andrzej Hajda]

From: YoungJun Cho yj44@samsung.com

The ippdrv-cmd_list requires cmd_lock.
So renames cmd_lock to lock for context.

Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Seong-Woo Kim sw0312@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Andrzej Hajda a.ha...@samsung.com
---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c | 12 ++--
 drivers/gpu/drm/exynos/exynos_drm_ipp.h |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 0968777..0d85433 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -507,7 +507,7 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, 
void *data,
goto err_free_stop;
}
 
-   mutex_init(c_node-cmd_lock);
+   mutex_init(c_node-lock);
mutex_init(c_node-mem_lock);
mutex_init(c_node-event_lock);
 
@@ -542,7 +542,7 @@ static void ipp_clean_cmd_node(struct 
drm_exynos_ipp_cmd_node *c_node)
list_del(c_node-list);
 
/* destroy mutex */
-   mutex_destroy(c_node-cmd_lock);
+   mutex_destroy(c_node-lock);
mutex_destroy(c_node-mem_lock);
mutex_destroy(c_node-event_lock);
 
@@ -979,7 +979,7 @@ int exynos_drm_ipp_queue_buf(struct drm_device *drm_dev, 
void *data,
}
break;
case IPP_BUF_DEQUEUE:
-   mutex_lock(c_node-cmd_lock);
+   mutex_lock(c_node-lock);
 
/* put event for destination buffer */
if (qbuf-ops_id == EXYNOS_DRM_OPS_DST)
@@ -987,7 +987,7 @@ int exynos_drm_ipp_queue_buf(struct drm_device *drm_dev, 
void *data,
 
ipp_clean_queue_buf(drm_dev, c_node, qbuf);
 
-   mutex_unlock(c_node-cmd_lock);
+   mutex_unlock(c_node-lock);
break;
default:
DRM_ERROR(invalid buffer control.\n);
@@ -1412,7 +1412,7 @@ void ipp_sched_cmd(struct work_struct *work)
return;
}
 
-   mutex_lock(c_node-cmd_lock);
+   mutex_lock(c_node-lock);
 
property = c_node-property;
 
@@ -1460,7 +1460,7 @@ void ipp_sched_cmd(struct work_struct *work)
DRM_DEBUG_KMS(ctrl[%d] done.\n, cmd_work-ctrl);
 
 err_unlock:
-   mutex_unlock(c_node-cmd_lock);
+   mutex_unlock(c_node-lock);
 }
 
 static int ipp_send_event(struct exynos_drm_ippdrv *ippdrv,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h 
b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
index eea4db3..fbb80ac 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
@@ -52,7 +52,7 @@ struct drm_exynos_ipp_cmd_work {
  * @list: list head to command queue information.
  * @event_list: list head of event.
  * @mem_list: list head to source,destination memory queue information.
- * @cmd_lock: lock for synchronization of access to ioctl.
+ * @lock: lock for synchronization of access to ioctl.
  * @mem_lock: lock for synchronization of access to memory nodes.
  * @event_lock: lock for synchronization of access to scheduled event.
  * @start_complete: completion of start of command.
@@ -68,7 +68,7 @@ struct drm_exynos_ipp_cmd_node {
struct list_headlist;
struct list_headevent_list;
struct list_headmem_list[EXYNOS_DRM_OPS_MAX];
-   struct mutexcmd_lock;
+   struct mutexlock;
struct mutexmem_lock;
struct mutexevent_lock;
struct completion   start_complete;
-- 
1.9.1

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Re: [PATCH 1/3] mmc: host: add slot argument to mmc_of_parse

[Jaehoon Chung]

Hi,

On 05/26/2014 05:09 PM, Ludovic Desroches wrote:
 On Fri, May 23, 2014 at 07:25:19PM +0900, Jaehoon Chung wrote:
 From: Ludovic Desroches ludovic.desroc...@atmel.com

 Some hosts manage several slots. In these case information such as the
 bus width, chi detect and others are into the slot node. So we have to
 
 /s/chi detect/chip detect
Will fix.

Tushar have suggested the rename mmc_of_parse_slot() instead of 
__mmc_of_parse().
I'm not sure which name is better. How about?

If never mind, i will change to mmc_of_parse_slot(), then send patch-v2.

Best Regards,
Jaehoon Chung
 
 parse child node. If not NULL, slot node will be used instead of the
 device node.

 Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 ---
  drivers/mmc/core/host.c  |   13 +
  include/linux/mmc/host.h |   10 +-
  2 files changed, 18 insertions(+), 5 deletions(-)

 diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
 index 95cceae..0f677b3 100644
 --- a/drivers/mmc/core/host.c
 +++ b/drivers/mmc/core/host.c
 @@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct 
 mmc_host *host)
  #endif
  
  /**
 - *  mmc_of_parse() - parse host's device-tree node
 + *  __mmc_of_parse() - parse host's device-tree node
   *  @host: host whose node should be parsed.
 + *  @slot : some device provide several slots so the node to parse
 + *  is not the host one.
   *
   * To keep the rest of the MMC subsystem unaware of whether DT has been
   * used to to instantiate and configure this host instance or not, we
   * parse the properties and set respective generic mmc-host flags and
   * parameters.
   */
 -int mmc_of_parse(struct mmc_host *host)
 +int __mmc_of_parse(struct mmc_host *host, struct device_node *slot)
  {
  struct device_node *np;
  u32 bus_width;
 @@ -317,7 +319,10 @@ int mmc_of_parse(struct mmc_host *host)
  if (!host-parent || !host-parent-of_node)
  return 0;
  
 -np = host-parent-of_node;
 +if (slot)
 +np = slot;
 +else
 +np = host-parent-of_node;
  
  /* bus-width is translated to MMC_CAP_*_BIT_DATA flags */
  if (of_property_read_u32(np, bus-width, bus_width)  0) {
 @@ -459,7 +464,7 @@ out:
  return ret;
  }
  
 -EXPORT_SYMBOL(mmc_of_parse);
 +EXPORT_SYMBOL(__mmc_of_parse);
  
  /**
   *  mmc_alloc_host - initialise the per-host structure.
 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
 index 7960424..c62af91 100644
 --- a/include/linux/mmc/host.h
 +++ b/include/linux/mmc/host.h
 @@ -372,7 +372,15 @@ struct mmc_host *mmc_alloc_host(int extra, struct 
 device *);
  int mmc_add_host(struct mmc_host *);
  void mmc_remove_host(struct mmc_host *);
  void mmc_free_host(struct mmc_host *);
 -int mmc_of_parse(struct mmc_host *host);
 +int __mmc_of_parse(struct mmc_host *host, struct device_node *slot);
 +/*
 + * mmc_of_parse - parse host's device-tree node
 + *  @host: host whose node should be parsed.
 + */
 +static inline int mmc_of_parse(struct mmc_host *host)
 +{
 +return __mmc_of_parse(host, NULL);
 +}
  
  static inline void *mmc_priv(struct mmc_host *host)
  {
 -- 
 1.7.9.5

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Re: [PATCH 1/3] mmc: host: add slot argument to mmc_of_parse

[Ulf Hansson]

On 26 May 2014 10:38, Jaehoon Chung jh80.ch...@gmail.com wrote:
 Hi,

 On 05/26/2014 05:09 PM, Ludovic Desroches wrote:
 On Fri, May 23, 2014 at 07:25:19PM +0900, Jaehoon Chung wrote:
 From: Ludovic Desroches ludovic.desroc...@atmel.com

 Some hosts manage several slots. In these case information such as the
 bus width, chi detect and others are into the slot node. So we have to

 /s/chi detect/chip detect
 Will fix.

 Tushar have suggested the rename mmc_of_parse_slot() instead of 
 __mmc_of_parse().
 I'm not sure which name is better. How about?

 If never mind, i will change to mmc_of_parse_slot(), then send patch-v2.

I would prefer to keep it as is, but just because that's my taste. :-)

Kind regards
Ulf Hansson
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Re: [PATCH v5] drm/exynos: enable fimd clocks in probe before accessing fimd registers

[Rahul Sharma]

Hi Daniel,

On 26 May 2014 13:11, Daniel Kurtz djku...@chromium.org wrote:
 On Mon, May 26, 2014 at 2:59 PM, Rahul Sharma rahul.sha...@samsung.com 
 wrote:

 Hi Inki,

 Please review this patch.
[snip]
  +
  +   ret = clk_prepare_enable(ctx-lcd_clk);

 Hi Rahul,

 Can you explain why exactly we are clearing windows here in probe(), anyway?

I am not sure why it was added there but it is present since the first
version of this
file. Probably Inki can explain about this :). I can see the change
coming from his
first patch for adding drm fimd driver.


 IIUC, bus_clk is the clock that enables FIMD register access, and
 lcd_clk clocks the scan out engine.
 Therefore, if we only need to read/write some registers, we only need
 the bus_clk, not lcd_clk, right?


Correct, bus_clk should be sufficient to access the registers. But unless we
are confident about all implicit clock requirements in all SoCs, it is
safer to follow
the power_on/off sequence. This implementation is as good as DPMS on - perform
reg operation - DPMS Off. It was same in the original version but
later clock enables
were moved out of the probe.

 However, fimd_clear_win() actually clears per-window registers.
 Writes to per-window registers typically do not take effect until the
 next vblank.
 Therefore we do would need to enable lcd_clk to ensure that these
 changes take effect.
 Furthermore, to ensure the window clear completes during probe(), we
 would also need to synchronously wait for the next vblank here - but
 only if FIMD scanout is actually enabled already, otherwise there will
 never be a next scanout, so we must check for that first.
 Lastly, waiting around for a vblank could take a while.  Doing so in
 probe() is not very friendly to boot up time, so the waiting should
 probably be moved out of the main probe() thread into some sort of
 asynchronous handler, which could then signal back when the clear is
 complete.

 Do you agree, or am I missing something?

I agree. There seems a room for improvement. But at present we have two options,
either fix the current implementation and try to improve it as you mentioned
above. OR remove fimd_clear_win from probe if it is just a legacy code which
is no more required.

@Inki, need your inputs here.

Regards,
Rahul Sharma.


 Thanks,
 -djk


  +   if (ret) {
[snip]
  +pm_put_err:
  +   return ret;
   }
 
   static void fimd_unbind(struct device *dev, struct device *master,
  --
  1.7.9.5
 
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Re: [PATCH v2 10/18] drm/exynos: fimd: support I80 interface

[Daniel Kurtz]

Hi YoungJun,

I am not famiilar with i80.  Reading through this patch, it looks like
it works something like below for a page flip...

- page_flip ioctl
exynos_drm_crtc_page_flip()
  exynos_drm_crtc_mode_set_commit()
exynos_plane_mode_set()
exynos_drm_crtc_commit()
  exynos_plane_commit()
exynos_drm_crtc_plane_commit()
  ops-win_commit() = fimd_win_commit()
update BASE (scanout) register
atomic_set(ctx-win_updated, 1);

... at the next TE event ...
fimd_te_handler()
  atomic_set(ctx-win_updated, 0);
  fimd_trigger(ctx-dev);
atomic_set(ctx-triggering, 1);
VIDINTCON0 |= VIDINTCON0_INT_ENABLE;
TRIGCON |= TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE
... start an i80 transaction to transfer frame data from BASE to
the panel ...

... write complete signalled by ...
- FIMD interrupt: source =  VIDINTCON0_INT_I80IFDONE |
VIDINTCON0_INT_SYSMAINCON (which one?)
fimd_irq_handler()
  atomic_set(ctx-triggering, 0);
  drm_handle_vblank(ctx-drm_dev, ctx-pipe);
  exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);

Some questions/points:
 (1) does the i80 done interrupt mean that the panel is now
displaying the new frame?  Or just that the new frame is pending in a
panel-side scanout buffer?  Is there a separate interrupt for (a) i80
transfer complete, and (b) new frame now on main display?

 (2) from the DPMS off patch, you mentioned that the panel sometimes
has an issue.  Do you mean that sometimes when you trigger the i80
transaction, there is no corresponding i80ifdone / sysmaincon
interrupt?   If so, then I think you want to start a timer in
fimd_trigger(), that, if it expires before an I80IFDONE irq, will call
exynos_drm_crtc_finish_pageflip(), rather than hiding handling this
condition in dpms off of the exynos_drm_crtc.c layer.

Thanks,
-djk




On Wed, May 21, 2014 at 12:43 PM, YoungJun Cho yj44@samsung.com wrote:
 To support MIPI DSI command mode interface, FIMD should do followings:
 - Sets LCD block configuration for I80 interface.
 - Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration.
 - Implements trigger feature which transfers image date if there is
   page flip request, and implements TE handler to call trigger function.
 - Sets command mode timings configuration.
 - Sets ideal(pixel) clock is 2 times faster than the original one to
   generate frame done IRQ prior to the next TE signal.

 Signed-off-by: YoungJun Cho yj44@samsung.com
 Acked-by: Inki Dae inki@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  drivers/gpu/drm/exynos/Kconfig   |1 +
  drivers/gpu/drm/exynos/exynos_drm_fimd.c |  277 
 +-
  include/video/samsung_fimd.h |3 +-
  3 files changed, 237 insertions(+), 44 deletions(-)

 diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
 index 5bf5bca..f4d34f0 100644
 --- a/drivers/gpu/drm/exynos/Kconfig
 +++ b/drivers/gpu/drm/exynos/Kconfig
 @@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
 bool Exynos DRM FIMD
 depends on DRM_EXYNOS  !FB_S3C  !ARCH_MULTIPLATFORM
 select FB_MODE_HELPERS
 +   select MFD_SYSCON
 help
   Choose this option if you want to use Exynos FIMD for DRM.

 diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
 b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
 index 173ee97..9d585f9 100644
 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
 +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
 @@ -20,11 +20,14 @@
  #include linux/of_device.h
  #include linux/pm_runtime.h
  #include linux/component.h
 +#include linux/mfd/syscon.h
 +#include linux/regmap.h

  #include video/of_display_timing.h
  #include video/of_videomode.h
  #include video/samsung_fimd.h
  #include drm/exynos_drm.h
 +#include drm/drm_panel.h

  #include exynos_drm_drv.h
  #include exynos_drm_fbdev.h
 @@ -60,6 +63,24 @@
  /* color key value register for hardware window 1 ~ 4. */
  #define WKEYCON1_BASE(x)   ((WKEYCON1 + 0x140) + ((x - 1) * 8))

 +/* i80 / RGB trigger control register */
 +#define TRIGCON0x1A4
 +#define TRGMODE_I80_RGB_ENABLE_I80 (1  0)
 +#define SWTRGCMD_I80_RGB_ENABLE(1  1)
 +
 +/* display mode change control register except exynos4 */
 +#define VIDOUT_CON 0x000
 +#define VIDOUT_CON_F_I80_LDI0  (0x2  8)
 +
 +/* i80 interface control for main LDI register */
 +#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
 +#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
 +#define LCD_CS_SETUP(x)((x)  16)
 +#define LCD_WR_SETUP(x)((x)  12)
 +#define LCD_WR_ACT(x)  ((x)  8)
 +#define LCD_WR_HOLD(x) ((x)  4)
 +#define I80IFEN_ENABLE (1  0)
 +
  /* FIMD has totally five hardware windows. */
  #define WINDOWS_NR 5

 @@ -67,10 +88,14 @@

  struct fimd_driver_data {
 unsigned 

Re: [PATCH 1/3] mmc: host: add slot argument to mmc_of_parse

[Jaehoon Chung]

Hi, Ulf.

On 05/26/2014 05:44 PM, Ulf Hansson wrote:
 On 26 May 2014 10:38, Jaehoon Chung jh80.ch...@gmail.com wrote:
 Hi,

 On 05/26/2014 05:09 PM, Ludovic Desroches wrote:
 On Fri, May 23, 2014 at 07:25:19PM +0900, Jaehoon Chung wrote:
 From: Ludovic Desroches ludovic.desroc...@atmel.com

 Some hosts manage several slots. In these case information such as the
 bus width, chi detect and others are into the slot node. So we have to

 /s/chi detect/chip detect
 Will fix.

 Tushar have suggested the rename mmc_of_parse_slot() instead of 
 __mmc_of_parse().
 I'm not sure which name is better. How about?

 If never mind, i will change to mmc_of_parse_slot(), then send patch-v2.
 
 I would prefer to keep it as is, but just because that's my taste. :-)
Ok. I think so.
I want to merge this patch-set for fixing the dw-mmc problem, before release 
the 3.16.

dw-mmc controller also used the slot concept, so some property didn't parse 
with mmc_of_parse().

Best Regards,
Jaehoon Chung
 
 
 Kind regards
 Ulf Hansson
 

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Re: [PATCH v2 04/18] video: add command mode and command mode display timing

[Thierry Reding]

On Wed, May 21, 2014 at 01:42:56PM +0900, YoungJun Cho wrote:
 This patch is based on videomode and display_timing relevant codes.
 To support command mode panel, it does not need to guide its timing
 information to the display controller like video mode panel,
 but it requires signal timings to transfer video data.
 So this patch adds cmdmode struct, cmdmode_display_timing struct and
 the according helper functions to convert cmdmode_display_timing
 to a generic cmdmode.
 
 Signed-off-by: YoungJun Cho yj44@samsung.com
 Acked-by: Inki Dae inki@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  drivers/video/Kconfig |3 +
  drivers/video/Makefile|2 +
  drivers/video/cmdmode.c   |   42 ++
  drivers/video/cmdmode_display_timing.c|   26 
  drivers/video/of_cmdmode.c|   55 
  drivers/video/of_cmdmode_display_timing.c |  212 
 +
  include/video/cmdmode.h   |   67 +
  include/video/cmdmode_display_timing.h|   59 
  include/video/of_cmdmode.h|   19 +++
  include/video/of_cmdmode_display_timing.h |   26 
  10 files changed, 511 insertions(+)
  create mode 100644 drivers/video/cmdmode.c
  create mode 100644 drivers/video/cmdmode_display_timing.c
  create mode 100644 drivers/video/of_cmdmode.c
  create mode 100644 drivers/video/of_cmdmode_display_timing.c
  create mode 100644 include/video/cmdmode.h
  create mode 100644 include/video/cmdmode_display_timing.h
  create mode 100644 include/video/of_cmdmode.h
  create mode 100644 include/video/of_cmdmode_display_timing.h

Cc'ing Heiko Stübner on this. Heiko, you seem to have done some work on
i80 in the past[0] and I'm wondering if you could share any insights you
may have here.

In particular I'd like your take on the approach taken in this patch to
describe i80 parameters to a generic command-mode display timings
structure. However it seems to me that these timings are really very i80
specific and don't apply in general to command-mode displays.

As such I'm beginning to think that this should rather be a property of
the attached display/panel rather than the interface that generates the
signal.

Thierry

[0]: https://lkml.org/lkml/2011/5/17/170

 diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
 index c7b4f0f..7090ee5 100644
 --- a/drivers/video/Kconfig
 +++ b/drivers/video/Kconfig
 @@ -38,6 +38,9 @@ config VGASTATE
  config VIDEOMODE_HELPERS
   bool
  
 +config CMDMODE_HELPERS
 + bool
 +
  config HDMI
   bool
  
 diff --git a/drivers/video/Makefile b/drivers/video/Makefile
 index 9ad3c17..619dd99 100644
 --- a/drivers/video/Makefile
 +++ b/drivers/video/Makefile
 @@ -8,6 +8,8 @@ obj-y   += backlight/
  obj-y  += fbdev/
  
  obj-$(CONFIG_VIDEOMODE_HELPERS) += display_timing.o videomode.o
 +obj-$(CONFIG_CMDMODE_HELPERS) += cmdmode_display_timing.o cmdmode.o
  ifeq ($(CONFIG_OF),y)
  obj-$(CONFIG_VIDEOMODE_HELPERS) += of_display_timing.o of_videomode.o
 +obj-$(CONFIG_CMDMODE_HELPERS) += of_cmdmode_display_timing.o of_cmdmode.o
  endif
 diff --git a/drivers/video/cmdmode.c b/drivers/video/cmdmode.c
 new file mode 100644
 index 000..3d3eeb8
 --- /dev/null
 +++ b/drivers/video/cmdmode.c
 @@ -0,0 +1,42 @@
 +/*
 + * generic cmdmode display timing functions
 + *
 + * Copyright (c) 2014 YoungJun Cho yj44@samsung.com
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 + */
 +
 +#include linux/errno.h
 +#include linux/export.h
 +#include video/cmdmode_display_timing.h
 +#include video/cmdmode.h
 +
 +void cmdmode_from_timing(const struct cmdmode_display_timing *cmdt,
 + struct cmdmode *cm)
 +{
 + cm-pixelclock = cmdt-pixelclock;
 + cm-hactive = cmdt-hactive;
 + cm-vactive = cmdt-vactive;
 + cm-cs_setup = cmdt-cs_setup;
 + cm-wr_setup = cmdt-wr_setup;
 + cm-wr_active = cmdt-wr_active;
 + cm-wr_hold = cmdt-wr_hold;
 +}
 +EXPORT_SYMBOL_GPL(cmdmode_from_timing);
 +
 +int cmdmode_from_timings(const struct cmdmode_display_timings *cmdts,
 + struct cmdmode *cm, unsigned int index)
 +{
 + struct cmdmode_display_timing *cmdt;
 +
 + cmdt = cmdmode_display_timings_get(cmdts, index);
 + if (!cmdt)
 + return -EINVAL;
 +
 + cmdmode_from_timing(cmdt, cm);
 +
 + return 0;
 +}
 +EXPORT_SYMBOL_GPL(cmdmode_from_timings);
 diff --git a/drivers/video/cmdmode_display_timing.c 
 b/drivers/video/cmdmode_display_timing.c
 new file mode 100644
 index 000..88bab08
 --- /dev/null
 +++ b/drivers/video/cmdmode_display_timing.c
 @@ -0,0 +1,26 @@
 +/*
 + * generic cmdmode display timing functions
 + *
 + * Copyright (c) 2014 YoungJun Cho yj44@samsung.com

Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

[Tomasz Figa]

Hi Chander,

On 16.05.2014 10:03, Chander Kashyap wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
 
 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.
 
 Tested on SMDK5420.
 
 This patch set depends on:
   1. [PATCH 0/5] MCPM backend for Exynos5420
  http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks
 
  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)
 

For the whole series,

Reviewed-by: Tomasz Figa t.f...@samsung.com

Best regards,
Tomasz
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Re: [PATCH v4 4/8] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5

[Tomasz Figa]

Thomas,

On 26.05.2014 08:05, Thomas Abraham wrote:
 Hi Tomasz,
 
 Thanks for your comments. Please see inline reply.
 
 On Sat, May 17, 2014 at 4:54 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Thomas,

 Please see my comments inline.

 On 14.05.2014 03:11, Thomas Abraham wrote:
 From; Thomas Abraham thomas...@samsung.com

 The clock blocks within the CMU_CPU clock domain are put together into a
 new composite clock type called the cpu clock. This clock type requires
 configuration data that will be atomically programmed in the multiple
 clock blocks encapsulated within the cpu clock type when the parent clock
 frequency is changed. This configuration data is held in the clock 
 controller
 node. Update clock binding documentation about this configuration data 
 format
 for Samsung Exynos4 and Exynos5 platforms.

 Cc: Tomasz Figa t.f...@samsung.com
 Cc: Rob Herring robh...@kernel.org
 Cc: Pawel Moll pawel.m...@arm.com
 Cc: Mark Rutland mark.rutl...@arm.com
 Cc: Ian Campbell ijc+devicet...@hellion.org.uk
 Cc: Kumar Gala ga...@codeaurora.org
 Cc: devicet...@vger.kernel.org
 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  .../devicetree/bindings/clock/exynos4-clock.txt|   37 
 
  .../devicetree/bindings/clock/exynos5250-clock.txt |   36 
 +++
  2 files changed, 73 insertions(+), 0 deletions(-)

 diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt 
 b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
 index f5a5b19..0934e02 100644
 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
 +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
 @@ -15,6 +15,35 @@ Required Properties:

  - #clock-cells: should be 1.

 +- samsung,armclk-divider-table: when the frequency of the APLL is changed
 +  the divider clocks in CMU_CPU clock domain also need to be updated. These
 +  divider clocks have SoC specific divider clock output requirements for a
 +  specific APLL clock speeds. When APLL clock rate is changed, these 
 divider
 +  clocks are reprogrammed with pre-determined values in order to maintain 
 the
 +  SoC specific divider clock outputs. This property lists the divider 
 values
 +  for divider clocks in the CMU_CPU block for supported APLL clock speeds.
 +  The format of each entry included in the arm-frequency-table should be
 +  as defined below

 As far as I understand, the relation is not between the APLL frequency
 and particular clocks in CPU domain, but rather between the latter and
 input clock to CPU domain, which is _after_ the two dividers (called
 DIV_CORE and DIV_CORE2 or ARM_DIV1 and ARM_DIV2), which is also exactly
 the output frequency of ARMCLK.

 +
 +  - for Exynos4210 and Exynos4212 based platforms:
 +  cell #1: arm clock parent frequency

 Considering my comment above, this should be rather ARMCLK frequency.
 
 The clocks SCLK_APLL, SCLK_HPM, ATCLK and PCLK_DBG have no relation to
 the ARMCLK frequency. These clocks are directly derived from the PLL
 clock and so it would not be correct to have them related to ARMCLK.

Oh, right, the old driver was changing DIV_APLL, DIV_ATB and
DIV_PCLK_DBG as well. Somehow I was under an impression that we need to
care only about those dividers on the path after DIV_CORE and DIV_CORE2.
In this case the parent rate is the key here, although I'd call it CPU
block parent rate (usually APLL).

However this means that the trick with using DIV_CORE and DIV_CORE2 to
divide the rate of temporary parent clock is not enough, because DIV_ATB
is sourced directly from MOUT_CORE.

 
 So, I see two solutions to this, first being preferred solution.
 
 [A] Cell #1 should define PLL (parent of armclk) clock speed. Cell #2
 and Cell #3  should define divider values for ARMCLK clock speed. The
 hardware does support PLL frequency != ARMCLK frequency and so DT
 binding should allow that (even though implementation in the linux
 kernel does not use this feature). BTW, this was what was done in v2
 of this series.
 
 [B] Embedded this data with the code and don't get this from DT. The
 reason for doing this is, these are SoC specific values and not board
 specific. And when we are clear about what we want to put in DT, have
 a provision to lookup DT first and if DT values are not found,
 fallback on data embedded with the code.

Well, they are not that generic as they might appear. I've seen
different values for the same SoC in different vendor kernels, depending
on device the kernel was targeted for. Also they will likely differ
between SoC revisions.

However it might be a good idea indeed to keep the table in the code as
a first step to get the driver running without creating new DT bindings.

By the way, I'm not fully convinced if there is really a need for such
hardcoded look-up tables at all. Those divisors certainly look like they
are calculated based on some upper bounds for certain clocks and the
driver could simply find them out itself if those limits were 

Re: [PATCH v2 04/18] video: add command mode and command mode display timing

[Heiko Stübner]

Am Montag, 26. Mai 2014, 12:14:43 schrieb Thierry Reding:
 On Wed, May 21, 2014 at 01:42:56PM +0900, YoungJun Cho wrote:
  This patch is based on videomode and display_timing relevant codes.
  To support command mode panel, it does not need to guide its timing
  information to the display controller like video mode panel,
  but it requires signal timings to transfer video data.
  So this patch adds cmdmode struct, cmdmode_display_timing struct and
  the according helper functions to convert cmdmode_display_timing
  to a generic cmdmode.
  
  Signed-off-by: YoungJun Cho yj44@samsung.com
  Acked-by: Inki Dae inki@samsung.com
  Acked-by: Kyungmin Park kyungmin.p...@samsung.com
  ---
  
   drivers/video/Kconfig |3 +
   drivers/video/Makefile|2 +
   drivers/video/cmdmode.c   |   42 ++
   drivers/video/cmdmode_display_timing.c|   26 
   drivers/video/of_cmdmode.c|   55 
   drivers/video/of_cmdmode_display_timing.c |  212
   + include/video/cmdmode.h  
   |   67 +
   include/video/cmdmode_display_timing.h|   59 
   include/video/of_cmdmode.h|   19 +++
   include/video/of_cmdmode_display_timing.h |   26 
   10 files changed, 511 insertions(+)
   create mode 100644 drivers/video/cmdmode.c
   create mode 100644 drivers/video/cmdmode_display_timing.c
   create mode 100644 drivers/video/of_cmdmode.c
   create mode 100644 drivers/video/of_cmdmode_display_timing.c
   create mode 100644 include/video/cmdmode.h
   create mode 100644 include/video/cmdmode_display_timing.h
   create mode 100644 include/video/of_cmdmode.h
   create mode 100644 include/video/of_cmdmode_display_timing.h
 
 Cc'ing Heiko Stübner on this. Heiko, you seem to have done some work on
 i80 in the past[0] and I'm wondering if you could share any insights you
 may have here.
 
 In particular I'd like your take on the approach taken in this patch to
 describe i80 parameters to a generic command-mode display timings
 structure. However it seems to me that these timings are really very i80
 specific and don't apply in general to command-mode displays.
 
 As such I'm beginning to think that this should rather be a property of
 the attached display/panel rather than the interface that generates the
 signal.

OMG ... your digging in my ancient history :-D

I always got the impression, i80 is somehow related to the MIPI-DBI protocol 
[1].

Also the display I was working on (AUO-K190x epaper controller) used the 
command mode to also transfer the display region to update and had a 
completely dfferent command set [2].

In the end, I temporarily settled in adding a glue driver, driving the s3c2416 
i80 controller [3]. But someday I'd like to integrate this into a real 
solution, as the s3c2416 lcd-controller can do the i80 also in hardware, maybe 
speeding things up a little.

So I guess the transfer method itself is generic, but the commands used seem 
to differ. But I of course don't know if regular MIPI-DBI/i80 displays use a 
command set of commands for their timings.


Heiko


[1] https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg29100.html
[2] 
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/video/fbdev/auo_k190x.h
[3] 
https://github.com/mmind/linux-es600/blob/topic/es600-devel/drivers/video/es600-epd.c

  diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
  index c7b4f0f..7090ee5 100644
  --- a/drivers/video/Kconfig
  +++ b/drivers/video/Kconfig
  @@ -38,6 +38,9 @@ config VGASTATE
  
   config VIDEOMODE_HELPERS
   
  bool
  
  +config CMDMODE_HELPERS
  +   bool
  +
  
   config HDMI
   
  bool
  
  diff --git a/drivers/video/Makefile b/drivers/video/Makefile
  index 9ad3c17..619dd99 100644
  --- a/drivers/video/Makefile
  +++ b/drivers/video/Makefile
  @@ -8,6 +8,8 @@ obj-y += backlight/
  
   obj-y+= fbdev/
   
   obj-$(CONFIG_VIDEOMODE_HELPERS) += display_timing.o videomode.o
  
  +obj-$(CONFIG_CMDMODE_HELPERS) += cmdmode_display_timing.o cmdmode.o
  
   ifeq ($(CONFIG_OF),y)
   obj-$(CONFIG_VIDEOMODE_HELPERS) += of_display_timing.o of_videomode.o
  
  +obj-$(CONFIG_CMDMODE_HELPERS) += of_cmdmode_display_timing.o of_cmdmode.o
  
   endif
  
  diff --git a/drivers/video/cmdmode.c b/drivers/video/cmdmode.c
  new file mode 100644
  index 000..3d3eeb8
  --- /dev/null
  +++ b/drivers/video/cmdmode.c
  @@ -0,0 +1,42 @@
  +/*
  + * generic cmdmode display timing functions
  + *
  + * Copyright (c) 2014 YoungJun Cho yj44@samsung.com
  + *
  + * This program is free software; you can redistribute it and/or modify
  + * it under the terms of the GNU General Public License version 2 as
  + * published by the Free Software Foundation.
  + */
  +
  +#include linux/errno.h
  +#include linux/export.h
  +#include video/cmdmode_display_timing.h
  

Re: [PATCH v11 0/3] Exynos 5410 support

[Tomasz Figa]

Hi,

On 26.05.2014 05:23, Tarek Dakhran wrote:
 The series of patches represent support of Exynos 5410 SoC
 
 The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture
 
 Patches add new platform description, support of clock controller and device
 tree for Exynos 5410.
 
 Has been build on Samsung Linux Kernel
   (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' 
 into for-next)
 
 Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig)
   2) Exynos 5410 reference board (multi_v7_defconfig)
   3) Odroid-XU board (exynos_defconfig)
   4) Odroid-XU board (multi_v7_defconfig)
 
 I hope this is clean and would be applied.
 
 Tarek.
 
 Tarek Dakhran (3):
   ARM: EXYNOS: Add support for EXYNOS5410 SoC
   clk: exynos5410: register clocks using common clock framework
   ARM: dts: Add initial device tree support for EXYNOS5410
 
  .../devicetree/bindings/clock/exynos5410-clock.txt |   45 +
  arch/arm/boot/dts/Makefile |1 +
  arch/arm/boot/dts/exynos5410-smdk5410.dts  |   82 
  arch/arm/boot/dts/exynos5410.dtsi  |  206 +++
  arch/arm/mach-exynos/Kconfig   |5 +
  arch/arm/mach-exynos/common.h  |   12 +-
  drivers/clk/samsung/Makefile   |1 +
  drivers/clk/samsung/clk-exynos5410.c   |  209 
 
  include/dt-bindings/clock/exynos5410.h |   33 
  9 files changed, 592 insertions(+), 2 deletions(-)
  create mode 100644 
 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
  create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
  create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
  create mode 100644 include/dt-bindings/clock/exynos5410.h
 

Reviewed-by: Tomasz Figa t.f...@samsung.com

Best regards,
Tomasz
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[BUG] Compile error with THUMB2

[Viresh Kumar]

Hi Guys,

I didn't had time to put in an effort on this but here is a problem
reported by Santosh. See if somebody can get this fixed..

arch/arm/mach-exynos/sleep.S: Assembler messages:
arch/arm/mach-exynos/sleep.S:57: Error: invalid immediate for address
calculation (value = 0x0004)

Its because of THUMB2 and a probably fix would be something
like this:

https://lkml.org/lkml/2010/3/31/235

NOTE: Mainline's defconfig doesn't get this as THUMB2 isn't
enabled.

Reproduced on 3.15-rc6

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[PATCHv2 0/3] mmc: fixed the mmc_of_parse for dwmmc

[Jaehoon Chung]

This patch-set is fixed the dw-mmc controller problem.
dw-mmc controller have the slot, but mmc_of_parse didn't parse the slot 
sub-node.
So dw-mmc controller didn't work correctly.

Jaehoon Chung (2):
  mmc: dw_mmc: use the __mmc_of_parse to parse the slot node
  ARM: dts: replace the broken-cd property into slot node for dwmmc.

Ludovic Desroches (1):
  mmc: host: add slot argument to mmc_of_parse

 arch/arm/boot/dts/exynos4412-odroidx.dts  |2 +-
 arch/arm/boot/dts/exynos4412-origen.dts   |2 +-
 arch/arm/boot/dts/exynos4412-trats2.dts   |4 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |2 +-
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |4 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |2 +-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts|2 +-
 arch/arm/boot/dts/socfpga_arria5.dtsi |2 +-
 arch/arm/boot/dts/socfpga_cyclone5.dtsi   |2 +-
 arch/arm/boot/dts/socfpga_vt.dts  |2 +-
 drivers/mmc/core/host.c   |   13 +
 drivers/mmc/host/dw_mmc.c |   25 ++---
 include/linux/mmc/host.h  |   10 +-
 14 files changed, 37 insertions(+), 37 deletions(-)

-- 
1.7.9.5

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[PATCHv2 3/3] ARM: dts: replace the broken-cd property into slot node for dwmmc.

[Jaehoon Chung]

dw-mmc controller can be support the multiple slot.
So each slot's property can be difference.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
Changelog V2:
- None

 arch/arm/boot/dts/exynos4412-odroidx.dts  |2 +-
 arch/arm/boot/dts/exynos4412-origen.dts   |2 +-
 arch/arm/boot/dts/exynos4412-trats2.dts   |4 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |2 +-
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |4 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |2 +-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts|2 +-
 arch/arm/boot/dts/socfpga_arria5.dtsi |2 +-
 arch/arm/boot/dts/socfpga_cyclone5.dtsi   |2 +-
 arch/arm/boot/dts/socfpga_vt.dts  |2 +-
 11 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..24ec351 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -46,7 +46,6 @@
 
num-slots = 1;
supports-highspeed;
-   broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -55,6 +54,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+   broken-cd;
};
};
 
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e2c0dca..ed712a6 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -129,7 +129,6 @@
 
num-slots = 1;
supports-highspeed;
-   broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -138,6 +137,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+   broken-cd;
};
};
 
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 73be464..37c3cb3 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -460,8 +460,6 @@
mmc@1255 {
num-slots = 1;
supports-highspeed;
-   broken-cd;
-   non-removable;
card-detect-delay = 200;
vmmc-supply = vemmc_reg;
clock-frequency = 4;
@@ -475,6 +473,8 @@
slot@0 {
reg = 0;
bus-width = 8;
+   non-removable;
+   broken-cd;
};
};
 
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 090f983..0c9a7da 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -400,7 +400,6 @@
status = okay;
num-slots = 1;
supports-highspeed;
-   broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -412,6 +411,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+   broken-cd;
};
};
 
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi 
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 2c1560d..7ab3b94 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -249,7 +249,6 @@
mmc@1220 {
num-slots = 1;
supports-highspeed;
-   broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -260,6 +259,7 @@
slot@0 {
reg = 0;
bus-width = 8;
+   broken-cd;
};
};
 
@@ -283,7 +283,6 @@
mmc@1223 {
num-slots = 1;
supports-highspeed;
-   broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -293,6 +292,7 @@
slot@0 {
reg = 0;
bus-width = 4;
+   broken-cd;
};
};
 
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..feffe24 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -283,7 +283,6 

[PATCHv2 2/3] mmc: dw_mmc: use the __mmc_of_parse to parse the slot node

[Jaehoon Chung]

dw-mmc controller have the multiple slot.
Then it needs to parse the property for each slot.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
Changelog V2:
- None

 drivers/mmc/host/dw_mmc.c |   25 ++---
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..d4800f8 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1015,12 +1015,11 @@ static int dw_mci_get_cd(struct mmc_host *mmc)
 {
int present;
struct dw_mci_slot *slot = mmc_priv(mmc);
-   struct dw_mci_board *brd = slot-host-pdata;
struct dw_mci *host = slot-host;
int gpio_cd = mmc_gpio_get_cd(mmc);
 
/* Use platform get_cd function, else try onboard card detect */
-   if (brd-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
+   if (slot-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
present = 1;
else if (!IS_ERR_VALUE(gpio_cd))
present = gpio_cd;
@@ -2010,6 +2009,9 @@ static struct dw_mci_of_slot_quirks {
{
.quirk  = disable-wp,
.id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
+   }, {
+   .quirk  = broken-cd,
+   .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
},
 };
 
@@ -2088,7 +2090,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned 
int id)
if (host-pdata-caps2)
mmc-caps2 = host-pdata-caps2;
 
-   mmc_of_parse(mmc);
+   __mmc_of_parse(mmc, dw_mci_of_find_slot_node(host-dev, slot-id));
 
if (host-pdata-blk_settings) {
mmc-max_segs = host-pdata-blk_settings-max_segs;
@@ -2231,23 +2233,13 @@ static inline bool dw_mci_ctrl_all_reset(struct dw_mci 
*host)
 }
 
 #ifdef CONFIG_OF
-static struct dw_mci_of_quirks {
-   char *quirk;
-   int id;
-} of_quirks[] = {
-   {
-   .quirk  = broken-cd,
-   .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
-   },
-};
-
 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
 {
struct dw_mci_board *pdata;
struct device *dev = host-dev;
struct device_node *np = dev-of_node;
const struct dw_mci_drv_data *drv_data = host-drv_data;
-   int idx, ret;
+   int ret;
u32 clock_frequency;
 
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
@@ -2264,11 +2256,6 @@ static struct dw_mci_board *dw_mci_parse_dt(struct 
dw_mci *host)
pdata-num_slots = 1;
}
 
-   /* get quirks */
-   for (idx = 0; idx  ARRAY_SIZE(of_quirks); idx++)
-   if (of_get_property(np, of_quirks[idx].quirk, NULL))
-   pdata-quirks |= of_quirks[idx].id;
-
if (of_property_read_u32(np, fifo-depth, pdata-fifo_depth))
dev_info(dev, fifo-depth property not found, using 
value of FIFOTH register as default\n);
-- 
1.7.9.5

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[PATCHv2 1/3] mmc: host: add slot argument to mmc_of_parse

[Jaehoon Chung]

From: Ludovic Desroches ludovic.desroc...@atmel.com

Some hosts manage several slots. In these case information such as the
bus width, chip detect and others are into the slot node. So we have to
parse child node. If not NULL, slot node will be used instead of the
device node.

Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
Changelog V2:
- Fix the typo.

 drivers/mmc/core/host.c  |   13 +
 include/linux/mmc/host.h |   10 +-
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 95cceae..0f677b3 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct 
mmc_host *host)
 #endif
 
 /**
- * mmc_of_parse() - parse host's device-tree node
+ * __mmc_of_parse() - parse host's device-tree node
  * @host: host whose node should be parsed.
+ * @slot : some device provide several slots so the node to parse
+ * is not the host one.
  *
  * To keep the rest of the MMC subsystem unaware of whether DT has been
  * used to to instantiate and configure this host instance or not, we
  * parse the properties and set respective generic mmc-host flags and
  * parameters.
  */
-int mmc_of_parse(struct mmc_host *host)
+int __mmc_of_parse(struct mmc_host *host, struct device_node *slot)
 {
struct device_node *np;
u32 bus_width;
@@ -317,7 +319,10 @@ int mmc_of_parse(struct mmc_host *host)
if (!host-parent || !host-parent-of_node)
return 0;
 
-   np = host-parent-of_node;
+   if (slot)
+   np = slot;
+   else
+   np = host-parent-of_node;
 
/* bus-width is translated to MMC_CAP_*_BIT_DATA flags */
if (of_property_read_u32(np, bus-width, bus_width)  0) {
@@ -459,7 +464,7 @@ out:
return ret;
 }
 
-EXPORT_SYMBOL(mmc_of_parse);
+EXPORT_SYMBOL(__mmc_of_parse);
 
 /**
  * mmc_alloc_host - initialise the per-host structure.
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 7960424..c62af91 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -372,7 +372,15 @@ struct mmc_host *mmc_alloc_host(int extra, struct device 
*);
 int mmc_add_host(struct mmc_host *);
 void mmc_remove_host(struct mmc_host *);
 void mmc_free_host(struct mmc_host *);
-int mmc_of_parse(struct mmc_host *host);
+int __mmc_of_parse(struct mmc_host *host, struct device_node *slot);
+/*
+ * mmc_of_parse - parse host's device-tree node
+ * @host: host whose node should be parsed.
+ */
+static inline int mmc_of_parse(struct mmc_host *host)
+{
+   return __mmc_of_parse(host, NULL);
+}
 
 static inline void *mmc_priv(struct mmc_host *host)
 {
-- 
1.7.9.5

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[PATCH v2 1/3] ARM: EXYNOS: Add support for clock handling in power domain

[Shaik Ameer Basha]

From: Prathyush K prathyus...@samsung.com

While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
   (aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on a
domain everytime.

This patch adds the framework for getting the required mux and parent clocks
through a power domain device node. With this patch, while powering off
a domain, parent is set to oscclk and while powering back on, its re-set
to the correct parent which is as per the recommended pd on/off
sequence.

Signed-off-by: Prathyush K prathyus...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
 .../bindings/arm/exynos/power_domain.txt   |   20 +++
 arch/arm/mach-exynos/pm_domains.c  |   59 +++-
 2 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b41..8b4f7b7f 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,18 @@ Required Properties:
 - reg: physical base address of the controller and length of memory mapped
 region.
 
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+   devices in this power domain are set to oscclk before power gating
+   and restored back after powering on a domain. This is required for
+   all domains which are powered on and off and not required for unused
+   domains.
+- clock-names: The following clocks can be specified:
+   - oscclk: Oscillator clock.
+   - pclkN, clkN: Pairs of parent of input clock and input clock to the
+   devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+   are supported currently.
+
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
@@ -19,6 +31,14 @@ Example:
reg = 0x10023C00 0x10;
};
 
+   mfc_pd: power-domain@10044060 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044060 0x20;
+   clocks = clock CLK_FIN_PLL, clock CLK_MOUT_SW_ACLK333,
+   clock CLK_MOUT_USER_ACLK333;
+   clock-names = oscclk, pclk0, clk0;
+   };
+
 Example of the node using power domain:
 
node {
diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index fe6570e..34d86b1 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -17,6 +17,7 @@
 #include linux/err.h
 #include linux/slab.h
 #include linux/pm_domain.h
+#include linux/clk.h
 #include linux/delay.h
 #include linux/of_address.h
 #include linux/of_platform.h
@@ -24,6 +25,8 @@
 
 #include regs-pmu.h
 
+#define MAX_CLK_PER_DOMAIN 4
+
 /*
  * Exynos specific wrapper around the generic power domain
  */
@@ -32,6 +35,9 @@ struct exynos_pm_domain {
char const *name;
bool is_off;
struct generic_pm_domain pd;
+   struct clk *oscclk;
+   struct clk *clk[MAX_CLK_PER_DOMAIN];
+   struct clk *pclk[MAX_CLK_PER_DOMAIN];
 };
 
 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -44,6 +50,18 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
pd = container_of(domain, struct exynos_pm_domain, pd);
base = pd-base;
 
+   /* Set oscclk before powering off a domain*/
+   if (!power_on) {
+   int i;
+   for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
+   if (IS_ERR(pd-clk[i]))
+   break;
+   if (clk_set_parent(pd-clk[i], pd-oscclk))
+   pr_err(%s: error setting oscclk as parent to 
clock %d\n,
+   pd-name, i);
+   }
+   }
+
pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
__raw_writel(pwr, base);
 
@@ -60,6 +78,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
cpu_relax();
usleep_range(80, 100);
}
+
+   /* Restore clocks after powering on a domain*/
+   if (power_on) {
+   int i;
+   for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
+   if (IS_ERR(pd-clk[i]))
+   

[PATCH v2 0/3] Power-domain clk handling

[Shaik Ameer Basha]

This patchset enables the clk handling in power domain for
working as per the recommended power domain on / off sequence for
exynos5 SoCs. I have posted an RFC for the same [1] and didnt get any
review comments / objections. So I am dropping the RFC tag and
posting the patch along with the required clk and dt support.

[1] https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg30479.html

Rebased on Kukjin Kim's linux-samsung.git, for-next branch
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git:for-next

Changes since v1:
Addressed review comments from Tomasz Figa.
- http://www.spinics.net/lists/linux-samsung-soc/msg31625.html
- http://www.spinics.net/lists/linux-samsung-soc/msg31626.html

Arun Kumar K (2):
  clk: exynos5420: Add IDs for clocks used in PD mfc
  ARM: dts: Add clock property for mfc_pd in 5420

Prathyush K (1):
  ARM: EXYNOS: Add support for clock handling in power domain

 .../bindings/arm/exynos/power_domain.txt   |   20 +++
 arch/arm/boot/dts/exynos5420.dtsi  |3 +
 arch/arm/mach-exynos/pm_domains.c  |   59 +++-
 drivers/clk/samsung/clk-exynos5420.c   |6 +-
 include/dt-bindings/clock/exynos5420.h |2 +
 5 files changed, 87 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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[PATCH v2 2/3] clk: exynos5420: Add IDs for clocks used in PD mfc

[Shaik Ameer Basha]

From: Arun Kumar K arun...@samsung.com

Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.

Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
 drivers/clk/samsung/clk-exynos5420.c   |6 --
 include/dt-bindings/clock/exynos5420.h |2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c 
b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7ee..f74f882f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] 
__initdata = {
SRC_TOP4, 16, 1),
MUX(0, mout_user_aclk266, mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, mout_user_aclk166, mout_user_aclk166_p, SRC_TOP4, 24, 1),
-   MUX(0, mout_user_aclk333, mout_user_aclk333_p, SRC_TOP4, 28, 1),
+   MUX(CLK_MOUT_USER_ACLK333, mout_user_aclk333, mout_user_aclk333_p,
+   SRC_TOP4, 28, 1),
 
MUX(0, mout_user_aclk400_disp1, mout_user_aclk400_disp1_p,
SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] 
__initdata = {
SRC_TOP11, 12, 1),
MUX(0, mout_sw_aclk266, mout_sw_aclk266_p, SRC_TOP11, 20, 1),
MUX(0, mout_sw_aclk166, mout_sw_aclk166_p, SRC_TOP11, 24, 1),
-   MUX(0, mout_sw_aclk333, mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+   MUX(CLK_MOUT_SW_ACLK333, mout_sw_aclk333, mout_sw_aclk333_p,
+   SRC_TOP11, 28, 1),
 
MUX(0, mout_sw_aclk400_disp1, mout_sw_aclk400_disp1_p,
SRC_TOP12, 4, 1),
diff --git a/include/dt-bindings/clock/exynos5420.h 
b/include/dt-bindings/clock/exynos5420.h
index 97dcb89..3fc08ff 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -203,6 +203,8 @@
 #define CLK_MOUT_G3D   641
 #define CLK_MOUT_VPLL  642
 #define CLK_MOUT_MAUDIO0   643
+#define CLK_MOUT_USER_ACLK333  644
+#define CLK_MOUT_SW_ACLK333645
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL 768
-- 
1.7.9.5

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[PATCH 1/3] regulator: s2mps11: Refactor setting ramp delay

[Krzysztof Kozlowski]

Prepare for merging the s2mpa01 regulator driver into s2mps11 by:
1. Adding common id for buck regulators.
2. Splitting shared ramp delay settings to match S2MPA01.
3. Adding a configuration of registers for setting ramp delay for each
   buck regulator.

The functionality of the driver should not change as this patch only
prepares for supporting S2MPA01 device.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
 drivers/regulator/s2mps11.c | 210 ++--
 1 file changed, 144 insertions(+), 66 deletions(-)

diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
index 02e2fb2fca66..fa12d75b784f 100644
--- a/drivers/regulator/s2mps11.c
+++ b/drivers/regulator/s2mps11.c
@@ -32,13 +32,32 @@
 #include linux/mfd/samsung/s2mps11.h
 #include linux/mfd/samsung/s2mps14.h
 
+/*
+ * Enum used as a common id of buck regulators on S2MPA01 and S2MPS11.
+ */
+enum s2mpx_bucks {
+   S2MPX_BUCK1,
+   S2MPX_BUCK2,
+   S2MPX_BUCK3,
+   S2MPX_BUCK4,
+   S2MPX_BUCK5,
+   S2MPX_BUCK6,
+   S2MPX_BUCK7,
+   S2MPX_BUCK8,
+   S2MPX_BUCK9,
+   S2MPX_BUCK10,
+};
+
 struct s2mps11_info {
+   enum sec_device_type dev_type;
unsigned int rdev_num;
int ramp_delay2;
-   int ramp_delay34;
+   int ramp_delay3;
+   int ramp_delay4;
int ramp_delay5;
int ramp_delay16;
-   int ramp_delay7810;
+   int ramp_delay7;
+   int ramp_delay810;
int ramp_delay9;
/*
 * One bit for each S2MPS14 regulator whether the suspend mode
@@ -49,6 +68,47 @@ struct s2mps11_info {
int *ext_control_gpio;
 };
 
+/*
+ * Description of ramp delay register for one buck regulator
+ * on S2MPA01 and S2MPS11.
+ */
+struct s2mpx_ramp_reg {
+   unsigned int ramp_shift;
+   unsigned int ramp_reg;
+   unsigned int enable_shift;
+   bool enable_supported;
+};
+
+#define s2mps11_ramp_reg(r_shift) {\
+   .ramp_shift = S2MPS11_ ## r_shift ## _RAMP_SHIFT,   \
+   .ramp_reg   = S2MPS11_REG_RAMP_BUCK,\
+   .enable_shift   = 0,\
+   .enable_supported   = false,\
+}
+#define s2mps11_buck2346_ramp_reg(r_shift, r_reg, e_shift) {   \
+   .ramp_shift = S2MPS11_ ## r_shift ## _RAMP_SHIFT,   \
+   .ramp_reg   = S2MPS11_REG_ ## r_reg,\
+   .enable_shift   = S2MPS11_ ## e_shift ## _RAMP_EN_SHIFT,\
+   .enable_supported   = true, \
+}
+
+static const struct s2mpx_ramp_reg s2mps11_ramp_regs[] = {
+   [S2MPX_BUCK1]   = s2mps11_ramp_reg(BUCK16),
+   [S2MPX_BUCK2]   = s2mps11_buck2346_ramp_reg(BUCK2, RAMP, BUCK2),
+   [S2MPX_BUCK3]   = s2mps11_buck2346_ramp_reg(BUCK34, RAMP, BUCK3),
+   [S2MPX_BUCK4]   = s2mps11_buck2346_ramp_reg(BUCK34, RAMP, BUCK4),
+   [S2MPX_BUCK5]   = s2mps11_ramp_reg(BUCK5),
+   [S2MPX_BUCK6]   = s2mps11_buck2346_ramp_reg(BUCK16, RAMP_BUCK, BUCK6),
+   [S2MPX_BUCK7]   = s2mps11_ramp_reg(BUCK7810),
+   [S2MPX_BUCK8]   = s2mps11_ramp_reg(BUCK7810),
+   [S2MPX_BUCK9]   = s2mps11_ramp_reg(BUCK9),
+   [S2MPX_BUCK10]  = s2mps11_ramp_reg(BUCK7810),
+};
+
+static const struct s2mpx_ramp_reg * const s2mpx_ramp_regs[] = {
+   [S2MPS11X] = s2mps11_ramp_regs,
+};
+
 static int get_ramp_delay(int ramp_delay)
 {
unsigned char cnt = 0;
@@ -68,6 +128,23 @@ static int get_ramp_delay(int ramp_delay)
return cnt;
 }
 
+/*
+ * Maps a buck regulator id to enum s2mpx_bucks.
+ * Valid only for buck regulators on on S2MPS11.
+ *
+ * Returns a value of enum s2mpx_bucks or -EINVAL.
+ */
+static int get_s2mpx_buck_id(enum sec_device_type dev_type,
+   int rdev_id)
+{
+   switch (dev_type) {
+   case S2MPS11X:
+   return rdev_id - S2MPS11_BUCK1;
+   default:
+   return -EINVAL;
+   }
+}
+
 static int s2mps11_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
   unsigned int old_selector,
   unsigned int new_selector)
@@ -75,29 +152,40 @@ static int s2mps11_regulator_set_voltage_time_sel(struct 
regulator_dev *rdev,
struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
unsigned int ramp_delay = 0;
int old_volt, new_volt;
+   int buck_id = get_s2mpx_buck_id(s2mps11-dev_type, rdev_get_id(rdev));
 
-   switch (rdev_get_id(rdev)) {
-   case S2MPS11_BUCK2:
+   switch (buck_id) {
+   case S2MPX_BUCK2:
ramp_delay = s2mps11-ramp_delay2;
break;
-   case S2MPS11_BUCK3:
-   case S2MPS11_BUCK4:
-   ramp_delay = s2mps11-ramp_delay34;
+   case S2MPX_BUCK3:
+   ramp_delay = s2mps11-ramp_delay3;
break;
-   case S2MPS11_BUCK5:
+

[PATCH 3/3] regulator: s2mpa01: Remove driver because it was merged into s2mps11

[Krzysztof Kozlowski]

The s2mpa01 regulator driver can be safely removed since it was merged
into s2mps11 driver.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
 Documentation/devicetree/bindings/mfd/s2mpa01.txt |  90 
 drivers/regulator/Kconfig |   7 -
 drivers/regulator/Makefile|   1 -
 drivers/regulator/s2mpa01.c   | 482 --
 4 files changed, 580 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mfd/s2mpa01.txt
 delete mode 100644 drivers/regulator/s2mpa01.c

diff --git a/Documentation/devicetree/bindings/mfd/s2mpa01.txt 
b/Documentation/devicetree/bindings/mfd/s2mpa01.txt
deleted file mode 100644
index c13d3d8c3947..
--- a/Documentation/devicetree/bindings/mfd/s2mpa01.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-
-* Samsung S2MPA01 Voltage and Current Regulator
-
-The Samsung S2MPA01 is a multi-function device which includes high
-efficiency buck converters including Dual-Phase buck converter, various LDOs,
-and an RTC. It is interfaced to the host controller using an I2C interface.
-Each sub-block is addressed by the host system using different I2C slave
-addresses.
-
-Required properties:
-- compatible: Should be samsung,s2mpa01-pmic.
-- reg: Specifies the I2C slave address of the PMIC block. It should be 0x66.
-
-Optional properties:
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
-  the interrupts from s2mpa01 are delivered to.
-- interrupts: An interrupt specifier for the sole interrupt generated by the
-  device.
-
-Optional nodes:
-- regulators: The regulators of s2mpa01 that have to be instantiated should be
-  included in a sub-node named 'regulators'. Regulator nodes and constraints
-  included in this sub-node use the standard regulator bindings which are
-  documented elsewhere.
-
-Properties for BUCK regulator nodes:
-- regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500
-  (default), 25000, or 5. May be 0 for disabling the ramp delay on
-  BUCK{1,2,3,4}.
-
- In the absence of the regulator-ramp-delay property, the default ramp
- delay will be used.
-
-  NOTE: Some BUCKs share the ramp rate setting i.e. same ramp value will be set
-  for a particular group of BUCKs. So provide same 
regulator-ramp-delay=value.
-
-  The following BUCKs share ramp settings:
-  * 1 and 6
-  * 2 and 4
-  * 8, 9, and 10
-
-The following are the names of the regulators that the s2mpa01 PMIC block
-supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
-as per the datasheet of s2mpa01.
-
-   - LDOn
- - valid values for n are 1 to 26
- - Example: LDO1, LD02, LDO26
-   - BUCKn
- - valid values for n are 1 to 10.
- - Example: BUCK1, BUCK2, BUCK9
-
-Example:
-
-   s2mpa01_pmic@66 {
-   compatible = samsung,s2mpa01-pmic;
-   reg = 0x66;
-
-   regulators {
-   ldo1_reg: LDO1 {
-   regulator-name = VDD_ALIVE;
-   regulator-min-microvolt = 100;
-   regulator-max-microvolt = 100;
-   };
-
-   ldo2_reg: LDO2 {
-   regulator-name = VDDQ_MMC2;
-   regulator-min-microvolt = 280;
-   regulator-max-microvolt = 280;
-   regulator-always-on;
-   };
-
-   buck1_reg: BUCK1 {
-   regulator-name = vdd_mif;
-   regulator-min-microvolt = 95;
-   regulator-max-microvolt = 135;
-   regulator-always-on;
-   regulator-boot-on;
-   };
-
-   buck2_reg: BUCK2 {
-   regulator-name = vdd_arm;
-   regulator-min-microvolt = 95;
-   regulator-max-microvolt = 135;
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-ramp-delay = 5;
-   };
-   };
-   };
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index c4aa87fd12af..d735ffb36c21 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -440,13 +440,6 @@ config REGULATOR_RC5T583
  through regulator interface. The device supports multiple DCDC/LDO
  outputs which can be controlled by i2c communication.
 
-config REGULATOR_S2MPA01
-   tristate Samsung S2MPA01 voltage regulator
-   depends on MFD_SEC_CORE
-   help
-This driver controls Samsung S2MPA01 voltage output regulator
-via I2C bus. S2MPA01 has 10 Bucks and 26 LDO outputs.

[PATCH 2/3] regulator: s2mps11: Merge S2MPA01 driver

[Krzysztof Kozlowski]

Add S2MPA01 support to the s2mps11 regulator driver. This obsoletes the
s2mpa01 regulator driver.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
 Documentation/devicetree/bindings/mfd/s2mps11.txt | 106 
 drivers/regulator/Kconfig |   4 +-
 drivers/regulator/s2mps11.c   | 283 +++---
 3 files changed, 315 insertions(+), 78 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt 
b/Documentation/devicetree/bindings/mfd/s2mps11.txt
index d81ba30c0d8b..63f9b0d7982a 100644
--- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
+++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
@@ -1,5 +1,5 @@
 
-* Samsung S2MPS11 and S2MPS14 Voltage and Current Regulator
+* Samsung S2MPA01, S2MPS11 and S2MPS14 Voltage and Current Regulator
 
 The Samsung S2MPS11 is a multi-function device which includes voltage and
 current regulators, RTC, charger controller and other sub-blocks. It is
@@ -7,21 +7,23 @@ interfaced to the host controller using an I2C interface. 
Each sub-block is
 addressed by the host system using different I2C slave addresses.
 
 Required properties:
-- compatible: Should be samsung,s2mps11-pmic or samsung,s2mps14-pmic.
+- compatible: Should be one of: samsung,s2mps11-pmic, samsung,s2mps14-pmic,
+  samsung,s2mpa01-pmic.
 - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
 
 Optional properties:
 - interrupt-parent: Specifies the phandle of the interrupt controller to which
   the interrupts from s2mps11 are delivered to.
-- interrupts: Interrupt specifiers for interrupt sources.
+- interrupts: An interrupt specifier for the sole interrupt generated by the
+  device.
 
 Optional nodes:
-- clocks: s2mps11 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz
+- clocks: S2MPS11 and S5M8767 provide three(AP/CP/BT) buffered 32.768 KHz
   outputs, so to register these as clocks with common clock framework
   instantiate a sub-node named clocks. It uses the common clock binding
   documented in :
   [Documentation/devicetree/bindings/clock/clock-bindings.txt]
-  The s2mps14 provides two (AP/BT) buffered 32.768 KHz outputs.
+  The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.
   - #clock-cells: should be 1.
 
   - The following is the list of clocks generated by the controller. Each clock
@@ -34,7 +36,8 @@ Optional nodes:
 32KhzBT2S2MPS11, S2MPS14, S5M8767
 
   - compatible: Should be one of: samsung,s2mps11-clk, samsung,s2mps14-clk,
-   samsung,s5m8767-clk
+samsung,s5m8767-clk
+
 
 - regulators: The regulators of s2mps11 that have to be instantiated should be
 included in a sub-node named 'regulators'. Regulator nodes included in this
@@ -44,24 +47,61 @@ sub-node should be of the format as listed below.
[standard regulator constraints];
};
 
- regulator-ramp-delay for BUCKs = [6250/12500/25000(default)/5] uV/us
-
- BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explictly
- regulator-ramp-delay = 0 can be used for them to disable ramp delay.
- In the absence of the regulator-ramp-delay property, the default ramp
- delay will be used.
-
-NOTE: Some BUCKs share the ramp rate setting i.e. same ramp value will be set
-for a particular group of BUCKs. So provide same regulator-ramp-delayvalue.
-Grouping of BUCKs sharing ramp rate setting is as follow : BUCK[1, 6],
-BUCK[3, 4], and BUCK[7, 8, 10]
-
-On S2MPS14 the LDO10, LDO11 and LDO12 can be configured to external control
-over GPIO. To turn this feature on this property must be added to the regulator
-sub-node:
-   - samsung,ext-control-gpios: GPIO specifier for one GPIO
-   controlling this regulator (enable/disable);
-Example:
+  The regulator constraints inside the regulator nodes use the standard
+  regulator bindings which are documented elsewhere.
+
+  The following are the names of the regulators that the s2mps11 pmic block
+  supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+  as per the datasheet of S2MPA01/S2MPS11/S2MPS14.
+
+  - LDOn
+- valid values for n are:
+  - S2MPA01: 1 to 26
+  - S2MPS11: 1 to 38
+  - S2MPS14: 1 to 25
+- Example: LDO1, LDO2, LDO28
+
+  - BUCKn
+- valid values for n are:
+  - S2MPA01: 1 to 10
+  - S2MPS11: 1 to 10
+  - S2MPS14: 1 to 5
+- Example: BUCK1, BUCK2, BUCK9
+
+  Properties for BUCK regulator nodes, only on S2MPA01 and S2MPS11:
+  - regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500, 25000
+or 5. May be 0 for disabling the ramp delay when this is supported.
+
+NOTE: Some BUCKs share the ramp rate setting i.e. same ramp value will
+be set for a particular group of BUCKs. So provide same
+regulator-ramp-delay=value.
+
+- S2MPA01:
+  Default ramp delay: 12500
+  Ramp delay can be disabled for BUCK{1,2,3,4}.
+  BUCKs sharing ramp settings:
+ 

Re: [PATCH] ASoC: max98090: Add NI/MI values for user pclk 19.2 MHz

[Mark Brown]

On Thu, May 22, 2014 at 01:21:43PM +0200, Sylwester Nawrocki wrote:
 From: Chen Zhen zhen1.c...@samsung.com
 
 This patch adds the clock divisor and multiplier NI, MI values for audio
 sampling frequencies 44100 and 48000 Hz and PCLK 19.2 MHz. This is useful
 for the Odroid X2/U2 boards when the codec works in master mode and its
 MCLK clock is fed from the I2S CDCLK output.

Applied, thanks.


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Re: [PATCH v2 13/18] ARM: dts: s6e3fa0: add DT bindings

[Thierry Reding]

On Wed, May 21, 2014 at 01:43:05PM +0900, YoungJun Cho wrote:
 This patch adds DT bindings for s6e3fa0 panel.
 The bindings describes panel resources, display timings and cpu mode timings.
 
 Signed-off-by: YoungJun Cho yj44@samsung.com
 Acked-by: Inki Dae inki@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |   45 
 
  1 file changed, 45 insertions(+)
  create mode 100644 
 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt

You're totally confusing me here. Half of this patch series is about
adding i80 support to Exynos FIMD, and then you go and add what is
apparently a DSI peripheral driver here that's supposed to be used by
this new i80 support. Nothing I've been able to dig up indicates that
i80 or DSI are in anyway related.

Even the Exynos DSI Master bindings[0] say that these two are not at all
the same thing:

port node:
- reg: (required) can be 0 for input RGB/I80 port or 1 for
  DSI port;

Am I missing something here?

Thierry

[0]: 
https://www.kernel.org/doc/Documentation/devicetree/bindings/video/exynos_dsim.txt


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Description: PGP signature

Re: [PATCHv2 1/3] mmc: host: add slot argument to mmc_of_parse

[Ulf Hansson]

On 26 May 2014 13:35, Jaehoon Chung jh80.ch...@samsung.com wrote:
 From: Ludovic Desroches ludovic.desroc...@atmel.com

 Some hosts manage several slots. In these case information such as the
 bus width, chip detect and others are into the slot node. So we have to
 parse child node. If not NULL, slot node will be used instead of the
 device node.

 Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com

Thanks Jaehoon/Ludovic,

Signed-off-by: Ulf Hansson ulf.hans...@linaro.org

 ---
 Changelog V2:
 - Fix the typo.

  drivers/mmc/core/host.c  |   13 +
  include/linux/mmc/host.h |   10 +-
  2 files changed, 18 insertions(+), 5 deletions(-)

 diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
 index 95cceae..0f677b3 100644
 --- a/drivers/mmc/core/host.c
 +++ b/drivers/mmc/core/host.c
 @@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct 
 mmc_host *host)
  #endif

  /**
 - * mmc_of_parse() - parse host's device-tree node
 + * __mmc_of_parse() - parse host's device-tree node
   * @host: host whose node should be parsed.
 + * @slot : some device provide several slots so the node to parse
 + * is not the host one.
   *
   * To keep the rest of the MMC subsystem unaware of whether DT has been
   * used to to instantiate and configure this host instance or not, we
   * parse the properties and set respective generic mmc-host flags and
   * parameters.
   */
 -int mmc_of_parse(struct mmc_host *host)
 +int __mmc_of_parse(struct mmc_host *host, struct device_node *slot)
  {
 struct device_node *np;
 u32 bus_width;
 @@ -317,7 +319,10 @@ int mmc_of_parse(struct mmc_host *host)
 if (!host-parent || !host-parent-of_node)
 return 0;

 -   np = host-parent-of_node;
 +   if (slot)
 +   np = slot;
 +   else
 +   np = host-parent-of_node;

 /* bus-width is translated to MMC_CAP_*_BIT_DATA flags */
 if (of_property_read_u32(np, bus-width, bus_width)  0) {
 @@ -459,7 +464,7 @@ out:
 return ret;
  }

 -EXPORT_SYMBOL(mmc_of_parse);
 +EXPORT_SYMBOL(__mmc_of_parse);

  /**
   * mmc_alloc_host - initialise the per-host structure.
 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
 index 7960424..c62af91 100644
 --- a/include/linux/mmc/host.h
 +++ b/include/linux/mmc/host.h
 @@ -372,7 +372,15 @@ struct mmc_host *mmc_alloc_host(int extra, struct device 
 *);
  int mmc_add_host(struct mmc_host *);
  void mmc_remove_host(struct mmc_host *);
  void mmc_free_host(struct mmc_host *);
 -int mmc_of_parse(struct mmc_host *host);
 +int __mmc_of_parse(struct mmc_host *host, struct device_node *slot);
 +/*
 + * mmc_of_parse - parse host's device-tree node
 + * @host: host whose node should be parsed.
 + */
 +static inline int mmc_of_parse(struct mmc_host *host)
 +{
 +   return __mmc_of_parse(host, NULL);
 +}

  static inline void *mmc_priv(struct mmc_host *host)
  {
 --
 1.7.9.5

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[PATCH v2] ARM: Exynos : Fix build error with thumb2

[Santosh Shukla]

From: santosh shukla santosh.shu...@linaro.org

add non-global symbol .LLl2x0_regs_phys to avoid build break in thumb2 mode.

IIUC, arm assembler fail to load value of global variable
l2xo_regs_phys for thum2 mode and wrapping it in non-global symbol like
.Ll2x0_regs_phys solves the build break issue.

arch/arm/mach-exynos/sleep.S: Assembler messages:
arch/arm/mach-exynos/sleep.S:57: Error: invalid immediate for address
calculation (value = 0x0004)

fix inspired from [1]

[1] : https://lkml.org/lkml/2010/3/31/235

Signed-off-by: santosh shukla santosh.shu...@linaro.org
---
 arch/arm/mach-exynos/sleep.S |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index a2613e9..dc8c6b6 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -54,7 +54,7 @@ ENTRY(exynos_cpu_resume)
ldr r1, =CPU_CORTEX_A9
cmp r0, r1
bne skip_l2_resume
-   adr r0, l2x0_regs_phys
+   adr r0, .Ll2x0_regs_phys
ldr r0, [r0]
cmp r0, #0
beq skip_l2_resume
@@ -79,6 +79,8 @@ skip_l2_resume:
b   cpu_resume
 ENDPROC(exynos_cpu_resume)
 #ifdef CONFIG_CACHE_L2X0
+
+.Ll2x0_regs_phys:
.globl l2x0_regs_phys
 l2x0_regs_phys:
.long   0
-- 
1.7.9.5

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Re: [PATCH v2] ARM: Exynos : Fix build error with thumb2

[Santosh Shukla]

Sorry for incorrect header version and even forgot to add correct list
in loop.. re-posting patch. Pl. ignore.

On 26 May 2014 20:59, Santosh Shukla santosh.shu...@linaro.org wrote:
 From: santosh shukla santosh.shu...@linaro.org

 add non-global symbol .LLl2x0_regs_phys to avoid build break in thumb2 mode.

 IIUC, arm assembler fail to load value of global variable
 l2xo_regs_phys for thum2 mode and wrapping it in non-global symbol like
 .Ll2x0_regs_phys solves the build break issue.

 arch/arm/mach-exynos/sleep.S: Assembler messages:
 arch/arm/mach-exynos/sleep.S:57: Error: invalid immediate for address
 calculation (value = 0x0004)

 fix inspired from [1]

 [1] : https://lkml.org/lkml/2010/3/31/235

 Signed-off-by: santosh shukla santosh.shu...@linaro.org
 ---
  arch/arm/mach-exynos/sleep.S |4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

 diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
 index a2613e9..dc8c6b6 100644
 --- a/arch/arm/mach-exynos/sleep.S
 +++ b/arch/arm/mach-exynos/sleep.S
 @@ -54,7 +54,7 @@ ENTRY(exynos_cpu_resume)
 ldr r1, =CPU_CORTEX_A9
 cmp r0, r1
 bne skip_l2_resume
 -   adr r0, l2x0_regs_phys
 +   adr r0, .Ll2x0_regs_phys
 ldr r0, [r0]
 cmp r0, #0
 beq skip_l2_resume
 @@ -79,6 +79,8 @@ skip_l2_resume:
 b   cpu_resume
  ENDPROC(exynos_cpu_resume)
  #ifdef CONFIG_CACHE_L2X0
 +
 +.Ll2x0_regs_phys:
 .globl l2x0_regs_phys
  l2x0_regs_phys:
 .long   0
 --
 1.7.9.5

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[PATCH] ARM: Exynos : Fix build error with thumb2

[Santosh Shukla]

From: santosh shukla santosh.shu...@linaro.org

Add non-global symbol .LLl2x0_regs_phys to avoid build break in thumb2 mode.

IIUC, arm assembler fail to load value of global variable
l2xo_regs_phys for thum2 mode and wrapping it in non-global symbol like
.Ll2x0_regs_phys solves the build break issue.

arch/arm/mach-exynos/sleep.S: Assembler messages:
arch/arm/mach-exynos/sleep.S:57: Error: invalid immediate for address
calculation (value = 0x0004)

fix inspired from [1]

[1] https://lkml.org/lkml/2010/3/31/235

Signed-off-by: santosh shukla santosh.shu...@linaro.org
---
 arch/arm/mach-exynos/sleep.S |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index a2613e9..dc8c6b6 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -54,7 +54,7 @@ ENTRY(exynos_cpu_resume)
ldr r1, =CPU_CORTEX_A9
cmp r0, r1
bne skip_l2_resume
-   adr r0, l2x0_regs_phys
+   adr r0, .Ll2x0_regs_phys
ldr r0, [r0]
cmp r0, #0
beq skip_l2_resume
@@ -79,6 +79,8 @@ skip_l2_resume:
b   cpu_resume
 ENDPROC(exynos_cpu_resume)
 #ifdef CONFIG_CACHE_L2X0
+
+.Ll2x0_regs_phys:
.globl l2x0_regs_phys
 l2x0_regs_phys:
.long   0
-- 
1.7.9.5

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Re: [PATCH] ASoC: samsung: Use params_width()

[Mark Brown]

On Fri, May 23, 2014 at 05:35:39PM +0530, Tushar Behera wrote:
 commit 8c5178fca4ce (ALSA: Add params_width() helpers) introduces
 a helper to get the sample width. Updating Samsung related sound
 drivers to use this helper.

Applied, thanks.


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Re: [PATCH v2] cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

[Kukjin Kim]

On 05/26/14 14:40, Viresh Kumar wrote:

On 26 May 2014 03:11, Kukjin Kimkgene@samsung.com  wrote:

I'm not sure Thomas' v5 cpufreq-cpu0 driver can be upstreamed for 3.16
because of dependency with others, some of them got ack though...

* PM / OPP: move cpufreq specific helpers out of OPP layer
- https://www.mail-archive.com/linux-omap@vger.kernel.org/msg104610.html


This is already lying in Rafael's tree.


Good.


* cpufreq: opp: Add device tree based lookup of boost mode frequency
- http://www.spinics.net/lists/arm-kernel/msg334336.html


Probably need more time?


So firstly, I've queued this instead with exynos-multiplatform series...

How do you think?


Looks fine to me. Thanks.


OK, I applied with your ack.

Thanks,
- Kukjin
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Re: [PATCH v11 0/3] Exynos 5410 support

[Kukjin Kim]

On 05/26/14 20:11, Tomasz Figa wrote:

Hi,


Hi


On 26.05.2014 05:23, Tarek Dakhran wrote:

The series of patches represent support of Exynos 5410 SoC

The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture

Patches add new platform description, support of clock controller and device
tree for Exynos 5410.

Has been build on Samsung Linux Kernel
   (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' 
into for-next)

Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig)
2) Exynos 5410 reference board (multi_v7_defconfig)
3) Odroid-XU board (exynos_defconfig)
4) Odroid-XU board (multi_v7_defconfig)


Thanks for your test with exynos_defconfig and multi_v7_defconfig.


I hope this is clean and would be applied.

Tarek.

Tarek Dakhran (3):
   ARM: EXYNOS: Add support for EXYNOS5410 SoC
   clk: exynos5410: register clocks using common clock framework
   ARM: dts: Add initial device tree support for EXYNOS5410

  .../devicetree/bindings/clock/exynos5410-clock.txt |   45 +
  arch/arm/boot/dts/Makefile |1 +
  arch/arm/boot/dts/exynos5410-smdk5410.dts  |   82 
  arch/arm/boot/dts/exynos5410.dtsi  |  206 +++
  arch/arm/mach-exynos/Kconfig   |5 +
  arch/arm/mach-exynos/common.h  |   12 +-
  drivers/clk/samsung/Makefile   |1 +
  drivers/clk/samsung/clk-exynos5410.c   |  209 
  include/dt-bindings/clock/exynos5410.h |   33 
  9 files changed, 592 insertions(+), 2 deletions(-)
  create mode 100644 
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
  create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
  create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
  create mode 100644 include/dt-bindings/clock/exynos5410.h



Reviewed-by: Tomasz Figat.f...@samsung.com


Applied this whole series.

Thanks,
Kukjin
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[GIT PULL 4th 2/2] Samsung Exynos 2nd SoC updates for 3.16

[Kukjin Kim]

The following changes since commit 43baa7dcb5fa0c95b1e443d2a739c14de1fbbe07:

  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM 
(2014-05-27 06:22:53 +0900)


are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/exynos-soc-2


for you to fetch changes up to 127cd84d7d1b7e50f5f3e728da23e6f8ac89d249:

  ARM: dts: Add initial device tree support for EXYNOS5410 (2014-05-27 
06:54:13 +0900)



Exynos 2nd new SoC support for 3.16

- add support for exynos5410 SoC and exynos5410-smdk5410 board


Tarek Dakhran (3):
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  clk: exynos5410: register clocks using common clock framework
  ARM: dts: Add initial device tree support for EXYNOS5410

 .../devicetree/bindings/clock/exynos5410-clock.txt |  45 +
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |  82 
 arch/arm/boot/dts/exynos5410.dtsi  | 206 


 arch/arm/mach-exynos/Kconfig   |   5 +
 arch/arm/mach-exynos/common.h  |  12 +-
 drivers/clk/samsung/Makefile   |   1 +
 drivers/clk/samsung/clk-exynos5410.c   | 209 
+

 include/dt-bindings/clock/exynos5410.h |  33 
 9 files changed, 592 insertions(+), 2 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/exynos5410-clock.txt

 create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
 create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos5410.c
 create mode 100644 include/dt-bindings/clock/exynos5410.h
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[GIT PULL 4th 1/2] Samsung Exynos multiplatform for 3.16

[Kukjin Kim]

Hi Arnd, Olof, Kevin

Sorry for late support multiplatform on exynos and now it's possible. 
Thanks for many guys' effort and time :-)


BRs,
Kukjin

The following changes since commit dfacdfef06090ca0c131f45dfd3f3ca3452a8ed3:

  Merge branch 'v3.16-next/dt-samsung' into v3.16-next/multiplatform 
(2014-05-26 06:19:01 +0900)


are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/exynos-multiplatform


for you to fetch changes up to 43baa7dcb5fa0c95b1e443d2a739c14de1fbbe07:

  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM 
(2014-05-27 06:22:53 +0900)



Exynos mutiplatform support for 3.16

Here is enabling the exynos platform as part of a multiplatform
kernel. This is including ARCH_EXYNOS related Kconfig entries
consolidation and update multi_v7_defconfig accordingly. And
fixes exynos-cpufreq driver compilation with ARCH_MULTIPLATFORM.

Note that this is based on tags/exynos-soc. And tags/samsung-dt,
tags/samsung-clk are merged on top of that.


Arnd Bergmann (1):
  ARM: EXYNOS: Enable multi-platform build support

Sachin Kamat (2):
  ARM: EXYNOS: Consolidate Kconfig entries
  ARM: multi_v7_defconfig: Enable Exynos platform

Tomasz Figa (1):
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

 arch/arm/Kconfig | 20 -
 arch/arm/configs/multi_v7_defconfig  | 12 ++
 arch/arm/mach-exynos/Kconfig | 81 


 arch/arm/mach-exynos/Makefile|  2 +
 arch/arm/plat-samsung/Makefile   |  3 ++
 drivers/cpufreq/Kconfig.arm  |  6 +--
 drivers/cpufreq/exynos-cpufreq.c |  2 -
 drivers/cpufreq/exynos-cpufreq.h | 30 +++--
 drivers/cpufreq/exynos4210-cpufreq.c | 39 ++---
 drivers/cpufreq/exynos4x12-cpufreq.c | 40 +++---
 drivers/cpufreq/exynos5250-cpufreq.c | 43 +++
 11 files changed, 163 insertions(+), 115 deletions(-)
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Re: [GIT PULL 4th 1/2] Samsung Exynos multiplatform for 3.16

[Olof Johansson]

On Mon, May 26, 2014 at 3:12 PM, Kukjin Kim kgene@samsung.com wrote:
 Hi Arnd, Olof, Kevin

 Sorry for late support multiplatform on exynos and now it's possible. Thanks
 for many guys' effort and time :-)

 BRs,
 Kukjin

 The following changes since commit dfacdfef06090ca0c131f45dfd3f3ca3452a8ed3:

   Merge branch 'v3.16-next/dt-samsung' into v3.16-next/multiplatform
 (2014-05-26 06:19:01 +0900)

 are available in the git repository at:


   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
 tags/exynos-multiplatform

 for you to fetch changes up to 43baa7dcb5fa0c95b1e443d2a739c14de1fbbe07:

   cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
 (2014-05-27 06:22:53 +0900)

 
 Exynos mutiplatform support for 3.16

 Here is enabling the exynos platform as part of a multiplatform
 kernel. This is including ARCH_EXYNOS related Kconfig entries
 consolidation and update multi_v7_defconfig accordingly. And
 fixes exynos-cpufreq driver compilation with ARCH_MULTIPLATFORM.

 Note that this is based on tags/exynos-soc. And tags/samsung-dt,
 tags/samsung-clk are merged on top of that.

 
 Arnd Bergmann (1):
   ARM: EXYNOS: Enable multi-platform build support

 Sachin Kamat (2):
   ARM: EXYNOS: Consolidate Kconfig entries
   ARM: multi_v7_defconfig: Enable Exynos platform

 Tomasz Figa (1):
   cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

  arch/arm/Kconfig | 20 -
  arch/arm/configs/multi_v7_defconfig  | 12 ++

Please send multi_v7_defconfig updates as patches to a...@kernel.org,
and don't include them in branches. They often conflict and we want to
apply them directly for that reason.


Thanks,

-Olof
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RE: [GIT PULL 4th 1/2] Samsung Exynos multiplatform for 3.16

[Kukjin Kim]

Olof Johansson wrote:
 
 On Mon, May 26, 2014 at 3:12 PM, Kukjin Kim kgene@samsung.com wrote:
  Hi Arnd, Olof, Kevin
 
  Sorry for late support multiplatform on exynos and now it's possible.
 Thanks
  for many guys' effort and time :-)
 
  BRs,
  Kukjin
 
  The following changes since commit
 dfacdfef06090ca0c131f45dfd3f3ca3452a8ed3:
 
Merge branch 'v3.16-next/dt-samsung' into v3.16-next/multiplatform
  (2014-05-26 06:19:01 +0900)
 
  are available in the git repository at:
 
 
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
  tags/exynos-multiplatform
 
  for you to fetch changes up to 43baa7dcb5fa0c95b1e443d2a739c14de1fbbe07:
 
cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  (2014-05-27 06:22:53 +0900)
 
  
  Exynos mutiplatform support for 3.16
 
  Here is enabling the exynos platform as part of a multiplatform
  kernel. This is including ARCH_EXYNOS related Kconfig entries
  consolidation and update multi_v7_defconfig accordingly. And
  fixes exynos-cpufreq driver compilation with ARCH_MULTIPLATFORM.
 
  Note that this is based on tags/exynos-soc. And tags/samsung-dt,
  tags/samsung-clk are merged on top of that.
 
  
  Arnd Bergmann (1):
ARM: EXYNOS: Enable multi-platform build support
 
  Sachin Kamat (2):
ARM: EXYNOS: Consolidate Kconfig entries
ARM: multi_v7_defconfig: Enable Exynos platform
 
  Tomasz Figa (1):
cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
 
   arch/arm/Kconfig | 20 -
   arch/arm/configs/multi_v7_defconfig  | 12 ++
 
 Please send multi_v7_defconfig updates as patches to a...@kernel.org,
 and don't include them in branches. They often conflict and we want to
 apply them directly for that reason.
 
Oh, I see.

So please kindly ignore this (4th) pull-request 1/2 and 2/2 for samsung-3.16, 
because 2/2 is based on this (1/2).

I will re-sort them out then will send it tonight in my time. Unfortunately I 
can't push anything in my office...

Thanks,
Kukjin

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