Hi Kevin,
We tested on 3 peach-pi boards. We are not observing this issue.
Even I tried with the below defconfig mentioned by you. No issues observed.
https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/eclass/cros-kernel/exynos5_defconfig
This is the u-boot
On 06/09/2014 03:43 PM, David Laight wrote:
From: Of Andrzej Hajda
...
You can't error out on module unload, although that's not really relevant
here. gpiochip_remove() is typically called when the device that registered
the GPIO chip is unbound. And despite some remove() callbacks having a
On pon, 2014-06-09 at 09:04 -0700, Doug Anderson wrote:
Krzystof,
On Mon, Jun 9, 2014 at 3:16 AM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
MAX77802 is a PMIC that contains 10 high efficiency Buck regulators,
32
On wto, 2014-06-10 at 00:55 +0200, Javier Martinez Canillas wrote:
Hello Krzystof,
Thanks a lot for your feedback.
On 06/09/2014 06:04 PM, Doug Anderson wrote:
Krzystof,
On Mon, Jun 9, 2014 at 3:16 AM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On pon, 2014-06-09 at 11:37
Hello Krzysztof,
On 10/06/2014, at 09:32, Krzysztof Kozlowski k.kozlow...@samsung.com wrote:
On pon, 2014-06-09 at 09:04 -0700, Doug Anderson wrote:
Krzystof,
On Mon, Jun 9, 2014 at 3:16 AM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On pon, 2014-06-09 at 11:37 +0200, Javier
On 10 June 2014 04:08, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:
[...]
Cold boot and resume from suspend are detected via various special
flags in various special locations. Resume from suspend looks at
INFORM1
On Tue, Dec 17, 2013 at 11:12 AM, Olof Johansson o...@lixom.net wrote:
On Tue, Dec 17, 2013 at 7:14 AM, Charles Keepax
ckee...@opensource.wolfsonmicro.com wrote:
On Mon, Dec 16, 2013 at 09:09:15PM +, Mark Brown wrote:
On Sat, Dec 14, 2013 at 04:41:06AM -0800, Tomasz Figa wrote:
-
This patch makes the changes in spi-s3c64xx.c driver to make use of
cs-gpios from SPI node(parent) instead of cs-gpio defined in
slaves controller-data(child) node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug
This patch returns an integer error value instead of the
pointer.
warning: return makes integer from pointer without a cast
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
---
This patch moves the cs-gpio field from controller-data child
node to under the spi device node.
Respective changes are preposed to spi-s3c64xx.c driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio = ;
...
};
On Tue, Jun 10, 2014 at 05:25:47AM +0100, Nicolas Pitre wrote:
On Mon, 9 Jun 2014, Lorenzo Pieralisi wrote:
I commented on Nico's patch because I did not like how it was
implemented (at least remove the CPU PM notifier calls please, because
they are not needed).
OK no problem. That's
Hi Naveen,
On Tue, Jun 10, 2014 at 2:30 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch returns an integer error value instead of the
pointer.
warning: return makes integer from pointer without a cast
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc:
Hello All,
On 10 June 2014 14:30, Naveen Krishna Chatradhi ch.nav...@samsung.com wrote:
This patch makes the changes in spi-s3c64xx.c driver to make use of
cs-gpios from SPI node(parent) instead of cs-gpio defined in
slaves controller-data(child) node.
Signed-off-by: Naveen Krishna
Hello Sachin,
On 10 June 2014 15:15, Sachin Kamat spk.li...@gmail.com wrote:
Hi Naveen,
On Tue, Jun 10, 2014 at 2:30 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch returns an integer error value instead of the
pointer.
warning: return makes integer from pointer
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio = ;
...
};
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio = ;
...
};
This patch moves the cs-gpio field from controller-data child
node to under the spi device node.
Respective changes are preposed to spi-s3c64xx.c driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson
On 10/06/14 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio
On Tue, Jun 10, 2014 at 01:29:17AM +0200, Javier Martinez Canillas wrote:
On 06/09/2014 09:38 PM, Mark Brown wrote:
On Mon, Jun 09, 2014 at 11:37:47AM +0200, Javier Martinez Canillas wrote:
+ case REGULATOR_MODE_STANDBY:/* switch off */
+ if (id !=
Hello Sylwester,
Thanks for the review.
On 10 June 2014 16:09, Sylwester Nawrocki s.nawro...@samsung.com wrote:
On 10/06/14 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
Hi Pankaj,
On 10.05.2014 08:56, Pankaj Dubey wrote:
As machine function ops are used only in this file let's make
them static. Also remove unused and unwanted declarations from
common.h.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/mach-exynos/common.h |8
Hi Pankaj,
On 10.05.2014 08:56, Pankaj Dubey wrote:
As exynos_cpuidle_init and exynos_cpufreq_init function have just one lines
of code for registering platform devices. We can move these lines to
exynos_dt_machine_init and delete exynos_cpuidle_init and exynos_cpufreq_init
function. This
On Thu, May 29, 2014 at 10:07 AM, Chander Kashyap
chander.kash...@linaro.org wrote:
On 28 May 2014 14:32, Daniel Lezcano daniel.lezc...@linaro.org wrote:
On 05/28/2014 06:35 AM, Kukjin Kim wrote:
Chander Kashyap wrote:
On 26 May 2014 15:59, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi
Hello Inki Dae,
The patch df5225bc9a87: drm/exynos: consider deferred probe case
from May 29, 2014, leads to the following static checker warning:
drivers/gpu/drm/exynos/exynos_drm_fimd.c:996 fimd_probe()
warn: 'ctx-display' isn't an ERR_PTR
Hi Olof,
On 03.06.2014 06:47, Olof Johansson wrote:
This solves a problem with building with CONFIG_SMP=n due to missing
sysram_base_addr (or sysram_ns_base_addr) variables.
The new setup method is more awkward than I'd like for it to be, but
it can't be done in init_early() since ioremap
Hi Olof,
On 03.06.2014 06:57, Olof Johansson wrote:
There's no reason to export these functions, and I have no idea why
they have over time ended up in the header file. As a result, none of
the checker tools caught it (i.e. sparse was silent on it).
Signed-off-by: Olof Johansson
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
Let's handle i2c interrupt re-configuration in i2c driver. This will
help us in removing some soc specific checks from machine files.
Since only Exynos5250, and Exynos5420 need to do this, added syscon
based phandle to i2c device nodes of
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
Since all these code has been moved into i2c driver, now we can
safely remove them from machine files.
CC: Russell King li...@arm.linux.org.uk
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/mach-exynos/exynos.c
On 10.05.2014 09:20, Pankaj Dubey wrote:
This patch removes usage of soc_is_exynos4/5 from exynos.c.
For this we need to separate machine descriptors for exynos4
and exynos5. While doing this patch does some consolidation also.
CC: Russell King li...@arm.linux.org.uk
CC: Thomas Abraham
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
This patch removed plat/cpu.h inclusion from hotplug.c as it
is not required.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/mach-exynos/hotplug.c |2 --
1 file changed, 2 deletions(-)
diff --git
On Tuesday 10 June 2014 15:55:09 Tomasz Figa wrote:
On 10.05.2014 09:20, Pankaj Dubey wrote:
This patch removes usage of soc_is_exynos4/5 from exynos.c.
For this we need to separate machine descriptors for exynos4
and exynos5. While doing this patch does some consolidation also.
CC:
From: Rob Herring r...@kernel.org
The addition of Exynos to multi-platform configs creates a mess of config
options with options appearing before the Exynos config option. This is
due to arch/arm/plat-samsung/Kconfig being included out of order with the
other Samsung platform kconfig files.
Hi Nico,
Sorry, I can't stay away from this thread ;)
On Tue, Jun 10, 2014 at 12:25:47AM -0400, Nicolas Pitre wrote:
On Mon, 9 Jun 2014, Lorenzo Pieralisi wrote:
4) When I am talking about firmware I am talking about sequences that
are very close to HW (disabling C bit, cleaning caches,
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
Exynos SoCs have Chipid, for identification of product IDs
and SoC revistions. Till now we are using static macros
such as soc_is_exynos and #ifdefs for run time identification
of SoCs and their revisions. This is leading to add new
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
This patch enables chipid driver for ARCH_EXYNOS and refactors
machine code as well as exynos cpufreq driver code for using
chipid driver for identification of SoC ID and SoC rev.
This patch also updates DT binding information in exynos4
Chander,
On Tue, Jun 10, 2014 at 1:12 AM, Chander Kashyap
chander.kash...@linaro.org wrote:
On 10 June 2014 04:08, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:
[...]
Cold boot and resume from suspend are detected via
Hi,
On 01.06.2014 19:15, Vasily Khoruzhick wrote:
Use dmaengine instead of legacy s3c24xx DMA API for s3c24xx and s3c2412
Signed-off-by: Vasily Khoruzhick anars...@gmail.com
---
v2: use hardcoded dma channel number
sound/soc/samsung/Kconfig | 9 +++
Hi,
On 01.06.2014 19:15, Vasily Khoruzhick wrote:
Signed-off-by: Vasily Khoruzhick anars...@gmail.com
---
v2: No changes
sound/soc/samsung/Kconfig | 3 -
sound/soc/samsung/Makefile | 2 -
sound/soc/samsung/dma.c| 460
-
3 files
Hi Kukjin,
On 30.05.2014 20:18, Kukjin Kim wrote:
On 05/30/14 20:41, Tomasz Figa wrote:
Hi,
On 23.05.2014 16:39, Tomasz Figa wrote:
This patch fixes reg entry sizes in GIC node that were not large enough
to cover whole regions.
Signed-off-by: Tomasz Figat.f...@samsung.com
---
Hi,
On 26.05.2014 13:56, Shaik Ameer Basha wrote:
From: Prathyush K prathyus...@samsung.com
While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG
Hi,
On 26.05.2014 13:56, Shaik Ameer Basha wrote:
From: Arun Kumar K arun...@samsung.com
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Shaik Ameer Basha
On Tue, 10 Jun 2014, Doug Anderson wrote:
My S-state knowledge is not strong, but I believe that Lorenzo's
questions matter if we're using S2 for CPUidle (where we actually turn
off power and hot unplug CPUs) but not when we're using S1 for CPUidle
(where we just enter WFI/WFE).
I believe
On Tue, 10 Jun 2014, Catalin Marinas wrote:
Hi Nico,
Sorry, I can't stay away from this thread ;)
;-)
On Tue, Jun 10, 2014 at 12:25:47AM -0400, Nicolas Pitre wrote:
On Mon, 9 Jun 2014, Lorenzo Pieralisi wrote:
4) When I am talking about firmware I am talking about sequences that
Hi,
On 10.05.2014 08:56, Pankaj Dubey wrote:
From: Young-Gun Jang yg1004.j...@samsung.com
Add support for mapping Samsung Power Management Unit (PMU)
base address from device tree. This patch also adds helper
function as get_exynos_pmuregmap. This function can be used
by other machine
Hi,
On Mon, Jun 9, 2014 at 11:48 PM, Shaik Ameer Basha
shaik.sams...@gmail.com wrote:
Hi Kevin,
We tested on 3 peach-pi boards. We are not observing this issue.
Even I tried with the below defconfig mentioned by you. No issues observed.
I'm trying to get the latest linux-next working on my Chromebook2
(it's booting to a serial console) and am now trying to get the
display working (at least for a frambuffer console.)
Since the display nodes seem to be present in the exynos5800-peach-pi
DTS, I tried enabling DRM and it's failing
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org wrote:
I'm trying to get the latest linux-next working on my Chromebook2
(it's booting to a serial console) and am now trying to get the
display working (at least for a frambuffer console.)
Since the display nodes seem to be
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the original pattern will not work with
new kernels any more. At least I would expect
On Tue, Jun 10, 2014 at 11:04 AM, Stéphane Marchesin
marc...@chromium.org wrote:
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org wrote:
I'm trying to get the latest linux-next working on my Chromebook2
(it's booting to a serial console) and am now trying to get the
display
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
controller-data {
-
On Tue, Jun 10, 2014 at 11:24 AM, Kevin Hilman khil...@linaro.org wrote:
On Tue, Jun 10, 2014 at 11:04 AM, Stéphane Marchesin
marc...@chromium.org wrote:
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org wrote:
I'm trying to get the latest linux-next working on my Chromebook2
On 10.06.2014 20:04, Stéphane Marchesin wrote:
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org wrote:
I'm trying to get the latest linux-next working on my Chromebook2
(it's booting to a serial console) and am now trying to get the
display working (at least for a frambuffer
On Tue, 10 Jun 2014, Catalin Marinas wrote:
On Tue, Jun 10, 2014 at 05:49:01PM +0100, Nicolas Pitre wrote:
The M-class processor should be treated the same way as firmware. It
ought to be flexible (certainly more than hardwired hardware), but it
shares all the same downsides as firmware
On 10.06.2014 20:26, Doug Anderson wrote:
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
On Tue, Jun 10, 2014 at 11:04 AM, Stéphane Marchesin
marc...@chromium.org wrote:
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org wrote:
I'm trying to get the latest linux-next working on my Chromebook2
(it's booting to a serial console) and am now trying to get the
display
On 10.06.2014 20:09, Doug Anderson wrote:
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the original pattern will not work with
Hi Naveen,
On 10.06.2014 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
[snip]
@@ -85,6 +83,7 @@ Example:
#size-cells = 0;
pinctrl-names = default;
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip select number of SPI devices (indicated by their reg
properties).
Moreover, is there a need to parse this manually in this
On 10.06.2014 21:58, Doug Anderson wrote:
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip select number of SPI devices (indicated by their reg
properties).
Moreover, is
Hello Doug,
On 06/10/2014 07:39 PM, Doug Anderson wrote:
Hi,
On Mon, Jun 9, 2014 at 11:48 PM, Shaik Ameer Basha
shaik.sams...@gmail.com wrote:
Hi Kevin,
We tested on 3 peach-pi boards. We are not observing this issue.
Even I tried with the below defconfig mentioned by you. No issues
Tomasz,
On Tue, Jun 10, 2014 at 12:59 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 10.06.2014 21:58, Doug Anderson wrote:
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip
Javier,
On Tue, Jun 10, 2014 at 1:03 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Yes, I did not have this issue before. However... I installed the latest Peach
pit recovery image you provided me and mainline kernel started to hang on
boot.
I remembered this thread so
On Tue, Jun 10, 2014 at 1:09 PM, Doug Anderson diand...@chromium.org wrote:
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the
Hi,
On 6/11/14, Kevin Hilman khil...@linaro.org wrote:
On Tue, Jun 10, 2014 at 11:04 AM, Stéphane Marchesin
marc...@chromium.org wrote:
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org
wrote:
I'm trying to get the latest linux-next working on my Chromebook2
(it's booting to
If there is no panel node in DT and instead display timings are provided
directly in FIMD node, there is no panel object created and ctx-panel
becomes NULL. However during Exynos DRM initialization
drm_helper_hpd_irq_event() is called, which in turns calls
exynos_dpi_detect(), which dereferences
Hi Ajay,
On Tue, Jun 10, 2014 at 1:51 PM, Ajay kumar ajayn...@gmail.com wrote:
Hi,
On 6/11/14, Kevin Hilman khil...@linaro.org wrote:
On Tue, Jun 10, 2014 at 11:04 AM, Stéphane Marchesin
marc...@chromium.org wrote:
On Tue, Jun 10, 2014 at 10:56 AM, Kevin Hilman khil...@linaro.org
wrote:
Hi Chanwoo,
On 11.06.2014 01:27, Chanwoo Choi wrote:
This patch set AUTOWAKEUP_EN bit to ARM_CORE_CONFIGURATION register
because Exynos3250 removes WFE in secure mode so that turn on automatically
after setting CORE_LOCAL_PWR_EN. Also, This patch use dbs_sev() macro
to guarantee the data
On 06/11/2014 08:35 AM, Tomasz Figa wrote:
Hi Chanwoo,
On 11.06.2014 01:27, Chanwoo Choi wrote:
This patch set AUTOWAKEUP_EN bit to ARM_CORE_CONFIGURATION register
because Exynos3250 removes WFE in secure mode so that turn on automatically
after setting CORE_LOCAL_PWR_EN. Also, This patch
On 11.06.2014 01:44, Chanwoo Choi wrote:
On 06/11/2014 08:35 AM, Tomasz Figa wrote:
Hi Chanwoo,
On 11.06.2014 01:27, Chanwoo Choi wrote:
This patch set AUTOWAKEUP_EN bit to ARM_CORE_CONFIGURATION register
because Exynos3250 removes WFE in secure mode so that turn on automatically
after
Exynos4 has saveral PPMUs and each of them has operation clock which
can be gated through CMU's SFR control.
New clocks are listed below. All clocks are added as a gate-typed clock.
CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE,
Hi Jonghwa,
On 11.06.2014 02:22, Jonghwa Lee wrote:
Exynos4 has saveral PPMUs and each of them has operation clock which
can be gated through CMU's SFR control.
New clocks are listed below. All clocks are added as a gate-typed clock.
CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV,
On 11 June 2014 03:48, Kevin Hilman khil...@linaro.org wrote:
Hi Ajay,
On Tue, Jun 10, 2014 at 1:51 PM, Ajay kumar ajayn...@gmail.com wrote:
Hi,
On 6/11/14, Kevin Hilman khil...@linaro.org wrote:
On Tue, Jun 10, 2014 at 11:04 AM, Stéphane Marchesin
marc...@chromium.org wrote:
On Tue, Jun
Hi Doug,
On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Tue, 10 Jun 2014, Doug Anderson wrote:
My S-state knowledge is not strong, but I believe that Lorenzo's
questions matter if we're using S2 for CPUidle (where we actually turn
off power and hot unplug
With next-20140610, Peach-pit/Peach-pi board hangs during boot if we
run 'sound init' during u-boot. The issue is fixed in following patches.
While at it, also enable audio support for Peach-pi board.
How to test audio on Peach-pi:
* On top of exynos_defconfig, enable SND_SOC_SNOW and PL330_DMA
When the output clock of AUDSS mux is disabled, we are getting kernel
oops while doing a clk_get() on other clocks provided by AUDSS. Though
user manual doesn't specify this dependency, we came across this issue
while disabling the parent of AUDSS mux clocks.
Keeping the parents of AUDSS mux
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
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