[PATCH v2] ARM: dts: Add mask-tpm-reset to the device tree
From: Doug Anderson diand...@chromium.org
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
---
changes since v1:
- removed fixed regulator and used hogs instead.
arch/arm/boot/dts/exynos5420-peach-pit.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 6c7cab0..c036d9e 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -211,6 +211,18 @@
pinctrl_0 {
+ pinctrl-names = default;
+ pinctrl-0 = mask_tpm_reset;
+
+ /* We need GPX0_6 to be low at sleep time; just keep it low always */
+ mask_tpm_reset: mask-tpm-reset {
+ samsung,pins = gpx0-6;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ samsung,pin-val = 0;
+ };
+
max98090_irq: max98090-irq {
samsung,pins = gpx0-2;
samsung,pin-function = 0;
--
1.7.9.5
--
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[PATCH v2] ARM: EXYNOS: Fix build with PM_SLEEP=n
Fix building of exynos defconfig with disabled PM_SLEEP:
CONFIG_PM_SLEEP=n
CONFIG_PM_SLEEP_SMP=n
CONFIG_SUSPEND=n
by moving functions for power up/down of CPU and cluster to platsmp.c
The build error messages:
arch/arm/mach-exynos/built-in.o: In function `exynos_boot_secondary':
arch/arm/mach-exynos/platsmp.c:111: undefined reference to
`exynos_cpu_power_state'
arch/arm/mach-exynos/platsmp.c:112: undefined reference to `exynos_cpu_power_up'
arch/arm/mach-exynos/platsmp.c:116: undefined reference to
`exynos_cpu_power_state'
make: *** [vmlinux] Error 1
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v1:
1. Use different solution - just move the power up/down functions to a
common place instead of adding stubs in common.h. Suggested by Tomasz
Figa.
---
arch/arm/mach-exynos/platsmp.c | 66 ++
arch/arm/mach-exynos/pm.c | 66 --
2 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index b15ea30faa7c..d435175671e0 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -31,6 +31,72 @@
extern void exynos4_secondary_startup(void);
+/**
+ * exynos_core_power_down : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power down the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_power_down(int cpu)
+{
+ __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_up : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_power_up(int cpu)
+{
+ __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+ return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu))
+ S5P_CORE_LOCAL_PWR_EN);
+}
+
+/**
+ * exynos_cluster_power_down : power down the specified cluster
+ * @cluster : the cluster to power down
+ */
+void exynos_cluster_power_down(int cluster)
+{
+ __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_up : power up the specified cluster
+ * @cluster : the cluster to power up
+ */
+void exynos_cluster_power_up(int cluster)
+{
+ __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_state : returns the power state of the cluster
+ * @cluster : the cluster to retrieve the power state from
+ *
+ */
+int exynos_cluster_power_state(int cluster)
+{
+ return (__raw_readl(EXYNOS_COMMON_STATUS(cluster))
+ S5P_CORE_LOCAL_PWR_EN);
+}
+
static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index fa7218a99580..6ab68a068e93 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -101,72 +101,6 @@ static int exynos_irq_set_wake(struct irq_data *data,
unsigned int state)
return -ENOENT;
}
-/**
- * exynos_core_power_down : power down the specified cpu
- * @cpu : the cpu to power down
- *
- * Power down the specified cpu. The sequence must be finished by a
- * call to cpu_do_idle()
- *
- */
-void exynos_cpu_power_down(int cpu)
-{
- __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
-}
-
-/**
- * exynos_cpu_power_up : power up the specified cpu
- * @cpu : the cpu to power up
- *
- * Power up the specified cpu
- */
-void exynos_cpu_power_up(int cpu)
-{
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-EXYNOS_ARM_CORE_CONFIGURATION(cpu));
-}
-
-/**
- * exynos_cpu_power_state : returns the power state of the cpu
- * @cpu : the cpu to retrieve the power state from
- *
- */
-int exynos_cpu_power_state(int cpu)
-{
- return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu))
- S5P_CORE_LOCAL_PWR_EN);
-}
-
-/**
- * exynos_cluster_power_down : power down the specified cluster
- * @cluster : the cluster to power down
- */
-void exynos_cluster_power_down(int cluster)
-{
- __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
-}
-
-/**
- * exynos_cluster_power_up : power up the specified cluster
- * @cluster : the cluster to power up
- */
-void exynos_cluster_power_up(int cluster)
-{
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-EXYNOS_COMMON_CONFIGURATION(cluster));
-}
-
-/**
- * exynos_cluster_power_state : returns the power state of the cluster
- * @cluster : the cluster to retrieve the power state from
- *
- */
-int exynos_cluster_power_state(int cluster)
-{
- return (__raw_readl(EXYNOS_COMMON_STATUS(cluster))
-
Re: [PATCH 1/6] mmc: sdhci-s3c: Fix local I/O clock gating
Looks good to me.
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
On 06/24/2014 10:57 PM, Tomasz Figa wrote:
For internal card detection mechanism it is required that the local I/O
clock is always running. However while current implementation accounts
for this, it does so incorrectly leading to race conditions and warnings
about unbalanced clock disables.
This patch fixes it by inverting the logic, which now increases local
I/O clock enable count when internal card detect is used, instead of
decreasing it otherwise.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Cc: Ben Dooks ben-li...@fluff.org
Cc: Chris Ball ch...@printf.net
Cc: Ulf Hansson ulf.hans...@linaro.org
Cc: linux-...@vger.kernel.org
---
drivers/mmc/host/sdhci-s3c.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index fa5954a..1795e1f 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -487,8 +487,13 @@ static int sdhci_s3c_probe(struct platform_device *pdev)
goto err_pdata_io_clk;
}
- /* enable the local io clock and keep it running for the moment. */
- clk_prepare_enable(sc-clk_io);
+ /*
+ * Keep local I/O clock enabled for internal card detect pin
+ * or runtime PM is disabled.
+ */
+ if (pdata-cd_type == S3C_SDHCI_CD_INTERNAL
+ || !IS_ENABLED(CONFIG_PM_RUNTIME))
+ clk_prepare_enable(sc-clk_io);
for (clks = 0, ptr = 0; ptr MAX_BUS_CLK; ptr++) {
char name[14];
@@ -611,15 +616,13 @@ static int sdhci_s3c_probe(struct platform_device *pdev)
goto err_req_regs;
}
-#ifdef CONFIG_PM_RUNTIME
- if (pdata-cd_type != S3C_SDHCI_CD_INTERNAL)
- clk_disable_unprepare(sc-clk_io);
-#endif
return 0;
err_req_regs:
err_no_busclks:
- clk_disable_unprepare(sc-clk_io);
+ if (pdata-cd_type == S3C_SDHCI_CD_INTERNAL
+ || !IS_ENABLED(CONFIG_PM_RUNTIME))
+ clk_disable_unprepare(sc-clk_io);
err_pdata_io_clk:
sdhci_free_host(host);
--
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Re: [PATCH 2/3] regulator: s2mpa01: Optimize the regulator description macro
On 08.07.2014 14:27, Amit Daniel Kachhap wrote:
This patch makes the regulator description macro take minimum and
steps voltage as parameter. In this way many repeated macros can be
removed. Now these macros are repeated only if the the LDO/BUCK ctrl
registers have non-linear positions. The good thing is these ctrl registers
are mostly linear so they are not passed as parameters.
This patch reduces the code size and also allow easy addition of more
s2mpxxx PMIC drivers which differs a lot in minimum/step voltages.
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
drivers/regulator/s2mpa01.c | 136
1 file changed, 37 insertions(+), 99 deletions(-)
diff --git a/drivers/regulator/s2mpa01.c b/drivers/regulator/s2mpa01.c
index 962c5f1..8073466 100644
--- a/drivers/regulator/s2mpa01.c
+++ b/drivers/regulator/s2mpa01.c
@@ -235,28 +235,14 @@ static struct regulator_ops s2mpa01_buck_ops = {
.set_ramp_delay = s2mpa01_set_ramp_delay,
};
-#define regulator_desc_ldo1(num) { \
+#define regulator_desc_ldo(num, min, step) { \
Why adding parameter for the 'min' value? It is always the same for LDOs
- 800 mV.
The same applies for the s2mps11 regulator driver.
Best regards,
Krzysztof
.name = LDO#num, \
.id = S2MPA01_LDO##num, \
.ops= s2mpa01_ldo_ops, \
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = MIN_800_MV, \
- .uV_step= STEP_50_MV, \
- .n_voltages = S2MPA01_LDO_N_VOLTAGES, \
- .vsel_reg = S2MPA01_REG_L1CTRL + num - 1, \
- .vsel_mask = S2MPA01_LDO_VSEL_MASK,\
- .enable_reg = S2MPA01_REG_L1CTRL + num - 1, \
- .enable_mask= S2MPA01_ENABLE_MASK \
-}
-#define regulator_desc_ldo2(num) { \
- .name = LDO#num, \
- .id = S2MPA01_LDO##num, \
- .ops= s2mpa01_ldo_ops, \
- .type = REGULATOR_VOLTAGE,\
- .owner = THIS_MODULE, \
- .min_uV = MIN_800_MV, \
- .uV_step= STEP_25_MV, \
+ .min_uV = min, \
+ .uV_step= step, \
.n_voltages = S2MPA01_LDO_N_VOLTAGES, \
.vsel_reg = S2MPA01_REG_L1CTRL + num - 1, \
.vsel_mask = S2MPA01_LDO_VSEL_MASK,\
@@ -296,14 +282,14 @@ static struct regulator_ops s2mpa01_buck_ops = {
.enable_mask= S2MPA01_ENABLE_MASK \
}
-#define regulator_desc_buck6_7(num){ \
+#define regulator_desc_buck6_10(num, min, step){ \
.name = BUCK#num, \
.id = S2MPA01_BUCK##num,\
.ops= s2mpa01_buck_ops,\
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = MIN_600_MV, \
- .uV_step= STEP_6_25_MV, \
+ .min_uV = min, \
+ .uV_step= step, \
.n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
.ramp_delay = S2MPA01_RAMP_DELAY, \
.vsel_reg = S2MPA01_REG_B6CTRL2 + (num - 6) * 2, \
@@ -312,91 +298,43 @@ static struct regulator_ops s2mpa01_buck_ops = {
.enable_mask= S2MPA01_ENABLE_MASK \
}
-#define regulator_desc_buck8 { \
- .name = BUCK8,\
- .id = S2MPA01_BUCK8,\
- .ops= s2mpa01_buck_ops,\
- .type = REGULATOR_VOLTAGE,\
- .owner = THIS_MODULE, \
- .min_uV = MIN_800_MV, \
- .uV_step= STEP_12_5_MV, \
- .n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
- .ramp_delay = S2MPA01_RAMP_DELAY, \
- .vsel_reg = S2MPA01_REG_B8CTRL2, \
- .vsel_mask = S2MPA01_BUCK_VSEL_MASK, \
- .enable_reg = S2MPA01_REG_B8CTRL1, \
- .enable_mask= S2MPA01_ENABLE_MASK \
-}
-
-#define regulator_desc_buck9 { \
- .name = BUCK9,
Re: [PATCH 1/3] regulator: s2mpxxx: Move regulator min/step voltages in common place
On 08.07.2014 14:27, Amit Daniel Kachhap wrote:
This is a cleanup patch and moves min/step voltages in a common samsung
header file so that they can be used by other s2mpxxx PMIC drivers. Only
few required macros are added currently and others can be added if needed.
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
drivers/regulator/s2mpa01.c | 32
drivers/regulator/s2mps11.c | 50 ++---
include/linux/mfd/samsung/core.h| 21
include/linux/mfd/samsung/s2mpa01.h | 12 -
include/linux/mfd/samsung/s2mps11.h | 9 ---
include/linux/mfd/samsung/s2mps14.h | 10
6 files changed, 62 insertions(+), 72 deletions(-)
Hi,
Looks good.
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Best regards,
Krzysztof
diff --git a/drivers/regulator/s2mpa01.c b/drivers/regulator/s2mpa01.c
index ee83b48..962c5f1 100644
--- a/drivers/regulator/s2mpa01.c
+++ b/drivers/regulator/s2mpa01.c
@@ -241,8 +241,8 @@ static struct regulator_ops s2mpa01_buck_ops = {
.ops= s2mpa01_ldo_ops, \
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = S2MPA01_LDO_MIN, \
- .uV_step= S2MPA01_LDO_STEP1,\
+ .min_uV = MIN_800_MV, \
+ .uV_step= STEP_50_MV, \
.n_voltages = S2MPA01_LDO_N_VOLTAGES, \
.vsel_reg = S2MPA01_REG_L1CTRL + num - 1, \
.vsel_mask = S2MPA01_LDO_VSEL_MASK,\
@@ -255,8 +255,8 @@ static struct regulator_ops s2mpa01_buck_ops = {
.ops= s2mpa01_ldo_ops, \
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = S2MPA01_LDO_MIN, \
- .uV_step= S2MPA01_LDO_STEP2,\
+ .min_uV = MIN_800_MV, \
+ .uV_step= STEP_25_MV, \
.n_voltages = S2MPA01_LDO_N_VOLTAGES, \
.vsel_reg = S2MPA01_REG_L1CTRL + num - 1, \
.vsel_mask = S2MPA01_LDO_VSEL_MASK,\
@@ -270,8 +270,8 @@ static struct regulator_ops s2mpa01_buck_ops = {
.ops= s2mpa01_buck_ops,\
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = S2MPA01_BUCK_MIN1,\
- .uV_step= S2MPA01_BUCK_STEP1, \
+ .min_uV = MIN_600_MV, \
+ .uV_step= STEP_6_25_MV, \
.n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
.ramp_delay = S2MPA01_RAMP_DELAY, \
.vsel_reg = S2MPA01_REG_B1CTRL2 + (num - 1) * 2, \
@@ -286,8 +286,8 @@ static struct regulator_ops s2mpa01_buck_ops = {
.ops= s2mpa01_buck_ops,\
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = S2MPA01_BUCK_MIN2,\
- .uV_step= S2MPA01_BUCK_STEP1, \
+ .min_uV = MIN_800_MV, \
+ .uV_step= STEP_6_25_MV, \
.n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
.ramp_delay = S2MPA01_RAMP_DELAY, \
.vsel_reg = S2MPA01_REG_B5CTRL2, \
@@ -302,8 +302,8 @@ static struct regulator_ops s2mpa01_buck_ops = {
.ops= s2mpa01_buck_ops,\
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = S2MPA01_BUCK_MIN1,\
- .uV_step= S2MPA01_BUCK_STEP1, \
+ .min_uV = MIN_600_MV, \
+ .uV_step= STEP_6_25_MV, \
.n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
.ramp_delay = S2MPA01_RAMP_DELAY, \
.vsel_reg = S2MPA01_REG_B6CTRL2 + (num - 6) * 2, \
@@ -318,8 +318,8 @@ static struct regulator_ops s2mpa01_buck_ops = {
.ops= s2mpa01_buck_ops,\
.type = REGULATOR_VOLTAGE,\
.owner = THIS_MODULE, \
- .min_uV = S2MPA01_BUCK_MIN2,\
- .uV_step= S2MPA01_BUCK_STEP2, \
+ .min_uV = MIN_800_MV, \
+ .uV_step
Re: [PATCH v2 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
Hi, On Wednesday 09 July 2014 05:19 PM, Sachin Kamat wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. There is a new Exynos PHY in town, Exynos 3250. Can you rebase your patch on top of that? Thanks Kishon Signed-off-by: Sachin Kamat sachin.ka...@samsung.com --- Changes since v1: * Added dependency on DWC2 gadget driver as suggested by Tomasz Figa. --- drivers/phy/Kconfig | 35 +++ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index fcdfe7c0e4a7..128f8b92b55c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -123,43 +123,30 @@ config PHY_SUN4I_USB config PHY_SAMSUNG_USB2 tristate Samsung USB 2.0 PHY driver depends on HAS_IOMEM + depends on USB_EHCI_EXYNOS || USB_OHCI_EXYNOS || USB_DWC2 select GENERIC_PHY select MFD_SYSCON + default ARCH_EXYNOS help Enable this to support the Samsung USB 2.0 PHY driver for Samsung - SoCs. This driver provides the interface for USB 2.0 PHY. Support for - particular SoCs has to be enabled in addition to this driver. Number - and type of supported phys depends on the SoC. + SoCs. This driver provides the interface for USB 2.0 PHY. Support + for particular PHYs will be enabled based on the SoC type in addition + to this driver. config PHY_EXYNOS4210_USB2 - bool Support for Exynos 4210 + bool depends on PHY_SAMSUNG_USB2 - depends on CPU_EXYNOS4210 - help - Enable USB PHY support for Exynos 4210. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 4210 four - phys are available - device, host, HSIC0 and HSIC1. + default CPU_EXYNOS4210 config PHY_EXYNOS4X12_USB2 - bool Support for Exynos 4x12 + bool depends on PHY_SAMSUNG_USB2 - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) - help - Enable USB PHY support for Exynos 4x12. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 4x12 four - phys are available - device, host, HSIC0 and HSIC1. + default SOC_EXYNOS4212 || SOC_EXYNOS4412 config PHY_EXYNOS5250_USB2 - bool Support for Exynos 5250 + bool depends on PHY_SAMSUNG_USB2 - depends on SOC_EXYNOS5250 - help - Enable USB PHY support for Exynos 5250. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 5250 four - phys are available - device, host, HSIC0 and HSIC. + default SOC_EXYNOS5250 || SOC_EXYNOS5420 config PHY_EXYNOS5_USBDRD tristate Exynos5 SoC series USB DRD PHY driver -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
Hi, On Mon, Jul 14, 2014 at 2:26 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Wednesday 09 July 2014 05:19 PM, Sachin Kamat wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. There is a new Exynos PHY in town, Exynos 3250. Can you rebase your patch on top of that? Sure. But I did not see it in linux-next yet. Is it merged somewhere? -- Regards, Sachin. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
On Monday 14 July 2014 02:29 PM, Sachin Kamat wrote: Hi, On Mon, Jul 14, 2014 at 2:26 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Wednesday 09 July 2014 05:19 PM, Sachin Kamat wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. There is a new Exynos PHY in town, Exynos 3250. Can you rebase your patch on top of that? Sure. But I did not see it in linux-next yet. Is it merged somewhere? It's in the list. I can push it to my tree if that helps. -Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
On Mon, Jul 14, 2014 at 2:32 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 14 July 2014 02:29 PM, Sachin Kamat wrote: Hi, On Mon, Jul 14, 2014 at 2:26 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Wednesday 09 July 2014 05:19 PM, Sachin Kamat wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. There is a new Exynos PHY in town, Exynos 3250. Can you rebase your patch on top of that? Sure. But I did not see it in linux-next yet. Is it merged somewhere? It's in the list. I can push it to my tree if that helps. That would be great to avoid any other conflicts. -- Regards, Sachin. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: remove display power domain for exynos5420
Hi Kukjin, Please consider this patch for your branch. This patch is important for Display for Exynos5 boards. Regards, Rahul Sharma. On 9 July 2014 17:00, Rahul Sharma rahul.sha...@samsung.com wrote: Hi Tomasz, On 8 July 2014 21:04, Tomasz Figa t.f...@samsung.com wrote: Hi Rahul, On 07.07.2014 15:37, Rahul Sharma wrote: Hi Andrej, Inki, On 18 June 2014 12:06, Rahul Sharma rahul.sha...@samsung.com wrote: Hi Andrej, On 18 June 2014 11:46, Andrzej Hajda a.ha...@samsung.com wrote: On 06/17/2014 07:49 AM, Rahul Sharma wrote: Hi All, Please review this patch. Regards, Rahul Sharma On 9 June 2014 16:58, Rahul Sharma rahul.sha...@samsung.com wrote: Display domain is removed due to instability issues. Explaining the problem below: exynos_init_late triggers the pm_genpd_poweroff_unused which powers off the unused power domains. This call hits before the trigger to deferred probes. DRM DP Panel defers the probe due to supply get failure. By the time, deferred probe is scheduled again, Display Power Domain is powered off by pm_genpd_poweroff_unused. FIMD and DP drivers are accessing registers during Probe and Bind callbacks. If display domain is enabled/disabled around register accesses, display domain gets unstable and we are getting Power Domain Disable fail notification. Increasing the Timeout also didn't help. As I understand the problem is that fimd and dp drivers access hw registers without enabling power domain. So the proper solution is to fix these drivers. That is also a problem but I fixed those accesses in my local kernel before hitting this issue. If we do register accesses in FIMD/DP probe/bind we observes Prefetch abort exception. But here the problem is that 'DP domain disable' starts failing if we enable/disable multiple times. Btw. there are already patches removing hw access from probe/bind of fimd. I guess removing also hw access from dp probe/bind could be a good solution. Please let me know the links for posted patches. I will test with those patches. Is there any update on this? Please share the patches which fixes the above issue or avoid the above scenario of multiple PM Domain enable/disable. I will test them for exynos5 based boards. Otherwise we should get this change merged else display will remain broken for exynos5 based boards. Andrzej is on holidays right now, so he won't be able to reply in this thread until he's back. Here are two patches I was able to find on the related MLs that might be fixing the cause of your issues: Ok. thanks for the update. We should test with Ajay's patches which includes DP probe deferring based on availability of bridge chip. + few patches which cleanup register access in FIMD and DP probe/bind OR few patches to enable Display power domain and clocks just before the register access. As done in https://lkml.org/lkml/2014/7/4/188. Later solution results into display power domain enable failure in case of DRM probe defer. I am just curious if Andrej has some solution for the first approach which can be tested for defer probe and S2R scenarios. Regards, Rahul Sharma. [PATCH] drm/exynos: remove hardware overlays disable from fimd probe (https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31629.html) [PATCH] drm/exynos: fimd: Keep power enabled during fimd_bind (https://lkml.org/lkml/2014/7/4/188) Best regards, Tomasz ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
On Monday 14 July 2014 02:36 PM, Sachin Kamat wrote: On Mon, Jul 14, 2014 at 2:32 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 14 July 2014 02:29 PM, Sachin Kamat wrote: Hi, On Mon, Jul 14, 2014 at 2:26 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Wednesday 09 July 2014 05:19 PM, Sachin Kamat wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. There is a new Exynos PHY in town, Exynos 3250. Can you rebase your patch on top of that? Sure. But I did not see it in linux-next yet. Is it merged somewhere? It's in the list. I can push it to my tree if that helps. That would be great to avoid any other conflicts. pushed to git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next. You can use it to rebase your patch. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
On Mon, Jul 14, 2014 at 2:39 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 14 July 2014 02:36 PM, Sachin Kamat wrote: On Mon, Jul 14, 2014 at 2:32 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 14 July 2014 02:29 PM, Sachin Kamat wrote: Hi, On Mon, Jul 14, 2014 at 2:26 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Wednesday 09 July 2014 05:19 PM, Sachin Kamat wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. There is a new Exynos PHY in town, Exynos 3250. Can you rebase your patch on top of that? Sure. But I did not see it in linux-next yet. Is it merged somewhere? It's in the list. I can push it to my tree if that helps. That would be great to avoid any other conflicts. pushed to git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next. You can use it to rebase your patch. Thanks. I will re-spin on top of it. -- Regards, Sachin. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal between
+ * MCU and FB to display video images. And the display controller
+ * should trigger to transfer video image at this signal. So the panel
+ * receives the TE IRQ, then calls this function to notify it to the
+ * display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
I've objected to this particular change before and that objection still
stands. I don't see how this is related to DSI. It seems like an
implementation detail of this particular setup and I think it should be
handled differently (within the Exynos DSI controller implementation
possibly).
Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so it
could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly
without mipi_dis_host_ops?
I've gone through the DSI specification again and the only mention of
the tearing effect is in section 8.12 TE Signaling in DSI. That says
the following:
A Command Mode display module has its own timing controller and
local frame buffer for display refresh. In some cases the host
processor needs to be notified of timing events on the display
module, e.g. the start of vertical blanking or similar timing
information. In a traditional parallel-bus interface like DBI-2,
a dedicated signal wire labeled TE (Tearing Effect) is provided
to convey such timing information to the host processor. In a
DSI system, the same information, with reasonably low latency,
shall be transmitted from the display module to the host
processor when requested, using the bidirectional Data Lane.
My interpretation of that is that a DSI peripheral doesn't have a
dedicated TE signal. Now the panel that you want to support here seems
to have one, so I'm wondering if maybe it isn't a DSI panel at all but
rather DBI.
Uhm, this panel is DSI panel right. It provides TE external pad to
transfer TE pulse to host AP and it also provides TE relevant 3 DCS, so
host AP could choose either of them.
But I think it's better to use IRQ instead of polling method.
As Inki commented before, I'll try to use remote-endpoint property of
DSI device node in exynos DSIM driver and call FIMD notifier.
Thank you.
Best regards YJ
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
On Mon, Jul 14, 2014 at 06:22:39PM +0900, YoungJun Cho wrote:
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received
bytes,
*or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ *The panel generates tearing effect synchronization signal
between
+ *MCU and FB to display video images. And the display
controller
+ *should trigger to transfer video image at this signal. So
the panel
+ *receives the TE IRQ, then calls this function to notify it
to the
+ *display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
I've objected to this particular change before and that objection still
stands. I don't see how this is related to DSI. It seems like an
implementation detail of this particular setup and I think it should be
handled differently (within the Exynos DSI controller implementation
possibly).
Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so it
could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly
without mipi_dis_host_ops?
I've gone through the DSI specification again and the only mention of
the tearing effect is in section 8.12 TE Signaling in DSI. That says
the following:
A Command Mode display module has its own timing controller and
local frame buffer for display refresh. In some cases the host
processor needs to be notified of timing events on the display
module, e.g. the start of vertical blanking or similar timing
information. In a traditional parallel-bus interface like DBI-2,
a dedicated signal wire labeled TE (Tearing Effect) is provided
to convey such timing information to the host processor. In a
DSI system, the same information, with reasonably low latency,
shall be transmitted from the display module to the host
processor when requested, using the bidirectional Data Lane.
My interpretation of that is that a DSI peripheral doesn't have a
dedicated TE signal. Now the panel that you want to support here seems
to have one, so I'm wondering if maybe it isn't a DSI panel at all but
rather DBI.
Uhm, this panel is DSI panel right. It provides TE external pad to transfer
TE pulse to host AP and it also provides TE relevant 3 DCS, so host AP could
choose either of them.
But I think it's better to use IRQ instead of polling method.
According to the
Re: [PATCH v2 4/6] ARM: SAMSUNG: Restore Samsung PM Debug functionality
Hi Kukjin, On 25.06.2014 13:43, Tomasz Figa wrote: Due to recently merged patches and previous merge conflicts, the Samsung PM Debug functionality no longer can be enabled. This patch fixes incorrect dependency of SAMSUNG_PM_DEBUG on an integer symbol and adds missing header inclusion. Signed-off-by: Tomasz Figa t.f...@samsung.com --- arch/arm/plat-samsung/Kconfig| 5 +++-- arch/arm/plat-samsung/pm-debug.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 301b892..ad9515f 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -413,8 +413,9 @@ config S5P_DEV_MFC comment Power management config SAMSUNG_PM_DEBUG - bool S3C2410 PM Suspend debug - depends on PM DEBUG_KERNEL DEBUG_S3C_UART + bool Samsung PM Suspend debug + depends on PM DEBUG_KERNEL + depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART help Say Y here if you want verbose debugging from the PM Suspend and Resume code. See file:Documentation/arm/Samsung-S3C24XX/Suspend.txt diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c index 8f19f66..3960960 100644 --- a/arch/arm/plat-samsung/pm-debug.c +++ b/arch/arm/plat-samsung/pm-debug.c @@ -14,6 +14,7 @@ */ #include linux/serial_core.h +#include linux/serial_s3c.h #include linux/io.h #include asm/mach/map.h Please consider this patch for next fixes pull request. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/6] ARM: EXYNOS: Fix core ID used by platsmp and hotplug code
Hi Kukjin, On 08.07.2014 15:21, Kukjin Kim wrote: Tomasz Figa wrote: When CPU topology is specified in device tree, cpu_logical_map() does not return core ID anymore, but rather full MPIDR value. This breaks existing calculation of PMU register offsets on Exynos SoCs. This patch fixes the problem by adjusting the code to use only core ID bits of the value returned by cpu_logical_map() to allow CPU topology to be specified in device tree on Exynos SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Looks good to me, but I think we don't need this fix in 3.16 because the CPU topology is not specified in DT yet...if I'm wrong, please correct me. CPU topology is already specified in DT for Exynos3250, 5250, 5260, 5410 and 5420/5800. This patch also fixes CPU hotplug on SoCs with more than 2 cores, because it removes incorrect condition check in platform_do_lowpower(). Please take this fix for next -rc release. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/6] ARM: EXYNOS: Fix suspend/resume sequences
Hi Kukjin,
On 25.06.2014 13:52, Tomasz Figa wrote:
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based boards.
This patch fixes the issue by removing exynos_pm_syscore_ops completely
and making the code rely only on CPU PM notifier.
Tested on Exynos4210-based Trats board.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/pm.c | 23 ---
1 file changed, 4 insertions(+), 19 deletions(-)
Changes since v1:
- rebased onto Kukjin's fixes branch.
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 202ca73..f23cc77 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -364,11 +364,6 @@ early_wakeup:
return;
}
-static struct syscore_ops exynos_pm_syscore_ops = {
- .suspend= exynos_pm_suspend,
- .resume = exynos_pm_resume,
-};
-
/*
* Suspend Ops
*/
@@ -438,22 +433,13 @@ static int exynos_cpu_pm_notifier(struct notifier_block
*self,
switch (cmd) {
case CPU_PM_ENTER:
- if (cpu == 0) {
- exynos_pm_central_suspend();
- if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
- exynos_cpu_save_register();
- }
+ if (cpu == 0)
+ exynos_pm_suspend();
break;
case CPU_PM_EXIT:
- if (cpu == 0) {
- if (read_cpuid_part_number() ==
- ARM_CPU_PART_CORTEX_A9) {
- scu_enable(S5P_VA_SCU);
- exynos_cpu_restore_register();
- }
- exynos_pm_central_resume();
- }
+ if (cpu == 0)
+ exynos_pm_resume();
break;
}
@@ -478,6 +464,5 @@ void __init exynos_pm_init(void)
tmp |= ((0xFF 8) | (0x1F 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
- register_syscore_ops(exynos_pm_syscore_ops);
suspend_set_ops(exynos_suspend_ops);
}
Please consider this patch for next fixes pull request. Without it
suspend/resume is broken for Exynos4 and probably other SoCs. This patch
just restores the sequence from before the patch moving things to PM
notifier, so I don't think it should need any special treatment.
Best regards,
Tomasz
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[PATCH 2/2] phy: Kconfig: Update config for Exynos USB DRD
USB DWC3 driver on Exynos platform does not work without its corresponding phy driver. Hence make the PHY driver depend on Exynos DWC3 driver and default it to yes to make things easier for the end user. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com Reviewed-by: Jingoo Han jg1@samsung.com --- drivers/phy/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c412ca4..c730e85 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -161,8 +161,10 @@ config PHY_EXYNOS5_USBDRD tristate Exynos5 SoC series USB DRD PHY driver depends on ARCH_EXYNOS5 OF depends on HAS_IOMEM + depends on USB_DWC3_EXYNOS select GENERIC_PHY select MFD_SYSCON + default y help Enable USB DRD PHY support for Exynos 5 SoC series. This driver provides PHY interface for USB 3.0 DRD controller -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
Hi Thierry,
On 07/14/2014 06:41 PM, Thierry Reding wrote:
On Mon, Jul 14, 2014 at 06:22:39PM +0900, YoungJun Cho wrote:
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal between
+ * MCU and FB to display video images. And the display controller
+ * should trigger to transfer video image at this signal. So the panel
+ * receives the TE IRQ, then calls this function to notify it to the
+ * display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
I've objected to this particular change before and that objection still
stands. I don't see how this is related to DSI. It seems like an
implementation detail of this particular setup and I think it should be
handled differently (within the Exynos DSI controller implementation
possibly).
Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so it
could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly
without mipi_dis_host_ops?
I've gone through the DSI specification again and the only mention of
the tearing effect is in section 8.12 TE Signaling in DSI. That says
the following:
A Command Mode display module has its own timing controller and
local frame buffer for display refresh. In some cases the host
processor needs to be notified of timing events on the display
module, e.g. the start of vertical blanking or similar timing
information. In a traditional parallel-bus interface like DBI-2,
a dedicated signal wire labeled TE (Tearing Effect) is provided
to convey such timing information to the host processor. In a
DSI system, the same information, with reasonably low latency,
shall be transmitted from the display module to the host
processor when requested, using the bidirectional Data Lane.
My interpretation of that is that a DSI peripheral doesn't have a
dedicated TE signal. Now the panel that you want to support here seems
to have one, so I'm wondering if maybe it isn't a DSI panel at all but
rather DBI.
Uhm, this panel is DSI panel right. It provides TE external pad to transfer
TE pulse to host AP and it also provides TE relevant 3 DCS, so host AP could
choose either of them.
But I think it's better to use IRQ instead of polling method.
According to the specification you don't
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote: On 07/14/2014 06:41 PM, Thierry Reding wrote: [...] That said, I've been doing some research and it seems like we have a somewhat similar feature on Tegra. What happens there is that there are three GPIO pins that can be repurposed for TE signalling. But as opposed to using them as interrupts the display controller can be configured to use them, upon which it will automatically handle the TE signal by sending the next frame. Could you explain more detail how the Tegra display controller could be configured with this GPIO pins? I have no idea except that the display controller registers this GPIO as an IRQ. On Tegra the display controller has a special register that can be programmed to use one of the three GPIOs as TE signal. Then the display controller can be configured in one-shot (non-continuous) mode, which means that software needs to explicitly set a trigger bit to tell the display controller to send a new frame. If TE signalling is enabled, then the display controller will not immediately send a new frame when triggered but wait for signalling of this GPIO. So we have at least two very different implementations of this on two different SoCs. Further the specification explicitly recommends using the BTA sequence and DSI protocol to wait for TE. So I still think that controllers that provide an additional, non-spec compliant method to signal TE should handle it separately rather than within DSI. Otherwise we essentially need to make the DSI core aware of all these quirks, and I'd rather avoid that. You mean, the DSI specification guides to use BTA, so it's better to use display controller rather than DSIM, right? What I'm saying is that there's nothing about a side-band TE wire in the DSI spec. In fact the spec explicitly says that this mechanism of an external TE wire from older protocols (DBI) was replaced by the BTA sequence over the protocol. Now, my understanding is that using the BTA sequence over the DSI protocol would introduce some latency and that forces some panel vendors to still provide a side-band TE wire even in DSI compliant panels. But since this is not part of the specification there is no standard way to do this (as evidenced by Tegra and Exynos). Therefore putting such functionality into the core DSI code is bad. But that doesn't mean that you have to put this functionality into the display controller driver on Exynos. What I'm saying is that it should be handled by the SoC driver rather than the core. Where exactly probably depends on the particular case. As Inki commented before, I'll try to use remote-endpoint property of DSI device node in exynos DSIM driver and call FIMD notifier. Sounds like it matches what I said above. I'm not a huge fan of notifiers, but if it works for you I suppose that's fine. The alternative would be to directly call a FIMD function, which is somewhat more explicit than a notifier. Yes, I also like explicit call, so I want to use dsi_host_ops and calls it in panel. But there is an objection to use dis_host_ops, we think notifier in exynos dsim for fimd(display controller). There are other ways to explicitly call into the display controller. You could for example get access to the CRTC that DSIM is currently connected to (via exynos_dsi.encoder-crtc) and then cast that to a struct exynos_drm_crtc and call a function to trigger a new frame to be sent (for example exynos_drm_crtc_send_frame()). This assumes that you can safely cast struct drm_crtc * to struct exynos_drm_crtc *, but that shouldn't be a problem. With the above, you could make the DSIM handle the TE signal interrupts and trigger the DC using the new exynos_drm_crtc_send_frame() function. Thierry pgpEml_1sKByX.pgp Description: PGP signature
Re: [PATCH 2/2] phy: Kconfig: Update config for Exynos USB DRD
On Mon, Jul 14, 2014 at 3:38 PM, Sachin Kamat sachin.ka...@samsung.com wrote: USB DWC3 driver on Exynos platform does not work without its corresponding phy driver. Hence make the PHY driver depend on Exynos DWC3 driver and default it to yes to make things easier for the end user. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com Reviewed-by: Jingoo Han jg1@samsung.com --- drivers/phy/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c412ca4..c730e85 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -161,8 +161,10 @@ config PHY_EXYNOS5_USBDRD tristate Exynos5 SoC series USB DRD PHY driver depends on ARCH_EXYNOS5 OF depends on HAS_IOMEM + depends on USB_DWC3_EXYNOS select GENERIC_PHY select MFD_SYSCON + default y help Enable USB DRD PHY support for Exynos 5 SoC series. This driver provides PHY interface for USB 3.0 DRD controller -- 1.7.9.5 Tested on Exynos5800 and Exynos5250, with exynos_defconfig patch : http://www.spinics.net/lists/linux-samsung-soc/msg33994.html Tested-by: Vivek Gautam gautam.vi...@samsung.com -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] cpuidle: big.LITTLE: add MCPM dependency
662322fcb6d (cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config) made it possible for the big-little cpuidle driver to run on exynos, which may or may not include MCPM support at compile time, so we run into a link error when it is disabled: drivers/built-in.o: In function `bl_enter_powerdown': :(.text+0x1889a0): undefined reference to `mcpm_cpu_powered_up' drivers/built-in.o: In function `bl_powerdown_finisher': :(.text+0x1889e8): undefined reference to `mcpm_set_entry_vector' :(.text+0x1889ec): undefined reference to `mcpm_cpu_suspend' This adds an explicit dependency to CONFIG_MCPM to avoid that case. Signed-off-by: Arnd Bergmann a...@arndb.de Cc: Chander Kashyap chander.kash...@linaro.org Cc: Tomasz Figa t.f...@samsung.com Cc: Daniel Lezcano daniel.lezc...@linaro.org --- I believe the broken commit is only present in the samsung/for-next tree (through v3.17-next/cpuidle-exynos), so it should be fixed there. On a side note, I wonder if we should have platform dependencies at all, or just the MCPM dependency by itself. diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 2f6b33ea6e08..459b7c91407a 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -10,6 +10,7 @@ config ARM_ARMADA_370_XP_CPUIDLE config ARM_BIG_LITTLE_CPUIDLE bool Support for ARM big.LITTLE processors depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS + depends on MCPM select ARM_CPU_SUSPEND select CPU_IDLE_MULTIPLE_DRIVERS help -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: EXYNOS: Fix MCPM build with SUSPEND=n
Building of EXYNOS5420_MCPM with disabled SUSPEND fails: arch/arm/mach-exynos/built-in.o: In function `exynos_mcpm_init': arch/arm/mach-exynos/mcpm-exynos.c:361: undefined reference to `mcpm_loopback' The exynos_mcpm_init() in mcp-exynos.c calls mcpm_loopback() which depends on cpu_suspend function (ARM_CPU_SUSPEND). Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Cc: sta...@vger.kernel.org Fixes: a6a4d3152e3cbb6 (ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster using the MCPM loopback) --- arch/arm/mach-exynos/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8f9b66c4ac78..5d4ff6571dcd 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -119,6 +119,7 @@ config EXYNOS5420_MCPM bool Exynos5420 Multi-Cluster PM support depends on MCPM SOC_EXYNOS5420 select ARM_CCI + select ARM_CPU_SUSPEND help This is needed to provide CPU and cluster power management on Exynos5420 implementing big.LITTLE. -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
On Mon, Jul 14, 2014 at 3:38 PM, Sachin Kamat sachin.ka...@samsung.com wrote: Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com Reviewed-by: Jingoo Han jg1@samsung.com --- Changes since v3: * Rebased the series on top of latest PHY tree [1]. [1] git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git --- drivers/phy/Kconfig | 35 +++ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5fceb33..c412ca4 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -132,43 +132,30 @@ config PHY_SUN4I_USB config PHY_SAMSUNG_USB2 tristate Samsung USB 2.0 PHY driver depends on HAS_IOMEM + depends on USB_EHCI_EXYNOS || USB_OHCI_EXYNOS || USB_DWC2 select GENERIC_PHY select MFD_SYSCON + default ARCH_EXYNOS help Enable this to support the Samsung USB 2.0 PHY driver for Samsung - SoCs. This driver provides the interface for USB 2.0 PHY. Support for - particular SoCs has to be enabled in addition to this driver. Number - and type of supported phys depends on the SoC. + SoCs. This driver provides the interface for USB 2.0 PHY. Support + for particular PHYs will be enabled based on the SoC type in addition + to this driver. config PHY_EXYNOS4210_USB2 - bool Support for Exynos 4210 + bool depends on PHY_SAMSUNG_USB2 - depends on CPU_EXYNOS4210 - help - Enable USB PHY support for Exynos 4210. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 4210 four - phys are available - device, host, HSIC0 and HSIC1. + default CPU_EXYNOS4210 config PHY_EXYNOS4X12_USB2 - bool Support for Exynos 3250/4x12 + bool depends on PHY_SAMSUNG_USB2 - depends on (SOC_EXYNOS3250 || SOC_EXYNOS4212 || SOC_EXYNOS4412) - help - Enable USB PHY support for Exynos 3250/4x12. This option requires - that Samsung USB 2.0 PHY driver is enabled and means that support for - this particular SoC is compiled in the driver. In case of Exynos 4x12 - four phys are available - device, host, HSIC0 and HSIC1. + default SOC_EXYNOS3250 || SOC_EXYNOS4212 || SOC_EXYNOS4412 config PHY_EXYNOS5250_USB2 - bool Support for Exynos 5250 + bool depends on PHY_SAMSUNG_USB2 - depends on SOC_EXYNOS5250 - help - Enable USB PHY support for Exynos 5250. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 5250 four - phys are available - device, host, HSIC0 and HSIC. + default SOC_EXYNOS5250 || SOC_EXYNOS5420 config PHY_EXYNOS5_USBDRD tristate Exynos5 SoC series USB DRD PHY driver -- 1.7.9.5 Tested on Exynos5800 and Exynos5250, with exynos_defconfig patch : http://www.spinics.net/lists/linux-samsung-soc/msg33994.html Tested-by: Vivek Gautam gautam.vi...@samsung.com -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 1/2] ASoC: samsung: Add machine driver for Odroid X2/U3
On 30/06/14 20:46, Mark Brown wrote:
On Wed, Jun 18, 2014 at 06:22:30PM +0200, Sylwester Nawrocki wrote:
+struct odroidx2_drv_data odroidx2_drvdata = {
+.dapm_widgets = odroidx2_dapm_widgets,
+.num_dapm_widgets = ARRAY_SIZE(odroidx2_dapm_widgets),
+};
+
+struct odroidx2_drv_data odroidu3_drvdata = {
+.dapm_widgets = odroidu3_dapm_widgets,
+.num_dapm_widgets = ARRAY_SIZE(odroidu3_dapm_widgets),
+};
+ret = snd_soc_of_parse_audio_routing(card, samsung,audio-routing);
+if (ret 0)
+return ret;
Given that the widgets don't have any actions defined and the routing is
all done by DT it might be easier and more flexible to just define all
the widgets all the time and let them hang there if they're not in use,
that way you don't need multiple compatible strings. If you do that
you're then very close to being able to use simple-card...
Too bad, I noticed this comment only just now. I'll consider this and
will try again and see how simple-card could be used. There is also the
samsung-i2s-sec secondary 'overlay' CPU DAI that would need to be handled,
and we have it now internally specified in the machine driver through
cpu_dai_name, rather than cpu_of_node.
There might be some more work in the driver needed to support the
secondary I2S interface generically with DT.
--
Regards,
Sylwester
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Re: [PATCH V2 1/2] ASoC: samsung: Add machine driver for Odroid X2/U3
On Mon, Jul 14, 2014 at 01:27:53PM +0200, Sylwester Nawrocki wrote: Too bad, I noticed this comment only just now. I'll consider this and will try again and see how simple-card could be used. There is also the samsung-i2s-sec secondary 'overlay' CPU DAI that would need to be handled, and we have it now internally specified in the machine driver through cpu_dai_name, rather than cpu_of_node. There might be some more work in the driver needed to support the secondary I2S interface generically with DT. You should be converting the device to DPCM for both that and the compressed audio path. signature.asc Description: Digital signature
Re: [PATCH] ARM: EXYNOS: Fix MCPM build with SUSPEND=n
On Mon, 14 Jul 2014, Krzysztof Kozlowski wrote: Building of EXYNOS5420_MCPM with disabled SUSPEND fails: arch/arm/mach-exynos/built-in.o: In function `exynos_mcpm_init': arch/arm/mach-exynos/mcpm-exynos.c:361: undefined reference to `mcpm_loopback' The exynos_mcpm_init() in mcp-exynos.c calls mcpm_loopback() which depends on cpu_suspend function (ARM_CPU_SUSPEND). Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Cc: sta...@vger.kernel.org No need to CC stable here as this code has not reached a released kernel yet. Fixes: a6a4d3152e3cbb6 (ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster using the MCPM loopback) And this is not clear yet if this commit ID is stable. Other than that: Acked-by: Nicolas Pitre n...@linaro.org Please send to RMK's patch system. --- arch/arm/mach-exynos/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8f9b66c4ac78..5d4ff6571dcd 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -119,6 +119,7 @@ config EXYNOS5420_MCPM bool Exynos5420 Multi-Cluster PM support depends on MCPM SOC_EXYNOS5420 select ARM_CCI + select ARM_CPU_SUSPEND help This is needed to provide CPU and cluster power management on Exynos5420 implementing big.LITTLE. -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 00/13] Add Maxim 77802 PMIC support
This series are based on drivers added by Simon Glass to the Chrome OS kernel and adds support for the Maxim 77802 Power Management IC, their regulators, clocks, RTC and i2c interface. This is a v8 of the patch-set that addresses issues pointed out in v7. Individual changes are added on each patch but the biggest changes are: * Patches 1-7 from v7 are not included since those were improvements to the max77686 mfd driver and can be applied independently. Lee Jones said that he is going to pick them from the posted v7 series. I've created a patchwork bundle with 1-7 from v7 to make it easy to apply: https://patchwork.kernel.org/bundle/javier/max77686-improvements/ * The Dynamic Voltage Scaling support has been removed since that can be added in a follow up series and shouldn't block the minimum PMIC support. The patch-set has been tested on both Daisy/Snow (max77686) and Peach Pit (max77802) Chromebooks and it's composed of the following patches: [PATCH v8 01/13] mfd: max77686: Add Maxim 77802 PMIC support [PATCH v8 02/13] mfd: max77802: Add DT binding documentation [PATCH v8 03/13] regulator: Add driver for Maxim 77802 PMIC regulators [PATCH v8 04/13] clk: max77686: Add DT include for MAX77686 PMIC clock [PATCH v8 05/13] clk: Add generic driver for Maxim PMIC clocks [PATCH v8 06/13] clk: max77686: Convert to the generic max clock driver [PATCH v8 07/13] clk: max77686: Improve Maxim 77686 PMIC clocks binding [PATCH v8 08/13] clk: Add driver for Maxim 77802 PMIC clocks [PATCH v8 09/13] clk: max77802: Add DT binding documentation [PATCH v8 10/13] rtc: max77686: Allow the max77686 rtc to wakeup the system [PATCH v8 11/13] rtc: max77686: Remove dead code for SMPL and WTSR [PATCH v8 12/13] rtc: Add driver for Maxim 77802 PMIC Real-Time-Clock [PATCH v8 13/13] ARM: dts: Add max77802 to exynos5420-peach-pit and exynos5800-peach-pi Patch 01/13 extend the max77686 mfd driver to also support the max77802 PMIC and patch 02/13 adds the DT binding documentation for this PMIC. Patch 03/13 adds support for the regulators found in the PMIC. Patch 04/13 to 07/13 are improvements and refactoring to the max77686 clock driver to avoid code duplication when adding max77802 clocks support in patch 08/13. Patch 09/13 adds the DT binding document for the max77802 clock driver. Patches 10/13 and 11/13 are improvements to max77686 RTC driver and patch 12/13 adds support for the RTC found in the max77802 PMIC. Finally patch 13/13 adds the required device node to the Peach Pit and Pi exynos5 based boards. Since there are cross-subsystems dependencies, I think that the best way to sort this out is if relevant maintainers ack the patches so 01/13 to 012/13 can be merged through the mfd tree. The patches and the relevant acks are: Patch 03/13 (regulator - Mark Brown) Patches 04/13 to 09/13 (clk - Mike Turquette) Patches 10/13 to 12/13 (rtc - Alessandro Zummo) Patch 13/13 is only a DTS change so it can be picked by Kukjin Kim once the other patches are picked by Lee Jones. Since we are in 3.16-rc5 already, it would be great if I can get your acks or feedback since I was hoping this series to make it to 3.17. This is due other series that were already posted depend on this one. Also, the series have been reviewed and tested by Samsung folks and most of the patches already collected Reviewed-by and Tested-by tags. Thanks a lot and best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 01/13] mfd: max77686: Add Maxim 77802 PMIC support
Maxim MAX77802 is a power management chip that contains 10 high
efficiency Buck regulators, 32 Low-dropout (LDO) regulators used
to power up application processors and peripherals, a 2-channel
32kHz clock outputs, a Real-Time-Clock (RTC) and a I2C interface
to program the individual regulators, clocks outputs and the RTC.
This patch adds support for MAX77802 to the MAX77686 driver and is
based on a driver added to the Chrome OS kernel 3.8 by Simon Glass.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes since v7:
- Don't add an entry in the i2c_device_id table. Suggested by Lee Jones.
- Use of_device_id match table instead of i2c_device_id to know the PMIC type.
Changes since v6:
- Fix comments grammar. Suggested by Krzysztof Kozlowski.
- Only unregister the RTC i2c device if the type is MAX77686.
Suggested by Krzysztof Kozlowski.
Changes since v5:
- Extend the 77686 driver to support 77802 instead of adding a new driver.
Suggested by Lee Jones.
Changes since v4:
- Use consistent expressions when checking for NULL values.
Suggested by Krzysztof Kozlowski.
- Remove unused defines. Suggested by Krzysztof Kozlowski.
- Explain why IRQ is disabled on suspend. Suggested by Krzysztof Kozlowski.
Changes since v3:
- Remove unnecessary OOM error message since the mm subsystem already logs it.
Changes since v2:
- Split the DT binding docs in a separate patch and improve the documentation.
Suggested by Mark Brown.
- Add all the devices in the MFD driver instead of doing in separate patches.
Suggested by Mark Brown.
Changes since v1:
- Convert max77{686,802} to regmap irq API and get rid of max77{686,802}-irq.c
Suggested by Krzysztof Kozlowski.
- Don't protect max77802 mfd_cells using Kconfig options since mfd core omits
devices that don't match. Suggested by Lee Jones.
- Change mfd driver to be tristate instead of boolean. Suggested by Mark Brown.
- Change binding voltage-regulators property to regulators to be consistent
with other PMIC drivers. Suggested by Mark Brown.
- Use regulators node names instead of the deprecated regulator-compatible
property. Suggested by Mark Brown.
- Use the new descriptor-based GPIO interface instead of the deprecated
---
drivers/mfd/Kconfig | 6 +-
drivers/mfd/max77686.c | 201 -
include/linux/mfd/max77686-private.h | 208 ++-
include/linux/mfd/max77686.h | 57 +-
4 files changed, 438 insertions(+), 34 deletions(-)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 3010204..de5abf2 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -380,15 +380,15 @@ config MFD_MAX14577
of the device.
config MFD_MAX77686
- bool Maxim Semiconductor MAX77686 PMIC Support
+ bool Maxim Semiconductor MAX77686/802 PMIC Support
depends on I2C=y
select MFD_CORE
select REGMAP_I2C
select REGMAP_IRQ
select IRQ_DOMAIN
help
- Say yes here to add support for Maxim Semiconductor MAX77686.
- This is a Power Management IC with RTC on chip.
+ Say yes here to add support for Maxim Semiconductor MAX77686 and
+ MAX77802 which are Power Management IC with an RTC on chip.
This driver provides common support for accessing the device;
additional drivers must be enabled in order to use the functionality
of the device.
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 8650832..b26335e 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -1,5 +1,5 @@
/*
- * max77686.c - mfd core driver for the Maxim 77686
+ * max77686.c - mfd core driver for the Maxim 77686/802
*
* Copyright (C) 2012 Samsung Electronics
* Chiwoong Byun woong.b...@smasung.com
@@ -43,6 +43,74 @@ static const struct mfd_cell max77686_devs[] = {
{ .name = max77686-clk, },
};
+static const struct mfd_cell max77802_devs[] = {
+ { .name = max77802-pmic, },
+ { .name = max77802-clk, },
+ { .name = max77802-rtc, },
+};
+
+static bool max77802_pmic_is_accessible_reg(struct device *dev,
+ unsigned int reg)
+{
+ return (reg = MAX77802_REG_DEVICE_ID reg MAX77802_REG_PMIC_END);
+}
+
+static bool max77802_rtc_is_accessible_reg(struct device *dev,
+ unsigned int reg)
+{
+ return (reg = MAX77802_RTC_INT reg MAX77802_RTC_END);
+}
+
+static bool max77802_is_accessible_reg(struct device *dev, unsigned int reg)
+{
+ return (max77802_pmic_is_accessible_reg(dev, reg) ||
+ max77802_rtc_is_accessible_reg(dev, reg));
+}
+
+static bool max77802_pmic_is_precious_reg(struct device *dev, unsigned int reg)
+{
+ return (reg == MAX77802_REG_INTSRC || reg ==
[PATCH v8 02/13] mfd: max77802: Add DT binding documentation
Add Device Tree binding documentation for Maxim 77802 PMIC.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v7:
- Remove information about DVS since that will be added as a follow up.
Changes since v6: None
Changes since v5:
- Use max77686,* properties instead of max77802,* since the support is
now in the max77686 driver and that IP defined the properties first.
- Fix issues in DT binding documentation. Suggested by Andreas Farber.
Changes since v4: None
Changes since v3: None
Changes since v2:
- Explain better the Dynamic Voltage Scaling (DVS) support in some Buck
regulators and the max77802,pmic-buck-{dvs,selb}-gpios properties.
Suggested by Mark Brown.
---
Documentation/devicetree/bindings/mfd/max77802.txt | 59 ++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/max77802.txt
diff --git a/Documentation/devicetree/bindings/mfd/max77802.txt
b/Documentation/devicetree/bindings/mfd/max77802.txt
new file mode 100644
index 000..9f72b8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77802.txt
@@ -0,0 +1,59 @@
+Maxim MAX77802 multi-function device
+
+MAX77802 is a Multifunction device with PMIC, RTC and Charger on chip. It is
+interfaced to host controller using i2c interface. PMIC, Charger and RTC
+submodules are addressed using same i2c slave address.
+
+This document describes the binding for mfd device and PMIC submodule.
+
+Binding for the built-in 32k clock generator block is defined separately
+in bindings/clk/maxim,max77802.txt file.
+
+Required properties:
+- compatible : Must be maxim,max77802;
+- reg : Specifies the i2c slave address of PMIC block.
+- interrupts : This i2c device has an IRQ line connected to the main SoC.
+- interrupt-parent : The parent interrupt controller.
+
+Optional node:
+- regulators : The regulators of max77802 have to be instantiated
+ under subnode named regulators using the following format.
+
+ regulator-name {
+ standard regulator constraints
+ };
+ refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+ The regulator node name should be initialized with a string
+to get matched with their hardware counterparts as follow. The valid names are:
+
+ -LDOn : for LDOs, where n can lie in range 1 to 35.
+ example: LDO1, LDO2, LDO35.
+ -BUCKn : for BUCKs, where n can lie in range 1 to 10.
+ example: BUCK1, BUCK5, BUCK10.
+Example:
+
+ max77802@09 {
+ compatible = maxim,max77802;
+ interrupt-parent = wakeup_eint;
+ interrupts = 26 0;
+ reg = 0x09;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ regulators {
+ ldo11_reg: LDO11 {
+ regulator-name = vdd_ldo11;
+ regulator-min-microvolt = 190;
+ regulator-max-microvolt = 190;
+ regulator-always-on;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = vdd_mif;
+ regulator-min-microvolt = 95;
+ regulator-max-microvolt = 130;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
--
2.0.0.rc2
--
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[PATCH v8 06/13] clk: max77686: Convert to the generic max clock driver
Clocks drivers for Maxim PMIC are very similar so they can
be converted to use the generic Maxim clock driver.
Also, while being there use module_platform_driver() helper
macro to eliminate more boilerplate code.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/clk/Kconfig| 1 +
drivers/clk/clk-max77686.c | 176 +++--
2 files changed, 9 insertions(+), 168 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 73f78e8..3fd4270 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -38,6 +38,7 @@ config COMMON_CLK_MAX_GEN
config COMMON_CLK_MAX77686
tristate Clock driver for Maxim 77686 MFD
depends on MFD_MAX77686
+ select COMMON_CLK_MAX_GEN
---help---
This driver supports Maxim 77686 crystal oscillator clock.
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index 185b611..ed0beb4 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -31,187 +31,37 @@
#include linux/clkdev.h
#include dt-bindings/clock/maxim,max77686.h
-
-struct max77686_clk {
- struct max77686_dev *iodev;
- u32 mask;
- struct clk_hw hw;
- struct clk_lookup *lookup;
-};
-
-static struct max77686_clk *to_max77686_clk(struct clk_hw *hw)
-{
- return container_of(hw, struct max77686_clk, hw);
-}
-
-static int max77686_clk_prepare(struct clk_hw *hw)
-{
- struct max77686_clk *max77686 = to_max77686_clk(hw);
-
- return regmap_update_bits(max77686-iodev-regmap,
- MAX77686_REG_32KHZ, max77686-mask,
- max77686-mask);
-}
-
-static void max77686_clk_unprepare(struct clk_hw *hw)
-{
- struct max77686_clk *max77686 = to_max77686_clk(hw);
-
- regmap_update_bits(max77686-iodev-regmap,
- MAX77686_REG_32KHZ, max77686-mask, ~max77686-mask);
-}
-
-static int max77686_clk_is_prepared(struct clk_hw *hw)
-{
- struct max77686_clk *max77686 = to_max77686_clk(hw);
- int ret;
- u32 val;
-
- ret = regmap_read(max77686-iodev-regmap,
- MAX77686_REG_32KHZ, val);
-
- if (ret 0)
- return -EINVAL;
-
- return val max77686-mask;
-}
-
-static unsigned long max77686_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return 32768;
-}
-
-static struct clk_ops max77686_clk_ops = {
- .prepare= max77686_clk_prepare,
- .unprepare = max77686_clk_unprepare,
- .is_prepared= max77686_clk_is_prepared,
- .recalc_rate= max77686_recalc_rate,
-};
+#include clk-max-gen.h
static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
[MAX77686_CLK_AP] = {
.name = 32khz_ap,
- .ops = max77686_clk_ops,
+ .ops = max_gen_clk_ops,
.flags = CLK_IS_ROOT,
},
[MAX77686_CLK_CP] = {
.name = 32khz_cp,
- .ops = max77686_clk_ops,
+ .ops = max_gen_clk_ops,
.flags = CLK_IS_ROOT,
},
[MAX77686_CLK_PMIC] = {
.name = 32khz_pmic,
- .ops = max77686_clk_ops,
+ .ops = max_gen_clk_ops,
.flags = CLK_IS_ROOT,
},
};
-static struct clk *max77686_clk_register(struct device *dev,
- struct max77686_clk *max77686)
-{
- struct clk *clk;
- struct clk_hw *hw = max77686-hw;
-
- clk = clk_register(dev, hw);
- if (IS_ERR(clk))
- return clk;
-
- max77686-lookup = kzalloc(sizeof(struct clk_lookup), GFP_KERNEL);
- if (!max77686-lookup)
- return ERR_PTR(-ENOMEM);
-
- max77686-lookup-con_id = hw-init-name;
- max77686-lookup-clk = clk;
-
- clkdev_add(max77686-lookup);
-
- return clk;
-}
-
static int max77686_clk_probe(struct platform_device *pdev)
{
struct max77686_dev *iodev = dev_get_drvdata(pdev-dev.parent);
- struct max77686_clk *max77686_clks[MAX77686_CLKS_NUM];
- struct clk **clocks;
- int i, ret;
-
- clocks = devm_kzalloc(pdev-dev, sizeof(struct clk *)
- * MAX77686_CLKS_NUM, GFP_KERNEL);
- if (!clocks)
- return -ENOMEM;
-
- for (i = 0; i MAX77686_CLKS_NUM; i++) {
- max77686_clks[i] = devm_kzalloc(pdev-dev,
- sizeof(struct max77686_clk),
GFP_KERNEL);
- if (!max77686_clks[i])
- return -ENOMEM;
- }
-
- for (i = 0; i MAX77686_CLKS_NUM; i++) {
- max77686_clks[i]-iodev = iodev;
- max77686_clks[i]-mask = 1 i;
- max77686_clks[i]-hw.init = max77686_clks_init[i];
-
-
[PATCH v8 13/13] ARM: dts: Add max77802 to exynos5420-peach-pit and exynos5800-peach-pi
Peach pit and pi boards uses a Maxim 77802 power management
IC to drive regulators and its Real Time Clock. This patch
adds support for this chip.
These are the device nodes and pinctrl configuration that
are present on the Peach pit DeviceTree source file in the
the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v7:
- Change Buck2 and 3 regulator name to vdd_arm and vdd_int.
Suggested by Naveen Krishna Chatradhi.
- Remove DVS properties since this is going to be added as a follow up.
Changes since v6: None
Changes since v5:
- Fix style issues and a typo on peach pit and pi DTS.
Suggested by Tushar Behera.
Changes since v4: None
Changes since v3:
- Add support for Exynos5800 based Peach pi board. Suggested by Doug Anderson.
- Model the actual regulators relationship instead of a simplistic model.
Suggested by Mark Brown.
Changes since v2: None
Changes since v1:
- Use regulators for child node instead of voltage-regulators to be
consistent with other PMIC. Suggested by Mark Brown.
- Use regulators node names instead of the deprecated regulator-compatible
property. Suggested by Mark Brown.
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 371 +
arch/arm/boot/dts/exynos5800-peach-pi.dts | 371 +
2 files changed, 742 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index b2f1237..e5d450a 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -143,6 +143,339 @@
ddc = i2c_2;
};
+hsi2c_4 {
+ status = okay;
+ clock-frequency = 40;
+
+ max77802-pmic@9 {
+ compatible = maxim,max77802;
+ interrupt-parent = gpx3;
+ interrupts = 1 0;
+ pinctrl-names = default;
+ pinctrl-0 = max77802_irq, pmic_selb,
+ pmic_dvs_1, pmic_dvs_2, pmic_dvs_3;
+ wakeup-source;
+ reg = 0x9;
+ #clock-cells = 1;
+
+ inb1-supply = tps65090_dcdc2;
+ inb2-supply = tps65090_dcdc1;
+ inb3-supply = tps65090_dcdc2;
+ inb4-supply = tps65090_dcdc2;
+ inb5-supply = tps65090_dcdc1;
+ inb6-supply = tps65090_dcdc2;
+ inb7-supply = tps65090_dcdc1;
+ inb8-supply = tps65090_dcdc1;
+ inb9-supply = tps65090_dcdc1;
+ inb10-supply = tps65090_dcdc1;
+
+ inl1-supply = buck5_reg;
+ inl2-supply = buck7_reg;
+ inl3-supply = buck9_reg;
+ inl4-supply = buck9_reg;
+ inl5-supply = buck9_reg;
+ inl6-supply = tps65090_dcdc2;
+ inl7-supply = buck9_reg;
+ inl9-supply = tps65090_dcdc2;
+ inl10-supply = buck7_reg;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = vdd_mif;
+ regulator-min-microvolt = 80;
+ regulator-max-microvolt = 130;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = 12500;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = vdd_arm;
+ regulator-min-microvolt = 80;
+ regulator-max-microvolt = 150;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = 12500;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = vdd_int;
+ regulator-min-microvolt = 80;
+ regulator-max-microvolt = 140;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = 12500;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = vdd_g3d;
+ regulator-min-microvolt = 70;
+ regulator-max-microvolt = 140;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = 12500;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = vdd_1v2;
+ regulator-min-microvolt = 120;
+
[PATCH v8 12/13] rtc: Add driver for Maxim 77802 PMIC Real-Time-Clock
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v6:
- Remove unused code for SMPL and WTSR. Suggested by Krzysztof Kozlowski.
- Don't spam the kernel log with unnecessarily info and just print for debug.
Suggested by Krzysztof Kozlowski.
- Use ARRAY_SIZE() instead of constant value. Suggested by Krzysztof Kozlowski.
- Remove duplicated register setup. Suggested by Krzysztof Kozlowski.
- Don't free/unregister managed allocated resources.
Suggested by Krzysztof Kozlowski.
---
drivers/rtc/Kconfig| 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-max77802.c | 508 +
3 files changed, 519 insertions(+)
create mode 100644 drivers/rtc/rtc-max77802.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index a672dd1..243ac72 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -288,6 +288,16 @@ config RTC_DRV_MAX77686
This driver can also be built as a module. If so, the module
will be called rtc-max77686.
+config RTC_DRV_MAX77802
+ tristate Maxim 77802 RTC
+ depends on MFD_MAX77686
+ help
+ If you say yes here you will get support for the
+ RTC of Maxim MAX77802 PMIC.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-max77802.
+
config RTC_DRV_RS5C372
tristate Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 70347d0..247de78 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_RTC_DRV_MAX8998) += rtc-max8998.o
obj-$(CONFIG_RTC_DRV_MAX8997) += rtc-max8997.o
obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o
obj-$(CONFIG_RTC_DRV_MAX77686) += rtc-max77686.o
+obj-$(CONFIG_RTC_DRV_MAX77802) += rtc-max77802.o
obj-$(CONFIG_RTC_DRV_MC13XXX) += rtc-mc13xxx.o
obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o
obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
diff --git a/drivers/rtc/rtc-max77802.c b/drivers/rtc/rtc-max77802.c
new file mode 100644
index 000..f8898ff
--- /dev/null
+++ b/drivers/rtc/rtc-max77802.c
@@ -0,0 +1,508 @@
+/*
+ * RTC driver for Maxim MAX77802
+ *
+ * Copyright (C) 2013 Google, Inc
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *
+ * based on rtc-max8997.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include linux/slab.h
+#include linux/rtc.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/mfd/max77686-private.h
+#include linux/irqdomain.h
+#include linux/regmap.h
+
+/* RTC Control Register */
+#define BCD_EN_SHIFT 0
+#define BCD_EN_MASK(1 BCD_EN_SHIFT)
+#define MODEL24_SHIFT 1
+#define MODEL24_MASK (1 MODEL24_SHIFT)
+/* RTC Update Register1 */
+#define RTC_UDR_SHIFT 0
+#define RTC_UDR_MASK (1 RTC_UDR_SHIFT)
+#define RTC_RBUDR_SHIFT4
+#define RTC_RBUDR_MASK (1 RTC_RBUDR_SHIFT)
+/* RTC Hour register */
+#define HOUR_PM_SHIFT 6
+#define HOUR_PM_MASK (1 HOUR_PM_SHIFT)
+/* RTC Alarm Enable */
+#define ALARM_ENABLE_SHIFT 7
+#define ALARM_ENABLE_MASK (1 ALARM_ENABLE_SHIFT)
+
+/* For the RTCAE1 register, we write this value to enable the alarm */
+#define ALARM_ENABLE_VALUE 0x77
+
+#define MAX77802_RTC_UPDATE_DELAY_US 200
+
+enum {
+ RTC_SEC = 0,
+ RTC_MIN,
+ RTC_HOUR,
+ RTC_WEEKDAY,
+ RTC_MONTH,
+ RTC_YEAR,
+ RTC_DATE,
+ RTC_NR_TIME
+};
+
+struct max77802_rtc_info {
+ struct device *dev;
+ struct max77686_dev *max77802;
+ struct i2c_client *rtc;
+ struct rtc_device *rtc_dev;
+ struct mutexlock;
+
+ struct regmap *regmap;
+
+ int virq;
+ int rtc_24hr_mode;
+};
+
+enum MAX77802_RTC_OP {
+ MAX77802_RTC_WRITE,
+ MAX77802_RTC_READ,
+};
+
+static inline int max77802_rtc_calculate_wday(u8 shifted)
+{
+ int counter = -1;
+
+ while (shifted) {
+ shifted = 1;
+ counter++;
+ }
+
+ return counter;
+}
+
+static void max77802_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
+ int rtc_24hr_mode)
+{
+ tm-tm_sec = data[RTC_SEC] 0xff;
+ tm-tm_min =
[PATCH 1/3] serial: samsung: get fifosize via device tree
UART modules on some SoCs only differ in the fifosize of each
UART channel. Its useless to duplicate the drv_data structure
or create a compatible name for such a change.
We can get fifosize via the device tree nodes (not mandating it).
Also updates the documentation.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: gre...@linuxfoundation.org
---
.../devicetree/bindings/serial/samsung_uart.txt|4
drivers/tty/serial/samsung.c | 12 +---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt
b/Documentation/devicetree/bindings/serial/samsung_uart.txt
index 85e8ee2..e85f37e 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.txt
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.txt
@@ -29,6 +29,9 @@ Required properties:
[1] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Optional properties:
+- samsung,uart-fifosize: The fifo size supported by the UART channel
+
Note: Each Samsung UART should have an alias correctly numbered in the
aliases node, according to serialN format, where N is the port number
(non-negative decimal integer) as specified by User's Manual of respective
@@ -51,4 +54,5 @@ Example:
clk_uart_baud3;
clocks = clocks PCLK_UART1, clocks PCLK_UART1,
clocks SCLK_UART;
+ samsung,uart-fifosize = 16;
};
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 6be852d..e49a945 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1295,9 +1295,15 @@ static int s3c24xx_serial_probe(struct platform_device
*pdev)
dev_get_platdata(pdev-dev) :
ourport-drv_data-def_cfg;
- ourport-port.fifosize = (ourport-info-fifosize) ?
- ourport-info-fifosize :
- ourport-drv_data-fifosize[index];
+ if (pdev-dev.of_node)
+ of_property_read_u32(pdev-dev.of_node,
+ samsung,uart-fifosize, ourport-port.fifosize);
+
+ if (!ourport-port.fifosize) {
+ ourport-port.fifosize = (ourport-info-fifosize) ?
+ ourport-info-fifosize :
+ ourport-drv_data-fifosize[index];
+ }
probe_index++;
--
1.7.9.5
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[PATCH 3/3] serial: samsung: improve code clarity by defining a variable
The of_node is derived from pdev for every usage, define a
device_node variable instead.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: gre...@linuxfoundation.org
---
drivers/tty/serial/samsung.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index d98f93d..4aff02d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1269,12 +1269,13 @@ static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
static int s3c24xx_serial_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev-dev.of_node;
struct s3c24xx_uart_port *ourport;
int index = probe_index;
int ret;
- if (pdev-dev.of_node) {
- ret = of_alias_get_id(pdev-dev.of_node, serial);
+ if (np) {
+ ret = of_alias_get_id(np, serial);
if (ret = 0)
index = ret;
}
@@ -1295,8 +1296,8 @@ static int s3c24xx_serial_probe(struct platform_device
*pdev)
dev_get_platdata(pdev-dev) :
ourport-drv_data-def_cfg;
- if (pdev-dev.of_node)
- of_property_read_u32(pdev-dev.of_node,
+ if (np)
+ of_property_read_u32(np,
samsung,uart-fifosize, ourport-port.fifosize);
if (!ourport-port.fifosize) {
--
1.7.9.5
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[PATCH 2/3] serial: samsung: correct the case and default order in switch
The cases should comes before default in a switch. Even if we want the case and default to share same code. Its good to define the case first followed by default. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: gre...@linuxfoundation.org --- drivers/tty/serial/samsung.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index e49a945..d98f93d 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1542,8 +1542,8 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud, case S3C2410_LCON_CS7: *bits = 7; break; - default: case S3C2410_LCON_CS8: + default: *bits = 8; break; } -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] serial: samsung: get fifosize from DT and clean up
This patch set does the following 1: Get fifosize from DT node. But, not mandating it. 2. Corrects the case and default order in a switch 3. Defines a variable to simply the code. Console messages on Exynos5420 based peach pit and pi works fine. Naveen Krishna Chatradhi (3): serial: samsung: get fifosize via device tree serial: samsung: correct the case and default order in switch serial: samsung: improve code clarity by defining a variable .../devicetree/bindings/serial/samsung_uart.txt|4 drivers/tty/serial/samsung.c | 19 +-- 2 files changed, 17 insertions(+), 6 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 09/13] clk: max77802: Add DT binding documentation
Add Device Tree binding documentation for the clocks
outputs in the Maxim 77802 Power Management IC.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v6: None
Changes since v5:
- Fix typo error in DT binding. Suggested by Andreas Farber.
- Add clock-output-names as an optional property since now is supported.
Changes since v4: None
Changes since v3:
- Don't use the same clock driver name in clock-names since it's a consumer
concept and most probably will be different. Suggested by Doug Anderson.
Changes since v2:
- Split the DT binding documentation in a separate patch.
---
.../devicetree/bindings/clock/maxim,max77802.txt | 44 ++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/maxim,max77802.txt
diff --git a/Documentation/devicetree/bindings/clock/maxim,max77802.txt
b/Documentation/devicetree/bindings/clock/maxim,max77802.txt
new file mode 100644
index 000..c6dc783
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/maxim,max77802.txt
@@ -0,0 +1,44 @@
+Binding for Maxim MAX77802 32k clock generator block
+
+This is a part of device tree bindings of MAX77802 multi-function device.
+More information can be found in bindings/mfd/max77802.txt file.
+
+The MAX77802 contains two 32.768khz clock outputs that can be controlled
+(gated/ungated) over I2C.
+
+Following properties should be present in main device node of the MFD chip.
+
+Required properties:
+- #clock-cells: From common clock binding; shall be set to 1.
+
+Optional properties:
+- clock-output-names: From common clock binding.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Following indices are allowed:
+ - 0: 32khz_ap clock,
+ - 1: 32khz_cp clock.
+
+Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
+header and can be used in device tree sources.
+
+Example: Node of the MFD chip
+
+ max77802: max77802@09 {
+ compatible = maxim,max77802;
+ interrupt-parent = wakeup_eint;
+ interrupts = 26 0;
+ reg = 0x09;
+ #clock-cells = 1;
+
+ /* ... */
+ };
+
+Example: Clock consumer node
+
+ foo@0 {
+ compatible = bar,foo;
+ /* ... */
+ clock-names = my-clock;
+ clocks = max77802 MAX77802_CLK_32K_AP;
+ };
--
2.0.0.rc2
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[PATCH v8 10/13] rtc: max77686: Allow the max77686 rtc to wakeup the system
From: Doug Anderson diand...@chromium.org
The max77686 includes an RTC that keeps power during suspend. It's
convenient to be able to use it as a wakeup source.
NOTE: due to wakeup ordering problems this patch alone doesn't work so
well on exynos5250-snow. You also need something that brings the i2c
bus up before the max77686 wakeup runs.
Signed-off-by: Doug Anderson diand...@chromium.org
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v6: None
Changes since v5:
- Fix $SUBJECT since the patch does not actually touch the mfd subsys.
Suggested by Lee Jones.
Changes since v4: None
Changes since v3:
- Keep the note that this patch needs another change due wakeup
ordering problems.
---
drivers/rtc/rtc-max77686.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/rtc/rtc-max77686.c b/drivers/rtc/rtc-max77686.c
index d20a7f0..c1c6055 100644
--- a/drivers/rtc/rtc-max77686.c
+++ b/drivers/rtc/rtc-max77686.c
@@ -583,6 +583,33 @@ static void max77686_rtc_shutdown(struct platform_device
*pdev)
#endif /* MAX77686_RTC_WTSR_SMPL */
}
+#ifdef CONFIG_PM_SLEEP
+static int max77686_rtc_suspend(struct device *dev)
+{
+ if (device_may_wakeup(dev)) {
+ struct max77686_rtc_info *info = dev_get_drvdata(dev);
+
+ return enable_irq_wake(info-virq);
+ }
+
+ return 0;
+}
+
+static int max77686_rtc_resume(struct device *dev)
+{
+ if (device_may_wakeup(dev)) {
+ struct max77686_rtc_info *info = dev_get_drvdata(dev);
+
+ return disable_irq_wake(info-virq);
+ }
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
+max77686_rtc_suspend, max77686_rtc_resume);
+
static const struct platform_device_id rtc_id[] = {
{ max77686-rtc, 0 },
{},
@@ -592,6 +619,7 @@ static struct platform_driver max77686_rtc_driver = {
.driver = {
.name = max77686-rtc,
.owner = THIS_MODULE,
+ .pm = max77686_rtc_pm_ops,
},
.probe = max77686_rtc_probe,
.shutdown = max77686_rtc_shutdown,
--
2.0.0.rc2
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Re: [PATCH 1/1] ARM: exynos_defconfig: Update exynos_defconfig
Tested-by: Arun Kumar K arun...@samsung.com on Samsung chromebook boards : Snow, pit and pi. Regards Arun On Wed, Jul 9, 2014 at 3:52 PM, Sachin Kamat sachin.ka...@samsung.com wrote: Removed outdated configs. Enabled most of the configs used on latest Exynos based platforms. This will provide a reference for users trying to verify and test various features on Exynos based platforms and also help in detecting breakages by widening the build coverage. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com --- arch/arm/configs/exynos_defconfig | 56 +++-- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e07a227ec0db..fc7d1683bf67 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -8,15 +8,17 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=3 -CONFIG_S3C24XX_PWM=y -CONFIG_ARCH_EXYNOS5=y -CONFIG_MACH_EXYNOS4_DT=y +CONFIG_ARCH_EXYNOS3=y +CONFIG_EXYNOS5420_MCPM=y CONFIG_SMP=y +CONFIG_BIG_LITTLE=y +CONFIG_BL_SWITCHER=y +CONFIG_BL_SWITCHER_DUMMY_IF=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y +CONFIG_CMA=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y @@ -24,6 +26,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE=root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M console=ttySAC1,115200 init=/linuxrc mem=256M CONFIG_VFP=y CONFIG_NEON=y +CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -34,6 +37,8 @@ CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_PROC_DEVICETREE=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y @@ -66,11 +71,22 @@ CONFIG_I2C=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_I2C_EXYNOS5=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SPI=y +CONFIG_SPI_S3C64XX=y CONFIG_I2C_S3C2410=y CONFIG_DEBUG_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_CHARGER_TPS65090=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_EXYNOS_THERMAL=y +CONFIG_EXYNOS_THERMAL_CORE=y +CONFIG_WATCHDOG=y +CONFIG_S3C2410_WATCHDOG=y CONFIG_MFD_CROS_EC=y CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_CROS_EC_SPI=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX8997=y CONFIG_MFD_SEC_CORE=y @@ -80,6 +96,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8997=y CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y @@ -88,28 +105,50 @@ CONFIG_FB_MODE_HELPERS=y CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y -CONFIG_EXYNOS_DP=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_7x14=y CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SNOW=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=y -CONFIG_USB_PHY=y -CONFIG_SAMSUNG_USB2PHY=y -CONFIG_SAMSUNG_USB3PHY=y +CONFIG_USB_HSIC_USB3503=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y CONFIG_MMC_DW=y CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_EXYNOS_IOMMU=y +CONFIG_IIO=y +CONFIG_EXYNOS_ADC=y +CONFIG_PWM=y +CONFIG_PWM_SAMSUNG=y +CONFIG_PHY_EXYNOS5250_SATA=y +CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_PHY_EXYNOS4210_USB2=y +CONFIG_PHY_EXYNOS4X12_USB2=y +CONFIG_PHY_EXYNOS5250_USB2=y +CONFIG_PHY_EXYNOS5_USBDRD=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y @@ -123,6 +162,7 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 05/13] clk: Add generic driver for Maxim PMIC clocks
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and are simpler enough that
can be converted to use a generic driver to consolidate code
and avoid duplication.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v6: None
Changes since v5:
- Fix generic driver changes merged into max77802 clock patch by mistake.
Suggested by Yadwinder Singh Brar.
- Register clock lookups using clk_register_clkdev() instead of doing manually.
- Use the managed devm_clk_register() function and remove clk un-registration.
- Add clock-output-names property support. Suggested by Yadwinder Singh Brar.
- Return the rate unconditionally in recalc_rate. Suggested by Mike Turquette.
Changes since v4: None
Changes since v3:
- Don't change clock-names property to make clear that it's
the consumer clock name and should not match the producer clock.
Suggested by Doug Anderson.
---
drivers/clk/Kconfig | 3 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-max-gen.c | 192 ++
drivers/clk/clk-max-gen.h | 32
4 files changed, 228 insertions(+)
create mode 100644 drivers/clk/clk-max-gen.c
create mode 100644 drivers/clk/clk-max-gen.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9f9c5ae..73f78e8 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -32,6 +32,9 @@ config COMMON_CLK_WM831X
source drivers/clk/versatile/Kconfig
+config COMMON_CLK_MAX_GEN
+bool
+
config COMMON_CLK_MAX77686
tristate Clock driver for Maxim 77686 MFD
depends on MFD_MAX77686
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 567f102..6c1aff6 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_BCM2835)+= clk-bcm2835.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_ARCH_HIGHBANK)+= clk-highbank.o
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
+obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
diff --git a/drivers/clk/clk-max-gen.c b/drivers/clk/clk-max-gen.c
new file mode 100644
index 000..6505049
--- /dev/null
+++ b/drivers/clk/clk-max-gen.c
@@ -0,0 +1,192 @@
+/*
+ * clk-max-gen.c - Generic clock driver for Maxim PMICs clocks
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * Copyright (C) 2012 Samsung Electornics
+ * Jonghwa Lee jonghwa3@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This driver is based on clk-max77686.c
+ *
+ */
+
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/err.h
+#include linux/regmap.h
+#include linux/platform_device.h
+#include linux/clk-provider.h
+#include linux/mutex.h
+#include linux/clkdev.h
+#include linux/of.h
+#include linux/export.h
+
+struct max_gen_clk {
+ struct regmap *regmap;
+ u32 mask;
+ u32 reg;
+ struct clk_hw hw;
+};
+
+static struct max_gen_clk *to_max_gen_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct max_gen_clk, hw);
+}
+
+static int max_gen_clk_prepare(struct clk_hw *hw)
+{
+ struct max_gen_clk *max_gen = to_max_gen_clk(hw);
+
+ return regmap_update_bits(max_gen-regmap, max_gen-reg,
+ max_gen-mask, max_gen-mask);
+}
+
+static void max_gen_clk_unprepare(struct clk_hw *hw)
+{
+ struct max_gen_clk *max_gen = to_max_gen_clk(hw);
+
+ regmap_update_bits(max_gen-regmap, max_gen-reg,
+ max_gen-mask, ~max_gen-mask);
+}
+
+static int max_gen_clk_is_prepared(struct clk_hw *hw)
+{
+ struct max_gen_clk *max_gen = to_max_gen_clk(hw);
+ int ret;
+ u32 val;
+
+ ret = regmap_read(max_gen-regmap, max_gen-reg, val);
+
+ if (ret 0)
+ return -EINVAL;
+
+ return val max_gen-mask;
+}
+
+static unsigned long max_gen_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+ return 32768;
+}
+
+struct clk_ops max_gen_clk_ops = {
+ .prepare= max_gen_clk_prepare,
+ .unprepare = max_gen_clk_unprepare,
+ .is_prepared= max_gen_clk_is_prepared,
+ .recalc_rate=
[PATCH v8 11/13] rtc: max77686: Remove dead code for SMPL and WTSR.
The MAX77686 RTC chip has two features called SMPL (Sudden Momentary
Power Loss) and WTSR (Watchdog Timeout and Software Resets).
Support for these features seems to be implemented in the driver but
compilation is disabled using a C pre-processor conditional.
This code has been disabled since the driver was original merged in
commit fca1dd03 (rtc: max77686: add Maxim 77686 driver).
So, since this code has never been built, let's just remove it.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/rtc/rtc-max77686.c | 101 -
1 file changed, 101 deletions(-)
diff --git a/drivers/rtc/rtc-max77686.c b/drivers/rtc/rtc-max77686.c
index c1c6055..7bb5433 100644
--- a/drivers/rtc/rtc-max77686.c
+++ b/drivers/rtc/rtc-max77686.c
@@ -32,15 +32,6 @@
#define RTC_UDR_MASK (1 RTC_UDR_SHIFT)
#define RTC_RBUDR_SHIFT4
#define RTC_RBUDR_MASK (1 RTC_RBUDR_SHIFT)
-/* WTSR and SMPL Register */
-#define WTSRT_SHIFT0
-#define SMPLT_SHIFT2
-#define WTSR_EN_SHIFT 6
-#define SMPL_EN_SHIFT 7
-#define WTSRT_MASK (3 WTSRT_SHIFT)
-#define SMPLT_MASK (3 SMPLT_SHIFT)
-#define WTSR_EN_MASK (1 WTSR_EN_SHIFT)
-#define SMPL_EN_MASK (1 SMPL_EN_SHIFT)
/* RTC Hour register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 HOUR_PM_SHIFT)
@@ -49,7 +40,6 @@
#define ALARM_ENABLE_MASK (1 ALARM_ENABLE_SHIFT)
#define MAX77686_RTC_UPDATE_DELAY 16
-#undef MAX77686_RTC_WTSR_SMPL
enum {
RTC_SEC = 0,
@@ -412,64 +402,6 @@ static const struct rtc_class_ops max77686_rtc_ops = {
.alarm_irq_enable = max77686_rtc_alarm_irq_enable,
};
-#ifdef MAX77686_RTC_WTSR_SMPL
-static void max77686_rtc_enable_wtsr(struct max77686_rtc_info *info, bool
enable)
-{
- int ret;
- unsigned int val, mask;
-
- if (enable)
- val = (1 WTSR_EN_SHIFT) | (3 WTSRT_SHIFT);
- else
- val = 0;
-
- mask = WTSR_EN_MASK | WTSRT_MASK;
-
- dev_info(info-dev, %s: %s WTSR\n, __func__,
- enable ? enable : disable);
-
- ret = regmap_update_bits(info-max77686-rtc_regmap,
-MAX77686_WTSR_SMPL_CNTL, mask, val);
- if (ret 0) {
- dev_err(info-dev, %s: fail to update WTSR reg(%d)\n,
- __func__, ret);
- return;
- }
-
- max77686_rtc_update(info, MAX77686_RTC_WRITE);
-}
-
-static void max77686_rtc_enable_smpl(struct max77686_rtc_info *info, bool
enable)
-{
- int ret;
- unsigned int val, mask;
-
- if (enable)
- val = (1 SMPL_EN_SHIFT) | (0 SMPLT_SHIFT);
- else
- val = 0;
-
- mask = SMPL_EN_MASK | SMPLT_MASK;
-
- dev_info(info-dev, %s: %s SMPL\n, __func__,
- enable ? enable : disable);
-
- ret = regmap_update_bits(info-max77686-rtc_regmap,
-MAX77686_WTSR_SMPL_CNTL, mask, val);
- if (ret 0) {
- dev_err(info-dev, %s: fail to update SMPL reg(%d)\n,
- __func__, ret);
- return;
- }
-
- max77686_rtc_update(info, MAX77686_RTC_WRITE);
-
- val = 0;
- regmap_read(info-max77686-rtc_regmap, MAX77686_WTSR_SMPL_CNTL, val);
- dev_info(info-dev, %s: WTSR_SMPL(0x%02x)\n, __func__, val);
-}
-#endif /* MAX77686_RTC_WTSR_SMPL */
-
static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
{
u8 data[2];
@@ -519,11 +451,6 @@ static int max77686_rtc_probe(struct platform_device *pdev)
goto err_rtc;
}
-#ifdef MAX77686_RTC_WTSR_SMPL
- max77686_rtc_enable_wtsr(info, true);
- max77686_rtc_enable_smpl(info, true);
-#endif
-
device_init_wakeup(pdev-dev, 1);
info-rtc_dev = devm_rtc_device_register(pdev-dev, max77686-rtc,
@@ -556,33 +483,6 @@ err_rtc:
return ret;
}
-static void max77686_rtc_shutdown(struct platform_device *pdev)
-{
-#ifdef MAX77686_RTC_WTSR_SMPL
- struct max77686_rtc_info *info = platform_get_drvdata(pdev);
- int i;
- u8 val = 0;
-
- for (i = 0; i 3; i++) {
- max77686_rtc_enable_wtsr(info, false);
- regmap_read(info-max77686-rtc_regmap,
MAX77686_WTSR_SMPL_CNTL, val);
- dev_info(info-dev, %s: WTSR_SMPL reg(0x%02x)\n, __func__,
- val);
- if (val WTSR_EN_MASK) {
- dev_emerg(info-dev, %s: fail to disable WTSR\n,
- __func__);
- } else {
- dev_info(info-dev, %s: success to disable WTSR\n,
-
[PATCH v8 08/13] clk: Add driver for Maxim 77802 PMIC clocks
The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with
Low Jitter Mode. This patch adds support for these two clocks.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v6: None
Changes since v5: None
Changes since v4: None
Changes since v3: None
Changes since v2: None
Changes since v1:
- Use module_platform_driver() instead of having init/exit functions.
Suggested by Mark Brown.
- Use the generic maxim clock driver to reduce code duplication with
clk-max77686.c driver.
---
drivers/clk/Kconfig| 7 +++
drivers/clk/Makefile | 1 +
drivers/clk/clk-max77802.c | 98 ++
include/dt-bindings/clock/maxim,max77802.h | 22 +++
4 files changed, 128 insertions(+)
create mode 100644 drivers/clk/clk-max77802.c
create mode 100644 include/dt-bindings/clock/maxim,max77802.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3fd4270..8808f2a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -42,6 +42,13 @@ config COMMON_CLK_MAX77686
---help---
This driver supports Maxim 77686 crystal oscillator clock.
+config COMMON_CLK_MAX77802
+ tristate Clock driver for Maxim 77802 PMIC
+ depends on MFD_MAX77686
+ select COMMON_CLK_MAX_GEN
+ ---help---
+ This driver supports Maxim 77802 crystal oscillator clock.
+
config COMMON_CLK_SI5351
tristate Clock driver for SiLabs 5351A/B/C
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 6c1aff6..520ff76 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
+obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
diff --git a/drivers/clk/clk-max77802.c b/drivers/clk/clk-max77802.c
new file mode 100644
index 000..8e480c5
--- /dev/null
+++ b/drivers/clk/clk-max77802.c
@@ -0,0 +1,98 @@
+/*
+ * clk-max77802.c - Clock driver for Maxim 77802
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * Copyright (C) 2012 Samsung Electornics
+ * Jonghwa Lee jonghwa3@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This driver is based on clk-max77686.c
+ */
+
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/err.h
+#include linux/platform_device.h
+#include linux/mfd/max77686-private.h
+#include linux/clk-provider.h
+#include linux/mutex.h
+#include linux/clkdev.h
+
+#include dt-bindings/clock/maxim,max77802.h
+#include clk-max-gen.h
+
+#define MAX77802_CLOCK_OPMODE_MASK 0x1
+#define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3
+
+static struct clk_init_data max77802_clks_init[MAX77802_CLKS_NUM] = {
+ [MAX77802_CLK_32K_AP] = {
+ .name = 32khz_ap,
+ .ops = max_gen_clk_ops,
+ .flags = CLK_IS_ROOT,
+ },
+ [MAX77802_CLK_32K_CP] = {
+ .name = 32khz_cp,
+ .ops = max_gen_clk_ops,
+ .flags = CLK_IS_ROOT,
+ },
+};
+
+static int max77802_clk_probe(struct platform_device *pdev)
+{
+ struct max77686_dev *iodev = dev_get_drvdata(pdev-dev.parent);
+ int ret;
+
+ ret = max_gen_clk_probe(pdev, iodev-regmap, MAX77802_REG_32KHZ,
+ max77802_clks_init, MAX77802_CLKS_NUM);
+
+ if (ret) {
+ dev_err(pdev-dev, generic probe failed %d\n, ret);
+ return ret;
+ }
+
+ /* Enable low-jitter mode on the 32khz clocks. */
+ ret = regmap_update_bits(iodev-regmap, MAX77802_REG_32KHZ,
+1 MAX77802_CLOCK_LOW_JITTER_SHIFT,
+1 MAX77802_CLOCK_LOW_JITTER_SHIFT);
+ if (ret 0)
+ dev_err(pdev-dev, failed to enable low-jitter mode\n);
+
+ return ret;
+}
+
+static int max77802_clk_remove(struct platform_device *pdev)
+{
+ return max_gen_clk_remove(pdev, MAX77802_CLKS_NUM);
+}
+
+static const struct platform_device_id max77802_clk_id[] = {
+ { max77802-clk, 0},
+ { },
+};
+MODULE_DEVICE_TABLE(platform,
[PATCH v8 03/13] regulator: Add driver for Maxim 77802 PMIC regulators
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the MAX77802 PMIC and is based on a driver added by Simon
Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v7:
- Remove DVS support since that can be added as a follow up.
Changes since v6: None
Changes since v5:
- Take out the mfd changes from v4 that were squashed by mistake.
Suggested by Lee Jones.
Changes since v4: None
Changes since v3:
- Set the supply_name for regulators to lookup their parent supply node.
Suggested by Mark Brown.
- Change Exyno5 for Exynos5420/Exynos5800 in regulator driver Kconfig.
Suggested by Doug Anderson.
---
drivers/regulator/Kconfig| 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77802.c | 578 +++
3 files changed, 588 insertions(+)
create mode 100644 drivers/regulator/max77802.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 789eb46..96d1c68 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -377,6 +377,15 @@ config REGULATOR_MAX77693
and one current regulator 'CHARGER'. This is suitable for
Exynos-4x12 chips.
+config REGULATOR_MAX77802
+ tristate Maxim 77802 regulator
+ depends on MFD_MAX77686
+ help
+ This driver controls a Maxim 77802 regulator
+ via I2C bus. The provided regulator is suitable for
+ Exynos5420/Exynos5800 SoCs to control various voltages.
+ It includes support for control of voltage and ramp speed.
+
config REGULATOR_MC13XXX_CORE
tristate
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index d461110..2aea4b6 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_REGULATOR_MAX8997) += max8997.o
obj-$(CONFIG_REGULATOR_MAX8998) += max8998.o
obj-$(CONFIG_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_REGULATOR_MAX77693) += max77693.o
+obj-$(CONFIG_REGULATOR_MAX77802) += max77802.o
obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c
new file mode 100644
index 000..5f022f8
--- /dev/null
+++ b/drivers/regulator/max77802.c
@@ -0,0 +1,578 @@
+/*
+ * max77802.c - Regulator driver for the Maxim 77802
+ *
+ * Copyright (C) 2013-2014 Google, Inc
+ * Simon Glass s...@chromium.org
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Chiwoong Byun woong.b...@smasung.com
+ * Jonghwa Lee jonghwa3@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This driver is based on max8997.c
+ */
+
+#include linux/kernel.h
+#include linux/bug.h
+#include linux/err.h
+#include linux/gpio.h
+#include linux/slab.h
+#include linux/gpio/consumer.h
+#include linux/platform_device.h
+#include linux/regulator/driver.h
+#include linux/regulator/machine.h
+#include linux/regulator/of_regulator.h
+#include linux/mfd/max77686.h
+#include linux/mfd/max77686-private.h
+
+/* Default ramp delay in case it is not manually set */
+#define MAX77802_RAMP_DELAY10 /* uV/us */
+
+#define MAX77802_OPMODE_SHIFT_LDO 6
+#define MAX77802_OPMODE_BUCK234_SHIFT 4
+#define MAX77802_OPMODE_MASK 0x3
+
+#define MAX77802_VSEL_MASK 0x3F
+#define MAX77802_DVS_VSEL_MASK 0xFF
+
+#define MAX77802_RAMP_RATE_MASK_2BIT 0xC0
+#define MAX77802_RAMP_RATE_SHIFT_2BIT 6
+#define MAX77802_RAMP_RATE_MASK_4BIT 0xF0
+#define MAX77802_RAMP_RATE_SHIFT_4BIT 4
+
+/* MAX77802 has two register formats: 2-bit and 4-bit */
+static const unsigned int ramp_table_77802_2bit[] = {
+ 12500,
+ 25000,
+ 5,
+ 10,
+};
+
+static unsigned int ramp_table_77802_4bit[] = {
+ 1000, 2000, 3030, 4000,
+ 5000, 5880, 7140, 8330,
+ 9090, 1, 0, 12500,
+ 16670, 25000, 5, 10,
+};
+
+struct max77802_regulator_prv {
+ int num_regulators;
+ struct regulator_dev *rdev[MAX77802_REG_MAX];
+ unsigned int opmode[MAX77802_REG_MAX];
+};
+
+static int max77802_get_opmode_shift(int id)
+{
+ if (id == MAX77802_BUCK1 || (id = MAX77802_BUCK5
+
[PATCH v8 07/13] clk: max77686: Improve Maxim 77686 PMIC clocks binding
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property is
used to specify the number of cells in a clock provider.
But the binding document is not clear enough that it shall
be set to 1 since the PMIC support multiple clocks outputs.
Also, explain that the clocks identifiers are defined in a
header file that can be included by Device Tree source with
client nodes to avoid using magic numbers.
Finally, add clock-output-names as an optional property
since now is supported by the clock driver.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Reviewed-by: Mike Turquette mturque...@linaro.org
---
Changes since v6: None
Changes since v5:
- Fix generic driver changes merged into max77802 clock patch by mistake.
Suggested by Yadwinder Singh Brar.
- Register clock lookups using clk_register_clkdev() instead of doing manually.
- Use the managed devm_clk_register() function and remove clk un-registration.
- Add clock-output-names property support. Suggested by Yadwinder Singh Brar.
- Return the rate unconditionally in recalc_rate. Suggested by Mike Turquette.
Changes since v4: None
Changes since v3:
- Don't change clock-names property to make clear that it's
the consumer clock name and should not match the producer clock.
Suggested by Doug Anderson.
---
.../devicetree/bindings/clock/maxim,max77686.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt
b/Documentation/devicetree/bindings/clock/maxim,max77686.txt
index 96ce71b..9c40739 100644
--- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt
+++ b/Documentation/devicetree/bindings/clock/maxim,max77686.txt
@@ -9,13 +9,21 @@ The MAX77686 contains three 32.768khz clock outputs that can
be controlled
Following properties should be presend in main device node of the MFD chip.
Required properties:
-- #clock-cells: simple one-cell clock specifier format is used, where the
- only cell is used as an index of the clock inside the provider. Following
- indices are allowed:
+
+- #clock-cells: from common clock binding; shall be set to 1.
+
+Optional properties:
+- clock-output-names: From common clock binding.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Following indices are allowed:
- 0: 32khz_ap clock,
- 1: 32khz_cp clock,
- 2: 32khz_pmic clock.
+Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
+header and can be used in device tree sources.
+
Example: Node of the MFD chip
max77686: max77686@09 {
@@ -34,5 +42,5 @@ Example: Clock consumer node
compatible = bar,foo;
/* ... */
clock-names = my-clock;
- clocks = max77686 2;
+ clocks = max77686 MAX77686_CLK_PMIC;
};
--
2.0.0.rc2
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[PATCH v8 04/13] clk: max77686: Add DT include for MAX77686 PMIC clock
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be used by both the max77686
clock driver and Device Tree source files.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reviewed-by: Mike Turquette mturque...@linaro.org
---
Changes since v6: None
Changes since v5:
- Improve wording in commit message. Suggested by Andreas Farber.
Changes since v4: None
Changes since v3:
- Keep the note that this patch needs another change due wakeup
ordering problems.
---
drivers/clk/clk-max77686.c | 7 +--
include/dt-bindings/clock/maxim,max77686.h | 23 +++
2 files changed, 24 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/clock/maxim,max77686.h
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index 3d7e8dd..185b611 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -30,12 +30,7 @@
#include linux/mutex.h
#include linux/clkdev.h
-enum {
- MAX77686_CLK_AP = 0,
- MAX77686_CLK_CP,
- MAX77686_CLK_PMIC,
- MAX77686_CLKS_NUM,
-};
+#include dt-bindings/clock/maxim,max77686.h
struct max77686_clk {
struct max77686_dev *iodev;
diff --git a/include/dt-bindings/clock/maxim,max77686.h
b/include/dt-bindings/clock/maxim,max77686.h
new file mode 100644
index 000..7b28b09
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77686.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP0
+#define MAX77686_CLK_CP1
+#define MAX77686_CLK_PMIC 2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */
--
2.0.0.rc2
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[PATCH] ARM: dts: Add mask-tpm-reset DT node to the exynos5800-peach-pi
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 28f2a25..caa8952 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -209,6 +209,18 @@
pinctrl_0 {
+ pinctrl-names = default;
+ pinctrl-0 = mask_tpm_reset;
+
+ /* We need GPX0_6 to be low at sleep time; just keep it low always */
+ mask_tpm_reset: mask-tpm-reset {
+ samsung,pins = gpx0-6;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ samsung,pin-val = 0;
+ };
+
max98091_irq: max98091-irq {
samsung,pins = gpx0-2;
samsung,pin-function = 0;
--
1.7.9.5
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Re: [PATCH] ARM: dts: Add mask-tpm-reset DT node to the exynos5800-peach-pi
Hello Vikas,
On 14 July 2014 17:36, Vikas Sajjan vikas.saj...@samsung.com wrote:
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
After merging Linus Walleij's for-next of pinctrl git.
S2R on Exynos5800 based Peach PI works fine.
Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 28f2a25..caa8952 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -209,6 +209,18 @@
pinctrl_0 {
+ pinctrl-names = default;
+ pinctrl-0 = mask_tpm_reset;
+
+ /* We need GPX0_6 to be low at sleep time; just keep it low always */
+ mask_tpm_reset: mask-tpm-reset {
+ samsung,pins = gpx0-6;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ samsung,pin-val = 0;
+ };
+
max98091_irq: max98091-irq {
samsung,pins = gpx0-2;
samsung,pin-function = 0;
--
1.7.9.5
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Re: [PATCH v2] ARM: dts: Add mask-tpm-reset to the device tree
Hello Vikas,
On 14 July 2014 12:03, Vikas Sajjan vikas.saj...@samsung.com wrote:
From: Doug Anderson diand...@chromium.org
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
After merging Linus Walleij's for-next branch of pinctrl git.
S2R on Exynos5420 based Peach PIT works fine.
Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
changes since v1:
- removed fixed regulator and used hogs instead.
arch/arm/boot/dts/exynos5420-peach-pit.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 6c7cab0..c036d9e 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -211,6 +211,18 @@
pinctrl_0 {
+ pinctrl-names = default;
+ pinctrl-0 = mask_tpm_reset;
+
+ /* We need GPX0_6 to be low at sleep time; just keep it low always */
+ mask_tpm_reset: mask-tpm-reset {
+ samsung,pins = gpx0-6;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ samsung,pin-val = 0;
+ };
+
max98090_irq: max98090-irq {
samsung,pins = gpx0-2;
samsung,pin-function = 0;
--
1.7.9.5
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[PATCH v3 7/8] ARM: dts: exynos4412-odroid: add support for GPIO buttons
This patch adds support for simple GPIO-based button availabled on
Exynos4 based Odroid boards. All supported boards have POWER button,
which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards
also have additional user-configurable button which has been mapped to
KEY_HOME. All defined keys have been marked as possible wakeup source.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 24
arch/arm/boot/dts/exynos4412-odroidx.dts| 21 +
2 files changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index ad2cb32a3439..d1b33a8efa9d 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -7,6 +7,7 @@
* published by the Free Software Foundation.
*/
+#include dt-bindings/input/input.h
#include exynos4412.dtsi
/ {
@@ -15,6 +16,22 @@
reg = 0x0204F000 0x1000;
};
+ gpio_keys {
+ compatible = gpio-keys;
+ pinctrl-names = default;
+ pinctrl-0 = gpio_power_key;
+
+ power_key {
+ interrupt-parent = gpx1;
+ interrupts = 3 0;
+ gpios = gpx1 3 1;
+ linux,code = KEY_POWER;
+ label = power key;
+ debounce-interval = 10;
+ gpio-key,wakeup;
+ };
+ };
+
mmc@1255 {
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
@@ -316,3 +333,10 @@
status = okay;
};
};
+
+pinctrl_1 {
+ gpio_power_key: power_key {
+ samsung,pins = gpx1-3;
+ samsung,pin-pud = 0;
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 8b453a31410d..cb1cfe7239c4 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -46,6 +46,20 @@
status = okay;
};
+ gpio_keys {
+ pinctrl-0 = gpio_power_key gpio_home_key;
+
+ home_key {
+ interrupt-parent = gpx2;
+ interrupts = 2 0;
+ gpios = gpx2 2 0;
+ linux,code = KEY_HOME;
+ label = home key;
+ debounce-interval = 10;
+ gpio-key,wakeup;
+ };
+ };
+
regulator_p3v3 {
compatible = regulator-fixed;
regulator-name = p3v3_en;
@@ -62,3 +76,10 @@
status = okay;
};
};
+
+pinctrl_1 {
+ gpio_home_key: home_key {
+ samsung,pins = gpx2-2;
+ samsung,pin-pud = 0;
+ };
+};
--
1.9.2
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[PATCH v3 2/8] ARM: dts: exynos4412-odroidx: enable common hardware blocks
This patch adds support for common hardware modules available on all
Exynos4412-based Odroid boards, which already have complete support in
mainline kernel. This includes secure firmware calls, watchdog, g2d and
fimc (mem2mem) multimedia accelerators.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 35
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a4bb33..fda9ac23dd55 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -22,6 +22,11 @@
reg = 0x4000 0x4000;
};
+ firmware@0204F000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x0204F000 0x1000;
+ };
+
leds {
compatible = gpio-leds;
led1 {
@@ -68,10 +73,40 @@
regulator-boot-on;
};
+ watchdog@1006 {
+ status = okay;
+ };
+
rtc@1007 {
status = okay;
};
+ g2d@1080 {
+ status = okay;
+ };
+
+ camera {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = ;
+
+ fimc_0: fimc@1180 {
+ status = okay;
+ };
+
+ fimc_1: fimc@1181 {
+ status = okay;
+ };
+
+ fimc_2: fimc@1182 {
+ status = okay;
+ };
+
+ fimc_3: fimc@1183 {
+ status = okay;
+ };
+ };
+
sdhci@1253 {
bus-width = 4;
pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
--
1.9.2
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[PATCH v3 1/8] ARM: dts: exynos4: add port sub-nodes to exynos usb host modules
This patch adds port sub-nodes to exynos4 ehci and ohci modules, which
are required by recently merged new exynos4 usb2 phy support.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 17b22e9cc2aa..868925ab2aa4 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -322,6 +322,23 @@
clocks = clock CLK_USB_HOST;
clock-names = usbhost;
status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ port@0 {
+ reg = 0;
+ phys = exynos_usbphy 1;
+ status = disabled;
+ };
+ port@1 {
+ reg = 1;
+ phys = exynos_usbphy 2;
+ status = disabled;
+ };
+ port@2 {
+ reg = 2;
+ phys = exynos_usbphy 3;
+ status = disabled;
+ };
};
ohci@1259 {
@@ -331,6 +348,13 @@
clocks = clock CLK_USB_HOST;
clock-names = usbhost;
status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ port@0 {
+ reg = 0;
+ phys = exynos_usbphy 1;
+ status = disabled;
+ };
};
i2s1: i2s@1396 {
--
1.9.2
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[PATCH v3 8/8] ARM: dts: exynos4412-odroid: fix T-FLASH hotplug detection
TFLASH (SDHCI2 controller) uses internal card detect line, but it looks that the driver fails to operate it properly. Use GPIO interrupt on SD_CDn line for detecting SD card state. Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index d1b33a8efa9d..0bc1a9b94f47 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -91,6 +91,8 @@ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4; pinctrl-names = default; vmmc-supply = ldo4_reg ldo21_reg; + cd-gpios = gpk2 2 0; + cd-inverted; status = okay; }; -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 6/8] ARM: dts: exynos4412-odroid-common: disable 'always on' for BUCK8 regulator
From: Kamil Debski k.deb...@samsung.com On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3 source, which is also connected to LAN9730 chip's nRESET signal. To reset lan chip on system reboot, the BUCK8 output should not be used in 'always on' mode. This change has no impact on X/X2 boards. Signed-off-by: Kamil Debski k.deb...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index f793f3b8f0b9..ad2cb32a3439 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -297,7 +297,6 @@ regulator-name = BUCK8_2.8V; regulator-min-microvolt = 280; regulator-max-microvolt = 280; - regulator-always-on; }; }; }; -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/8] Add Exynos4412 based Odroid X2 and U2/U3/U3+ support
Hello, This is the third version of the initial patch series adding support for Exynos 4412 based Odroid X2 and U2/U3/U3+ boards and improving support for Odroid X. Complete USB support for Odroid U2/U3/U3+ still requires some fixes in Exynos4 USB2 Phy driver and clock driver for CLKOUT: http://thread.gmane.org/gmane.linux.kernel/1731843/ http://www.spinics.net/lists/linux-usb/msg109587.html The above changes however don't affect Odroid DTS files, but without them, usb3503 hub is not yet functional. Support for audio codec and HDMI video output is available in separate patch series. If one is interested in more complete and open-source Odroid board support, there are also patches for u-boot project: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/188295/focus=188610 Best regards Marek Szyprowski Samsung RD Institute Poland Changelog: v3: - added fix for total memory size (last megabyte is used by secure firmware and should not be accessed by Linux kernel) - added patch defining GPIO button(s) - added patch fixing TFLASH (SD card) detection v2: - added fix for broken LAN after reboot (removed BUCK8 always on property) - restored all 4 uarts for Odroid X/X2 until correct patch for UART driver is developed - rmoved incorrect port@2 node in ehci node for odroidx dts - updated links for latest version of CLKOUT and PHY patches v1: - initial version *** BLURB HERE *** Kamil Debski (2): ARM: dts: exynos4412-odroidx: add support for USB (phy, host, device) ARM: dts: exynos4412-odroid-common: disable 'always on' for BUCK8 regulator Marek Szyprowski (6): ARM: dts: exynos4: add port sub-nodes to exynos usb host modules ARM: dts: exynos4412-odroidx: enable common hardware blocks ARM: dts: exynos4412-odroidx: correct memory size ARM: dts: refactor Odroid DTS file and add support for Odroid X2 and U2/U3 ARM: dts: exynos4412-odroid: add support for GPIO buttons ARM: dts: exynos4412-odroid: fix T-FLASH hotplug detection arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/exynos4.dtsi | 24 ++ arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 344 arch/arm/boot/dts/exynos4412-odroidu3.dts | 49 arch/arm/boot/dts/exynos4412-odroidx.dts| 279 ++- arch/arm/boot/dts/exynos4412-odroidx2.dts | 23 ++ 6 files changed, 471 insertions(+), 250 deletions(-) create mode 100644 arch/arm/boot/dts/exynos4412-odroid-common.dtsi create mode 100644 arch/arm/boot/dts/exynos4412-odroidu3.dts create mode 100644 arch/arm/boot/dts/exynos4412-odroidx2.dts -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 5/8] ARM: dts: refactor Odroid DTS file and add support for Odroid X2 and U2/U3
This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and
U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz
instead of 1.4GHz), while U2/U3 differs from X2 by different way of
routing signals to host USB hub. It also lacks some hw modules not yet
supported by those dts files (i.e. LCD touch panel).
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/Makefile | 2 +
...2-odroidx.dts = exynos4412-odroid-common.dtsi} | 57 +---
arch/arm/boot/dts/exynos4412-odroidu3.dts | 49
arch/arm/boot/dts/exynos4412-odroidx.dts | 326 +
arch/arm/boot/dts/exynos4412-odroidx2.dts | 23 ++
5 files changed, 89 insertions(+), 368 deletions(-)
copy arch/arm/boot/dts/{exynos4412-odroidx.dts =
exynos4412-odroid-common.dtsi} (86%)
create mode 100644 arch/arm/boot/dts/exynos4412-odroidu3.dts
create mode 100644 arch/arm/boot/dts/exynos4412-odroidx2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index adb5ed9e269e..ed2f4e115134 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -66,7 +66,9 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
+ exynos4412-odroidu3.dtb \
exynos4412-odroidx.dtb \
+ exynos4412-odroidx2.dtb \
exynos4412-origen.dtb \
exynos4412-smdk4412.dtb \
exynos4412-tiny4412.dtb \
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
similarity index 86%
copy from arch/arm/boot/dts/exynos4412-odroidx.dts
copy to arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index bcf331543fb0..f793f3b8f0b9 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -1,48 +1,20 @@
/*
- * Hardkernel's Exynos4412 based ODROID-X board device tree source
- *
- * Copyright (c) 2012 Dongjin Kim tobet...@gmail.com
- *
- * Device tree source file for Hardkernel's ODROID-X board which is based on
- * Samsung's Exynos4412 SoC.
+ * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
+ * device tree source
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-/dts-v1/;
#include exynos4412.dtsi
/ {
- model = Hardkernel ODROID-X board based on Exynos4412;
- compatible = hardkernel,odroid-x, samsung,exynos4412,
samsung,exynos4;
-
- memory {
- reg = 0x4000 0x3FF0;
- };
-
firmware@0204F000 {
compatible = samsung,secure-firmware;
reg = 0x0204F000 0x1000;
};
- leds {
- compatible = gpio-leds;
- led1 {
- label = led1:heart;
- gpios = gpc1 0 1;
- default-state = on;
- linux,default-trigger = heartbeat;
- };
- led2 {
- label = led2:mmc0;
- gpios = gpc1 2 1;
- default-state = on;
- linux,default-trigger = mmc0;
- };
- };
-
mmc@1255 {
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
@@ -63,16 +35,6 @@
};
};
- regulator_p3v3 {
- compatible = regulator-fixed;
- regulator-name = p3v3_en;
- regulator-min-microvolt = 330;
- regulator-max-microvolt = 330;
- gpio = gpa1 1 1;
- enable-active-high;
- regulator-boot-on;
- };
-
watchdog@1006 {
status = okay;
};
@@ -123,14 +85,6 @@
status = okay;
};
- serial@1382 {
- status = okay;
- };
-
- serial@1383 {
- status = okay;
- };
-
fixed-rate-clocks {
xxti {
compatible = samsung,clock-xxti;
@@ -148,7 +102,7 @@
pinctrl-names = default;
status = okay;
- usb3503@08 {
+ usb3503: usb3503@08 {
compatible = smsc,usb3503;
reg = 0x08;
@@ -359,10 +313,7 @@
vusb_a-supply = ldo12_reg;
};
- ehci@1258 {
+ ehci: ehci@1258 {
status = okay;
- port@1 {
- status = okay;
- };
};
};
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts
b/arch/arm/boot/dts/exynos4412-odroidu3.dts
new file mode 100644
index
[PATCH v3 4/8] ARM: dts: exynos4412-odroidx: correct memory size
Last megabyte of RAM is used by secure firmware and should not be accessed
by Linux kernel, so correct available memory size in DTS file.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 4c853fbf7202..bcf331543fb0 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -19,7 +19,7 @@
compatible = hardkernel,odroid-x, samsung,exynos4412,
samsung,exynos4;
memory {
- reg = 0x4000 0x4000;
+ reg = 0x4000 0x3FF0;
};
firmware@0204F000 {
--
1.9.2
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[PATCH v3 3/8] ARM: dts: exynos4412-odroidx: add support for USB (phy, host, device)
From: Kamil Debski k.deb...@samsung.com
This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: Kamil Debski k.deb...@samsung.com
[removed incorrect port@2 node]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index fda9ac23dd55..4c853fbf7202 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -148,6 +148,16 @@
pinctrl-names = default;
status = okay;
+ usb3503@08 {
+ compatible = smsc,usb3503;
+ reg = 0x08;
+
+ intn-gpios = gpx3 0 0;
+ connect-gpios = gpx3 4 0;
+ reset-gpios = gpx3 5 0;
+ initial-mode = 1;
+ };
+
max77686: pmic@09 {
compatible = maxim,max77686;
reg = 0x09;
@@ -338,4 +348,21 @@
};
};
};
+
+ exynos-usbphy@125B {
+ status = okay;
+ };
+
+ hsotg@1248 {
+ status = okay;
+ vusb_d-supply = ldo15_reg;
+ vusb_a-supply = ldo12_reg;
+ };
+
+ ehci@1258 {
+ status = okay;
+ port@1 {
+ status = okay;
+ };
+ };
};
--
1.9.2
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[PATCH v3 2/4] usb: host: xhci-plat: Get PHYs for xhci's hcds
The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore, facilitate getting the two possible PHYs, viz.
USB 2.0 type (UTMI+) and USB 3.0 type (PIPE3).
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/xhci-plat.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 1a0cf9f..d097d60 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -16,6 +16,7 @@
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/phy/phy.h
#include linux/slab.h
#include linux/usb/xhci_pdriver.h
@@ -180,6 +181,14 @@ static int xhci_plat_probe(struct platform_device *pdev)
goto put_hcd;
}
+ /* Get possile USB 2.0 type PHY (UTMI+) available with xhci */
+ hcd-gen_phy = devm_phy_get(pdev-dev, usb2-phy);
+ if (IS_ERR(hcd-gen_phy)) {
+ ret = PTR_ERR(hcd-gen_phy);
+ if (ret != -ENOSYS ret != -ENODEV)
+ dev_dbg(pdev-dev, no usb2 phy configured\n);
+ }
+
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (ret)
goto disable_clk;
@@ -209,6 +218,14 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (HCC_MAX_PSA(xhci-hcc_params) = 4)
xhci-shared_hcd-can_do_streams = 1;
+ /* Get possile USB 3.0 type PHY (PIPE3) available with xhci */
+ xhci-shared_hcd-gen_phy = devm_phy_get(pdev-dev, usb3-phy);
+ if (IS_ERR(xhci-shared_hcd-gen_phy)) {
+ ret = PTR_ERR(xhci-shared_hcd-gen_phy);
+ if (ret != -ENOSYS ret != -ENODEV)
+ dev_dbg(pdev-dev, no usb3 phy configured\n);
+ }
+
ret = usb_add_hcd(xhci-shared_hcd, irq, IRQF_SHARED);
if (ret)
goto put_usb3_hcd;
--
1.7.10.4
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[PATCH v3 4/4] phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800
Adding phy calibrate callback, which facilitates setting certain
PHY settings post initialization of the PHY controller.
Exynos5420 and Exynos5800 have 28nm USB 3.0 DRD PHY for which
the Loss-of-Signal (LOS) Detector Threshold Level as well as
Tx-Vboost-Level should be controlled for Super-Speed operations.
Additionally set proper time to wait for RxDetect measurement,
for desired PHY reference clock, so as to solve issue with enumeration
of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive
on the controller.
We are using CR_port for this purpose to send required data
to override the LOS values.
On testing with USB 3.0 devices on USB 3.0 port present on
SMDK5420, and peach-pit boards should see following message:
usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
and without this patch, should see below shown message:
usb 1-1: new high-speed USB device number 2 using xhci-hcd
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 169 ++
1 file changed, 169 insertions(+)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index 56285af..30adbcb 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -89,8 +89,20 @@
#define PHYCLKRST_COMMONONNBIT(0)
#define EXYNOS5_DRD_PHYREG00x14
+
+#define EXYNOS5_DRD_PHYREG0_SSC_REF_CLK_SELBIT(21)
+#define EXYNOS5_DRD_PHYREG0_SSC_RANGE BIT(20)
+#define EXYNOS5_DRD_PHYREG0_CR_WRITE BIT(19)
+#define EXYNOS5_DRD_PHYREG0_CR_READBIT(18)
+#define EXYNOS5_DRD_PHYREG0_CR_DATA_IN(_x) ((_x) 2)
+#define EXYNOS5_DRD_PHYREG0_CR_CAP_DATABIT(1)
+#define EXYNOS5_DRD_PHYREG0_CR_CAP_ADDRBIT(0)
+
#define EXYNOS5_DRD_PHYREG10x18
+#define EXYNOS5_DRD_PHYREG1_CR_DATA_OUT(_x)((_x) 1)
+#define EXYNOS5_DRD_PHYREG1_CR_ACK BIT(0)
+
#define EXYNOS5_DRD_PHYPARAM0 0x1c
#define PHYPARAM0_REF_USE_PAD BIT(31)
@@ -118,6 +130,26 @@
#define EXYNOS5_DRD_PHYRESUME 0x34
#define EXYNOS5_DRD_LINKPORT 0x44
+/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
+#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15)
+
+#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 13)
+#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 13)
+#define LOSLEVEL_OVRD_IN_EN(0x1 10)
+#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 0)
+
+#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12)
+#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 13)
+#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 13)
+
+#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M(0x4 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5(0x20 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M(0x40 4)
+
#define KHZ1000
#define MHZ(KHZ * KHZ)
@@ -135,12 +167,14 @@ struct exynos5_usbdrd_phy_config {
void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
unsigned int (*set_refclk)(struct phy_usb_instance *inst);
+ int (*phy_calibrate)(struct phy_usb_instance *inst);
};
struct exynos5_usbdrd_phy_drvdata {
const struct exynos5_usbdrd_phy_config *phy_cfg;
u32 pmu_offset_usbdrd0_phy;
u32 pmu_offset_usbdrd1_phy;
+ void (*calibrate)(struct exynos5_usbdrd_phy *phy_drd);
};
/**
@@ -487,6 +521,138 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
return 0;
}
+static void crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
+ u32 val, u32 cmd)
+{
+ u32 usec = 100;
+ u32 result;
+
+ writel(val | cmd, phy_drd-reg_phy + EXYNOS5_DRD_PHYREG0);
+
+ do {
+ result = readl(phy_drd-reg_phy + EXYNOS5_DRD_PHYREG1);
+ if (result EXYNOS5_DRD_PHYREG1_CR_ACK)
+ break;
+
+ udelay(1);
+ } while (usec-- 0);
+
+ if (!usec)
+ dev_err(phy_drd-dev,
+ CRPORT handshake timeout1 (0x%08x)\n, val);
+
+ usec = 100;
+
+ writel(val, phy_drd-reg_phy + EXYNOS5_DRD_PHYREG0);
+
+ do {
+ result = readl(phy_drd-reg_phy + EXYNOS5_DRD_PHYREG1);
+ if (!(result EXYNOS5_DRD_PHYREG1_CR_ACK))
+ break;
+
+ udelay(1);
+ } while (usec-- 0);
+
+ if (!usec)
+ dev_err(phy_drd-dev,
+
[PATCH v3 3/4] usb: hcd: Caibrate PHY post hcd reset
Some quirky PHYs may require to be calibrated post the
hcd initialization.
The USB 3.0 DRD PHY on Exynos5420/5800 systems, coming along
with Synopsys's DWC3 controller, is one such PHY which needs
to be calibrated post xhci's reset at initialization time and
at resume time, to get the controller work at SuperSpeed.
So facilitating the HCDs to calibrate the PHY.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/core/hcd.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 2841149..a344b76 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -2206,6 +2206,7 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t
msg)
struct usb_hcd *hcd = container_of(rhdev-bus, struct usb_hcd, self);
int status;
int old_state = hcd-state;
+ int ret;
dev_dbg(rhdev-dev, usb %sresume\n,
(PMSG_IS_AUTO(msg) ? auto- : ));
@@ -2220,6 +2221,17 @@ int hcd_bus_resume(struct usb_device *rhdev,
pm_message_t msg)
hcd-state = HC_STATE_RESUMING;
status = hcd-driver-bus_resume(hcd);
+
+ /* calibrate the phy here */
+ if (!IS_ERR(hcd-gen_phy)) {
+ ret = phy_calibrate(hcd-gen_phy);
+ if (ret 0 ret != -ENOTSUPP) {
+ dev_err(hcd-self.controller,
+ failed to calibrate USB PHY\n);
+ return ret;
+ }
+ }
+
clear_bit(HCD_FLAG_WAKEUP_PENDING, hcd-flags);
if (status == 0) {
struct usb_device *udev;
@@ -2742,6 +2754,16 @@ int usb_add_hcd(struct usb_hcd *hcd,
}
hcd-rh_pollable = 1;
+ /* calibrate the phy here */
+ if (!IS_ERR(hcd-gen_phy)) {
+ retval = phy_calibrate(hcd-gen_phy);
+ if (retval 0 retval != -ENOTSUPP) {
+ dev_err(hcd-self.controller,
+ failed to calibrate USB PHY\n);
+ return retval;
+ }
+ }
+
/* NOTE: root hub and controller capabilities may not be the same */
if (device_can_wakeup(hcd-self.controller)
device_can_wakeup(hcd-self.root_hub-dev))
--
1.7.10.4
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[PATCH v3 0/4] Fine tune USB 3.0 PHY on exynos5420
This series is based on Heikki's patches for simpliefied phy lookup table: [PATCHv2 0/6] phy: simplified phy lookup [1], applied against 'next' branch of Kishon's linux-phy tree. Changes since v2: 1) Removed any check for DWC3 in xhci-plat for getting usb2-phy and usb3-phy, in order to make it more generic. 2) Moved the phy_calibration calls to core/hcd.c to enable a more generic solution for issues of calibrating the PHYs. Changes since v1: 1) Using 'gen_phy' member of 'hcd' instead of declaring more variables to hold phys. 2) Added a check for compatible match for 'Synopsys-dwc3' controller, since the 'gen_phy' member of 'hcd' already gets the 'usb' PHY in core/hcd.c; but XHCI on Synopsys-dwc3 doesn't need that, instead two separate PHYs for UTMI+ and PIPE3 for the two HCDs (main hcd and shared hcd). 3) Restructured the code in 'xhci_plat_setup()' and 'xhci_plat_resume()' to use hcd-gen_phy directly. Also added the check for Synopsys's DWC3 controller while trying to calibrate the PHY. Explanation for the need of this patch-series: The DWC3-exynos eXtensible host controller present on Exynos5420/5800 SoCs is quirky. The PHY serving this controller operates at High-Speed by default, so it detects even Super-speed devices as high-speed ones. Certain PHY parameters like Tx LOS levels and Boost levels need to be calibrated further post initialization of xHCI controller, to get SuperSpeed operations working. [1] https://lkml.org/lkml/2014/6/5/358 Vivek Gautam (4): phy: Add provision for calibrating phy. usb: host: xhci-plat: Get PHYs for xhci's hcds usb: hcd: Caibrate PHY post hcd reset phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800 drivers/phy/phy-core.c | 36 drivers/phy/phy-exynos5-usbdrd.c | 169 ++ drivers/usb/core/hcd.c | 22 + drivers/usb/host/xhci-plat.c | 17 include/linux/phy/phy.h |8 ++ 5 files changed, 252 insertions(+) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/4] phy: Add provision for calibrating phy.
Some PHY controllers may need to calibrate certain
PHY settings after initialization of the controller and
sometimes even after initializing the PHY-consumer too.
Add support for the same in order to let consumers do so in need.
Signed-off-by: vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-core.c | 36
include/linux/phy/phy.h |8
2 files changed, 44 insertions(+)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 0f35f7e..7c5f6cc 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -376,6 +376,42 @@ int phy_power_off(struct phy *phy)
EXPORT_SYMBOL_GPL(phy_power_off);
/**
+ * phy_calibrate - calibrate a phy post initialization
+ * @phy: Pointer to 'phy' from consumer
+ *
+ * For certain PHYs, it may be needed to calibrate few phy parameters
+ * post initialization. The need to calibrate may arise after the
+ * initialization of consumer itself, in order to prevent further any
+ * loss of phy settings post consumer-initialization.
+ * example: USB 3.0 DRD PHY on Exynos5420/5800 systems is one such
+ * phy which needs calibration after the host controller reset
+ * has happened.
+ */
+int phy_calibrate(struct phy *phy)
+{
+ int ret = -ENOTSUPP;
+
+ if (!phy)
+ return 0;
+
+ mutex_lock(phy-mutex);
+ if (phy-ops-calibrate) {
+ ret = phy-ops-calibrate(phy);
+ if (ret 0) {
+ dev_err(phy-dev,
+ phy calibration failed -- %d\n, ret);
+ goto out;
+ }
+ }
+
+out:
+ mutex_unlock(phy-mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_calibrate);
+
+/**
* _of_phy_get() - lookup and obtain a reference to a phy by phandle
* @np: device_node for which to get the phy
* @index: the index of the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 5a537a5..b7f33ee 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -27,6 +27,7 @@ struct phy;
* @exit: operation to be performed while exiting
* @power_on: powering on the phy
* @power_off: powering off the phy
+ * @calibrate: calibrate the phy post init
* @owner: the module owner containing the ops
*/
struct phy_ops {
@@ -34,6 +35,7 @@ struct phy_ops {
int (*exit)(struct phy *phy);
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
+ int (*calibrate)(struct phy *phy);
struct module *owner;
};
@@ -124,6 +126,7 @@ int phy_init(struct phy *phy);
int phy_exit(struct phy *phy);
int phy_power_on(struct phy *phy);
int phy_power_off(struct phy *phy);
+int phy_calibrate(struct phy *phy);
static inline int phy_get_bus_width(struct phy *phy)
{
return phy-attrs.bus_width;
@@ -227,6 +230,11 @@ static inline int phy_power_off(struct phy *phy)
return -ENOSYS;
}
+static inline int phy_calibrate(struct phy *phy)
+{
+ return -ENOSYS;
+}
+
static inline int phy_get_bus_width(struct phy *phy)
{
return -ENOSYS;
--
1.7.10.4
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Re: [PATCH] ARM: EXYNOS: Fix MCPM build with SUSPEND=n
On pon, 2014-07-14 at 07:35 -0400, Nicolas Pitre wrote: On Mon, 14 Jul 2014, Krzysztof Kozlowski wrote: Building of EXYNOS5420_MCPM with disabled SUSPEND fails: arch/arm/mach-exynos/built-in.o: In function `exynos_mcpm_init': arch/arm/mach-exynos/mcpm-exynos.c:361: undefined reference to `mcpm_loopback' The exynos_mcpm_init() in mcp-exynos.c calls mcpm_loopback() which depends on cpu_suspend function (ARM_CPU_SUSPEND). Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Cc: sta...@vger.kernel.org No need to CC stable here as this code has not reached a released kernel yet. Fixes: a6a4d3152e3cbb6 (ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster using the MCPM loopback) And this is not clear yet if this commit ID is stable. Other than that: Acked-by: Nicolas Pitre n...@linaro.org Please send to RMK's patch system. Sure, I'll remove the cc-stable tag, add your ack and send to the patch system. Thanks, Krzysztof --- arch/arm/mach-exynos/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8f9b66c4ac78..5d4ff6571dcd 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -119,6 +119,7 @@ config EXYNOS5420_MCPM bool Exynos5420 Multi-Cluster PM support depends on MCPM SOC_EXYNOS5420 select ARM_CCI + select ARM_CPU_SUSPEND help This is needed to provide CPU and cluster power management on Exynos5420 implementing big.LITTLE. -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v6: - Fixes suggested by Amit Daniel amit.dan...@samsung.com. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: register exynos5420 apll/kpll configuration data clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support arch/arm/boot/dts/exynos4210-origen.dts |6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts |6 + arch/arm/boot/dts/exynos4210.dtsi | 27 ++ arch/arm/boot/dts/exynos5250-arndale.dts|6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 23 + arch/arm/boot/dts/exynos5420-smdk5420.dts |6 + arch/arm/boot/dts/exynos5420.dtsi | 32 ++ arch/arm/mach-exynos/exynos.c | 15 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 576 +++ drivers/clk/samsung/clk-exynos4.c | 25 +- drivers/clk/samsung/clk-exynos5250.c| 16 +- drivers/clk/samsung/clk-exynos5420.c| 60 ++- drivers/clk/samsung/clk.h |5 + drivers/cpufreq/Kconfig.arm | 22 - drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 drivers/cpufreq/exynos5250-cpufreq.c| 210 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 23 files changed, 802 insertions(+), 442 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
From: Thomas Abraham thomas...@samsung.com
For Exynos 4210/5250/5420 based platforms, add CPU nodes, operating points and
cpu clock data for migrating from Exynos specific cpufreq driver to using
generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6
arch/arm/boot/dts/exynos4210-trats.dts |6
arch/arm/boot/dts/exynos4210-universal_c210.dts |6
arch/arm/boot/dts/exynos4210.dtsi | 27
arch/arm/boot/dts/exynos5250-arndale.dts|6
arch/arm/boot/dts/exynos5250-cros-common.dtsi |6
arch/arm/boot/dts/exynos5250-smdk5250.dts |6
arch/arm/boot/dts/exynos5250.dtsi | 23 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts |6
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
10 files changed, 130 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..49a97fc 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -33,6 +33,12 @@
bootargs =root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC2,115200 init=/linuxrc;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck1_reg;
+ };
+ };
+
regulators {
compatible = simple-bus;
#address-cells = 1;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..fe32b6a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,6 +30,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5
rootwait earlyprintk panic=5;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = varm_breg;
+ };
+ };
+
regulators {
compatible = simple-bus;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..8ab12d6 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw
rootwait earlyprintk panic=5 maxcpus=1;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = vdd_arm_reg;
+ };
+ };
+
sysram@0202 {
smp-sysram@0 {
status = disabled;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..c3a73bf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,33 @@
pinctrl2 = pinctrl_2;
};
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
+ };
+ };
+
sysram@0202 {
compatible = mmio-sram;
reg = 0x0202 0x2;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..d9b803b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -26,6 +26,12 @@
bootargs = console=ttySAC2,115200;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
rtc@101E {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@
chosen {
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+
[PATCH v7 3/6] clk: exynos: use cpu-clock provider type to represent arm clock
From: Thomas Abraham thomas...@samsung.com
Register cpu clocks using the new cpu-clock provider type for exynos platforms.
The differnt clock blocks that are now encapsulated within the cpu-clock can be
marked with read-only attribute.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 25 +
drivers/clk/samsung/clk-exynos5250.c | 16 +++-
drivers/clk/samsung/clk-exynos5420.c | 32 +++-
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 ++
5 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 75573a4..10f1818 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -471,7 +471,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4210, SRC_CAM, 4, 4),
@@ -530,7 +531,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
MUX(0, mout_jpeg, mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_DMC, 12, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, mout_vpll_p, SRC_TOP0, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4x12, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4x12, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, mout_fimc2, group1_p4x12, SRC_CAM, 8, 4),
@@ -572,8 +574,10 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_core2, div_core, DIV_CPU0, 28, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
DIV(0, div_fimc1, mout_fimc1, DIV_CAM, 4, 4),
DIV(0, div_fimc2, mout_fimc2, DIV_CAM, 8, 4),
@@ -619,8 +623,10 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1016,7 +1022,6 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
static struct samsung_clock_alias exynos4_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
- ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
};
@@ -1255,6 +1260,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_gate_clks));
samsung_clk_register_alias(ctx, exynos4210_aliases,
ARRAY_SIZE(exynos4210_aliases));
+ exynos_register_cpu_clock(ctx, 0, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], np);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1264,6 +1271,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4x12_gate_clks));
samsung_clk_register_alias(ctx,
[PATCH v7 1/6] clk: samsung: add infrastructure to register cpu clocks
From: Thomas Abraham thomas...@samsung.com
This patch defines a new clock type for CPU clock provider and adds
infrastructure to register the CPU clock providers for Samsung platforms.
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs and so this new clock type provides a way to encapsulate these
blocks into CPU clock type.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 576 +
drivers/clk/samsung/clk.h |5 +
3 files changed, 582 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 69e8177..f4edd31 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..0d62968
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the CPU clocks
+ * for Samsung platforms.
+*/
+
+#include linux/errno.h
+#include clk.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK((0x7 4) | (0x7 0))
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)\
+ (((apll) 24) | ((pclk_dbg) 20) | ((atb) 16) | \
+ ((periph) 12) | ((corem1) 8) | ((corem0) 4))
+#define E4210_CPU_DIV1(hpm, copy) \
+ (((hpm) 4) | ((copy) 0))
+
+#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+(periph 12) | (acp 8) | (cpud 4)))
+#define E5250_CPU_DIV1(hpm, copy) \
+ (((hpm) 4) | (copy))
+
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+(cpud 4)))
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ (((kpll 24) | (pclk 20) | (aclk 4)))
+
+enum cpuclk_type {
+ EXYNOS4210,
+ EXYNOS5250,
+ EXYNOS5420,
+};
+
+/**
+ * struct exynos4210_cpuclk_data: config data to setup cpu clocks.
+ * @prate: frequency of the primary parent clock (in KHz).
+ * @div0: value to be programmed in the div_cpu0 register.
+ * @div1: value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for dividers in the CPU
+ * clock domain. The parent frequency at which these divider values are valid
is
+ * specified in @prate. The @prate is the frequency of the primary parent
clock.
+ * For CPU clock domains that do not have a DIV1 register, the @div1 member
+ * is optional.
+ */
+struct exynos4210_cpuclk_data {
+ unsigned long prate;
+ unsigned intdiv0;
+ unsigned intdiv1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw:handle between CCF and CPU clock.
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @offset: offset from the ctrl_base address where the CPU clock div/mux
+ * registers can be accessed.
+ * @lock: cpu clock domain register access lock.
+ * @type: type of the CPU clock.
+ * @data: optional data which the actual instantiation of this clock
+ * can use.
+ * @clk_nb: clock
[PATCH v7 6/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
From: Thomas Abraham thomas...@samsung.com
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 22
drivers/cpufreq/Makefile |2 -
drivers/cpufreq/exynos4210-cpufreq.c | 184 -
drivers/cpufreq/exynos5250-cpufreq.c | 210 --
4 files changed, 418 deletions(-)
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index ebac671..7a2f289 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
-config ARM_EXYNOS4210_CPUFREQ
- bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS4210
- SoC (S5PV310 or S5PC210).
-
- If in doubt, say N.
-
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
If in doubt, say N.
-config ARM_EXYNOS5250_CPUFREQ
- bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS5250
- SoC.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
bool SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..fac36ef 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
deleted file mode 100644
index 61a5431..000
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/module.h
-#include linux/kernel.h
-#include linux/err.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/slab.h
-#include linux/cpufreq.h
-#include linux/of.h
-#include linux/of_address.h
-
-#include exynos-cpufreq.h
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
- 125, 115, 105, 975000, 95,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {0, L0, 1200 * 1000},
- {0, L1, 1000 * 1000},
- {0, L2, 800 * 1000},
- {0, L3, 500 * 1000},
- {0, L4, 200 * 1000},
- {0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
- /*
-* values:
-* freq
-* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL,
RESERVED
-* clock divider for COPY, HPM, RESERVED
-* PLL M, P, S
-*/
- APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
- APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
- APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
- APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
- APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
- __raw_writel(tmp, cpufreq-cmu_regs + EXYNOS4_CLKDIV_CPU);
-
- do {
[PATCH v7 5/6] ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250/5420
From: Thomas Abraham thomas...@samsung.com
Remove the platform device instantiation for exynos cpufreq driver and add the
platform device for generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 2a43a17..5028b35 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -183,7 +183,20 @@ void __init exynos_cpuidle_init(void)
void __init exynos_cpufreq_init(void)
{
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ char *dev_name;
+
+ if (of_machine_is_compatible(samsung,exynos5440))
+ return;
+ if (of_machine_is_compatible(samsung,exynos5420))
+ dev_name = arm-bL-cpufreq-dt;
+ else
+ if (of_machine_is_compatible(samsung,exynos4412) ||
+ of_machine_is_compatible(samsung,exynos4212))
+ dev_name = exynos-cpufreq;
+ else
+ dev_name = cpufreq-cpu0;
+
+ platform_device_register_simple(dev_name, -1, NULL, 0);
}
void __iomem *sysram_base_addr;
--
1.7.9.5
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[PATCH v7 2/6] clk: samsung: register exynos5420 apll/kpll configuration data
From: Thomas Abraham thomas...@samsung.com
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index cc14ac8..95f83be 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1169,6 +1169,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[]
__initdata = {
GATE(CLK_G3D, g3d, mout_user_aclk_g3d, GATE_IP_G3D, 9, 0, 0),
};
+static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(19, 475, 6, 0),
+ PLL_35XX_RATE(18, 225, 3, 0),
+ PLL_35XX_RATE(17, 425, 6, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, fout_apll, fin_pll, APLL_LOCK,
APLL_CON0, NULL),
@@ -1222,6 +1244,12 @@ static void __init exynos5x_clk_init(struct device_node
*np,
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
ext_clk_match);
+
+ if (_get_rate(fin_pll) == 24 * MHZ) {
+ exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ }
+
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
reg_base);
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
--
1.7.9.5
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[PATCH 0/2] ARM: EXYNOS: Fix builds with PM_SLEEP=n
Hi, This patch series fixes builds with CONFIG_PM_SLEEP config option disabled. They are on top of: - next-20140714 + - [PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequencies + (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html) - [PATCH v2] ARM: EXYNOS: Fix build with PM_SLEEP=n (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34007.html) Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (2): ARM: EXYNOS: Fix build with PM_SLEEP=n part #2 ARM: EXYNOS: Fix build with PM_SLEEP=n and ARM_EXYNOS_CPUIDLE=y arch/arm/mach-exynos/Kconfig | 5 + arch/arm/mach-exynos/Makefile | 3 +- arch/arm/mach-exynos/common.h | 7 ++ arch/arm/mach-exynos/exynos.c | 2 + arch/arm/mach-exynos/pm.c | 178 +--- arch/arm/mach-exynos/suspend.c | 203 + arch/arm/plat-samsung/Makefile | 1 + 7 files changed, 224 insertions(+), 175 deletions(-) create mode 100644 arch/arm/mach-exynos/suspend.c -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: EXYNOS: Fix build with PM_SLEEP=n part #2
Fix building of exynos_defconfig with disabled CONFIG_PM_SLEEP by
adding checking whether Exynos cpuidle support is enabled before
accessing exynos_enter_aftr.
The build error message:
arch/arm/mach-exynos/built-in.o:(.data+0x74): undefined reference to
`exynos_enter_aftr'
make: *** [vmlinux] Error 1
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 2a43a17..769cecb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -171,7 +171,9 @@ static void exynos_restart(enum reboot_mode mode, const
char *cmd)
static struct platform_device exynos_cpuidle = {
.name = exynos_cpuidle,
+#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
.dev.platform_data = exynos_enter_aftr,
+#endif
.id= -1,
};
--
1.8.2.3
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[PATCH 2/2] ARM: EXYNOS: Fix build with PM_SLEEP=n and ARM_EXYNOS_CPUIDLE=y
Fix building of exynos_defconfig with CONFIG_PM_SLEEP disabled and
CONFIG_ARM_EXYNOS_CPUIDLE enabled by:
* adding EXYNOS_CPU_SUSPEND config option
* building pm.o and sleep.o if EXYNOS_CPU_SUSPEND is enabled
* moving suspend specific code from pm.c to suspend.c
* enabling pm-common.o build also for EXYNOS_CPU_SUSPEND option
The build error messages:
drivers/built-in.o: In function `exynos_enter_core0_aftr':
/home/bzolnier/linux/drivers/cpuidle/cpuidle-exynos.c:36: undefined reference
to `cpu_suspend'
arch/arm/mach-exynos/built-in.o:(.data+0x74): undefined reference to
`exynos_enter_aftr'
make: *** [vmlinux] Error 1
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 5 +
arch/arm/mach-exynos/Makefile | 3 +-
arch/arm/mach-exynos/common.h | 7 ++
arch/arm/mach-exynos/pm.c | 178 +---
arch/arm/mach-exynos/suspend.c | 203 +
arch/arm/plat-samsung/Makefile | 1 +
6 files changed, 222 insertions(+), 175 deletions(-)
create mode 100644 arch/arm/mach-exynos/suspend.c
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8f9b66c..e42e725 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -123,4 +123,9 @@ config EXYNOS5420_MCPM
This is needed to provide CPU and cluster power management
on Exynos5420 implementing big.LITTLE.
+config EXYNOS_CPU_SUSPEND
+ bool
+ select ARM_CPU_SUSPEND
+ default PM_SLEEP || ARM_EXYNOS_CPUIDLE
+
endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 788f26d..b78980f 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -16,7 +16,8 @@ obj- :=
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o
-obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
+obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_PM_SLEEP) += suspend.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9c..780d53b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -121,6 +121,12 @@ void exynos_firmware_init(void);
extern u32 exynos_get_eint_wake_mask(void);
#ifdef CONFIG_PM_SLEEP
+extern void __init exynos_pm_suspend_init(void);
+#else
+static inline void exynos_pm_suspend_init(void) {}
+#endif
+
+#ifdef CONFIG_EXYNOS_CPU_SUSPEND
extern void __init exynos_pm_init(void);
#else
static inline void exynos_pm_init(void) {}
@@ -155,6 +161,7 @@ extern int exynos_cpu_power_state(int cpu);
extern void exynos_cluster_power_down(int cluster);
extern void exynos_cluster_power_up(int cluster);
extern int exynos_cluster_power_state(int cluster);
+extern void exynos_pm_do_save(void);
extern void exynos_enter_aftr(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 6581d15..4198c4b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - Power Management support
@@ -14,39 +14,19 @@
*/
#include linux/init.h
-#include linux/suspend.h
-#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
-#include linux/irqchip/arm-gic.h
#include linux/err.h
-#include linux/clk.h
-#include asm/cacheflush.h
-#include asm/hardware/cache-l2x0.h
#include asm/smp_scu.h
-#include asm/suspend.h
#include plat/pm-common.h
-#include plat/pll.h
#include plat/regs-srom.h
-#include mach/map.h
-
#include common.h
#include regs-pmu.h
#include regs-sys.h
-/**
- * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
- * @hwirq: Hardware IRQ signal of the GIC
- * @mask: Mask in PMU wake-up mask register
- */
-struct exynos_wkup_irq {
- unsigned int hwirq;
- u32 mask;
-};
-
static struct sleep_save exynos5_sys_save[] = {
SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
};
@@ -60,47 +40,6 @@ static struct sleep_save exynos_core_save[] = {
SAVE_ITEM(S5P_SROM_BC3),
};
-/*
- * GIC wake-up support
- */
-
-static u32 exynos_irqwake_intmask = 0x;
-
-static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
- { 76, BIT(1) }, /* RTC alarm */
- { 77, BIT(2) }, /* RTC tick */
- { /* sentinel */ },
-};
-
-static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
- { 75, BIT(1) }, /* RTC alarm */
- { 76, BIT(2) }, /* RTC tick */
- { /* sentinel */ },
-};
-
-static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
-{
- const struct exynos_wkup_irq *wkup_irq;
-
- if
[PATCH] ARM: dts: Add sound nodes for Odroid-X2/U3 boards
Add MAX98090 audio codec, I2S interface and the sound complex
nodes to enable audio on Odroid-X2/U3 boards.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
This patch depends on the series from Marek [1] adding dt sources
for Odroid X2/U3. My testing branch can be pulled from [2].
[1] http://www.spinics.net/lists/linux-samsung-soc/msg32544.html
[2] git://linuxtv.org/snawrocki/samsung.git v3.16-rc5-odroid-sound
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 27 +++
arch/arm/boot/dts/exynos4412-odroidu3.dts | 12 ++
arch/arm/boot/dts/exynos4412-odroidx2.dts |9
3 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 0bc1a9b..6d6d23c 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -32,6 +32,21 @@
};
};
+ i2s0: i2s@0383 {
+ pinctrl-0 = i2s0_bus;
+ pinctrl-names = default;
+ status = okay;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+clock_audss EXYNOS_DOUT_AUD_BUS;
+ clock-names = iis, i2s_opclk0;
+ };
+
+ sound: sound {
+ compatible = samsung,odroidx2-audio;
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = max98090;
+ };
+
mmc@1255 {
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
@@ -321,6 +336,18 @@
};
};
+ i2c@1387 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_bus;
+ status = okay;
+ max98090: max98090@10 {
+ compatible = maxim,max98090;
+ reg = 0x10;
+ interrupt-parent = gpx0;
+ interrupts = 0 0;
+ };
+ };
+
exynos-usbphy@125B {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts
b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index 287aa0d..c8a64be 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -47,3 +47,15 @@
status = okay;
};
};
+
+sound {
+ compatible = samsung,odroidu3-audio;
+ samsung,model = Odroid-U3;
+ samsung,audio-routing =
+ Headphone Jack, HPL,
+ Headphone Jack, HPR,
+ Headphone Jack, MICBIAS,
+ IN1, Headphone Jack,
+ Speakers, SPKL,
+ Speakers, SPKR;
+};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts
b/arch/arm/boot/dts/exynos4412-odroidx2.dts
index e9ae161..96b43f4 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx2.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts
@@ -21,3 +21,12 @@
reg = 0x4000 0x7FF0;
};
};
+
+sound {
+ samsung,model = Odroid-X2;
+ samsung,audio-routing =
+ Headphone Jack, HPL,
+ Headphone Jack, HPR,
+ IN1, Mic Jack,
+ Mic Jack, MICBIAS;
+};
--
1.7.9.5
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Re: [alsa-devel] [PATCH V3 2/2] ASoC: samsung: Add machine driver for Odroid X2/U3
On Thu, Jul 10, 2014 at 5:15 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: On 08/07/14 11:15, Daniel Drake wrote: Testing on ODROID-U2, v3 is not quite working for me, but v2 of the patch was fine. I boot up, run: # speaker-test -c 2 -t wav As soon as I hear the word front I press ctrl+c and then run the command again. Now the command hangs with no audible output. Any ideas? Let me know if you have trouble reproducing. I just posted a patch addressing this, please let me know if there are any further issues. Sorry for not testing sooner. Your patch solves the issue. Thanks Daniel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 3/3] clk: exynos-audss: Use samsung clock APIs to register/unregister clocks
On 11/07/14 14:00, Tushar Behera wrote:
@@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct
platform_device *pdev)
return PTR_ERR(reg_base);
}
- clk_table = devm_kzalloc(pdev-dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
+ ctx = samsung_clk_init(pdev-dev.of_node, reg_base, nr_clks);
There is an issue here that this registers the clk provider before all
its clocks are registered with the clk core. Therefore it introduces
a race condition.
Please have a look at patch [1], you may want to rebase this series
onto that patch.
+ samsung_clk_register_div(ctx, exynos_audss_div_clks,
+ ARRAY_SIZE(exynos_audss_div_clks));
[...]
+ samsung_clk_register_gate(ctx, exynos_audss_gate_clks,
+ ARRAY_SIZE(exynos_audss_gate_clks));
[...]
- ret = of_clk_add_provider(pdev-dev.of_node, of_clk_src_onecell_get,
- clk_data);
- if (ret) {
- dev_err(pdev-dev, failed to add clock provider\n);
- goto unregister;
+ samsung_clk_register_gate(ctx, exynos5420_audss_gate_clks,
+ ARRAY_SIZE(exynos5420_audss_gate_clks));
}
[1]
https://git.kernel.org/cgit/linux/kernel/git/tfiga/samsung-clk.git/commit/?h=samsung-clk-nextid=d5e136a21b2028fb1f45143ea7112d5869bfc6c7
--
Regards,
Sylwester
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Re: [PATCH v3 0/4] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled
Hi Bartlomiej, On Wed, Jul 9, 2014 at 6:17 PM, Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com wrote: This patch series adds support for AFTR idle mode on boards with secure firmware enabled and allows EXYNOS cpuidle driver usage on Exynos4x12 SoCs. It has been tested on Trats2 board (using Exynos4412 SoC with secure firmware enabled) on which AFTR mode reduces power consumption by ~12% when EXYNOS cpuidle driver is enabled (in both cases the default exynos_defconfig config is used and CPU1-3 are offlined). Thanks for this, I have tested it on ODROID-U2. I don't have any equipment to measure the power usage, but after offlining CPUs 1,2,3 via sysfs online file, a printk I added confirms that the system is going to enter aftr mode, and system stability seems as good as ever. Is there any automatic way that the cpus should be offlined, or is the intention that it must be done by hand like this? Thanks, Daniel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] cpuidle: big.LITTLE: add MCPM dependency
On Mon, 14 Jul 2014, Arnd Bergmann wrote: 662322fcb6d (cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config) made it possible for the big-little cpuidle driver to run on exynos, which may or may not include MCPM support at compile time, so we run into a link error when it is disabled: drivers/built-in.o: In function `bl_enter_powerdown': :(.text+0x1889a0): undefined reference to `mcpm_cpu_powered_up' drivers/built-in.o: In function `bl_powerdown_finisher': :(.text+0x1889e8): undefined reference to `mcpm_set_entry_vector' :(.text+0x1889ec): undefined reference to `mcpm_cpu_suspend' This adds an explicit dependency to CONFIG_MCPM to avoid that case. Signed-off-by: Arnd Bergmann a...@arndb.de Cc: Chander Kashyap chander.kash...@linaro.org Cc: Tomasz Figa t.f...@samsung.com Cc: Daniel Lezcano daniel.lezc...@linaro.org --- I believe the broken commit is only present in the samsung/for-next tree (through v3.17-next/cpuidle-exynos), so it should be fixed there. On a side note, I wonder if we should have platform dependencies at all, or just the MCPM dependency by itself. This was discussed in some other thread already but I'm too lazy to dig a reference to it. Only a dependency on MCPM alone is needed here. And then: Acked-by: Nicolas Pitre n...@linaro.org diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 2f6b33ea6e08..459b7c91407a 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -10,6 +10,7 @@ config ARM_ARMADA_370_XP_CPUIDLE config ARM_BIG_LITTLE_CPUIDLE bool Support for ARM big.LITTLE processors depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS + depends on MCPM select ARM_CPU_SUSPEND select CPU_IDLE_MULTIPLE_DRIVERS help ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] ARM: exynos_defconfig: Update exynos_defconfig
Sachin, On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat sachin.ka...@samsung.com wrote: Removed outdated configs. Enabled most of the configs used on latest Exynos based platforms. This will provide a reference for users trying to verify and test various features on Exynos based platforms and also help in detecting breakages by widening the build coverage. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com --- arch/arm/configs/exynos_defconfig | 56 +++-- 1 file changed, 48 insertions(+), 8 deletions(-) How about CONFIG_CPU_FREQ=y + related configs? I'm pretty sure that CPU_FREQ works on exynos5250-snow and the config didn't hurt last time I tried on exynos5420/5800. Once Javier's changes land we'll need to add max77802 in here, but it's fine to leave it out until then. I'd also wonder about CONFIG_DRM eventually being set for graphics, but I'll admit to very little knowledge there. That seems like it could be in a followup patch. I would strongly suggest PREMPT_VOLUNTARY=y for now (again in a separate patch). With your config and 'slub_debug=FZPUA' I continue to get constant errors reported. These errors are not your fault (they also show up on tegra boards). I've already reported this and it's pretty much gone nowhere. Another suggestion is to enable the WiFi that's on ARM Chromebooks: CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m ...and that probably means some WiFi configs. I'm not an expert, but possibly these. The first of these appears to be needed to keep shill (present in the default ChromeOS rootfilesystem) from crashing wildly: CONFIG_CFG80211=m CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m Possibly you should be enabling the battery eventually since Chromebooks have these too: CONFIG_BATTERY_SBS=m You're enabling the adc, but not what's hooked up to it: CONFIG_SENSORS_NTC_THERMISTOR=m The eMMC that ships on Chromebooks has more than 8 partitions, so you probably should have this: CONFIG_MMC_BLOCK_MINORS=16 There's a light sensor on most ARM Chromebooks: CONFIG_SENSORS_ISL29018=m All of the above could be in followup patches, so: Tested-by: Doug Anderson diand...@chromium.org Reviewed-by: Doug Anderson diand...@chromium.org diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e07a227ec0db..fc7d1683bf67 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -8,15 +8,17 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=3 -CONFIG_S3C24XX_PWM=y -CONFIG_ARCH_EXYNOS5=y -CONFIG_MACH_EXYNOS4_DT=y +CONFIG_ARCH_EXYNOS3=y +CONFIG_EXYNOS5420_MCPM=y CONFIG_SMP=y +CONFIG_BIG_LITTLE=y +CONFIG_BL_SWITCHER=y +CONFIG_BL_SWITCHER_DUMMY_IF=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y +CONFIG_CMA=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y @@ -24,6 +26,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE=root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M console=ttySAC1,115200 init=/linuxrc mem=256M CONFIG_VFP=y CONFIG_NEON=y +CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -34,6 +37,8 @@ CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_PROC_DEVICETREE=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y @@ -66,11 +71,22 @@ CONFIG_I2C=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_I2C_EXYNOS5=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SPI=y +CONFIG_SPI_S3C64XX=y CONFIG_I2C_S3C2410=y CONFIG_DEBUG_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_CHARGER_TPS65090=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_EXYNOS_THERMAL=y +CONFIG_EXYNOS_THERMAL_CORE=y +CONFIG_WATCHDOG=y +CONFIG_S3C2410_WATCHDOG=y CONFIG_MFD_CROS_EC=y CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_CROS_EC_SPI=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX8997=y CONFIG_MFD_SEC_CORE=y @@ -80,6 +96,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8997=y CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y @@ -88,28 +105,50 @@ CONFIG_FB_MODE_HELPERS=y CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y -CONFIG_EXYNOS_DP=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_7x14=y CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SNOW=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=y -CONFIG_USB_PHY=y -CONFIG_SAMSUNG_USB2PHY=y -CONFIG_SAMSUNG_USB3PHY=y +CONFIG_USB_HSIC_USB3503=y CONFIG_MMC=y
Re: [PATCH v2] ARM: dts: Add mask-tpm-reset to the device tree
Vikas, On Sun, Jul 13, 2014 at 11:33 PM, Vikas Sajjan vikas.saj...@samsung.com wrote: From: Doug Anderson diand...@chromium.org The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from being reset across sleep/wake. If we don't set it to anything then the TPM will be reset. U-Boot will detect this as invalid and will reset the system on resume time. This GPIO can always be low and not hurt anything. It will get pulled back high again during a normal warm reset when it will default back to an input. To properly preserve the TPM state across suspend/resume and to make the chrome U-Boot happy, properly set the GPIO to mask the reset to the TPM. Signed-off-by: Doug Anderson diand...@chromium.org Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com --- changes since v1: - removed fixed regulator and used hogs instead. arch/arm/boot/dts/exynos5420-peach-pit.dts | 12 1 file changed, 12 insertions(+) This looks reasonable to me except for two things: 1. You need to apply this to pit and pi (not just pi) 2. The proper sort ordering for elements within a pin control group is by pin number, so this pin should be _after_ gpx0-2, not before. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Add mask-tpm-reset to the device tree
Vikas, On Mon, Jul 14, 2014 at 10:00 AM, Doug Anderson diand...@chromium.org wrote: Vikas, On Sun, Jul 13, 2014 at 11:33 PM, Vikas Sajjan vikas.saj...@samsung.com wrote: From: Doug Anderson diand...@chromium.org The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from being reset across sleep/wake. If we don't set it to anything then the TPM will be reset. U-Boot will detect this as invalid and will reset the system on resume time. This GPIO can always be low and not hurt anything. It will get pulled back high again during a normal warm reset when it will default back to an input. To properly preserve the TPM state across suspend/resume and to make the chrome U-Boot happy, properly set the GPIO to mask the reset to the TPM. Signed-off-by: Doug Anderson diand...@chromium.org Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com --- changes since v1: - removed fixed regulator and used hogs instead. arch/arm/boot/dts/exynos5420-peach-pit.dts | 12 1 file changed, 12 insertions(+) This looks reasonable to me except for two things: 1. You need to apply this to pit and pi (not just pi) Sorry, just realized that you had two patches and they weren't just revisions (I got confused when one was v1 and one was v2). I would have just put them in the same patch, but two patches is OK. 2. The proper sort ordering for elements within a pin control group is by pin number, so this pin should be _after_ gpx0-2, not before. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 00/10] drm: exynos: few patches to enhance bridge chip support
Inki, You have acks, and you have the tested-bys you requested. Can you please pick this up quickly so that we can have graphics working with an upstream kernel on chromebooks? Dave, if Inki keeps dragging his feet like this can you please apply this series directly? These delays are ridiculous and it's hurting forward progress on the platform as a whole. Thanks, -Olof On Tue, Jul 8, 2014 at 11:11 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Daniel, Thierry and Rob, Currently, the following boards are working fine with the bridge chip series: - snow - spring - peach_pit - peach_pi And, I did change my original patchset based on your comments here: (1) [RFC V2 0/3] drm/bridge: panel and chaining http://www.spinics.net/lists/linux-samsung-soc/msg30160.html (2) [RFC V3 0/3] drm/bridge: panel and chaining http://www.spinics.net/lists/linux-samsung-soc/msg30507.html If you think this is not the right way of doing it, please come forward with more suggestions, or kindly ACK it. I am just wondering how long can I keep waiting for comments? Regards, Ajay -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v6] spi: s3c64xx: fix broken cs_gpios usage in the driver
On Mon, Jul 14, 2014 at 11:11:44AM +0530, Naveen Krishna Chatradhi wrote:
@@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
spi-controller_data = cs;
}
+ /* For the non-DT platforms derive chip selects from controller data */
+ if (!spi-dev.of_node)
+ spi-cs_gpio = cs-line;
+
if (IS_ERR_OR_NULL(cs)) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
return -ENODEV;
@@ -819,17 +811,16 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
if (!spi_get_ctldata(spi)) {
/* Request gpio only if cs line is asserted by gpio pins */
- if (sdd-cs_gpio) {
- err = gpio_request_one(cs-line, GPIOF_OUT_INIT_HIGH,
- dev_name(spi-dev));
+ if (gpio_is_valid(spi-cs_gpio)) {
As previously mentioned gpio_is_valid() is *not* a direct substitute for
checking if the boolean flag cs_gpio has been set since 0 is a valid
GPIO on at least some of these platforms and as discussed several times
already some of the SoCs require the use of the built in chip select.
In general it's quite hard to tie the description in the patch to the
code changes, not helped by the decision to do separate refactorings
like this conversion to gpio_is_valid() as part of the one patch. The
description of the patch now makes some statements about what the
problem that's intended to be fixed is but it still doesn't seem
entirely clear that everything has been thought through fully and tied
to the code.
The original code appears to be buggy which isn't helping anything but
it's hard to have confidence that this isn't going to break some other
use case that currently works given the lack of clarity and the number
of revisions that have been required so far.
I think some combination of smaller changes and a clearer working
through of the before and after states for both DT and non DT cases to
show that everything has been considered would help a lot. I may have
another stare at this but it's worrying how hard I'm needing to think.
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Re: [PATCH 17/17] ASoC: Samsung: remove s5pc100 related codes
On Tue, Jul 01, 2014 at 06:32:27AM +0900, Kukjin Kim wrote: This patch removes s5pc100 related codes in linux/platform_data/asoc-s3c.h. Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH v2 04/17] ASoC: samsung: no more support for S5P6440 and S5P6450 SoCs
On Thu, Jul 03, 2014 at 07:40:17AM +0900, Kukjin Kim wrote: This patch removes s5p64x0 related WM8580 because of removing support for s5p64x0 SoCs. Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH v3 2/4] usb: host: xhci-plat: Get PHYs for xhci's hcds
On Mon, Jul 14, 2014 at 5:49 AM, Vivek Gautam gautam.vi...@samsung.com wrote:
The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore, facilitate getting the two possible PHYs, viz.
USB 2.0 type (UTMI+) and USB 3.0 type (PIPE3).
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/xhci-plat.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 1a0cf9f..d097d60 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -16,6 +16,7 @@
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/phy/phy.h
#include linux/slab.h
#include linux/usb/xhci_pdriver.h
@@ -180,6 +181,14 @@ static int xhci_plat_probe(struct platform_device *pdev)
goto put_hcd;
}
+ /* Get possile USB 2.0 type PHY (UTMI+) available with xhci */
+ hcd-gen_phy = devm_phy_get(pdev-dev, usb2-phy);
+ if (IS_ERR(hcd-gen_phy)) {
+ ret = PTR_ERR(hcd-gen_phy);
+ if (ret != -ENOSYS ret != -ENODEV)
+ dev_dbg(pdev-dev, no usb2 phy configured\n);
nit: This message is not really accurate anymore, right? If there is
no phy configured, you get ENODEV and (correctly) skip the message
completely. What you probably want is dev_warn(..., error retrieving
usb2 phy: %d\n); or something like that.
+ }
+
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (ret)
goto disable_clk;
@@ -209,6 +218,14 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (HCC_MAX_PSA(xhci-hcc_params) = 4)
xhci-shared_hcd-can_do_streams = 1;
+ /* Get possile USB 3.0 type PHY (PIPE3) available with xhci */
+ xhci-shared_hcd-gen_phy = devm_phy_get(pdev-dev, usb3-phy);
+ if (IS_ERR(xhci-shared_hcd-gen_phy)) {
+ ret = PTR_ERR(xhci-shared_hcd-gen_phy);
+ if (ret != -ENOSYS ret != -ENODEV)
+ dev_dbg(pdev-dev, no usb3 phy configured\n);
+ }
+
ret = usb_add_hcd(xhci-shared_hcd, irq, IRQF_SHARED);
if (ret)
goto put_usb3_hcd;
--
1.7.10.4
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[PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..46e64cc 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,24 +15,4 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFGS3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3 (14) -#define S3C_CLKCON_PCLK_UART2 (13) -#define S3C_CLKCON_PCLK_UART1 (12) -#define S3C_CLKCON_PCLK_UART0 (11) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ +/#endif /* _PLAT_REGS_CLOCK_H */ -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
On 07/14/14 11:14, Nicholas Krause wrote: This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..46e64cc 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,24 +15,4 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x)(S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATES3C_CLKREG(0x34) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3(14) -#define S3C_CLKCON_PCLK_UART2(13) -#define S3C_CLKCON_PCLK_UART1(12) -#define S3C_CLKCON_PCLK_UART0(11) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ +/#endif /* _PLAT_REGS_CLOCK_H */ I don't know about the other changes, but that last line looks like an error. Did you build anything that #includes this header file? -- ~Randy -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
On 07/14/14 11:14, Nicholas Krause wrote: This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..46e64cc 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,24 +15,4 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x)(S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATES3C_CLKREG(0x34) There is another header file that uses the #define S3C_PCLK_GATE above. Deleting it here should be causing a problem here: ./arch/arm/mach-s3c64xx/include/mach/pm-core.h:24: u32 tmp = __raw_readl(S3 C_PCLK_GATE); ./arch/arm/mach-s3c64xx/include/mach/pm-core.h:37: __raw_writel(tmp, S3C_PC LK_GATE); Please check things like this in advance. -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3(14) used by pm-core.h -#define S3C_CLKCON_PCLK_UART2(13) used by pm-core.h -#define S3C_CLKCON_PCLK_UART1(12) used by pm-core.h -#define S3C_CLKCON_PCLK_UART0(11) used by pm-core.h - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ +/#endif /* _PLAT_REGS_CLOCK_H */ -- ~Randy -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
On Mon, 2014-07-14 at 11:23 -0700, Randy Dunlap wrote: On 07/14/14 11:14, Nicholas Krause wrote: This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..46e64cc 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,24 +15,4 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFGS3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3 (14) -#define S3C_CLKCON_PCLK_UART2 (13) -#define S3C_CLKCON_PCLK_UART1 (12) -#define S3C_CLKCON_PCLK_UART0 (11) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ +/#endif /* _PLAT_REGS_CLOCK_H */ I don't know about the other changes, but that last line looks like an error. Did you build anything that #includes this header file? I just did git grep -n S3C_CLKCON_PCLK_UART It was just a guess. I did not cherry pick the defines that covers! The output of that command is, I think, pretty clear. Nicholas, I think you've been told already to stop doing what you're doing again here. I try not to use colorful language on the net, but you're really pushing me here. Please go find something other to do than grepping the kernel tree for FIXMEs! Paul Bolle -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] cpuidle: big.LITTLE: add MCPM dependency
On 07/14/2014 01:23 PM, Arnd Bergmann wrote: 662322fcb6d (cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config) made it possible for the big-little cpuidle driver to run on exynos, which may or may not include MCPM support at compile time, so we run into a link error when it is disabled: drivers/built-in.o: In function `bl_enter_powerdown': :(.text+0x1889a0): undefined reference to `mcpm_cpu_powered_up' drivers/built-in.o: In function `bl_powerdown_finisher': :(.text+0x1889e8): undefined reference to `mcpm_set_entry_vector' :(.text+0x1889ec): undefined reference to `mcpm_cpu_suspend' This adds an explicit dependency to CONFIG_MCPM to avoid that case. Signed-off-by: Arnd Bergmann a...@arndb.de Cc: Chander Kashyap chander.kash...@linaro.org Cc: Tomasz Figa t.f...@samsung.com Cc: Daniel Lezcano daniel.lezc...@linaro.org --- I believe the broken commit is only present in the samsung/for-next tree (through v3.17-next/cpuidle-exynos), so it should be fixed there. On a side note, I wonder if we should have platform dependencies at all, or just the MCPM dependency by itself. diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 2f6b33ea6e08..459b7c91407a 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -10,6 +10,7 @@ config ARM_ARMADA_370_XP_CPUIDLE config ARM_BIG_LITTLE_CPUIDLE bool Support for ARM big.LITTLE processors depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS + depends on MCPM Why do we want to depend on MCPM ? If I want to enable the cpuidle driver, the Kconfig should select the dependencies instead of letting the user to figure out what dependency is missing in order to enable the cpuidle option, no ? + select MCPM select ARM_CPU_SUSPEND select CPU_IDLE_MULTIPLE_DRIVERS help -- http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro Facebook | http://twitter.com/#!/linaroorg Twitter | http://www.linaro.org/linaro-blog/ Blog -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
On 07/14/14 11:40, Paul Bolle wrote: On Mon, 2014-07-14 at 11:23 -0700, Randy Dunlap wrote: On 07/14/14 11:14, Nicholas Krause wrote: This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..46e64cc 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,24 +15,4 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFGS3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3 (14) -#define S3C_CLKCON_PCLK_UART2 (13) -#define S3C_CLKCON_PCLK_UART1 (12) -#define S3C_CLKCON_PCLK_UART0 (11) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ +/#endif /* _PLAT_REGS_CLOCK_H */ I don't know about the other changes, but that last line looks like an error. Did you build anything that #includes this header file? I just did git grep -n S3C_CLKCON_PCLK_UART It was just a guess. I did not cherry pick the defines that covers! The output of that command is, I think, pretty clear. Nicholas, I think you've been told already to stop doing what you're doing again here. I try not to use colorful language on the net, but you're really pushing me here. Please go find something other to do than grepping the kernel tree for FIXMEs! Yes. FIXMEs are not a suggested starting point for kernel beginners. If they were easy to fix, they would already be fixed or most likely would never have been introduced. -- ~Randy -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] ARM: exynos_defconfig: Update exynos_defconfig
On Mon, Jul 14, 2014 at 9:47 AM, Doug Anderson diand...@chromium.org wrote: Sachin, On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat sachin.ka...@samsung.com wrote: Removed outdated configs. Enabled most of the configs used on latest Exynos based platforms. This will provide a reference for users trying to verify and test various features on Exynos based platforms and also help in detecting breakages by widening the build coverage. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com --- arch/arm/configs/exynos_defconfig | 56 +++-- 1 file changed, 48 insertions(+), 8 deletions(-) How about CONFIG_CPU_FREQ=y + related configs? I'm pretty sure that CPU_FREQ works on exynos5250-snow and the config didn't hurt last time I tried on exynos5420/5800. Once Javier's changes land we'll need to add max77802 in here, but it's fine to leave it out until then. I'd also wonder about CONFIG_DRM eventually being set for graphics, but I'll admit to very little knowledge there. That seems like it could be in a followup patch. I would strongly suggest PREMPT_VOLUNTARY=y for now (again in a separate patch). With your config and 'slub_debug=FZPUA' I continue to get constant errors reported. These errors are not your fault (they also show up on tegra boards). I've already reported this and it's pretty much gone nowhere. Another suggestion is to enable the WiFi that's on ARM Chromebooks: CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m ...and that probably means some WiFi configs. I'm not an expert, but possibly these. The first of these appears to be needed to keep shill (present in the default ChromeOS rootfilesystem) from crashing wildly: CONFIG_CFG80211=m CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m Possibly you should be enabling the battery eventually since Chromebooks have these too: CONFIG_BATTERY_SBS=m You're enabling the adc, but not what's hooked up to it: CONFIG_SENSORS_NTC_THERMISTOR=m The eMMC that ships on Chromebooks has more than 8 partitions, so you probably should have this: CONFIG_MMC_BLOCK_MINORS=16 There's a light sensor on most ARM Chromebooks: CONFIG_SENSORS_ISL29018=m All of the above could be in followup patches, so: Tested-by: Doug Anderson diand...@chromium.org Reviewed-by: Doug Anderson diand...@chromium.org Gave this a go on my board farm as well, it looks better than before for sure. Boot logs are at: http://arm-soc.lixom.net/bootlogs/misc/v3.16-rc4-360-g1501776 There are still some issues to resolve but this is an improvement so let's pick it up and fix with new patches on top. Some of the new warnings are: [WARN] [0.785066] usb@1200 supply vdd33 not found, using dummy regulator [WARN] [0.791071] usb@1200 supply vdd10 not found, using dummy regulator [WARN] [0.998658] usb@1240 supply vdd33 not found, using dummy regulator [WARN] [1.004049] usb@1240 supply vdd10 not found, using dummy regulator [WARN] [1.673277] 1006.tmu supply vtmu not found, using dummy regulator [WARN] [1.685873] 10064000.tmu supply vtmu not found, using dummy regulator [WARN] [1.706262] 10068000.tmu supply vtmu not found, using dummy regulator [WARN] [1.720076] 1006c000.tmu supply vtmu not found, using dummy regulator [WARN] [1.733957] 100a.tmu supply vtmu not found, using dummy regulator On snow there is also the below. The L2C might be fixed on -next, it needs to be checked for. [ERR] [0.00] L2C: failed to init: -19 [ERR] [2.118115] cros-ec-i2c-tunnel cros-ec-i2c-tunnel.2: Couldn't read remote-bus property [ERR] [2.726727] max98095 7-0011: ASoC: mux Linein Mux has no paths [ERR] [2.731092] max98095 7-0011: ASoC: mux External MIC has no paths [WARN] [2.125843] cros-ec-i2c-tunnel: probe of cros-ec-i2c-tunnel.2 failed with error -22 [WARN] [2.138322] tps65090 104-0048: No cache defaults, reading back from HW [WARN] [2.296011] tps65090-charger tps65090-charger: Unable to get charger irq = -22 [WARN] [2.313705] tps65090-charger: probe of tps65090-charger failed with error -22 -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
On Monday 14 July 2014 14:14:24 Nicholas Krause wrote: This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. I believe the comment is meant to change the code still using those definitions so they are no longer needed. Just removing them would of course break e.g. s3c_pm_debug_init_uart(). Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) I have actually got a patch to move s3c64xx into multiplatform, following the s5pv210 work that Tomasz did, see patch below. Related to that would be a move of all header files that are not included by plat-samsung/* from arch/arm/mach-s3c64xx/include/mach/ to arch/arm/mach-s3c64xx/. The most significant change in my patch set is the move of gpio-samsung.c back from the drivers directory into plat-samsung. I have discussed this with Linus Walleij as the gpio maintainer, and the conclusion is that this would be the least invasive way to deal with the problem. The driver is expected to eventually go away, and it is not used by DT-base machines. The S3C_ADC is the one remaining show-stopper at this point, because the existing board files rely on this for hwmon (smartq only) and for the touchscreen (mini6410, real6410, smartq and smdk6410) and need to be converted to use the iio driver instead. Arnd commit ac0839aaf5042547ab11f5ce77c4e1cc28b4e84d Author: Arnd Bergmann a...@arndb.de Date: Mon Jul 7 14:25:15 2014 +0200 ARM: s3c64xx experimental multiplatform support Signed-off-by: Arnd Bergmann a...@arndb.de arch/arm/Kconfig | 26 -- arch/arm/configs/multi_v7_defconfig| 3 +++ arch/arm/mach-s3c64xx/Kconfig | 23 +++ arch/arm/mach-s3c64xx/Makefile | 3 +++ arch/arm/mach-s3c64xx/common.c | 1 + arch/arm/mach-s3c64xx/dev-uart.c | 1 + arch/arm/mach-s3c64xx/include/mach/irqs.h | 2 +- arch/arm/mach-s3c64xx/include/mach/pm-core.h | 1 + arch/arm/mach-s3c64xx/mach-anw6410.c | 1 + arch/arm/mach-s3c64xx/mach-crag6410-module.c | 2 ++ arch/arm/mach-s3c64xx/mach-crag6410.c | 1 + arch/arm/mach-s3c64xx/mach-mini6410.c | 1 + arch/arm/mach-s3c64xx/mach-real6410.c | 1 + arch/arm/mach-s3c64xx/mach-smdk6410.c | 1 + arch/arm/plat-samsung/Kconfig | 5 - arch/arm/plat-samsung/Makefile | 5 - .../gpio = arch/arm/plat-samsung}/gpio-samsung.c | 1 + drivers/gpio/Kconfig | 7 -- drivers/gpio/Makefile | 1 - 19 files changed, 49 insertions(+), 37 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 37a3a0947e4e..fceb014c54a1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,32 +609,6 @@ config ARCH_S3C24XX (http://www.simtec.co.uk/products/EB110ITX/), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). -config ARCH_S3C64XX - bool Samsung S3C64XX - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select ARM_VIC - select ATAGS - select CLKDEV_LOOKUP - select CLKSRC_SAMSUNG_PWM - select COMMON_CLK_SAMSUNG - select CPU_V6K - select GENERIC_CLOCKEVENTS - select GPIO_SAMSUNG - select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG - select HAVE_TCM - select NO_IOPORT_MAP - select PLAT_SAMSUNG - select PM_GENERIC_DOMAINS if PM - select S3C_DEV_NAND - select S3C_GPIO_TRACK - select SAMSUNG_ATAGS - select SAMSUNG_WAKEMASK if PM - select SAMSUNG_WDT_RESET - help - Samsung S3C64XX series based systems - config ARCH_DAVINCI bool TI DaVinci select ARCH_HAS_HOLES_MEMORYMODEL diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 58f40f123316..f5af8242358d 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -9,6 +9,9 @@ CONFIG_PERF_EVENTS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MULTI_V7=y +# CONFIG_ARCH_MULTI_V5 if not set +# CONFIG_ARCH_MULTI_V4 if not set CONFIG_ARCH_VIRT=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index eff95e950d81..77dc554435ce 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -2,6 +2,29 @@ # Simtec Electronics, Ben Dooks b...@simtec.co.uk # # Licensed under GPLv2 +menuconfig ARCH_S3C64XX + bool Samsung S3C64XX if ARCH_MULTI_V6 + select ARCH_REQUIRE_GPIOLIB +
Re: [PATCH 3/4] ASoC: samsung: s3c24xx dmaengine follow-up
On Fri, Jul 11, 2014 at 03:45:07PM +0200, Arnd Bergmann wrote: Commit ae602456e83c92 (ASoC: samsung: drop support for legacy S3C24XX DMA API) removed the old code for the samsung specific DMA interfaces, now that everybody can use dmaengine. Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH 4/4] ASoC: samsung: remove unused DMA data
On Fri, Jul 11, 2014 at 03:45:08PM +0200, Arnd Bergmann wrote: The s3c_dma_client structures and the 'ch' and 'ops' members in s3c_dma_params were only used by the legacy DMA driver and serve no function any more. This removes any reference to them. Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH] mach-s3c64xx: Remove all defintions not related to regs-clocks
On Mon, Jul 14, 2014 at 2:45 PM, Randy Dunlap rdun...@infradead.org wrote: On 07/14/14 11:40, Paul Bolle wrote: On Mon, 2014-07-14 at 11:23 -0700, Randy Dunlap wrote: On 07/14/14 11:14, Nicholas Krause wrote: This patch addresses the fix me message in this file that states to remove all definitions not related to reg-clocks in this header file. Signed-off-by: Nicholas Krause xerofo...@gmail.com --- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-cloclinux-ker...@vger.kernel.orgk.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..46e64cc 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,24 +15,4 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFGS3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3 (14) -#define S3C_CLKCON_PCLK_UART2 (13) -#define S3C_CLKCON_PCLK_UART1 (12) -#define S3C_CLKCON_PCLK_UART0 (11) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ +/#endif /* _PLAT_REGS_CLOCK_H */ I don't know about the other changes, but that last line looks like an error. Did you build anything that #includes this header file? I just did git grep -n S3C_CLKCON_PCLK_UART It was just a guess. I did not cherry pick the defines that covers! The output of that command is, I think, pretty clear. Nicholas, I think you've been told already to stop doing what you're doing again here. I try not to use colorful language on the net, but you're really pushing me here. Please go find something other to do than grepping the kernel tree for FIXMEs! linux-ker...@vger.kernel.org Yes. FIXMEs are not a suggested starting point for kernel beginners. If they were easy to fix, they would already be fixed or most likely would never have been introduced. -- ~Randy Randy, My mistake I didn't check the tree for files linking to these definitions. I will be more careful ,next time. Niclk -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] cpuidle: big.LITTLE: add MCPM dependency
On Monday 14 July 2014 20:44:50 Daniel Lezcano wrote: --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -10,6 +10,7 @@ config ARM_ARMADA_370_XP_CPUIDLE config ARM_BIG_LITTLE_CPUIDLE bool Support for ARM big.LITTLE processors depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS + depends on MCPM Why do we want to depend on MCPM ? If I want to enable the cpuidle driver, the Kconfig should select the dependencies instead of letting the user to figure out what dependency is missing in order to enable the cpuidle option, no ? + select MCPM MCPM is a user-selectable option, which doesn't mix well with 'select'. If you want to use 'select' here, better also change bool Multi-Cluster Power Management to just bool in the ARM global Kconfig. The normal way to deal with these dependencies though is to have platforms 'select' the features they allow and have device drivers 'depends on' the same symbol. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v6] spi: s3c64xx: fix broken cs_gpios usage in the driver
Hello Mark,
On 14 July 2014 22:55, Mark Brown broo...@kernel.org wrote:
On Mon, Jul 14, 2014 at 11:11:44AM +0530, Naveen Krishna Chatradhi wrote:
@@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
spi-controller_data = cs;
}
+ /* For the non-DT platforms derive chip selects from controller data */
+ if (!spi-dev.of_node)
+ spi-cs_gpio = cs-line;
+
if (IS_ERR_OR_NULL(cs)) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
return -ENODEV;
@@ -819,17 +811,16 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
if (!spi_get_ctldata(spi)) {
/* Request gpio only if cs line is asserted by gpio pins */
- if (sdd-cs_gpio) {
- err = gpio_request_one(cs-line, GPIOF_OUT_INIT_HIGH,
- dev_name(spi-dev));
+ if (gpio_is_valid(spi-cs_gpio)) {
As previously mentioned gpio_is_valid() is *not* a direct substitute for
checking if the boolean flag cs_gpio has been set since 0 is a valid
GPIO on at least some of these platforms and as discussed several times
already some of the SoCs require the use of the built in chip select.
Yes, gpio_is_valid() is not a direct substitute for boolean cs_gpio.
It was a review comment to use gpio_is_valid() and quickly iterated
another version with that change. Now that we see gpio_is_valid() is
breaking the native chip select for gpio number 0. Shall i go back to
using the boolean or do you have a better way to do this.
In general it's quite hard to tie the description in the patch to the
code changes, not helped by the decision to do separate refactorings
like this conversion to gpio_is_valid() as part of the one patch. The
description of the patch now makes some statements about what the
problem that's intended to be fixed is but it still doesn't seem
entirely clear that everything has been thought through fully and tied
to the code.
The original code appears to be buggy which isn't helping anything but
it's hard to have confidence that this isn't going to break some other
use case that currently works given the lack of clarity and the number
of revisions that have been required so far.
spi-s3c64xx.c is supporting a wide range of SoCs ranging from s3c64xx
series followed by s5p series and then exynos4 and exynos5 series.
However, Exynos4 and Exynos5 series currently available are all DT based.
Support for DT and non-DT was taken good care.
Revision number went to 5 for minor changes like
1. Missing documentation
2. Using gpio_is_valid() instead of boolean cs_gpio
3. Adding SignedOff-By and Acked-By
I think some combination of smaller changes and a clearer working
through of the before and after states for both DT and non DT cases to
show that everything has been considered would help a lot. I may have
another stare at this but it's worrying how hard I'm needing to think.
The intention of the patch was to fix the broken platforms by implementing
dt bindings similar to generic SPI core in spi-s3c64xx.c.
Current dt bindings:
spi-s3c64xx.c is expects the cs-gpio property in the SPI DT node
and also defined under the controller-data.
Solution 1:
Add support for cs-gpios property in the SPI DT node and
remove cs-gpio from sub node controller-data.
Solution 2:
As Javier suggested
//
Inverting the default of cs_gpio. and By default not having the
cs-gpio property in the SPI dev node should mean that the cs-gpio
property in the controller-data node should be used to signal the
chip-select and having the cs-gpio property in the SPI node should
mean that the native chip select should be used instead of a GPIO.
That preserves the old DT binding semantic while making the GPIO to be optional
//
in this case spi-s3c64xx.c will continue to ignore the generic SPI cs-gpios
implementation.
I'm willing to implement any suggestion to fix this issue.
--
Regards,
(: Naveen :)
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