Hi Humberto,
On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote:
Added clock register definitions for the majority of the relevant
clocks inside the SoC, including the definitions of all PLL's clocks.
The definitions are now ordered by name, in order to make the
It
Hi Humberto,
On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote:
This patch implements all the necessary code that handles register
saving and restoring during a suspend/resume cycle.
To make this possible, the local variable reg_base from the function
Hi Tushar,
Am 31.07.2014 07:42, schrieb Tushar Behera:
We are getting a system hang on Arndale-Octa board if PL330_DMA is not
enabled. The issue is related to [1].
AUDSS block provides the clock for audio DMA controller. Any operation
on this clock requires that the clock to AUDSS block be
Hi Humberto,
On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote:
Added the remaining PLL clocks, and also registered the configuration
tables with the PLL coefficients for the supported frequencies.
These frequency tables are valid when a 24MHz clock is supplied as
On Wed, Jul 30, 2014 at 1:37 PM, Thomas Abraham thomas...@samsung.com wrote:
Changes since v8:
- Fixes suggested by Tomasz Figa.
This patch series removes the use of Exynos4210 and Exynos5250 specific
cpufreq
drivers and enables the use of cpufreq-cpu0 driver for these platforms. This
Andreas,
On Thu, Jul 31, 2014 at 1:02 AM, Andreas Färber afaer...@suse.de wrote:
Hi Ajay,
Am 30.07.2014 08:21, schrieb Ajay kumar:
On Tue, Jul 29, 2014 at 4:51 PM, Andreas Färber afaer...@suse.de wrote:
Am 28.07.2014 08:13, schrieb Ajay kumar:
On 7/27/14, Andreas Färber afaer...@suse.de
Ajay,
Am 31.07.2014 10:38, schrieb Ajay kumar:
On Thu, Jul 31, 2014 at 1:02 AM, Andreas Färber afaer...@suse.de wrote:
Am 30.07.2014 08:21, schrieb Ajay kumar:
On Tue, Jul 29, 2014 at 4:51 PM, Andreas Färber afaer...@suse.de wrote:
Am 28.07.2014 08:13, schrieb Ajay kumar:
On 7/27/14, Andreas
-- Forwarded message --
From: Humberto Naves hsna...@gmail.com
Date: Thu, Jul 31, 2014 at 11:01 AM
Subject: Re: Role of PLL_ENABLE_BIT
To: Yadwinder Singh Brar yadi.bra...@gmail.com
Cc: linux-samsung-soc linux-samsung-soc@vger.kernel.org, Mike
Turquette mturque...@linaro.org,
Hi,
Am 31.07.2014 11:49, schrieb Ajay kumar:
On Thu, Jul 31, 2014 at 2:56 PM, Andreas Färber afaer...@suse.de wrote:
Am 30.07.2014 15:50, schrieb Andreas Färber:
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts
b/arch/arm/boot/dts/exynos5250-spring.dts
new file mode 100644
index
On Thu, Jul 31, 2014 at 3:23 PM, Andreas Färber afaer...@suse.de wrote:
Hi,
Am 31.07.2014 11:49, schrieb Ajay kumar:
On Thu, Jul 31, 2014 at 2:56 PM, Andreas Färber afaer...@suse.de wrote:
Am 30.07.2014 15:50, schrieb Andreas Färber:
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts
Hi Humberto,
Somehow the original message didn't arrive on linux-samsung-soc...
Am 31.07.2014 06:51, schrieb Yadwinder Singh Brar:
--- Original Message ---
Sender : Humberto Naveshsna...@gmail.com
Date : Jul 31, 2014 00:16 (GMT+09:00)
Title : Role of PLL_ENABLE_BIT
Hi,
I am
On Thu, Jul 31, 2014 at 2:27 PM, Andreas Färber afaer...@suse.de wrote:
Ajay,
Am 31.07.2014 10:38, schrieb Ajay kumar:
On Thu, Jul 31, 2014 at 1:02 AM, Andreas Färber afaer...@suse.de wrote:
Am 30.07.2014 08:21, schrieb Ajay kumar:
On Tue, Jul 29, 2014 at 4:51 PM, Andreas Färber
On Thu, Jul 31, 2014 at 10:57:55AM +0200, Andreas Färber wrote:
Am 31.07.2014 10:38, schrieb Ajay kumar:
[...]
With just the spring-bridge.v6 branch of your own tree, I am able to see
bootup logo on Skate(a variant of spring which also contains ps8622).
I have tried both exynos_defconfig
Am 31.07.2014 12:23, schrieb Thierry Reding:
On Thu, Jul 31, 2014 at 10:57:55AM +0200, Andreas Färber wrote:
Am 31.07.2014 10:38, schrieb Ajay kumar:
[...]
With just the spring-bridge.v6 branch of your own tree, I am able to see
bootup logo on Skate(a variant of spring which also contains
Hi Andreas,
I guess the original message was not plain text, and majordomo refused
to deliver it :-(
The signedness is not an issue, if I just use what I sent in the
patch, the set_rate function works like a charm. But otherwise, the
whole system freezes and I have to reboot the machine.
Best,
On Thu, Jul 31, 2014 at 11:50 AM, Chander M. Kashyap
chander.kash...@gmail.com wrote:
On Wed, Jul 30, 2014 at 1:37 PM, Thomas Abraham thomas...@samsung.com wrote:
Changes since v8:
- Fixes suggested by Tomasz Figa.
This patch series removes the use of Exynos4210 and Exynos5250 specific
On Wed, Jul 30, 2014 at 09:33:28PM +0530, Ajay kumar wrote:
On Wed, Jul 30, 2014 at 8:38 PM, Thierry Reding thierry.red...@gmail.com
wrote:
[...]
I think it should even be possible to do this in more separate steps.
For example you could add the new bridge infrastructure without touching
On Wed, Jul 30, 2014 at 09:44:32PM +0530, Ajay kumar wrote:
On Wed, Jul 30, 2014 at 9:10 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Wed, Jul 30, 2014 at 08:46:44PM +0530, Ajay kumar wrote:
On Wed, Jul 30, 2014 at 5:35 PM, Thierry Reding thierry.red...@gmail.com
wrote:
On
This patch implements all the necessary code that handles register
saving and restoring during a suspend/resume cycle. To make this
possible, the local variable reg_base from the function
exynos5410_clk_init was changed to global. In addition, new
clock register definitions were added for the
Added the remaining PLL clocks, and also added the configuration
tables with the PLL coefficients for the supported frequencies.
These frequency tables are only installed when a 24MHz clock is
supplied as the input clock source. To reflect these changes, new
constants were added to the dt-bindings
This implements the fixed rate clocks generated either inside or
outside the SoC. It also adds a dt-binding constant for the
sclk_hdmiphy clock, which shall be later used by other drivers,
such as the DRM.
Since the external fixed rate clock fin_pll is now registered by
the clk-exynos5410 file,
Hi,
This patch series slightly improves the exynos5410 clock driver. Below is
a list of changes introduced by the patch:
- Basic validation in the clock initialization routine
- Added resume/suspend handler
- Implemented some fixed rate clocks and changed the way fin_pll is defined
- Added
Added NULL pointer checks for device_node input parameter and
for the samsung_clk_provider context returned by samsung_clk_init.
Even though the *current* samsung_clk_init function never returns
a NULL pointer, it is good to keep this check in place to avoid
possible problems in the future due to
The different register groups (SRC, DIV, PLL, GATE, etc) are
now separated by a blank line, and within the same group, the
definitions are ordered by address. This is done to reduce the
chances of potential conflicts when adding new entries, and
to improve the readability of code. While at it,
(dropping linux-doc ML and Randy from Cc)
On 31/07/14 13:22, Humberto Silva Naves wrote:
This implements the fixed rate clocks generated either inside or
outside the SoC. It also adds a dt-binding constant for the
sclk_hdmiphy clock, which shall be later used by other drivers,
such as the
Hello,
This is a small series that improve the modeling of the power
scheme on the Peach Pit and Pi boards. Besides making the DTS
to better describe the hardware these changes allows the core
regulator to know what's the real supply for a child to fetch
the parent output voltage if the child
The DeviceTree files for the Peach Pit and Pi machines have
a simplistic model of the connections between the different
regulators since not all the tps65090 regulators get their
input supply voltage from the VDC. DCDC1-3, LD0-1 and fet7
parent supply is indded VDC but the fet1-6 get their input
Both Exynos5420 Peach Pit and Exynos5800 Peach Pi boards
have a tps65090 PMU that has a number of switches (FETs)
that are just on/off devices but they do have a current
limit and the output voltage of the switch is ramped up
within a controlled slope.
After the switch is turned on, a safety
On Thu, Jul 31, 2014 at 4:29 PM, Thomas Abraham ta.oma...@gmail.com wrote:
On Thu, Jul 31, 2014 at 11:50 AM, Chander M. Kashyap
chander.kash...@gmail.com wrote:
On Wed, Jul 30, 2014 at 1:37 PM, Thomas Abraham thomas...@samsung.com
wrote:
Changes since v8:
- Fixes suggested by Tomasz Figa.
According to the tps65090 data manual [0], the DCDC1 and DCDC2
step-down converters and the LDO's have a fixed output voltage.
Add this information to the driver since these fixed regulators
can be used as parent input supply for switches that don't have
an output voltage defined. So the
Hi Humberto,
Please see my comments inline.
On 31.07.2014 13:22, Humberto Silva Naves wrote:
Added NULL pointer checks for device_node input parameter and
for the samsung_clk_provider context returned by samsung_clk_init.
Even though the *current* samsung_clk_init function never returns
a
Hi Humberto,
Please see my comments inline.
On 31.07.2014 13:22, Humberto Silva Naves wrote:
The different register groups (SRC, DIV, PLL, GATE, etc) are
now separated by a blank line, and within the same group, the
definitions are ordered by address. This is done to reduce the
chances of
Hi Humberto,
You can find my comments inline.
On 31.07.2014 13:22, Humberto Silva Naves wrote:
This implements the fixed rate clocks generated either inside or
outside the SoC. It also adds a dt-binding constant for the
sclk_hdmiphy clock, which shall be later used by other drivers,
such as
Hi Humberto,
You can find my comments inline.
On 31.07.2014 13:22, Humberto Silva Naves wrote:
Added the remaining PLL clocks, and also added the configuration
tables with the PLL coefficients for the supported frequencies.
These frequency tables are only installed when a 24MHz clock is
Hi Humberto,
On 31.07.2014 13:22, Humberto Silva Naves wrote:
This patch implements all the necessary code that handles register
saving and restoring during a suspend/resume cycle. To make this
possible, the local variable reg_base from the function
exynos5410_clk_init was changed to global.
On 31.07.2014 15:13, Humberto Naves wrote:
Hi,
I am bit confused by your response: first you mentioned that I should
remove the NULL check for variable np, but later on you suggested that
I should rearrange the conditional statement to avoid adding more
indentation.
That was just a side
Hi,
I am bit confused by your response: first you mentioned that I should
remove the NULL check for variable np, but later on you suggested that
I should rearrange the conditional statement to avoid adding more
indentation. My guess is that I should remove that if statement
altogether?
Regarding
Hi Tomasz,
I perfectly see your point.
However my question was why you did you decide to postpone
Sylwester's? Was there any specific reason?
I suppose it would break all the dtb compatibility, but besides that,
was there any other reason?
Best,
Humberto
On Thu, Jul 31, 2014 at 2:53 PM, Tomasz
On 31.07.2014 12:46, Humberto Naves wrote:
Hi Andreas,
I guess the original message was not plain text, and majordomo refused
to deliver it :-(
The signedness is not an issue, if I just use what I sent in the
patch, the set_rate function works like a charm. But otherwise, the
whole system
Hi Tomasz,
I remember checking these rates on my calculator. You might notice the
odd frequency of 45158401Hz (no pun intended) in the EPLL clock. This
particular clock frequency was giving me a big headache in a previous
project, since it was wrongly listed as 45158400. At first it seems
On 31.07.2014 15:23, Humberto Naves wrote:
Hi Tomasz,
I perfectly see your point.
However my question was why you did you decide to postpone
Sylwester's? Was there any specific reason?
I suppose it would break all the dtb compatibility, but besides that,
was there any other reason?
We
On 30.07.2014 10:07, Thomas Abraham wrote:
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked
Hi Thomas,
On 30.07.2014 10:07, Thomas Abraham wrote:
Changes since v8:
- Fixes suggested by Tomasz Figa.
This patch series removes the use of Exynos4210 and Exynos5250 specific
cpufreq
drivers and enables the use of cpufreq-cpu0 driver for these platforms. This
series also enables
Am 31.07.2014 12:23, schrieb Thierry Reding:
On Thu, Jul 31, 2014 at 10:57:55AM +0200, Andreas Färber wrote:
Am 31.07.2014 10:38, schrieb Ajay kumar:
With just the spring-bridge.v6 branch of your own tree, I am able to see
bootup logo on Skate(a variant of spring which also contains ps8622).
Hi,
On Thursday, July 31, 2014 08:09:49 AM Andreas Färber wrote:
Hi Tushar,
Am 31.07.2014 07:42, schrieb Tushar Behera:
We are getting a system hang on Arndale-Octa board if PL330_DMA is not
enabled. The issue is related to [1].
AUDSS block provides the clock for audio DMA
On 31.07.2014 15:37, Humberto Naves wrote:
Hi Tomasz,
I remember checking these rates on my calculator. You might notice the
odd frequency of 45158401Hz (no pun intended) in the EPLL clock. This
particular clock frequency was giving me a big headache in a previous
project, since it was
From: Tomasz Figa tomasz.f...@gmail.com
Hi Mike,
The following changes since commit bdfcdf18c380a3c376b42709a89eb2cc52e95ae0:
Merge branch 'v3.16-samsung-clk-fixes-1' into samsung-clk-next (2014-06-30
15:06:43 +0200)
are available in the git repository at:
Jaehoon
On Wed, Jul 30, 2014 at 10:35 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Slot quirks disable-wp is deprecated.
Instead, use the host quirk disable-wp.
(Because the slot-node is removed in dt-file.)
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Tested-by: Sachin Kamat
Hello,
Based on the preinstalled 3.8 based ChromeOS kernel and previous 3.15
based attempts by Stephan and me that broke for 3.16, I've prepared a
device tree for the HP Chromebook 11 aka Google Spring.
v4 fixes a pinctrl bug.
Not yet enabled are trackpad, Wifi and sound.
My rebasing branch
Adds initial support for the HP Chromebook 11.
Cc: Vincent Palatin vpala...@chromium.org
Cc: Doug Anderson diand...@chromium.org
Cc: Stephan van Schaik step...@synkhronix.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
v3 - v4:
* Fixed samsung,pin-function 1 - 0 for dp-hpd-gpio
*
Use the new style of referencing inherited nodes and use symbolic names.
Suggested-by: Doug Anderson diand...@chromium.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
v3 - v4: Unchanged
v3: New (Doug Anderson)
arch/arm/boot/dts/exynos5250-snow.dts | 182
The pinctrl properties should be on the device directly and not on the
slot sub-node.
Reported-by: Doug Anderson diand...@chromium.org
Cc: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
v3 - v4: Unchanged
v3: New (Doug Anderson)
Redundant with Jaehoon
The remaining common ChromeOS pieces are fairly minor.
Suggested-by: Doug Anderson diand...@chromium.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
v3 - v4: Unchanged
v2 - v3:
* Renamed subject to match Kukjin's style
* Rebased onto MMC pinctrl bug fix (Doug Anderson)
v2: New
Am 31.07.2014 18:08, schrieb Andreas Färber:
Hello,
Based on the preinstalled 3.8 based ChromeOS kernel and previous 3.15
based attempts by Stephan and me that broke for 3.16, I've prepared a
device tree for the HP Chromebook 11 aka Google Spring.
v4 fixes a pinctrl bug.
Once again,
Always a bit late to the game.
One small comment inline.
Reviewed-by: Vincent Palatin vpala...@chromium.org
On Thu, Jul 31, 2014 at 9:08 AM, Andreas Färber afaer...@suse.de wrote:
Adds initial support for the HP Chromebook 11.
Cc: Vincent Palatin vpala...@chromium.org
Cc: Doug Anderson
Remove runtime checks for pdata sanity from exynos_tmu_initialize().
The current values hardcoded in pdata will never trigger the checks
and checking itself is not proper. The checks in question are done
at runtime in a production code for data that is hardcoded inside
driver during development
There is no need for abstracting configuration for registers that
are identical on all SoC types.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
pdata-reference_voltage and pdata-gain are always defined
to non-zero values so remove the redundant checks from
exynos_tmu_control().
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park
* Remove dead temp check from temp_to_code() (this function users
in exynos_tmu_initialize() always pass correct temperatures and
exynos_tmu_set_emulation() returns early for EXYNOS4210 because
TMU_SUPPORT_EMULATION flag is not set on this SoC).
* Move temp_code check from code_to_temp() to
Remove runtime checks for negative return values of temp_to_code()
from exynos_tmu_initialize().
The current level temperature data hardcoded in pdata will never
cause a negative temp_to_code() return values and checking itself
is not proper. The checks in question are done at runtime in
a
Remove unused / write-only entries from struct exynos_tmu_registers.
Then remove unused defines while at it.
We don't keep the unused/untested features in the kernel just
in case that some future hardware might need it. Such code has
a real maintainance cost (all other code changes have to take
Hi,
This patch series contains various cleanups for EXYNOS thermal
driver. Overall it decreases driver's LOC by 9%. It is based
on next-20140731 kernel. It should not cause any functionality
changes.
Changes since v2 (https://lkml.org/lkml/2014/6/17/436):
- synced patches against next
Cache number of non-hardware trigger levels in a new pdata field
(non_hw_trigger_levels) and convert code in exynos_tmu_initialize()
accordingly.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park
The commit 1928457 (thermal: exynos: Add hardware mode thermal
calibration support) has added HW_MODE feature but it has never
been enabled. As such it has been a dead code for over a year
now and should be removed from the kernel.
We don't keep the unused/untested features in the kernel just
in
Hi,
Am 31.07.2014 19:00, schrieb Vincent Palatin:
Always a bit late to the game.
One small comment inline.
Reviewed-by: Vincent Palatin vpala...@chromium.org
Thanks,
On Thu, Jul 31, 2014 at 9:08 AM, Andreas Färber afaer...@suse.de wrote:
+ usb3_vbus_reg: regulator-usb3 {
+
Hi,
On Tuesday, July 29, 2014 08:58:48 AM Eduardo Valentin wrote:
On Mon, Jul 28, 2014 at 08:30:53PM +0530, amit daniel kachhap wrote:
Hi Eduardo,
Hello Amit,
Please reject this entire series as this is not re-based recently.
Actually two point trimming which this series seeks to
Modify exynos_dpi driver to support the new panel calls:
prepare and unprepare.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dpi.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
This patch adds dummy definition for prepare and unprepare
routines to ld9040 panel driver.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/panel/panel-ld9040.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-ld9040.c
This patch adds dummy definition for prepare and unprepare
routines to s6e8aa0 panel driver.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/panel/panel-s6e8aa0.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-s6e8aa0.c
Modify tegra output driver to support the new panel calls:
prepare and unprepare.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/tegra/output.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
index
Most of the panels need an init sequence as mentioned below:
-- poweron LCD unit/LCD_EN
-- start video data
-- poweron LED unit/BACKLIGHT_EN
And, a de-init sequence as mentioned below:
-- poweroff LED unit/BACKLIGHT_EN
-- stop video data
-- poweroff
For most of the panels, we need to provide delays during
various stages of panel powerup/powerdown.
So, Add a structure to hold those delay values and use them
in corresponding functions.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/panel/panel-simple.c | 30
Add a helper function drm_panel_get_modes to get modes from the panel.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
include/drm/drm_panel.h |8
1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 9addc69..efc63cc 100644
---
This series is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
This is originally a part of the bridge chip series:
http://www.spinics.net/lists/linux-samsung-soc/msg34826.html
But, since we can handle panel and bridge
Move out code from enable and disable routines to prepare
and unprepare routines, so that functionality is properly
distributed across all the panel functions.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/panel/panel-ld9040.c | 22 +++---
1 file
Move out code from enable and disable routines to prepare
and unprepare routines, so that functionality is properly
distributed across all the panel functions.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/panel/panel-s6e8aa0.c | 22 +++---
1 file
Modify exynos_dsi driver to support the new panel calls:
prepare and unprepare.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git
Move out code from enable and disable routines to prepare
and unprepare routines, so that functionality is properly
distributed across all the panel functions.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/panel/panel-simple.c | 37 +-
1
Add drm_panel controls to support powerup/down of the
eDP panel, if one is present at the sink side.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig |1 +
drivers/gpu/drm/exynos/exynos_dp_core.c | 88 ---
Add commit callback for exynos_dp, and move the DP link training,
video configuration code from the hotplug handler into commit().
Signed-off-by: Sean Paul seanp...@chromium.org
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 24
Add panel_desc structure for auo_b133htn01 eDP panel.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
.../devicetree/bindings/panel/auo,b133htn01.txt|7 +
drivers/gpu/drm/panel/panel-simple.c | 31
2 files changed, 38 insertions(+)
create
The following changes since commit 6da287ad0266cca1fa8f88fb8b1c466e8164671f:
Merge branch 'v3.17-next/power-exynos' into v3.17-next/dt-samsung-2
(2014-07-29 06:09:42 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
Hi Tomasz,
On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 30.07.2014 10:07, Thomas Abraham wrote:
With some of the Exynos SoCs switched over to use the generic CPUfreq
drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock
On Thu, Jul 31, 2014 at 7:45 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
On 30.07.2014 10:07, Thomas Abraham wrote:
Changes since v8:
- Fixes suggested by Tomasz Figa.
This patch series removes the use of Exynos4210 and Exynos5250 specific
cpufreq
drivers and enables the use
On 08/01/14 03:20, Kukjin Kim wrote:
Hi Arnd and Olof,
Probably you may see merge conflict when you merge this branch into
arm-soc because of cros-ec-keyboard related patches from Stephen.
Here is my preferred resolution.
diff --cc arch/arm/boot/dts/exynos5250-snow.dts
index
On 07/30/14 17:07, Thomas Abraham wrote:
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz
Hi Viresh,
On Thu, Jul 31, 2014 at 11:55 PM, Thomas Abraham ta.oma...@gmail.com wrote:
On Thu, Jul 31, 2014 at 7:45 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
On 30.07.2014 10:07, Thomas Abraham wrote:
Changes since v8:
- Fixes suggested by Tomasz Figa.
This patch series
On 08/01/14 01:02, Doug Anderson wrote:
Jaehoon
On Wed, Jul 30, 2014 at 10:35 PM, Jaehoon Chungjh80.ch...@samsung.com wrote:
Slot quirks disable-wp is deprecated.
Instead, use the host quirk disable-wp.
(Because the slot-node is removed in dt-file.)
Signed-off-by: Jaehoon
On 31.07.2014 20:24, Thomas Abraham wrote:
Hi Tomasz,
On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 30.07.2014 10:07, Thomas Abraham wrote:
With some of the Exynos SoCs switched over to use the generic CPUfreq
drivers,
the unused clock aliases can be
On 08/01/14 01:02, Doug Anderson wrote:
Jaehoon
On Wed, Jul 30, 2014 at 10:35 PM, Jaehoon Chungjh80.ch...@samsung.com wrote:
Slot quirks disable-wp is deprecated.
Instead, use the host quirk disable-wp.
(Because the slot-node is removed in dt-file.)
Signed-off-by: Jaehoon
Kukjin,
On 31.07.2014 20:32, Kukjin Kim wrote:
On 07/30/14 17:07, Thomas Abraham wrote:
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use
On 08/01/14 01:08, Andreas Färber wrote:
The pinctrl properties should be on the device directly and not on the
slot sub-node.
Reported-by: Doug Andersondiand...@chromium.org
Cc: Jaehoon Chungjh80.ch...@samsung.com
Signed-off-by: Andreas Färberafaer...@suse.de
---
v3 - v4: Unchanged
v3:
On 31.07.2014 20:41, Thomas Abraham wrote:
On Fri, Aug 1, 2014 at 12:05 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 31.07.2014 20:24, Thomas Abraham wrote:
Hi Tomasz,
On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 30.07.2014 10:07, Thomas Abraham wrote:
On Fri, Aug 1, 2014 at 12:16 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 31.07.2014 20:41, Thomas Abraham wrote:
On Fri, Aug 1, 2014 at 12:05 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 31.07.2014 20:24, Thomas Abraham wrote:
Hi Tomasz,
On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa
On 31.07.2014 20:40, Tomasz Figa wrote:
Kukjin,
On 31.07.2014 20:32, Kukjin Kim wrote:
On 07/30/14 17:07, Thomas Abraham wrote:
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not
Hi Arnd, Olof
One more pull-request. Sorry.
Thanks,
Kukjin
The following changes since commit f1ff47454bb2fe0d5644f981679d1bea532816fd:
clk: samsung: s5pv210: Remove legacy board support (2014-07-19
04:32:19 +0900)
are available in the git repository at:
Hi Andreas,
Sorry for joining the party a bit late, but there were patches with less
people involved so I preferred to review them first.
You can find my comments inline.
On 31.07.2014 18:08, Andreas Färber wrote:
Adds initial support for the HP Chromebook 11.
[snip]
+ gpio-keys {
+
Hi Kukjin,
On 17.07.2014 17:56, Tomasz Figa wrote:
On Exynos-based boards running secure firmware the sequence of low level
operations to enter and leave system-wide sleep mode is different than
on those without the firmware. Namely:
- CP15 power control and diagnostic registers cannot be
On 17.07.2014 18:38, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from secure mode.
First four
On 31.07.2014 18:08, Andreas Färber wrote:
The pinctrl properties should be on the device directly and not on the
slot sub-node.
Reported-by: Doug Anderson diand...@chromium.org
Cc: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
v3 - v4: Unchanged
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