On Sat, Sep 20, 2014 at 8:57 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
[adding Kukjin as cc]
Hello Ajay,
On Sat, Sep 20, 2014 at 1:22 PM, Ajay kumar ajayn...@gmail.com wrote:
Generally speaking, I sense that we have different views of how display
devices and drivers are
Hi Tomasz,
On Sat, Sep 13, 2014 at 4:57 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Abhilash,
Please see my comments inline.
On 13.09.2014 10:50, Abhilash Kesavan wrote:
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7
Dear Javier,
On 09/17/2014 08:50 PM, Javier Martinez Canillas wrote:
commit 546b117fdf17 (rtc: s3c: add support for RTC of Exynos3250 SoC)
added an rtc_src DT property for the Samsung's S3C Real Time Clock
controller that specifies the 32.768 kHz clock that uses the RTC as its
source clock.
Dear Javier,
On 09/17/2014 08:50 PM, Javier Martinez Canillas wrote:
commit 546b117fdf17 (rtc: s3c: add support for RTC of Exynos3250 SoC)
added an rtc_src DT property for the Samsung's S3C Real Time Clock
controller that specifies the 32.768 kHz clock that uses the RTC as its
source clock.
On Wed, Sep 17, 2014 at 12:27:13PM +0300, Laurent Pinchart wrote:
Hi Ajay,
On Wednesday 17 September 2014 14:37:30 Ajay kumar wrote:
On Mon, Sep 15, 2014 at 11:07 PM, Laurent Pinchart wrote:
Hi Ajay,
Thank you for the patch.
I think we're moving in the right direction, but
On Wed, Sep 17, 2014 at 02:52:42PM +0300, Tomi Valkeinen wrote:
On 27/08/14 17:39, Ajay Kumar wrote:
Add documentation for DT properties supported by ps8622/ps8625
eDP-LVDS converter.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
On 22.09.2014 08:17, Abhilash Kesavan wrote:
Hi Tomasz,
On Sat, Sep 13, 2014 at 4:57 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Abhilash,
Please see my comments inline.
On 13.09.2014 10:50, Abhilash Kesavan wrote:
Exynos7 uses different offsets for wakeup interrupt configuration
On Wed, Sep 17, 2014 at 07:22:05PM +0300, Tomi Valkeinen wrote:
On 17/09/14 17:29, Ajay kumar wrote:
Hi Tomi,
Thanks for your comments.
On Wed, Sep 17, 2014 at 5:22 PM, Tomi Valkeinen tomi.valkei...@ti.com
wrote:
On 27/08/14 17:39, Ajay Kumar wrote:
Add documentation for DT
On Thu, Sep 18, 2014 at 11:20:40AM +0530, Ajay kumar wrote:
Hi Tomi,
On Wed, Sep 17, 2014 at 9:52 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On 17/09/14 17:29, Ajay kumar wrote:
Hi Tomi,
Thanks for your comments.
On Wed, Sep 17, 2014 at 5:22 PM, Tomi Valkeinen
On Fri, Sep 19, 2014 at 05:28:37PM +0300, Tomi Valkeinen wrote:
On 19/09/14 16:59, Ajay kumar wrote:
I am not really able to understand, what's stopping us from using this
bridge on a board with complex display connections. To use ps8622 driver,
one needs to attach it to the DRM
On 02.09.2014 15:21, Krzysztof Kozlowski wrote:
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.
The DMC clock domain uses different address space (0x105C) than
standard clock domain (0x1003 - 0x1005).
Hi Thierry,
On Mon, Sep 22, 2014 at 1:40 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Sep 18, 2014 at 11:20:40AM +0530, Ajay kumar wrote:
Hi Tomi,
On Wed, Sep 17, 2014 at 9:52 PM, Tomi Valkeinen tomi.valkei...@ti.com
wrote:
On 17/09/14 17:29, Ajay kumar wrote:
Hi Tomi,
On 09.09.2014 14:14, Krzysztof Kozlowski wrote:
On 05.09.2014 13:54, Pankaj Dubey wrote:
As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
drivers/clk/samsung/clk-exynos3250.c |4 ++--
1 file changed, 2
On 09.09.2014 14:14, Krzysztof Kozlowski wrote:
On 09.09.2014 13:54, Pankaj Dubey wrote:
Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
drivers/clk/samsung/clk-exynos3250.c |2 +-
1 file
On 09.09.2014 14:24, Krzysztof Kozłowski wrote:
On 06.09.2014 15:03, Pankaj Dubey wrote:
As per user manual of Exynos3250 SRC_CAM can select
div_cam_blk_320 if it's value is 0xC, so placing
div_cam_blk_320 at proper index in parent list of mout_cam_blk.
Signed-off-by: Pankaj Dubey
On 22.09.2014 06:55, Pankaj Dubey wrote:
Hi Tomasz,
Will you please take this patch and following three Exynos3250 clock fixes
in your tree.
1: clk: samsung: exynos3250: fix width field of mout_mmc0/1
https://lkml.org/lkml/2014/9/5/265
2: clk: samsung: exynos3250: fix width and shift
Hi Abhilash,
On 22.09.2014 06:47, Abhilash Kesavan wrote:
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
All KMS objects are destroyed by drm_mode_config_cleanup in proper order
so component drivers should not care about it.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Hi Inki,
This is another spin-off of exynos_drm tests regarding your
component support update.
The patch is based as usual
On Mon, Sep 22, 2014 at 10:10:07AM +0530, Pankaj Dubey wrote:
Currently a syscon entity can be only registered directly through a
platform device that binds to a dedicated syscon driver. However in
certain use cases it is desirable to make a device used with another
driver a syscon interface
Hi,
[...]
+static struct regmap_config syscon_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
};
-static int syscon_match_node(struct device *dev, void *data)
+static struct syscon *of_syscon_register(struct device_node *np)
{
- struct
On Wed, Sep 17, 2014 at 03:02:48PM +0530, Ajay kumar wrote:
On Tue, Sep 16, 2014 at 6:14 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
[adding Laurent Pinchart to cc who had concerns with a previous
version of this patch-set]
Hello Ajay,
On Wed, Aug 27, 2014 at 4:29 PM,
On Mon, Sep 22, 2014 at 02:01:38PM +0530, Ajay kumar wrote:
Hi Thierry,
On Mon, Sep 22, 2014 at 1:40 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Sep 18, 2014 at 11:20:40AM +0530, Ajay kumar wrote:
Hi Tomi,
On Wed, Sep 17, 2014 at 9:52 PM, Tomi Valkeinen
On Mon, Sep 22, 2014 at 4:11 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Sep 22, 2014 at 02:01:38PM +0530, Ajay kumar wrote:
Hi Thierry,
On Mon, Sep 22, 2014 at 1:40 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Sep 18, 2014 at 11:20:40AM +0530, Ajay kumar wrote:
On Mon, Sep 22, 2014 at 04:53:22PM +0530, Ajay kumar wrote:
On Mon, Sep 22, 2014 at 4:11 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Sep 22, 2014 at 02:01:38PM +0530, Ajay kumar wrote:
Hi Thierry,
On Mon, Sep 22, 2014 at 1:40 PM, Thierry Reding
thierry.red...@gmail.com
The PWM block is required for system clock source so it must be always
enabled. This patch fixes boot issues on SMDK6410 which did not have the
node enabled explicitly for other purposes.
Fixes: eeb93d02c5d8 (clocksource: of: Respect device tree node status)
Signed-off-by: Tomasz Figa
Tomasz Figa wrote:
The PWM block is required for system clock source so it must be always
enabled. This patch fixes boot issues on SMDK6410 which did not have the
node enabled explicitly for other purposes.
Fixes: eeb93d02c5d8 (clocksource: of: Respect device tree node status)
Andreas Färber wrote:
Am 17.09.2014 um 17:47 schrieb Doug Anderson:
Hi,
On Wed, Sep 17, 2014 at 4:50 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
commit 546b117fdf17 (rtc: s3c: add support for RTC of Exynos3250 SoC)
added an rtc_src DT property for the
On 16.09.2014 13:54, Marek Szyprowski wrote:
This patch adds missing smmu_g2d clock implementation and updates
comment about Exynos4 clocks from 278-282 range. Those clocks are
available on all Exynos4 SoC series, so the misleading comment has been
removed.
Signed-off-by: Marek Szyprowski
On Mon, Sep 22, 2014 at 5:05 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Sep 22, 2014 at 04:53:22PM +0530, Ajay kumar wrote:
On Mon, Sep 22, 2014 at 4:11 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Sep 22, 2014 at 02:01:38PM +0530, Ajay kumar wrote:
Hi Thierry,
sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
On 22.09.2014 14:17, Marek Szyprowski wrote:
sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect
Commit 90c0ae50097 changed how the frame_type of a decoded frame
gets determined, by switching from the get_dec_frame_type to
get_disp_frame_type operation. Unfortunately it seems that on MFC v5 the
result of get_disp_frame_type is always 0 (no display) when decoding
(tested with H264), resulting
Hello,
This patchset adds support for early console defined in device tree. As
an example, DTS files for all Exynos4 based machines are updated with
the correct value for common chosen/sdtout property.
To get it fully functional additional improvements (support for
early_ioremap) are needed in
From: Tomasz Figa t.f...@samsung.com
This patch adds support for early console initialized from device tree
to all variants of Samsung serial driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/tty/serial/Kconfig | 1 +
From: Tomasz Figa t.f...@samsung.com
This patch adds stdout-path property to chosen nodes of Exynos4 boards
to enable use of earlycon feature without the need to hardcode port
number in kernel itself.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski
Hi Tomasz,
On Mon, Sep 22, 2014 at 4:49 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 22.09.2014 01:10, Alim Akhtar wrote:
[snip]
As you said there is no support for ioremap on ARM, so this is not
tested on ARM.
Don't forget that this driver is primarily targeted for ARM platforms
On 22/09/14 10:54, Thierry Reding wrote:
I wish all new display component bindings would use the video
ports/endpoints to describe the connections. It will be very difficult
to improve the display driver model later if we're missing such critical
pieces from the DT bindings.
I disagree.
On 22/09/14 11:06, Thierry Reding wrote:
Why do we need a complex graph when it can be handled using a simple
phandle?
Maybe in your case you can handle it with simple phandle. Can you
guarantee that it's enough for everyone, on all platforms?
Nobody can guarantee that. An interesting
On 22/09/14 11:26, Thierry Reding wrote:
On Fri, Sep 19, 2014 at 05:28:37PM +0300, Tomi Valkeinen wrote:
On 19/09/14 16:59, Ajay kumar wrote:
I am not really able to understand, what's stopping us from using this
bridge on a board with complex display connections. To use ps8622 driver,
one
On 20/09/14 18:27, Javier Martinez Canillas wrote:
I see that Documentation/devicetree/bindings/video/ti,omap-dss.txt
mentions that the Video Ports binding documentation is in
Documentation/devicetree/bindings/video/video-ports.txt but I don't
see that this file exists in the kernel [1]. I
On Monday 22 September 2014 13:35:15 Thierry Reding wrote:
On Mon, Sep 22, 2014 at 04:53:22PM +0530, Ajay kumar wrote:
On Mon, Sep 22, 2014 at 4:11 PM, Thierry Reding wrote:
On Mon, Sep 22, 2014 at 02:01:38PM +0530, Ajay kumar wrote:
On Mon, Sep 22, 2014 at 1:40 PM, Thierry Reding wrote:
Hi Thierry,
On Monday 22 September 2014 09:40:38 Thierry Reding wrote:
On Wed, Sep 17, 2014 at 12:27:13PM +0300, Laurent Pinchart wrote:
On Wednesday 17 September 2014 14:37:30 Ajay kumar wrote:
On Mon, Sep 15, 2014 at 11:07 PM, Laurent Pinchart wrote:
Hi Ajay,
Thank you for
On Thu, Sep 18, 2014 at 12:42:16PM +0200, Paul Bolle wrote:
On Thu, 2014-09-04 at 18:02 +0200, Arnd Bergmann wrote:
I think it would be nice if you could submit a patch to remove the
drivers from ASoC, then we can see if anybody complains.
Also the same thing for v3.17-rc5 and
On Thu, Sep 18, 2014 at 11:57:07PM +0200, Paul Bolle wrote:
Mark Brown schreef op do 18-09-2014 om 10:57 [-0700]:
On Thu, Sep 18, 2014 at 11:43:29AM +0200, Paul Bolle wrote:
Done on top of next-20140918. Untested.
-8-
From: Paul Bolle pebo...@tiscali.nl
Please
Hi Paul,
On 09/12/2014 05:41 PM, Paul Bolle wrote:
On Fri, 2014-09-05 at 13:30 +0900, Chanwoo Choi wrote:
This patch add exynos-ppmu devfreq event driver to provider raw data about
the utilization of each IP in Exynos SoC series.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by:
On Tue, Sep 23, 2014 at 03:29:13AM +0300, Laurent Pinchart wrote:
Hi Thierry,
On Monday 22 September 2014 09:40:38 Thierry Reding wrote:
On Wed, Sep 17, 2014 at 12:27:13PM +0300, Laurent Pinchart wrote:
On Wednesday 17 September 2014 14:37:30 Ajay kumar wrote:
On Mon, Sep 15, 2014 at
On Mon, Sep 22, 2014 at 05:42:41PM +0300, Tomi Valkeinen wrote:
On 22/09/14 11:26, Thierry Reding wrote:
On Fri, Sep 19, 2014 at 05:28:37PM +0300, Tomi Valkeinen wrote:
On 19/09/14 16:59, Ajay kumar wrote:
I am not really able to understand, what's stopping us from using this
bridge on
On Tue, Sep 23, 2014 at 03:00:37AM +0300, Laurent Pinchart wrote:
On Monday 22 September 2014 13:35:15 Thierry Reding wrote:
On Mon, Sep 22, 2014 at 04:53:22PM +0530, Ajay kumar wrote:
On Mon, Sep 22, 2014 at 4:11 PM, Thierry Reding wrote:
On Mon, Sep 22, 2014 at 02:01:38PM +0530, Ajay
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