[PATCH v5 RESEND 1/2] usb: host: ehci-exynos: Remove unnecessary usb-phy support
Now that we have completely moved from older USB-PHY drivers
to newer GENERIC-PHY drivers for PHYs available with USB controllers
on Exynos series of SoCs, we can remove the support for the same
in our host drivers too.
We also defer the probe for our host in case we end up getting
EPROBE_DEFER error when getting PHYs.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
Acked-by: Alan Stern
---
Changes since v4:
- returning 'ret' instead of PTR_ERR(phy), since ret is nothing but that only.
Changes since v3:
- Addressed review comments by Alan:
-- Skipped renaming 'phy_number' variable,
-- resorted to just adding minimal change required for phy assignment.
-- updated patch description to mention EPROBE_DEFER support.
drivers/usb/host/ehci-exynos.c | 74 +++-
1 file changed, 20 insertions(+), 54 deletions(-)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 2eed9a4..7189f2e 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -21,11 +21,8 @@
#include
#include
#include
-#include
-#include
#include
#include
-#include
#include "ehci.h"
@@ -47,9 +44,7 @@ static struct hc_driver __read_mostly exynos_ehci_hc_driver;
struct exynos_ehci_hcd {
struct clk *clk;
- struct usb_phy *phy;
- struct usb_otg *otg;
- struct phy *phy_g[PHY_NUMBER];
+ struct phy *phy[PHY_NUMBER];
};
#define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)->priv)
@@ -60,8 +55,9 @@ static int exynos_ehci_get_phy(struct device *dev,
struct device_node *child;
struct phy *phy;
int phy_number;
- int ret = 0;
+ int ret;
+ /* Get PHYs for the controller */
for_each_available_child_of_node(dev->of_node, child) {
ret = of_property_read_u32(child, "reg", &phy_number);
if (ret) {
@@ -77,31 +73,21 @@ static int exynos_ehci_get_phy(struct device *dev,
}
phy = devm_of_phy_get(dev, child, NULL);
+ exynos_ehci->phy[phy_number] = phy;
of_node_put(child);
- if (IS_ERR(phy))
- /* Lets fallback to older USB-PHYs */
- goto usb_phy_old;
- exynos_ehci->phy_g[phy_number] = phy;
- /* Make the older PHYs unavailable */
- exynos_ehci->phy = ERR_PTR(-ENXIO);
- }
-
- return 0;
-
-usb_phy_old:
- exynos_ehci->phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(exynos_ehci->phy)) {
- ret = PTR_ERR(exynos_ehci->phy);
- if (ret != -ENXIO && ret != -ENODEV) {
- dev_err(dev, "no usb2 phy configured\n");
- return ret;
+ if (IS_ERR(phy)) {
+ ret = PTR_ERR(phy);
+ if (ret == -EPROBE_DEFER) {
+ return ret;
+ } else if (ret != -ENOSYS && ret != -ENODEV) {
+ dev_err(dev,
+ "Error retrieving usb2 phy: %d\n", ret);
+ return ret;
+ }
}
- dev_dbg(dev, "Failed to get usb2 phy\n");
- } else {
- exynos_ehci->otg = exynos_ehci->phy->otg;
}
- return ret;
+ return 0;
}
static int exynos_ehci_phy_enable(struct device *dev)
@@ -111,16 +97,13 @@ static int exynos_ehci_phy_enable(struct device *dev)
int i;
int ret = 0;
- if (!IS_ERR(exynos_ehci->phy))
- return usb_phy_init(exynos_ehci->phy);
-
for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
- if (!IS_ERR(exynos_ehci->phy_g[i]))
- ret = phy_power_on(exynos_ehci->phy_g[i]);
+ if (!IS_ERR(exynos_ehci->phy[i]))
+ ret = phy_power_on(exynos_ehci->phy[i]);
if (ret)
for (i--; i >= 0; i--)
- if (!IS_ERR(exynos_ehci->phy_g[i]))
- phy_power_off(exynos_ehci->phy_g[i]);
+ if (!IS_ERR(exynos_ehci->phy[i]))
+ phy_power_off(exynos_ehci->phy[i]);
return ret;
}
@@ -131,14 +114,9 @@ static void exynos_ehci_phy_disable(struct device *dev)
struct exynos_ehci_hcd *exynos_ehci = to_exynos_ehci(hcd);
int i;
- if (!IS_ERR(exynos_ehci->phy)) {
- usb_phy_shutdown(exynos_ehci->phy);
- return;
- }
-
for (i = 0; i < PHY_NUMBER; i++)
- if (!IS_ERR(exynos_ehci->phy_g[i]))
- phy_power_off(exynos_ehci->phy_g[i]);
+ if (!IS_ERR(exynos_ehci->phy[i]))
+ phy_power_off(exynos_ehci->phy[i]);
}
static void exynos_setup_vbus_gpio(struct device *dev)
@@ -231,9 +209,6 @@
Re: [PATCH v5 1/2] usb: host: ehci-exynos: Remove unnecessary usb-phy support
On Mon, Sep 29, 2014 at 7:21 AM, Greg KH wrote: > On Thu, Sep 25, 2014 at 10:50:22AM +0530, Vivek Gautam wrote: >> Hi Greg, >> >> >> On Mon, Sep 22, 2014 at 11:15 AM, Vivek Gautam >> wrote: >> > Now that we have completely moved from older USB-PHY drivers >> > to newer GENERIC-PHY drivers for PHYs available with USB controllers >> > on Exynos series of SoCs, we can remove the support for the same >> > in our host drivers too. >> > >> > We also defer the probe for our host in case we end up getting >> > EPROBE_DEFER error when getting PHYs. >> > >> > Signed-off-by: Vivek Gautam >> > Acked-by: Jingoo Han >> > Acked-by: Alan Stern >> > --- >> >> Did this one got missed for usb-next ? >> I can only see "usb: host: ohci-exynos: Remove unnecessary usb-phy support" >> in the next branch. >> >> Ignore me if you have already taken care of this, and plan to queue it up. > > If it's not in my tree already, please resend as I don't have this in my > queue anymore. yea, i don't see it in usb-next. I will resend it then. > > greg k-h > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Best Regards Vivek Gautam Samsung R&D Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 1/2] usb: host: ehci-exynos: Remove unnecessary usb-phy support
On Thu, Sep 25, 2014 at 10:50:22AM +0530, Vivek Gautam wrote: > Hi Greg, > > > On Mon, Sep 22, 2014 at 11:15 AM, Vivek Gautam > wrote: > > Now that we have completely moved from older USB-PHY drivers > > to newer GENERIC-PHY drivers for PHYs available with USB controllers > > on Exynos series of SoCs, we can remove the support for the same > > in our host drivers too. > > > > We also defer the probe for our host in case we end up getting > > EPROBE_DEFER error when getting PHYs. > > > > Signed-off-by: Vivek Gautam > > Acked-by: Jingoo Han > > Acked-by: Alan Stern > > --- > > Did this one got missed for usb-next ? > I can only see "usb: host: ohci-exynos: Remove unnecessary usb-phy support" > in the next branch. > > Ignore me if you have already taken care of this, and plan to queue it up. If it's not in my tree already, please resend as I don't have this in my queue anymore. greg k-h -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/5] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Hi Tomasz,
On Tue, Sep 23, 2014 at 8:19 PM, Tomasz Figa wrote:
> On 23.09.2014 10:16, Abhilash Kesavan wrote:
> [snip]
>> @@ -383,9 +377,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
>> *irqd, unsigned int on)
>> /*
>> * irq_chip for wakeup interrupts
>> */
>> -static struct exynos_irq_chip exynos_wkup_irq_chip = {
>> +static struct exynos_irq_chip *exynos_wkup_irq_chip;
>> +
> [snip]
>> @@ -459,7 +480,7 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
>> struct irq_desc *desc)
>> static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
>> irq_hw_number_t hw)
>> {
>> - irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
>> + irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip->chip,
>> handle_level_irq);
>> irq_set_chip_data(virq, h->host_data);
>> set_irq_flags(virq, IRQF_VALID);
>> @@ -491,7 +512,12 @@ static int exynos_eint_wkup_init(struct
>> samsung_pinctrl_drv_data *d)
>> int idx, irq;
>>
>> for_each_child_of_node(dev->of_node, np) {
>> - if (of_match_node(exynos_wkup_irq_ids, np)) {
>> + const struct of_device_id *match;
>> +
>> + match = of_match_node(exynos_wkup_irq_ids, np);
>> + if (match) {
>> + exynos_wkup_irq_chip = kmemdup(match->data,
>> + sizeof(struct exynos_irq_chip), GFP_KERNEL);
>
> That's not exactly what I had in my mind.
>
> You just changed the code to write to another global variable. This is
> not the best practice and might cause hard to track issues in future,
> when extending the driver.
>
> From what I can see, the best solution would be to add .irq_chip field
> to samsung_pin_bank struct. Then exynos_wkup_irq_map() could access it
> through h->host_data pointer and exynos_irq_demux_eint16_31() could also
> retrieve the irq chip through bank struct without the need too add chip
> field to exynos_muxed_weint_data struct.
>
> As a side effect, it would be possible to consolidate
> exynos_wkup_irqd_ops with exynos_gpio_irqd_ops, which currently only
> differ in irq chip passed as argument to irq_set_chip_and_handler() in
> .map() callback.
I have posted v3 adding a new irq_chip field to the samsung_pin_bank
structure as per your suggestion. Please take a look.
Regards,
Abhilash
>
> Best regards,
> Tomasz
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] serial: samsung: Fix serial config dependencies for exynos7
From: Pankaj Dubey Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Abhilash Kesavan Cc: Greg Kroah-Hartman --- Build tested with s3c6400_defconfig, exynos_defconfig and arm64's defconfig with and without the serial driver enabled. drivers/tty/serial/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 81f6ee7..e6c0bcb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -249,14 +249,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 5/6] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Tomasz Figa
Cc: Linus Walleij
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..c7c41c1
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
[PATCH v3 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Rob Herring Cc: Catalin Marinas Cc: Tomasz Figa Cc: Linus Walleij --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1874e1a..4ee1250 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -146,6 +146,8 @@ config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/6] pinctrl: exynos: Add initial driver data for Exynos7
From: Naveen Krishna Ch
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 113
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
4 files changed, 117 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index f80519a..8425838 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 4ec2d3d..29e6070 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1189,3 +1189,116 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = "exynos5420-gpio-ctrl4",
},
};
+
+/* pin banks of exynos7 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller - BUS0 */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
+};
+
+/* pin banks of exynos7 pin-controller - NFC */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FF */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - ESE */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS0 */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS1 */
+static struct samsung_pin_bank exynos7_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
+};
+
+struct samsung_pin_ctrl exynos7_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos7_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos7-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 BUS0 data */
+ .pin_banks = exynos7_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos7-gpio-ctrl1",
+ }, {
+ /* pin-controller instance 2 NFC data */
+ .pin_banks = exynos7_pin_banks2,
+ .nr_banks = ARR
[PATCH v3 3/6] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 45 +++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 54ebcb6..4ec2d3d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = "samsung,exynos4210-wakeup-eint", },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -385,9 +379,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd,
unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
.chip = {
- .name = "exynos_wkup_irq_chip",
+ .name = "exynos4210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -401,6 +395,31 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ .irq_request_resources = exynos_irq_request_resources,
+ .irq_release_resources = exynos_irq_release_resources,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = "samsung,exynos4210-wakeup-eint",
+ .data = &exynos4210_wkup_irq_chip },
+ { .compatible = "samsung,exynos7-wakeup-eint",
+ .data = &exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -469,12 +488,18 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
struct samsung_pin_bank *bank;
struct exynos_weint_data *weint_data;
struct exynos_muxed_weint_data *muxed_data;
+ struct exynos_irq_chip *exynos_wkup_irq_chip;
unsigned int muxed_banks = 0;
unsigned int i;
int idx, irq;
for_each_child_of_node(dev->of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_wkup_irq_ids, np);
+ if (match) {
+ exynos_wkup_irq_chip = kmemdup(match->data,
+ sizeof(struct exynos_irq_chip), GFP_KERNEL);
wkup_np = np;
break;
}
@@ -494,7 +519,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
return -ENXIO;
[PATCH v3 2/6] pinctrl: exynos: Consolidate irq domain callbacks
Adding a irq_chip field to the samsung_pin_bank struct helps in
consolidating the irq domain callbacks for external gpio and wakeup
interrupt controllers. The exynos_wkup_irqd_ops and exynos_gpio_irqd_ops
have now been merged into a single exynos_eint_irqd_ops.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 32 ++
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 14b9b44..54ebcb6 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -254,7 +254,7 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = {
.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
};
-static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct samsung_pin_bank *b = h->host_data;
@@ -267,10 +267,10 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
}
/*
- * irq domain callbacks for external gpio interrupt controller.
+ * irq domain callbacks for external gpio and wakeup interrupt controllers.
*/
-static const struct irq_domain_ops exynos_gpio_irqd_ops = {
- .map= exynos_gpio_irq_map,
+static const struct irq_domain_ops exynos_eint_irqd_ops = {
+ .map= exynos_eint_irq_map,
.xlate = irq_domain_xlate_twocell,
};
@@ -330,7 +330,7 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_gpio_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "gpio irq domain add failed\n");
ret = -ENXIO;
@@ -457,26 +457,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- struct samsung_pin_bank *b = h->host_data;
-
- irq_set_chip_and_handler(virq, &b->irq_chip->chip,
- handle_level_irq);
- irq_set_chip_data(virq, h->host_data);
- set_irq_flags(virq, IRQF_VALID);
- return 0;
-}
-
-/*
- * irq domain callbacks for external wakeup interrupt controller.
- */
-static const struct irq_domain_ops exynos_wkup_irqd_ops = {
- .map= exynos_wkup_irq_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
/*
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
@@ -508,7 +488,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_wkup_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/6] pinctrl: exynos: Generalize the eint16_31 demux code
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask register
offset values from the exynos_irq_chip structure. This is done by adding a
irq_chip field to the samsung_pin_bank struct.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 14 ++
drivers/pinctrl/samsung/pinctrl-samsung.h |2 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d7154ed..14b9b44 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -260,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
struct samsung_pin_bank *b = h->host_data;
irq_set_chip_data(virq, b);
- irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID);
return 0;
@@ -344,6 +344,8 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
ret = -ENOMEM;
goto err_domains;
}
+
+ bank->irq_chip = &exynos_gpio_irq_chip;
}
return 0;
@@ -445,9 +447,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
- pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
+ pend = readl(d->virt_base + b->irq_chip->eint_pend
+ b->eint_offset);
- mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
+ mask = readl(d->virt_base + b->irq_chip->eint_mask
+ b->eint_offset);
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
@@ -458,7 +460,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
- irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
+ struct samsung_pin_bank *b = h->host_data;
+
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
irq_set_chip_data(virq, h->host_data);
set_irq_flags(virq, IRQF_VALID);
@@ -510,6 +514,8 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
return -ENXIO;
}
+ bank->irq_chip = &exynos_wkup_irq_chip;
+
if (!of_find_property(bank->of_node, "interrupts", NULL)) {
bank->eint_type = EINT_TYPE_WKUP_MUX;
++muxed_banks;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h
b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 5cedc9d..d2c38c8 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -127,6 +127,7 @@ struct samsung_pin_bank_type {
* @irq_domain: IRQ domain of the bank.
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
+ * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
* @slock: spinlock protecting bank registers
* @pm_save: saved register values during suspend
*/
@@ -146,6 +147,7 @@ struct samsung_pin_bank {
struct irq_domain *irq_domain;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
+ struct exynos_irq_chip *irq_chip;
spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/6] Add initial support for pinctrl on Exynos7
Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140926). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) "tty/serial: fix config dependencies for samsung serial" https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) "dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 799 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey wrote:
> Hi Chanwoo,
>
> On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
>> To: Pankaj Dubey
>> Cc: linux-arm-ker...@lists.infradead.org;
> linux-samsung-soc@vger.kernel.org;
>> kgene@samsung.com; tomasz.f...@gmail.com; robh...@kernel.org;
>> li...@arm.linux.org.uk; naus...@samsung.com; Mike Turquette; Sylwester
>> Nawrocki
>> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
> clocks
>>
>> Hi Pankaj,
>>
>> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
>> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
>> > missing clock entries for UART2 and UART3.
>> >
>> > CC: Mike Turquette
>> > CC: Sylwester Nawrocki
>> > Signed-off-by: Pankaj Dubey
>> > ---
>> > drivers/clk/samsung/clk-exynos3250.c | 11 +++
>> > include/dt-bindings/clock/exynos3250.h | 10 +-
>> > 2 files changed, 20 insertions(+), 1 deletion(-)
>>
>> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
>>
>
> As per Exynos3250 user manual that I have with me it supports UART(0,1,2,3).
> It has been mentioned
which UM do you use? There are two UARTs at rev0.01
> in UART Chapter as well as CMU IP details also mentioned about the clock
> entries. We have tested it
> also on Espresso3250 board which is based on Exynos3250 SoC.
I can't find it at my UM.
Kyungmin Park
>
> Thanks,
> Pankaj Dubey
>
>> Thanks,
>> Chanwoo Choi
>>
>> >
>> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
>> > b/drivers/clk/samsung/clk-exynos3250.c
>> > index dc85f8e..0722fef 100644
>> > --- a/drivers/clk/samsung/clk-exynos3250.c
>> > +++ b/drivers/clk/samsung/clk-exynos3250.c
>> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
> __initdata =
>> {
>> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>> >
>> > /* SRC_PERIL0 */
>> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
>> 12, 4),
>> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8,
>> 4),
>> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4,
>> 4),
>> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0,
>> 4),
>> >
>> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
> __initdata = {
>> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> >
>> > /* DIV_PERIL0 */
>> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
>> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
>> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>> >
>> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
> __initdata
>> = {
>> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
>> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
>> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7
>> @@
>> > static struct samsung_gate_clock gate_clks[] __initdata = {
>> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0,
>> 0),
>> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
>> 0, 0),
>> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
>> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0,
>> 0),
>> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0,
>> 0),
>> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0,
>> 0),
>> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
>> @@
>> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata
> = {
>> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
>> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
>> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
>> > }; diff --git a/include/dt-bindings/clock/exynos3250.h
>> > b/include/dt-bindings/clock/exynos3250.h
>> > index b535e9d..ffeb695 100644
>> > --- a/include/dt-bindings/clock/exynos3250.h
>> > +++ b/include/dt-bindings/clock/exynos3250.h
>> > @@ -78,6 +78,8 @@
>> > #define CLK_MOUT_CORE 58
>> > #define CLK_MOUT_APLL 59
>> > #defi
RE: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
Hi Chanwoo,
On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
> To: Pankaj Dubey
> Cc: linux-arm-ker...@lists.infradead.org;
linux-samsung-soc@vger.kernel.org;
> kgene@samsung.com; tomasz.f...@gmail.com; robh...@kernel.org;
> li...@arm.linux.org.uk; naus...@samsung.com; Mike Turquette; Sylwester
> Nawrocki
> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
clocks
>
> Hi Pankaj,
>
> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> > missing clock entries for UART2 and UART3.
> >
> > CC: Mike Turquette
> > CC: Sylwester Nawrocki
> > Signed-off-by: Pankaj Dubey
> > ---
> > drivers/clk/samsung/clk-exynos3250.c | 11 +++
> > include/dt-bindings/clock/exynos3250.h | 10 +-
> > 2 files changed, 20 insertions(+), 1 deletion(-)
>
> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
>
As per Exynos3250 user manual that I have with me it supports UART(0,1,2,3).
It has been mentioned
in UART Chapter as well as CMU IP details also mentioned about the clock
entries. We have tested it
also on Espresso3250 board which is based on Exynos3250 SoC.
Thanks,
Pankaj Dubey
> Thanks,
> Chanwoo Choi
>
> >
> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
> > b/drivers/clk/samsung/clk-exynos3250.c
> > index dc85f8e..0722fef 100644
> > --- a/drivers/clk/samsung/clk-exynos3250.c
> > +++ b/drivers/clk/samsung/clk-exynos3250.c
> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
__initdata =
> {
> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
> >
> > /* SRC_PERIL0 */
> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
> 12, 4),
> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8,
> 4),
> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4,
> 4),
> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0,
> 4),
> >
> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
__initdata = {
> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> >
> > /* DIV_PERIL0 */
> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
> >
> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
__initdata
> = {
> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7
> @@
> > static struct samsung_gate_clock gate_clks[] __initdata = {
> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0,
> 0),
> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
> 0, 0),
> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0,
> 0),
> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0,
> 0),
> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0,
> 0),
> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> @@
> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata
= {
> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> > }; diff --git a/include/dt-bindings/clock/exynos3250.h
> > b/include/dt-bindings/clock/exynos3250.h
> > index b535e9d..ffeb695 100644
> > --- a/include/dt-bindings/clock/exynos3250.h
> > +++ b/include/dt-bindings/clock/exynos3250.h
> > @@ -78,6 +78,8 @@
> > #define CLK_MOUT_CORE 58
> > #define CLK_MOUT_APLL 59
> > #define CLK_MOUT_ACLK_266_SUB 60
> > +#define CLK_MOUT_UART2 61
> > +#define CLK_MOUT_UART3 62
> >
> > /* Dividers */
> > #define CLK_DIV_GPL64
> > @@ -126,6 +128,8 @@
> > #define CLK_DIV_CORE
Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
Hi Pankaj,
On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> missing clock entries for UART2 and UART3.
>
> CC: Mike Turquette
> CC: Sylwester Nawrocki
> Signed-off-by: Pankaj Dubey
> ---
> drivers/clk/samsung/clk-exynos3250.c | 11 +++
> include/dt-bindings/clock/exynos3250.h | 10 +-
> 2 files changed, 20 insertions(+), 1 deletion(-)
Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
Thanks,
Chanwoo Choi
>
> diff --git a/drivers/clk/samsung/clk-exynos3250.c
> b/drivers/clk/samsung/clk-exynos3250.c
> index dc85f8e..0722fef 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
> MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>
> /* SRC_PERIL0 */
> + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
> + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
> MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
> MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>
> @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[] __initdata = {
> DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>
> /* DIV_PERIL0 */
> + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
> + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>
> @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[] __initdata
> = {
> GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> @@ -679,6 +687,7 @@ static struct samsung_gate_clock gate_clks[] __initdata =
> {
> GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
> GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
> GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
> GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
> GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
> GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> @@ -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata =
> {
> GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
> + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> };
> diff --git a/include/dt-bindings/clock/exynos3250.h
> b/include/dt-bindings/clock/exynos3250.h
> index b535e9d..ffeb695 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -78,6 +78,8 @@
> #define CLK_MOUT_CORE58
> #define CLK_MOUT_APLL59
> #define CLK_MOUT_ACLK_266_SUB60
> +#define CLK_MOUT_UART2 61
> +#define CLK_MOUT_UART3 62
>
> /* Dividers */
> #define CLK_DIV_GPL 64
> @@ -126,6 +128,8 @@
> #define CLK_DIV_CORE 107
> #define CLK_DIV_HPM 108
> #define CLK_DIV_COPY 109
> +#define CLK_DIV_UART2110
> +#define CLK_DIV_UART3111
>
> /* Gates */
> #define CLK_ASYNC_G3D128
> @@ -222,6 +226,8 @@
> #define CLK_BLOCK_MFC219
> #define CLK_BLOCK_CAM220
> #define CLK_SMIES221
> +#define CLK_UART2222
> +#define CLK_UART3223
>
> /* Special clocks */
> #define CLK_SCLK_JPEG224
> @@ -248,11 +254,13 @@
> #define CLK_SCLK_SPI0245
> #define CLK_SCLK_UART1 246
> #define CLK_SCLK_UART0
