From: Thierry Reding tred...@nvidia.com
struct mipi_dsi_msg is a read-only structure, drivers should never need
to modify it. Make this explicit by making all references to the struct
const.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 +-
On Thu, Oct 09, 2014 at 11:40:17PM +0200, Javier Martinez Canillas wrote:
On 10/09/2014 07:48 PM, Mark Brown wrote:
On Thu, Oct 09, 2014 at 04:27:37PM +0200, Javier Martinez Canillas wrote:
only two modes: ON and OFF (and some of them have a third Low Power mode).
...but let's be clear,
On 10/13/2014 12:16 PM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
struct mipi_dsi_msg is a read-only structure, drivers should never need
to modify it. Make this explicit by making all references to the struct
const.
Signed-off-by: Thierry Reding tred...@nvidia.com
Changes in v3:
-Rework the entire intermediate step which was suggested in v2.
That means solving the race condition, but also cope with PM domains
that are initialized in powered off state.
Changes in v2:
-Added some acks.
-Updated commit messages.
There may be more than one device in a PM domain which then will be
probed at different points in time.
Depending on timing and runtime PM support, in for the device related
driver/subsystem, a PM domain may be advised to power off after a
successful probe sequence.
A general requirement for a
To provide users control over whether the power should be maintained,
implement the -get|put() callbacks for genpd's PM domain.
A usage count variable keeps track of the number of users. A positive
value tells genpd to keep supplying power and also to power up if it's
the first user.
Do note,
To sucessfully probe some devices their corresponding PM domains may
need to be powered.
Use the dev_pm_domain_get|put() APIs, to control the behavior of the PM
domain.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/spi/spi.c | 7 +++
1 file changed, 7 insertions(+)
diff
There are currently no users of this API, let's remove it.
Additionally, if such feature would be needed future wise, a better
option is likely use pm_runtime_set_active|suspended() in some form.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
Acked-by: Geert Uytterhoeven
To sucessfully probe some devices their corresponding PM domains may
need to be powered.
Use the dev_pm_domain_get|put() APIs, to control the behavior of the PM
domain.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/i2c/i2c-core.c | 7 +++
1 file changed, 7 insertions(+)
To sucessfully probe some devices their corresponding PM domains may
need to be powered.
Use the dev_pm_domain_get|put() APIs, to control the behavior of the PM
domain.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/amba/bus.c | 8
1 file changed, 8 insertions(+)
diff
To sucessfully probe some devices their corresponding PM domains may
need to be powered.
Use the dev_pm_domain_get|put() APIs, to control the behavior of the PM
domain.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/mmc/core/sdio_bus.c | 7 +++
1 file changed, 7 insertions(+)
To sucessfully probe some devices their corresponding PM domains may
need to be powered.
Use the dev_pm_domain_get|put() APIs, to control the behavior of the PM
domain.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/base/platform.c | 7 +++
1 file changed, 7 insertions(+)
Align the behvaior to how other buses are handling attachment of PM
domains. Additionally, let's add error handling.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/mmc/core/sdio_bus.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git
Hi,
On Mon, Oct 13, 2014 at 01:54:59PM +0900, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver.
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk
Hello,
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver.
Hi Tomasz,
On Tue, Oct 14, 2014 at 6:56 AM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the
Hi Felipe,
On Tue, Oct 14, 2014 at 4:14 AM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Mon, Oct 13, 2014 at 01:54:59PM +0900, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As
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