On czw, 2014-10-23 at 19:20 +0300, Grygorii Strashko wrote:
Hi Krzysztof,
On 10/23/2014 04:48 PM, Krzysztof Kozlowski wrote:
When resuming the system the power domain has to be powered on early so
any runtime PM aware devices could resume.
This fixes following scenario reproduced on
Initialize all structures and register to iommu subsystem only on Exynos
compatible platforms.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Acked-by: Arnd Bergmann a...@arndb.de
---
drivers/iommu/exynos-iommu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
On 20/10/14 05:32, Chanwoo Choi wrote:
The Exynos4415 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.
I think the above text is not relevant, DT binding is
Hi Sylwester,
On 10/24/2014 07:32 PM, Sylwester Nawrocki wrote:
On 20/10/14 05:32, Chanwoo Choi wrote:
The Exynos4415 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are
On 20/10/14 05:32, Chanwoo Choi wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
and function clocks for
On 10/24/2014 07:54 PM, Sylwester Nawrocki wrote:
On 20/10/14 05:32, Chanwoo Choi wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system
This patch adds new clock controller device driver for Exynos4415 SoC.
Changes from v1:
- Separate only clock patches from Exynos4415 patchset[1]
[1] [PATCH 0/5] Support new Exynos4415 SoC based on Cortex-A9 quad cores
: https://lkml.org/lkml/2014/10/19/253
- Fix string issue on documentation
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
and function clocks for individual IPs.
Cc: Sylwester Nawrocki
This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
This patch add support for device tree sources for Samsung Rinato baord
(Gear 2) based on Exynos3250 SoC.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC
This patchset adds new board dts file for Samsung Rinato board (Gear 2) which
is based on Exynos3250 SoC and adds sleep mode pin configuration using pinctrl
subsystem to reduce leakage power-consumption in sleep state.
This patchset is based on linux-samsung.git (for-next branch).
Changes from
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park Kyungmin p...@samsung.com
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 16
This patch add sleep mode of regulator for exynos3250-rinato board to optimize
power-consumption in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Mark Brown broo...@kernel.org
---
Hi Chanwoo,
On 20.10.2014 05:32, Chanwoo Choi wrote:
This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC
processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a
target
speed of 1.6GHz and provides 8.5GB/s memory bandwidth.
Cc: Kukjin Kim
Hi Tomasz,
On 10/24/2014 08:43 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 20.10.2014 05:32, Chanwoo Choi wrote:
This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC
processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a
target
speed of 1.6GHz and
Hi Chanwoo,
On 24.10.2014 13:39, Chanwoo Choi wrote:
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park Kyungmin p...@samsung.com
I
Hi Tomasz,
On 10/24/2014 08:48 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 24.10.2014 13:39, Chanwoo Choi wrote:
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
On 24.10.2014 13:39, Chanwoo Choi wrote:
This patch add support for device tree sources for Samsung Rinato baord
(Gear 2) based on Exynos3250 SoC.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
-
On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Can you please pick this series up.
Yes, sorry for the delay. I've applied patches
1,2,3,4. The patches to the DTS files should be taken
through whatever tree funnels arm64 dts files.
I hope Tomasz can rebase
On Wed, Oct 8, 2014 at 12:23 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Thu, Oct 2, 2014 at 8:52 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This series intends to clean up data structures used by pinctrl-samsung
driver.
More specifically, it separates initial compile time
On 24/10/14 13:07, Chanwoo Choi wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
and function clocks for
Hi Krzysztof,
On 10/24/2014 08:57 PM, Krzysztof Kozłowski wrote:
On 24.10.2014 13:39, Chanwoo Choi wrote:
This patch add support for device tree sources for Samsung Rinato baord
(Gear 2) based on Exynos3250 SoC.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
Hi Linus,
On 24.10.2014 14:01, Linus Walleij wrote:
On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Can you please pick this series up.
Yes, sorry for the delay. I've applied patches
1,2,3,4. The patches to the DTS files should be taken
through
Hi Sylwester,
On 10/24/2014 09:03 PM, Sylwester Nawrocki wrote:
On 24/10/14 13:07, Chanwoo Choi wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and
This patchset adds new board dts file for Samsung Rinato board (Gear 2) which
is based on Exynos3250 SoC and adds sleep mode pin configuration using pinctrl
subsystem to reduce leakage power-consumption in sleep state.
This patchset is based on linux-samsung.git (for-next branch).
Changes from
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 16
This patch add sleep mode of regulator for exynos3250-rinato board to optimize
power-consumption in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Mark Brown broo...@kernel.org
---
This patch add support for device tree sources for Samsung Rinato baord
(Gear 2) based on Exynos3250 SoC.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds new exynos4415.dtsi to support Exynos4415 SoC
based on Cortex-A9 quad cores and includes following dt nodes:
There's a lot in common between your new exynos4415.dtsi and the
existing exynos4.dtsi.
Would
On 23/10/14 20:41, Stephen Boyd wrote:
On 10/23/2014 07:06 AM, Russell King - ARM Linux wrote:
On Thu, Oct 23, 2014 at 03:51:16PM +0200, Marcin Jabrzyk wrote:
[1.] One line summary of the problem: BUG: sleeping function called from
invalid context at mm/slub.c:1250 after CPU hotplug
I'm
On 24.10.2014 15:18, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked
On 24.10.2014 15:23, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds new exynos4415.dtsi to support Exynos4415 SoC
based on Cortex-A9 quad cores and includes following dt nodes:
There's a lot in common between your new
Hello,
On 2014-10-24 15:23, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds new exynos4415.dtsi to support Exynos4415 SoC
based on Cortex-A9 quad cores and includes following dt nodes:
There's a lot in common between your new
Hi Daniel,
On 10/24/2014 10:18 PM, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls
On Fri, Oct 24, 2014 at 7:34 AM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
Well, I also thought about such approach, but there are some fundamental
differences:
interrupt and clock controllers are completely different. Using a common
exynos4.dtsi
and overriding them in every node will
Hi Daniel,
On 10/24/2014 10:23 PM, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds new exynos4415.dtsi to support Exynos4415 SoC
based on Cortex-A9 quad cores and includes following dt nodes:
There's a lot in common between your
On 24/10/14 15:18, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked
Hi Sylwester,
On 10/24/2014 09:03 PM, Sylwester Nawrocki wrote:
On 24/10/14 13:07, Chanwoo Choi wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and
Hi Chanwoo,
On 24/10/14 16:07, Chanwoo Choi wrote:
[...]
How about prefixing the table names below with exynos4415, rather than
samsung ?
'struct samsung_fixed_factor_clock' is common for Exynos SoC.
Do you means that add 'exynos4415' prefix as following:
- fixed_factor_clks -
+Sylwester
On Wed, Oct 8, 2014 at 11:18 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Tomasz,
On Tue, Oct 7, 2014 at 9:46 AM, Kukjin Kim kg...@kernel.org wrote:
Tomasz Figa wrote:
On 30.09.2014 17:12, Abhilash Kesavan wrote:
Hi Tomasz,
On Mon, Sep 22, 2014 at 2:22 PM,
Hi Linus,
On Fri, Oct 24, 2014 at 5:31 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Can you please pick this series up.
Yes, sorry for the delay. I've applied patches
1,2,3,4. The patches to the DTS
Hello Kevin,
On Thu, Oct 23, 2014 at 9:26 PM, Kevin Hilman khil...@kernel.org wrote:
Abhilash Kesavan a.kesa...@samsung.com writes:
The change was based on my reading of the platsmp file of the
Odroid-xu3 3.10 kernel and issues experienced previously. From what I
understand, the platsmp code
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
On Thu, Oct 23, 2014 at 9:26 PM, Kevin Hilman khil...@kernel.org wrote:
Abhilash Kesavan a.kesa...@samsung.com writes:
The change was based on my reading of the platsmp file of the
Odroid-xu3 3.10 kernel and issues experienced previously.
Ulf Hansson ulf.hans...@linaro.org writes:
Changes in v3:
-Rework the entire intermediate step which was suggested in v2.
That means solving the race condition, but also cope with PM domains
that are initialized in powered off state.
Changes in v2:
-Added some
On Fri, Oct 24, 2014 at 09:12:39AM -0700, Kevin Hilman wrote:
Ulf Hansson ulf.hans...@linaro.org writes:
There may be more than one device in a PM domain which then will be
probed at different points in time.
Depending on timing and runtime PM support, in for the device related
On Thu, Oct 23, 2014 at 11:28:09AM +0200, Javier Martinez Canillas wrote:
Please fix your mailer to word wrap within paragraphs - you should know
this by now :/ I've reflowed for legibility.
However this is an implementation detail and should not change the DT
bindings in the current version.
-Original Message-
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
Excessive debug messages might cause timing issues that prevent correct
usb enumeration. This patch hides information about USB bus reset to let
driver enumerate
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
This patch removes duplicated code and sets last_rst variable in the
function which does the hardware reset.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
This patch changes s3c_hsotg_core_init function to leave hardware in
soft disconnect mode, so the moment of coupling the hardware to the usb
bus can be later controlled by the separate functions
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
This patch moves phy enable/disable calls from pullup() method to
udc_start/stop functions. This solves the issue related to limited caller
context for PHY functions, because they cannot be
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
This patch moves udc initialization from pullup() method to
s3c_hsotg_udc_start(), so that method ends with hardware fully
initialized and left in soft-disconnected state. After this change, the
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
This patch moves calls to phy enable/disable out of spinlock protected
blocks in device suspend/resume to fix incorrect caller context. Phy
related functions must not be called from atomic
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
Suspend/resume code assumed that the gadget was always enabled and
connected to usb bus. This means that the actual state of the gadget
(soft-enabled/disabled or connected/disconnected) was not
From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
Sent: Monday, October 20, 2014 3:46 AM
This patch adds a call to s3c_hsotg_disconnect() from 'end session'
interrupt (GOTGINT_SES_END_DET) to correctly notify gadget subsystem
about unplugged usb cable. 'disconnected' interrupt
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