Re: [PATCH] ASoC: rt5631: Fixing compilation warning when DT is disabled
FYI your Suggestion was: You need to add an ifdef around the struct (or perhaps a __maybey_unused type annotation if there's something suitable) for such configurations. Following your suggestion I have sent a patch (187024b36c635bd454c1b1587b58c9439d3a46ad on your git, branch: rt5631 ) using ifdef which you have already applied. Since there are more suggestion asking for second (__maybe_unused) method, I have sent another patch for which below is the link. You may be applying the second patch on the already applied first patch. so I request you to apply only second patch in place of first and abandon first patch. Already applied patch in your git: http://www.spinics.net/lists/linux-samsung-soc/msg39044.html [pls remove this and instead apply the below mentioned patch] Patch to apply: http://www.spinics.net/lists/linux-samsung-soc/msg39465.html -Krishna -- From: Mark Brown broo...@kernel.org Sent: Monday, November 24, 2014 10:34 PM To: Krishna Mohan Dani krishna...@samsung.com Cc: linux-samsung-soc@vger.kernel.org; linux-arm-ker...@lists.infradead.org; alsa-de...@alsa-project.org; kgene@samsung.com; Claude Youn claude.y...@gmail.com Subject: Re: [PATCH] ASoC: rt5631: Fixing compilation warning when DT is disabled On Mon, Nov 24, 2014 at 04:52:42PM +0530, Krishna Mohan Dani wrote: Fixes the following compilation warning: Warning: 'rt5631_i2c_dt_ids' defined but not used - when DT is not used. This doesn't apply, please check and resend. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: Samsung: Add arndale_rt5631 machine driver and binding
Adding machine driver to instantiate I2S based realtek's ALC5631
sound card on Arndale board.
There are other variants of Audio Daughter Cards for Arndale
Board for which support already exists but there is no support for
Realtek's alc5631 codec hence support for ALC5631 based machine
driver is being added.
This patch also documents the device tree binding for the Arndale
board based machine driver.
Signed-off-by: Claude Youn claude.y...@gmail.com
Signed-off-by: Krishna Mohan Dani krishna...@samsung.com
---
.../devicetree/bindings/sound/arndale.txt | 24
sound/soc/samsung/Kconfig |6 +
sound/soc/samsung/Makefile |2 +
sound/soc/samsung/arndale_rt5631.c | 150
4 files changed, 182 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/arndale.txt
create mode 100644 sound/soc/samsung/arndale_rt5631.c
diff --git a/Documentation/devicetree/bindings/sound/arndale.txt
b/Documentation/devicetree/bindings/sound/arndale.txt
new file mode 100644
index 000..0e76946
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/arndale.txt
@@ -0,0 +1,24 @@
+Audio Binding for Arndale boards
+
+Required properties:
+- compatible : Can be the following,
+ samsung,arndale-rt5631
+
+- samsung,audio-cpu: The phandle of the Samsung I2S controller
+- samsung,audio-codec: The phandle of the audio codec
+
+Optional:
+- samsung,model: The name of the sound-card
+
+Arndale Boards has many audio daughter cards, one of them is
+rt5631/alc5631. Below example shows audio bindings for rt5631/
+alc5631 based codec.
+
+Example:
+
+sound {
+ compatible = samsung,arndale-rt5631;
+
+ samsung,audio-cpu = i2s0
+ samsung,audio-codec = rt5631;
+};
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 55a3869..80b5c61 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -239,3 +239,9 @@ config SND_SOC_ODROIDX2
select SND_SAMSUNG_I2S
help
Say Y here to enable audio support for the Odroid-X2/U3.
+
+config SND_SOC_ARNDALE_RT5631_ALC5631
+tristate Audio support for RT5631(ALC5631) on Arndale Board
+depends on SND_SOC_SAMSUNG
+select SND_SAMSUNG_I2S
+select SND_SOC_RT5631
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index 91505dd..31e3dba 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -45,6 +45,7 @@ snd-soc-lowland-objs := lowland.o
snd-soc-littlemill-objs := littlemill.o
snd-soc-bells-objs := bells.o
snd-soc-odroidx2-max98090-objs := odroidx2_max98090.o
+snd-soc-arndale-rt5631-objs := arndale_rt5631.o
obj-$(CONFIG_SND_SOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o
obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
@@ -71,3 +72,4 @@ obj-$(CONFIG_SND_SOC_LOWLAND) += snd-soc-lowland.o
obj-$(CONFIG_SND_SOC_LITTLEMILL) += snd-soc-littlemill.o
obj-$(CONFIG_SND_SOC_BELLS) += snd-soc-bells.o
obj-$(CONFIG_SND_SOC_ODROIDX2) += snd-soc-odroidx2-max98090.o
+obj-$(CONFIG_SND_SOC_ARNDALE_RT5631_ALC5631) += snd-soc-arndale-rt5631.o
diff --git a/sound/soc/samsung/arndale_rt5631.c
b/sound/soc/samsung/arndale_rt5631.c
new file mode 100644
index 000..1e2b61c
--- /dev/null
+++ b/sound/soc/samsung/arndale_rt5631.c
@@ -0,0 +1,150 @@
+/*
+ * arndale_rt5631.c
+ *
+ * Copyright (c) 2014, Insignal Co., Ltd.
+ *
+ * Author: Claude cla...@insginal.co.kr
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/clk.h
+
+#include sound/soc.h
+#include sound/soc-dapm.h
+#include sound/pcm.h
+#include sound/pcm_params.h
+
+#include i2s.h
+
+static int arndale_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream-private_data;
+ struct snd_soc_dai *cpu_dai = rtd-cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd-codec_dai;
+ int rfs, ret;
+ unsigned long rclk;
+
+ rfs = 256;
+
+ rclk = params_rate(params) * rfs;
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK,
+ 0, SND_SOC_CLOCK_OUT);
+ if (ret 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_RCLKSRC_0,
+ 0, SND_SOC_CLOCK_OUT);
+
+ if (ret 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT);
+ if (ret 0)
+ return ret;
+
+ return 0;
+}
+
+static struct snd_soc_ops arndale_ops = {
+ .hw_params =
Re: [RFC] ARM: exynos: MCPM: [is this a] fix for secondary boot on 5422?
Kevin Hilman khilman at kernel.org writes: From: Kevin Hilman khilman at linaro.org Using the current exynos_defconfig on the exynos5422-odroid-xu3, only 6 of 8 CPUs come online with MCPM boot. CPU0 is an A7, CPUs 1-4 are A15s and CPU5-7 are the other A7s, but with the current code, CPUs 5 and 7 do not boot: [...] Exynos MCPM support installed CPU1: update cpu_capacity 1535 CPU1: thread -1, cpu 0, socket 0, mpidr 8000 CPU2: update cpu_capacity 1535 CPU2: thread -1, cpu 1, socket 0, mpidr 8001 CPU3: update cpu_capacity 1535 CPU3: thread -1, cpu 2, socket 0, mpidr 8002 CPU4: update cpu_capacity 1535 CPU4: thread -1, cpu 3, socket 0, mpidr 8003 CPU5: failed to come online CPU6: update cpu_capacity 448 CPU6: thread -1, cpu 2, socket 1, mpidr 8102 CPU7: failed to come online Brought up 6 CPUs CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13) CPU: This may indicate a broken bootloader or firmware. Thanks to a tip from Abhilash, this patch gets all 8 CPUs booting again, but the warning about CPUs started in inconsistent modes remains. Also, not being terribly familiar with Exynos internals, it's not at all obvious to me why this register write (done for *all* secondaries) makes things work works for the 2 secondary CPUs that didn't come online. It's also not obvious whether this is the right general fix, since it doesn't seem to be needed on other 542x or 5800 platforms. Hi, Very interesting to see your post. I was also suffering from the same problem with my Odroid-XU3 board. With your patch 8 CPUs are brought up, but Cortex-A15 CPUs are always offline, showing low performance. heesub@odroid:~$ cat /sys/devices/system/cpu/online 0,5-7 heesub@odroid:~$ cat /sys/devices/system/cpu/offline 1-4 Any suggestion? Thanks a lot!! Heesub -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] dmaengine: pl330: Set residue in tx_status callback
Fill txstate.residue with the amount of bytes remaining in the current
transfer if the transfer is not complete. This will be of particular
use to i2s DMA transfers, providing more accurate hw_ptr values to ASoC.
I had taken the code from Dylan Reid dgr...@chromium.org patch from the
below link and modified according to the current dmaengine framework.
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/23007
Cc: Dylan Reid dgr...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This patch has been tested for audio playback on exynos5420 peach-pit.
drivers/dma/pl330.c | 67 +-
1 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index b7493d2..db880ae 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2182,11 +2182,74 @@ static void pl330_free_chan_resources(struct dma_chan
*chan)
pm_runtime_put_autosuspend(pch-dmac-ddma.dev);
}
+static inline int
+pl330_src_addr_in_desc(struct dma_pl330_desc *desc, unsigned int sar)
+{
+ return ((desc-px.src_addr = sar)
+ (sar = (desc-px.src_addr + desc-px.bytes)));
+}
+
+static inline int
+pl330_dst_addr_in_desc(struct dma_pl330_desc *desc, unsigned int dar)
+{
+ return ((desc-px.dst_addr = dar)
+ (dar = (desc-px.dst_addr + desc-px.bytes)));
+}
+
static enum dma_status
pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
- return dma_cookie_status(chan, cookie, txstate);
+ dma_addr_t sar, dar;
+ struct dma_pl330_chan *pch = to_pchan(chan);
+ void __iomem *regs = pch-dmac-base;
+ struct pl330_thread *thrd = pch-thread;
+ struct dma_pl330_desc *desc;
+ unsigned int residue = 0;
+ unsigned long flags;
+ bool first = true;
+ dma_cookie_t first_c, current_c;
+ dma_cookie_t used;
+ enum dma_status ret;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+ list_for_each_entry(desc, pch-work_list, node) {
+ if (desc-status == BUSY) {
+ current_c = desc-txd.cookie;
+ if (first) {
+ first_c = desc-txd.cookie;
+ first = false;
+ }
+
+ if (first_c current_c)
+ residue += desc-px.bytes;
+ else {
+ if (desc-rqcfg.src_inc
pl330_src_addr_in_desc(desc, sar)) {
+ residue += desc-px.bytes;
+ residue -= sar - desc-px.src_addr;
+ } else if (desc-rqcfg.dst_inc
pl330_dst_addr_in_desc(desc, dar)) {
+ residue += desc-px.bytes;
+ residue -= dar - desc-px.dst_addr;
+ }
+ }
+ } else if (desc-status == PREP)
+ residue += desc-px.bytes;
+
+ if (desc-txd.cookie == used)
+ break;
+ }
+ spin_unlock_irqrestore(pch-lock, flags);
+ dma_set_residue(txstate, residue);
+ return ret;
}
static void pl330_issue_pending(struct dma_chan *chan)
@@ -2631,7 +2694,7 @@ static int pl330_dma_device_slave_caps(struct dma_chan
*dchan,
caps-directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
caps-cmd_pause = false;
caps-cmd_terminate = true;
- caps-residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ caps-residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
return 0;
}
--
1.7.4.4
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Re: [RESEND,2/7] ARM: Exynos: add support for sub-power domains
+CC: Amit Daniel Kachhap
Hi Andrzej,
On Monday 24 November 2014 01:00 PM, Andrzej Hajda wrote:
From: Marek Szyprowski m.szyprow...@samsung.com
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP, which needs to have more than one power
domain enabled to be operational.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 2 ++
arch/arm/mach-exynos/pm_domains.c | 9 -
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index abde1ea..cad9476 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,8 @@ Optional Properties:
- pclkN, clkN: Pairs of parent of input clock and input clock to the
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
are supported currently.
+- power-domain-master: phandle to a master power domain that the given domain
+ is a part of
If you are trying to make parent, child relationship using this, please
have a look to following thread [1] where Amit also trying to make such
attempt and some discussion are happening on this thread, so that we can
come up with single approach for all such needs.
[1]: https://patchwork.kernel.org/patch/5366171/
Thanks,
Pankaj Dubey
Node of a device using power domains must have a samsung,power-domain property
defined with a phandle to respective power domain.
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index 20f2671..373ac62 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -108,7 +108,7 @@ static int exynos_pd_power_off(struct generic_pm_domain
*domain)
static __init int exynos4_pm_init_power_domain(void)
{
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np, *master_np;
for_each_compatible_node(np, NULL, samsung,exynos4210-pd) {
struct exynos_pm_domain *pd;
@@ -159,6 +159,13 @@ no_clk:
pm_genpd_init(pd-pd, NULL, !on);
of_genpd_add_provider_simple(np, pd-pd);
+
+ /* make master and slave hierarchy */
+ master_np = of_parse_phandle(np, power-domain-master, 0);
+ if (master_np) {
+ pm_genpd_add_subdomain_names(master_np-name, np-name);
+ of_node_put(master_np);
+ }
}
return 0;
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[PATCH 3/4] clk: samsung: add cpu clock support for Exynos7
The divider and mux register offsets and bits are different on
Exynos7 from the older SoCs. Add new pre/post rate change callbacks
for Exynos7 to handle these differences. To do this:
- Add a new exynos_cpuclk_soc_data structure that will hold
the SoC-specific pre/post rate change call-backs
- Modify exynos_register_cpu_clock() prototype to include a
node pointer
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.c| 130 +-
drivers/clk/samsung/clk-cpu.h| 33 -
drivers/clk/samsung/clk-exynos4.c|2 +-
drivers/clk/samsung/clk-exynos5250.c |2 +-
drivers/clk/samsung/clk-exynos5420.c |4 +-
5 files changed, 163 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 009a21b..6c00802 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -51,6 +51,13 @@
#define DIV_MASK_ALL 0x
#define MUX_MASK 7
+#define EXYNOS7_SRC_CPU0x208
+#define EXYNOS7_STAT_CPU 0x408
+#define EXYNOS7_DIV_CPU0 0x600
+#define EXYNOS7_DIV_CPU1 0x604
+#define EXYNOS7_DIV_STAT_CPU0 0x700
+#define EXYNOS7_DIV_STAT_CPU1 0x704
+
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
@@ -128,6 +135,88 @@ static void exynos_set_safe_div(void __iomem *base,
unsigned long div,
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
}
+static void exynos7_set_safe_div(void __iomem *base, unsigned long div,
+ unsigned long mask)
+{
+ unsigned long div0;
+
+ div0 = readl(base + EXYNOS7_DIV_CPU0);
+ div0 = (div0 ~mask) | (div mask);
+ writel(div0, base + EXYNOS7_DIV_CPU0);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, mask);
+}
+
+/* Exynos7 handler for pre-rate change notification from parent clock */
+static int exynos7_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk-cfg;
+ unsigned long alt_prate = clk_get_rate(cpuclk-alt_parent);
+ unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
+ unsigned long div0, div1 = 0, mux_reg;
+
+ /* find out the divider values to use for clock data */
+ while ((cfg_data-prate * 1000) != ndata-new_rate) {
+ if (cfg_data-prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+
+ spin_lock(cpuclk-lock);
+
+ /*
+* If the new and old parent clock speed is less than the clock speed
+* of the alternate parent, then it should be ensured that at no point
+* the armclk speed is more than the old_prate until the dividers are
+* set.
+*/
+ div0 = cfg_data-div0;
+ if (alt_prate ndata-old_rate) {
+ alt_div = DIV_ROUND_UP(alt_prate, ndata-old_rate) - 1;
+ WARN_ON(alt_div = MAX_DIV);
+
+ exynos7_set_safe_div(base, alt_div, alt_div_mask);
+ div0 |= alt_div;
+ }
+
+ /* select mout_bus0_pll_atlas as the alternate parent */
+ mux_reg = readl(base + EXYNOS7_SRC_CPU);
+ writel(mux_reg | (1 0), base + EXYNOS7_SRC_CPU);
+ wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 1);
+
+ /* alternate parent is active now. set the dividers */
+ writel(div0, base + EXYNOS7_DIV_CPU0);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, DIV_MASK_ALL);
+
+ if (test_bit(CLK_CPU_HAS_DIV1, cpuclk-flags)) {
+ writel(div1, base + EXYNOS7_DIV_CPU1);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU1,
+ DIV_MASK_ALL);
+ }
+
+ spin_unlock(cpuclk-lock);
+ return 0;
+}
+
+/* Exynos7 handler for post-rate change notification from parent clock */
+static int exynos7_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ unsigned long div = 0, div_mask = DIV_MASK;
+ unsigned long mux_reg;
+
+ spin_lock(cpuclk-lock);
+
+ /* select mout_atlas_pll as the alternate parent */
+ mux_reg = readl(base + EXYNOS7_SRC_CPU);
+ writel(mux_reg ~(1 0), base + EXYNOS7_SRC_CPU);
+ wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 0);
+
+ exynos7_set_safe_div(base, div, div_mask);
+ spin_unlock(cpuclk-lock);
+ return 0;
+}
+
/* handler for pre-rate change notification from parent clock */
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
@@ -248,25 +337,58 @@ static int exynos_cpuclk_notifier_cb(struct
notifier_block *nb,
[PATCH 1/4] clk: samsung: exynos7: add clocks for CPU block
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h| 20 +++-
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f8..0b4ba7f 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-atlas
- samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
@@ -61,6 +62,11 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for atlas clock controller:
+ - fin_pll
+ - fout_atlas_pll
+ - mout_sclk_bus0_pll_atlas
+
Input clocks for ccore clock controller:
- fin_pll
- dout_aclk_ccore_133
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index a79bf23..78f66b4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -35,6 +35,34 @@
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
+static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = {
+ /* rate, m, p, s */
+ PLL_35XX_RATE(249600, 208, 2, 0),
+ PLL_35XX_RATE(24, 200, 2, 0),
+ PLL_35XX_RATE(230400, 288, 3, 0),
+ PLL_35XX_RATE(22, 275, 3, 0),
+ PLL_35XX_RATE(21, 175, 2, 0),
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(189600, 158, 2, 0),
+ PLL_35XX_RATE(18, 150, 2, 0),
+ PLL_35XX_RATE(170400, 142, 2, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 2, 1),
+ PLL_35XX_RATE(14, 350, 3, 1),
+ PLL_35XX_RATE(13, 325, 3, 1),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 350, 3, 2),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -50,6 +78,8 @@ PNAME(mout_bus1_pll_ctrl_p) = { fin_pll, fout_bus1_pll
};
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
PNAME(mout_mfc_pll_ctrl_p) = { fin_pll, fout_mfc_pll };
+PNAME(mout_topc_group1)= { mout_bus0_pll_ctrl,
ffac_topc_bus0_pll_div2,
+mout_bus1_pll_ctrl, mout_cci_pll };
PNAME(mout_topc_group2) = { mout_sclk_bus0_pll_cmuc,
mout_sclk_bus1_pll_cmuc, mout_sclk_cc_pll_cmuc,
mout_sclk_mfc_pll_cmuc };
@@ -104,6 +134,8 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(MOUT_SCLK_BUS0_PLL_ATLAS, mout_sclk_bus0_pll_atlas,
+ mout_topc_group1, MUX_SEL_TOPC1, 4, 2),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -402,6 +434,95 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_ATLAS (0x1180) */
+#defineATLAS_PLL_LOCK 0x
+#defineATLAS_PLL_CON0 0x0100
+#defineMUX_SEL_ATLAS0 0x0200
+#defineMUX_SEL_ATLAS1 0x0204
+#defineMUX_SEL_ATLAS2 0x0208
+#defineDIV_ATLAS0 0x0600
+#defineDIV_ATLAS1 0x0604
+#defineENABLE_IP_ATLAS00x0B00
+
+/* List of parent clocks for Muxes in CMU_ATLAS */
+PNAME(mout_atlas_pll_ctrl_p) = { fin_pll, fout_atlas_pll };
+PNAME(mout_bus_pll_atlas_p) = { fin_pll, mout_sclk_bus0_pll_atlas };
+PNAME(mout_atlas_p) = { mout_atlas_pll_ctrl, mout_bus_pll_atlas };
+
+static unsigned long atlas_clk_regs[] __initdata = {
+ ATLAS_PLL_LOCK,
+ ATLAS_PLL_CON0,
+ MUX_SEL_ATLAS0,
+ MUX_SEL_ATLAS1,
+ MUX_SEL_ATLAS2,
+
[PATCH 0/4] Add CPU clock support for Exynos7
These patches add the atlas clocks on Exynos7. It also modifies the existing cpu clock infrastructure to handle exynos7 differences. These patches are a pre-requisite for enabling CPUFreq on Exynos7. Following are the dependencies: 1) arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg38734.html 2) cpufreq: use generic cpufreq drivers for exynos platforms http://www.spinics.net/lists/linux-samsung-soc/msg39332.html For testing I have applied the following: 1) mfd: sec: add S2MPS15 PMIC support https://lkml.org/lkml/2014/10/14/50 2) regulator: s2mps11: add support for S2MPS15 regulators https://lkml.org/lkml/2014/10/14/52 3) Regulators dt nodes were added in the espresso dts file and I2C channel 4 which has the PMIC on it was tested. Abhilash Kesavan (4): clk: samsung: exynos7: add clocks for CPU block clk: samsung: retrieve the clock provider information from samsung_cmu_register_one clk: samsung: add cpu clock support for Exynos7 clk: samsung: add cpu clock configuration data and instantiate cpu clock .../devicetree/bindings/clock/exynos7-clock.txt|6 + drivers/clk/samsung/clk-cpu.c | 130 - drivers/clk/samsung/clk-cpu.h | 38 - drivers/clk/samsung/clk-exynos4.c |2 +- drivers/clk/samsung/clk-exynos5250.c |2 +- drivers/clk/samsung/clk-exynos5420.c |4 +- drivers/clk/samsung/clk-exynos7.c | 147 drivers/clk/samsung/clk.c |6 +- drivers/clk/samsung/clk.h |4 +- include/dt-bindings/clock/exynos7-clk.h| 21 ++- 10 files changed, 347 insertions(+), 13 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] clk: samsung: retrieve the clock provider information from samsung_cmu_register_one
In case of SoCs with multiple CMUs like Exynos7 and Exynos5260 we are
making use of a common samsung_cmu_register_one function for pll, div,
mux registration. To register the cpu domain clock (for cpufreq) we need
a reference to this clock provider information in the cpu cmu block. Make
this information accessible by returning it from samsung_cmu_register_one().
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk.c |6 --
drivers/clk/samsung/clk.h |4 ++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index dd1f7c9..4a653fe 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -374,8 +374,8 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
* Common function which registers plls, muxes, dividers and gates
* for each CMU. It also add CMU register list to register cache.
*/
-void __init samsung_cmu_register_one(struct device_node *np,
- struct samsung_cmu_info *cmu)
+struct samsung_clk_provider * __init samsung_cmu_register_one(
+ struct device_node *np, struct samsung_cmu_info *cmu)
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
@@ -410,4 +410,6 @@ void __init samsung_cmu_register_one(struct device_node *np,
cmu-nr_clk_regs);
samsung_clk_of_add_provider(np, ctx);
+
+ return ctx;
}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 3f471e9..24ae23c 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -396,8 +396,8 @@ extern void __init samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_list,
unsigned int nr_clk, void __iomem *base);
-extern void __init samsung_cmu_register_one(struct device_node *,
- struct samsung_cmu_info *);
+extern struct samsung_clk_provider * __init
+samsung_cmu_register_one(struct device_node *, struct samsung_cmu_info *);
extern unsigned long _get_rate(const char *clk_name);
--
1.7.9.5
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[PATCH 4/4] clk: samsung: add cpu clock configuration data and instantiate cpu clock
Add the Atlas CPU clock configuration data and instantiate the CPU clock
type for Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.h |5 +
drivers/clk/samsung/clk-exynos7.c | 28 +++-
include/dt-bindings/clock/exynos7-clk.h |3 ++-
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 24e844e..1fd7f51 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -31,6 +31,11 @@
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) 24) | ((pclk) 20) | ((aclk) 4)))
+#define EXYNOS7_ATL_DIV0(aclk, pclk, atclk, pclk_dbg) \
+ ((aclk 8) | (pclk 12) | (atclk 20) | (pclk_dbg 26))
+#define EXYNOS7_ATL_DIV1(pll, hpm, cntclk) \
+ ((pll 0) | (hpm 4) | (cntclk 8))
+
/**
* struct exynos_cpuclk_data: config data to setup cpu clocks.
* @prate: frequency of the primary parent clock (in KHz).
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 78f66b4..dc9b7fb 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -14,6 +14,7 @@
#include linux/of.h
#include clk.h
+#include clk-cpu.h
#include dt-bindings/clock/exynos7-clk.h
/* Register Offset definitions for CMU_TOPC (0x1057) */
@@ -63,6 +64,25 @@ static const struct samsung_pll_rate_table
pll1450x_24mhz_tbl[] = {
PLL_35XX_RATE(2, 200, 3, 3),
};
+static const struct exynos_cpuclk_cfg_data exynos7_atlclk_d[] __initconst = {
+ { 160, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 150, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 140, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 130, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 120, EXYNOS7_ATL_DIV0(1, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 110, EXYNOS7_ATL_DIV0(1, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 100, EXYNOS7_ATL_DIV0(1, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 2, 6), },
+ { 90, EXYNOS7_ATL_DIV0(1, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 2, 6), },
+ { 80, EXYNOS7_ATL_DIV0(1, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 2, 5), },
+ { 70, EXYNOS7_ATL_DIV0(1, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 2, 5), },
+ { 60, EXYNOS7_ATL_DIV0(1, 4, 4, 4), EXYNOS7_ATL_DIV1(1, 2, 4), },
+ { 50, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 40, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 30, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 20, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 0 },
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -518,7 +538,13 @@ static struct samsung_cmu_info atlas_cmu_info __initdata =
{
static void __init exynos7_clk_atlas_init(struct device_node *np)
{
- samsung_cmu_register_one(np, atlas_cmu_info);
+ struct samsung_clk_provider *ctx;
+
+ ctx = samsung_cmu_register_one(np, atlas_cmu_info);
+ exynos_register_cpu_clock(ctx, CLK_ATLAS_CLK, atlclk,
+ mout_atlas_p[0], mout_atlas_p[1], 0x0,
+ exynos7_atlclk_d, ARRAY_SIZE(exynos7_atlclk_d),
+ CLK_CPU_HAS_DIV1, np);
}
CLK_OF_DECLARE(exynos7_clk_atlas, samsung,exynos7-clock-atlas,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 93c78f9..33bc166 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -55,7 +55,8 @@
#define CLK_ATLAS 12
#define DOUT_SCLK_HPM_ATLAS13
#define DOUT_ATLAS_PLL 14
-#define ATLAS_NR_CLK 15
+#define CLK_ATLAS_CLK 15
+#define ATLAS_NR_CLK 16
/* CCORE */
#define PCLK_RTC 1
--
1.7.9.5
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Re: [RFC PATCH] drm/exynos: Add DECON driver
On 2014년 11월 25일 23:02, Ajay kumar wrote: On Tue, Nov 25, 2014 at 6:59 PM, Inki Dae inki@samsung.com wrote: On 2014년 11월 25일 22:08, Ajay kumar wrote: Hi Inki, On Tue, Nov 25, 2014 at 6:30 PM, Inki Dae inki@samsung.com wrote: On 2014년 11월 25일 21:17, Ajay kumar wrote: ping. You'd need to clean up clocks and fix up binding file. And then let's have review in more details. I wish that other people also give you their reviews. Nice to hear. Earlier, you mentioned that its good if FIMD driver itself is modified to support Exynos7 DECON. So, what is your take now? 1) Should I add it in FIMD driver itself? We may need to add lot of driver_data for that, since offsets are much different. 2) Or, create two seperate register level files for Exynos5 and Exynos7? 3) Or the current way - Entirely different driver This one, 3), for now because they, Exynos4, Exynos543x and Exynos7, are much different each other. So for next version of your patch, you'd need to change the driver name to exynos7-decon or what you want so that each driver can be entirely separated in SoC name somehow. i.e., - exynos_drm_fimd covers Exynos64xx, Exynos3250, all Exynos4 series and Exynos5250 ~ 5422 SoC. - exynos5-decon covers Exynos5430 and Exynos5433 SoC. Use exynos543x-decon here. - exynos7-decon covers Exynos7 and maybe later SoC. Ok. I will use exynos7-decon. By the way, On which branch of exynos-drm tree should I create this patch? Please, use exynos-drm-next branch. Thanks, Inki Dae Ajay After that, let's consider how we can integrate these drivers later. Thanks, Inki Dae Anyway, below is my answer. Thanks, Inki Dae On Tue, Nov 11, 2014 at 10:08 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Inki, On Mon, Nov 3, 2014 at 3:31 PM, Inki Dae inki@samsung.com wrote: Hi, Fortunately, I could get the user manual for Exynos7420. Below are my comments. Thanks, Inki Dae On 2014년 10월 23일 01:34, Ajay kumar wrote: On Wed, Oct 22, 2014 at 8:26 PM, Inki Dae inki@samsung.com wrote: Thanks for contribution. It seems reasonable that you separate device drivers into FIMD and DECON because many registers of them have many different offsets and fields. However, there may be a good solution that we can combine common sets of these drivers later. Yes, this is the main reason behind sending this as RFC patch. I want to know what's the best way to do this. FIMD, 5433 DECON and Exynos7 DECON - all are different. Also, in Exynos7 DECON-INT is same as DECON-EXT(Mixer). So, even I am not sure how the driver layouts should be! Please, make sure Exynos SoC name, Exynos7410 or Exynos7420. In my understanding, Exynos7 doesn't mean one real SoC. We shall use Exynos7 as per the discussion. Just for the time being. Ok. Below are my comments. Thanks, Inki Dae On 2014년 10월 10일 21:48, Ajay Kumar wrote: This series is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON was used since Exynos5430. And is Exynos5433 different from Exynos7? If so, could I get the Exynos7 user manual (TRM) for review? Yes, Exynos5433 DECON is very much different than Exynos7 DECON. Do not use Exynos7 word and use Exynos7410 or Exynos7420 instead. Again, we shall use Exynos7. I will see how manual can be arranged. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. Signed-off-by: Akshu Agrawal aksh...@samsung.com Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- .../devicetree/bindings/video/exynos-decon.txt | 68 ++ drivers/gpu/drm/exynos/Kconfig | 11 +- drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_decon.c | 1086 drivers/gpu/drm/exynos/exynos_drm_drv.c| 17 +- drivers/gpu/drm/exynos/exynos_drm_drv.h| 11 + include/video/samsung_decon.h | 346 +++ 7 files changed, 1537 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/video/exynos-decon.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_decon.c create mode 100644 include/video/samsung_decon.h diff --git a/Documentation/devicetree/bindings/video/exynos-decon.txt b/Documentation/devicetree/bindings/video/exynos-decon.txt new file mode 100644 index 000..e865650 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and
[PATCH v3 0/2] Add regulator-haptic driver
This patch series adds regulator-haptic driver. The regulator-haptic has haptic motor and it is controlled by voltage of regulator via force feedback framework. Changes in v3: - fix typo in Documentation - add define in header file Changes in v2: - remove driver owner - merge enable/disable function - support platform data - fix wrong suspends_state check in regulator_haptic_resume() Jaewon Kim (2): Input: add regulator haptic driver ARM: dts: Add regulator-haptic device node for exynos3250-rinato .../devicetree/bindings/input/regulator-haptic.txt | 21 ++ arch/arm/boot/dts/exynos3250-rinato.dts|7 + drivers/input/misc/Kconfig | 11 + drivers/input/misc/Makefile|1 + drivers/input/misc/regulator-haptic.c | 247 include/linux/input/regulator-haptic.h | 31 +++ 6 files changed, 318 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/regulator-haptic.txt create mode 100644 drivers/input/misc/regulator-haptic.c create mode 100644 include/linux/input/regulator-haptic.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 2/2] arm64: exynos: Add bus1 pinctrl node on exynos7
Hi Vivek,
On Mon, Nov 24, 2014 at 6:36 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
Looks good to me.
Reviewed-by: Alim Akhtar alim.akh...@samsung.com
This patch was part of series:
[PATCH 00/11] Exynos7: Adding USB 3.0 support
https://lkml.org/lkml/2014/11/21/247
Changes since V1:
- Added support for all pin banks which are part of BUS1 pin controller.
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 82
+++
arch/arm64/boot/dts/exynos/exynos7.dtsi |7 ++
2 files changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 2eef4a2..c367f0a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -335,6 +335,88 @@
};
};
+pinctrl_bus1 {
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf5: gpf5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
pinctrl_nfc {
gpj0: gpj0 {
gpio-controller;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 1d9e4c9..e633b02 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -26,6 +26,7 @@
pinctrl5 = pinctrl_ese;
pinctrl6 = pinctrl_fsys0;
pinctrl7 = pinctrl_fsys1;
+ pinctrl8 = pinctrl_bus1;
};
cpus {
@@ -242,6 +243,12 @@
interrupts = 0 383 0;
};
+ pinctrl_bus1: pinctrl@1487 {
+ compatible = samsung,exynos7-pinctrl;
+ reg = 0x1487 0x1000;
+ interrupts = 0 384 0;
+ };
+
pinctrl_nfc: pinctrl@14cd {
compatible = samsung,exynos7-pinctrl;
reg = 0x14cd 0x1000;
--
1.7.10.4
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[PATCH v3 2/2] ARM: dts: Add regulator-haptic device node for exynos3250-rinato
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 84380fa..da03005 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -104,6 +104,13 @@
};
};
};
+
+ haptics {
+ compatible = regulator-haptic;
+ haptic-supply = motor_reg;
+ min-microvolt = 110;
+ max-microvolt = 270;
+ };
};
adc {
--
1.7.9.5
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[PATCH v3 1/2] Input: add regulator haptic driver
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
---
.../devicetree/bindings/input/regulator-haptic.txt | 21 ++
drivers/input/misc/Kconfig | 11 +
drivers/input/misc/Makefile|1 +
drivers/input/misc/regulator-haptic.c | 247
include/linux/input/regulator-haptic.h | 31 +++
5 files changed, 311 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/regulator-haptic.txt
create mode 100644 drivers/input/misc/regulator-haptic.c
create mode 100644 include/linux/input/regulator-haptic.h
diff --git a/Documentation/devicetree/bindings/input/regulator-haptic.txt
b/Documentation/devicetree/bindings/input/regulator-haptic.txt
new file mode 100644
index 000..3ed1c7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/regulator-haptic.txt
@@ -0,0 +1,21 @@
+* Regulator Haptic Device Tree Bindings
+
+Required Properties:
+ - compatible : Should be regulator-haptic
+ - haptic-supply : Power supply to the haptic motor.
+ [*] refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+ - max-microvolt : The maximum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+ - min-microvolt : The minimum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+Example:
+
+ haptics {
+ compatible = regulator-haptic;
+ haptic-supply = motor_regulator;
+ max-microvolt = 270;
+ min-microvolt = 110;
+ };
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 23297ab..e5e556d 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -394,6 +394,17 @@ config INPUT_CM109
To compile this driver as a module, choose M here: the module will be
called cm109.
+config INPUT_REGULATOR_HAPTIC
+ tristate regulator haptics support
+ select INPUT_FF_MEMLESS
+ help
+ This option enables device driver support for the haptic controlled
+ by regulator. This driver supports ff-memless interface
+ from input framework.
+
+ To compile this driver as a module, choose M here: the
+ module will be called regulator-haptic.
+
config INPUT_RETU_PWRBUTTON
tristate Retu Power button Driver
depends on MFD_RETU
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 19c7603..1f135af 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o
obj-$(CONFIG_INPUT_POWERMATE) += powermate.o
obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o
obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o
+obj-$(CONFIG_INPUT_REGULATOR_HAPTIC) += regulator-haptic.o
obj-$(CONFIG_INPUT_RETU_PWRBUTTON) += retu-pwrbutton.o
obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER)+= rotary_encoder.o
obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o
diff --git a/drivers/input/misc/regulator-haptic.c
b/drivers/input/misc/regulator-haptic.c
new file mode 100644
index 000..c61dd99
--- /dev/null
+++ b/drivers/input/misc/regulator-haptic.c
@@ -0,0 +1,247 @@
+/*
+ * Regulator haptic driver
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Jaewon Kim jaewon02@samsung.com
+ * Author: Hyunhee Kim hyunhee@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/input.h
+#include linux/input/regulator-haptic.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+
+#define MAX_MAGNITUDE_SHIFT16
+
+struct regulator_haptic {
+ struct device *dev;
+ struct input_dev *input_dev;
+ struct regulator *regulator;
+ struct work_struct work;
+
+ bool enabled;
+ bool suspend_state;
+ unsigned int max_volt;
+ unsigned int min_volt;
+ unsigned int intensity;
+ unsigned int magnitude;
+};
+
+static void regulator_haptic_enable(struct regulator_haptic *haptic, bool
state)
+{
+ int error;
+
+ if (haptic-enabled == state)
+ return;
+
+ if (state)
+ error = regulator_enable(haptic-regulator);
+ else
+ error =
Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7
Hi Vivek,
On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Linus Walleij linus.wall...@linaro.org
---
Looks good to me.
Thanks!
Reviewed-by: Alim Akhtar alim.akh...@samsung.com
This patch was part of series:
[PATCH 00/11] Exynos7: Adding USB 3.0 support
https://lkml.org/lkml/2014/11/21/247
Changes since V1:
- Added support for all pin banks which are part of BUS1 pin controller.
drivers/pinctrl/samsung/pinctrl-exynos.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d5d4cfc..44e60dc 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data
exynos7_pin_banks7[] __initconst = {
EXYNOS_PIN_BANK_EINTG(8, 0x060, gpr3, 0x0c),
};
+/* pin banks of exynos7 pin-controller - BUS1 */
+static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst =
{
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpf0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpf1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, gpf2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, gpf3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpf4, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0c0, gpf5, 0x14),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0e0, gpg1, 0x18),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, gpg2, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x120, gph1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(3, 0x140, gpv6, 0x24),
+};
+
const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 Alive data */
@@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[]
__initconst = {
.pin_banks = exynos7_pin_banks7,
.nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
.eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 8 BUS1 data */
+ .pin_banks = exynos7_pin_banks8,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
+ .eint_gpio_init = exynos_eint_gpio_init,
},
};
--
1.7.10.4
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[PATCH v2 3/5] pinctrl: exynos: Fix GPIO setup failure because domain clock being gated
The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
operate properly on GPIOs the main block clock 'mau_epll' must be
enabled.
This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0)
after introducing runtime PM to pl330 DMA driver. After that commit the
'mau_epll' was gated, because the amba clock was disabled and there
were no more users of mau_epll.
The system hang just before probing i2s0 because
samsung_pinmux_setup() tried to access memory from audss block which was
gated.
Add a clock property to the pinctrl driver and enable the clock during
GPIO setup. During normal GPIO operations (set, get, set_direction) the
clock is not enabled.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt | 6 ++
drivers/pinctrl/samsung/pinctrl-samsung.c | 110 +++--
drivers/pinctrl/samsung/pinctrl-samsung.h | 2 +
3 files changed, 111 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 8425838a6dff..eb121daabe9d 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -93,6 +93,12 @@ Required Properties:
pin configuration should use the bindings listed in the
pinctrl-bindings.txt
file.
+Optional Properties:
+- clocks: Optional clock needed to access the block. Will be enabled/disabled
+ during GPIO configuration, suspend and resume but not during GPIO operations
+ (like set, get, set direction).
+- clock-names: Must be block.
+
External GPIO and Wakeup Interrupts:
The controller supports two types of external interrupts over gpio. The first
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c
b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ec580af35856..96419aba7650 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -24,6 +24,7 @@
#include linux/platform_device.h
#include linux/io.h
#include linux/slab.h
+#include linux/clk.h
#include linux/err.h
#include linux/gpio.h
#include linux/irqdomain.h
@@ -55,6 +56,32 @@ static LIST_HEAD(drvdata_list);
static unsigned int pin_base;
+static int pctl_clk_enable(struct pinctrl_dev *pctldev)
+{
+ struct samsung_pinctrl_drv_data *drvdata;
+ int ret;
+
+ drvdata = pinctrl_dev_get_drvdata(pctldev);
+ if (!drvdata-clk)
+ return 0;
+
+ ret = clk_enable(drvdata-clk);
+ if (ret)
+ dev_err(pctldev-dev, failed to enable clock: %d\n, ret);
+
+ return ret;
+}
+
+static void pctl_clk_disable(struct pinctrl_dev *pctldev)
+{
+ struct samsung_pinctrl_drv_data *drvdata;
+
+ drvdata = pinctrl_dev_get_drvdata(pctldev);
+
+ /* clk/core.c does the check if clk != NULL */
+ clk_disable(drvdata-clk);
+}
+
static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
{
return container_of(gc, struct samsung_pin_bank, gpio_chip);
@@ -374,7 +401,9 @@ static void samsung_pinmux_setup(struct pinctrl_dev
*pctldev, unsigned selector,
const struct samsung_pmx_func *func;
const struct samsung_pin_group *grp;
+ pctl_clk_enable(pctldev);
drvdata = pinctrl_dev_get_drvdata(pctldev);
+
func = drvdata-pmx_functions[selector];
grp = drvdata-pin_groups[group];
@@ -398,6 +427,8 @@ static void samsung_pinmux_setup(struct pinctrl_dev
*pctldev, unsigned selector,
writel(data, reg + type-reg_offset[PINCFG_TYPE_FUNC]);
spin_unlock_irqrestore(bank-slock, flags);
+
+ pctl_clk_disable(pctldev);
}
/* enable a specified pinmux by writing to registers */
@@ -469,20 +500,37 @@ static int samsung_pinconf_set(struct pinctrl_dev
*pctldev, unsigned int pin,
{
int i, ret;
+ ret = pctl_clk_enable(pctldev);
+ if (ret)
+ goto out;
+
for (i = 0; i num_configs; i++) {
ret = samsung_pinconf_rw(pctldev, pin, configs[i], true);
if (ret 0)
- return ret;
+ goto out;
} /* for each config */
- return 0;
+out:
+ pctl_clk_disable(pctldev);
+
+ return ret;
}
/* get the pin config settings for a specified pin */
static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
- return samsung_pinconf_rw(pctldev, pin, config, false);
+ int ret;
+
+ ret = pctl_clk_enable(pctldev);
+ if (ret)
+ return ret;
+
+ ret = samsung_pinconf_rw(pctldev, pin, config, false);
+
+ pctl_clk_disable(pctldev);
+
+ return ret;
}
/* set the pin config settings for a specified pin group */
@@ -1057,10 +1105,23 @@ static int samsung_pinctrl_probe(struct
[PATCH v2 1/5] clk: samsung: Fix double add of syscore ops after driver rebind
During driver unbind the syscore ops were not unregistered which lead to
double add on syscore list:
$ echo 381.audss-clock-controller
/sys/bus/platform/drivers/exynos-audss-clk/unbind
$ echo 381.audss-clock-controller
/sys/bus/platform/drivers/exynos-audss-clk/bind
[ 1463.044061] [ cut here ]
[ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36
__list_add+0x8c/0xc0()
[ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84.
[ 1463.061625] Modules linked in:
[ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: GW
3.18.0-rc5-next-20141121-5-ga8fab06eab42-dirty #1022
[ 1463.075338] [c0014e2c] (unwind_backtrace) from [c0011d80]
(show_stack+0x10/0x14)
[ 1463.083046] [c0011d80] (show_stack) from [c048bb70]
(dump_stack+0x70/0xbc)
[ 1463.090236] [c048bb70] (dump_stack) from [c00233d4]
(warn_slowpath_common+0x74/0xb0)
[ 1463.098295] [c00233d4] (warn_slowpath_common) from [c00234a4]
(warn_slowpath_fmt+0x30/0x40)
[ 1463.106962] [c00234a4] (warn_slowpath_fmt) from [c020fe80]
(__list_add+0x8c/0xc0)
[ 1463.114760] [c020fe80] (__list_add) from [c0282094]
(register_syscore_ops+0x30/0x3c)
[ 1463.122819] [c0282094] (register_syscore_ops) from [c0392f20]
(exynos_audss_clk_probe+0x36c/0x460)
[ 1463.132091] [c0392f20] (exynos_audss_clk_probe) from [c0283084]
(platform_drv_probe+0x48/0xa4)
[ 1463.141013] [c0283084] (platform_drv_probe) from [c0281a14]
(driver_probe_device+0x13c/0x37c)
[ 1463.149852] [c0281a14] (driver_probe_device) from [c0280560]
(bind_store+0x90/0xe0)
[ 1463.157822] [c0280560] (bind_store) from [c027fd10]
(drv_attr_store+0x20/0x2c)
[ 1463.165363] [c027fd10] (drv_attr_store) from [c0143898]
(sysfs_kf_write+0x4c/0x50)
[ 1463.173252] [c0143898] (sysfs_kf_write) from [c0142c80]
(kernfs_fop_write+0xbc/0x198)
[ 1463.181395] [c0142c80] (kernfs_fop_write) from [c00e2be0]
(vfs_write+0xa0/0x1a8)
[ 1463.189104] [c00e2be0] (vfs_write) from [c00e2f00] (SyS_write+0x40/0x8c)
[ 1463.196122] [c00e2f00] (SyS_write) from [c000f2a0]
(ret_fast_syscall+0x0/0x48)
[ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]---
[ 1463.208244] exynos-audss-clk 381.audss-clock-controller: setup completed
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Fixes: 1241ef94ccc3 (clk: samsung: register audio subsystem clocks using
common clock framework)
Cc: sta...@vger.kernel.org
---
drivers/clk/samsung/clk-exynos-audss.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index acce708ace18..7c4368e75ede 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -210,6 +210,10 @@ static int exynos_audss_clk_remove(struct platform_device
*pdev)
{
int i;
+#ifdef CONFIG_PM_SLEEP
+ unregister_syscore_ops(exynos_audss_clk_syscore_ops);
+#endif
+
of_clk_del_provider(pdev-dev.of_node);
for (i = 0; i clk_data.clk_num; i++) {
--
1.9.1
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[PATCH v2 5/5] clk: samsung: Fix memory leak of clock gate/divider/mux structures
While fixing audss clock access when domain is gated (commit clk:
samsung: Fix clock disable failure because domain being gated) generic
code from clk-gate/divider/mux was taken and modified.
This generic code leaks memory allocated for internal structures (struct
clk_gate/clk_divider/clk_mux). Fix the leak by using resourced managed
allocations.
The audss clocks are now attached to platform device.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/clk/samsung/clk-exynos-audss.c | 63 ++
1 file changed, 26 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 9ec7de866ab4..229d54981825 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -142,8 +142,6 @@ static const struct clk_ops audss_clk_gate_ops = {
/*
* A simplified copy of clk-gate.c:clk_register_gate() to mimic
* clk-gate behavior while using customized ops.
- *
- * TODO: just like clk-gate it leaks memory for struct clk_gate.
*/
static struct clk *audss_clk_register_gate(struct device *dev, const char
*name,
const char *parent_name, unsigned long flags, u8 bit_idx)
@@ -153,7 +151,7 @@ static struct clk *audss_clk_register_gate(struct device
*dev, const char *name,
struct clk_init_data init;
/* allocate the gate */
- gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+ gate = devm_kzalloc(dev, sizeof(struct clk_gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
@@ -172,9 +170,6 @@ static struct clk *audss_clk_register_gate(struct device
*dev, const char *name,
clk = clk_register(dev, gate-hw);
- if (IS_ERR(clk))
- kfree(gate);
-
return clk;
}
@@ -238,7 +233,7 @@ static struct clk *audss_clk_register_divider(struct device
*dev,
struct clk_init_data init;
/* allocate the divider */
- div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
+ div = devm_kzalloc(dev, sizeof(struct clk_divider), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
@@ -260,9 +255,6 @@ static struct clk *audss_clk_register_divider(struct device
*dev,
/* register the clock */
clk = clk_register(dev, div-hw);
- if (IS_ERR(clk))
- kfree(div);
-
return clk;
}
@@ -319,7 +311,7 @@ static struct clk *audss_clk_register_mux(struct device
*dev, const char *name,
u32 mask = BIT(width) - 1;
/* allocate the mux */
- mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
+ mux = devm_kzalloc(dev, sizeof(struct clk_mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
@@ -340,9 +332,6 @@ static struct clk *audss_clk_register_mux(struct device
*dev, const char *name,
clk = clk_register(dev, mux-hw);
- if (IS_ERR(clk))
- kfree(mux);
-
return clk;
}
@@ -398,9 +387,9 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
}
- clk_table[EXYNOS_MOUT_AUDSS] = audss_clk_register_mux(NULL,
mout_audss,
- mout_audss_p, ARRAY_SIZE(mout_audss_p),
- CLK_SET_RATE_NO_REPARENT, 0, 1);
+ clk_table[EXYNOS_MOUT_AUDSS] = audss_clk_register_mux(pdev-dev,
+ mout_audss, mout_audss_p, ARRAY_SIZE(mout_audss_p),
+ CLK_SET_RATE_NO_REPARENT, 0, 1);
cdclk = devm_clk_get(pdev-dev, cdclk);
sclk_audio = devm_clk_get(pdev-dev, sclk_audio);
@@ -408,40 +397,40 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
mout_i2s_p[1] = __clk_get_name(cdclk);
if (!IS_ERR(sclk_audio))
mout_i2s_p[2] = __clk_get_name(sclk_audio);
- clk_table[EXYNOS_MOUT_I2S] = audss_clk_register_mux(NULL, mout_i2s,
- mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
- CLK_SET_RATE_NO_REPARENT, 2, 2);
+ clk_table[EXYNOS_MOUT_I2S] = audss_clk_register_mux(pdev-dev,
+ mout_i2s, mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
+ CLK_SET_RATE_NO_REPARENT, 2, 2);
- clk_table[EXYNOS_DOUT_SRP] = audss_clk_register_divider(NULL,
dout_srp,
- mout_audss, 0, 0, 4);
+ clk_table[EXYNOS_DOUT_SRP] = audss_clk_register_divider(pdev-dev,
+ dout_srp, mout_audss, 0, 0, 4);
- clk_table[EXYNOS_DOUT_AUD_BUS] = audss_clk_register_divider(NULL,
+ clk_table[EXYNOS_DOUT_AUD_BUS] = audss_clk_register_divider(pdev-dev,
dout_aud_bus, dout_srp, 0, 4, 4);
- clk_table[EXYNOS_DOUT_I2S] = audss_clk_register_divider(NULL,
dout_i2s,
- mout_i2s, 0, 8, 4);
+ clk_table[EXYNOS_DOUT_I2S] = audss_clk_register_divider(pdev-dev,
+
[PATCH v2 4/5] ARM: dts: exynos5420: Add clock for audss pinctrl
The pinctrl for audio subsystem needs 'mau_epll' clock to be enabled in
order to properly access memory during GPIO setup.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index ba686e40eac7..c0ca0da36ade 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -696,6 +696,9 @@
};
pinctrl@0386 {
+ clocks = clock CLK_MAU_EPLL;
+ clock-names = block;
+
gpz: gpz {
gpio-controller;
#gpio-cells = 2;
--
1.9.1
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[PATCH v2 2/5] clk: samsung: Fix clock disable failure because domain being gated
Audio subsystem clocks are located in separate block. If clock for this
block (from main clock domain) 'mau_epll' is gated then any read or
write to audss registers will block.
This was observed on Exynos 5420 platforms (Arndale Octa and Peach
Pi/Pit) after introducing runtime PM to pl330 DMA driver. After that
commit the 'mau_epll' was gated, because the amba clock was disabled
and there were no more users of mau_epll. The system hang on disabling
unused clocks from audss block.
Unfortunately the 'mau_epll' clock is not parent of some of audss clocks.
Whenever system wants to operate on audss clocks it has to enable epll
clock. The solution reuses common clk-gate/divider/mux code and duplicates
clk_register_*() functions. In the same time the patch tries to limit
functional changes of the driver so it does not fix minor issues with existing
code (like leaking memory allocated for clk-gate/clk-mux/clk-divider code).
This is addressed later.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reported-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reported-by: Kevin Hilman khil...@kernel.org
---
drivers/clk/samsung/clk-exynos-audss.c | 346 +
1 file changed, 311 insertions(+), 35 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 7c4368e75ede..9ec7de866ab4 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -29,6 +29,7 @@ static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
static struct clk_onecell_data clk_data;
+static struct clk *pll_in;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
@@ -75,6 +76,276 @@ static const struct of_device_id
exynos_audss_clk_of_match[] = {
{},
};
+static int pll_clk_enable(void)
+{
+ if (!IS_ERR(pll_in))
+ return clk_enable(pll_in);
+
+ return 0;
+}
+
+static void pll_clk_disable(void)
+{
+ if (!IS_ERR(pll_in))
+ clk_disable(pll_in);
+}
+
+static int audss_clk_gate_enable(struct clk_hw *hw)
+{
+ int ret;
+
+ ret = pll_clk_enable();
+ if (ret)
+ return ret;
+
+ ret = clk_gate_ops.enable(hw);
+
+ pll_clk_disable();
+
+ return ret;
+}
+
+static void audss_clk_gate_disable(struct clk_hw *hw)
+{
+ int ret;
+
+ ret = pll_clk_enable();
+ if (ret)
+ return;
+
+ clk_gate_ops.disable(hw);
+
+ pll_clk_disable();
+}
+
+static int audss_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ int ret;
+
+ ret = pll_clk_enable();
+ if (ret)
+ return ret;
+
+ ret = clk_gate_ops.is_enabled(hw);
+
+ pll_clk_disable();
+
+ return ret;
+}
+
+static const struct clk_ops audss_clk_gate_ops = {
+ .enable = audss_clk_gate_enable,
+ .disable = audss_clk_gate_disable,
+ .is_enabled = audss_clk_gate_is_enabled,
+};
+
+/*
+ * A simplified copy of clk-gate.c:clk_register_gate() to mimic
+ * clk-gate behavior while using customized ops.
+ *
+ * TODO: just like clk-gate it leaks memory for struct clk_gate.
+ */
+static struct clk *audss_clk_register_gate(struct device *dev, const char
*name,
+ const char *parent_name, unsigned long flags, u8 bit_idx)
+{
+ struct clk_gate *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = audss_clk_gate_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_gate assignments */
+ gate-reg = reg_base + ASS_CLK_GATE;
+ gate-bit_idx = bit_idx;
+ gate-flags = 0;
+ gate-lock = lock;
+ gate-hw.init = init;
+
+ clk = clk_register(dev, gate-hw);
+
+ if (IS_ERR(clk))
+ kfree(gate);
+
+ return clk;
+}
+
+static unsigned long audss_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ unsigned long ret;
+
+ ret = pll_clk_enable();
+ if (ret) {
+ WARN(ret, Could not enable pll_in clock\n);
+ return parent_rate;
+ }
+
+ ret = clk_divider_ops.recalc_rate(hw, parent_rate);
+
+ pll_clk_disable();
+
+ return ret;
+}
+
+static long audss_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return clk_divider_ops.round_rate(hw, rate, prate);
+}
+
+static int audss_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int ret;
+
+ ret = pll_clk_enable();
+ if (ret)
+ return
[PATCH v2 0/5] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
Hi, Changes since v1 1. clocks-audss: Reimplement own clock register functions instead changing clk API. Minor fixes. (after idea from Tomasz Figa) 2. Add new patches: fix for pinctrl and minor fixes in clk-audss. Description === This patchset tries to solve dependency between AudioSS components (clocks and GPIO) and main clock controller on Exynos platform. This solves boot failure of Peach Pi/Pit and Arndale Octa [1]. Any access to memory of audss block (like checking if clock is enabled or configuring GPIO) will hang if main audss clock is gated. Tested on Arndale Octa board. [1] http://www.spinics.net/lists/linux-samsung-soc/msg39331.html Best regards, Krzysztof Kozlowski Krzysztof Kozlowski (3): clk: samsung: Fix clock disable failure because domain being gated pinctrl: exynos: Fix GPIO setup failure because domain clock being gated ARM: dts: exynos5420: Add clock for audss pinctrl .../bindings/pinctrl/samsung-pinctrl.txt | 6 + arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 3 + drivers/clk/samsung/clk-exynos-audss.c | 367 +++-- drivers/pinctrl/samsung/pinctrl-samsung.c | 110 +- drivers/pinctrl/samsung/pinctrl-samsung.h | 2 + 5 files changed, 446 insertions(+), 42 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Fix Penguin Penalty 17th October2014 ( mail-archive.com )
Dear Sir Did your website get hit by Google Penguin update on October 17th 2014? What basically is Google Penguin Update? It is actually a code name for Google algorithm which aims at decreasing your websites search engine rankings that violate Googles guidelines by using black hat SEO techniques to rank your webpage by giving number of spammy links to the page. We are one of those few SEO companies that can help you avoid penalties from Google Updates like Penguin and Panda. Our clients have survived all the previous and present updates with ease. They have never been hit because we use 100% white hat SEO techniques to rank Webpages. Simple thing that we do to keep websites away from any Penguin or Panda penalties is follow Google guidelines and we give Google users the best answers to their queries. If you are looking to increase the quality of your websites and to get more targeted traffic or save your websites from these Google penalties email us back with your interest. We will be glad to serve you and help you grow your business. Regards Roshni Patel SEO Manager ( TOB ) B7 Green Avenue, Amritsar 143001 Punjab NO CLICK in the subject to STOP EMAILS -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] ARM: exynos: MCPM: [is this a] fix for secondary boot on 5422?
Hello, Heesub Shin heesub.s...@samsung.com writes: Using the current exynos_defconfig on the exynos5422-odroid-xu3, only 6 of 8 CPUs come online with MCPM boot. CPU0 is an A7, CPUs 1-4 are A15s and CPU5-7 are the other A7s, but with the current code, CPUs 5 and 7 do not boot: [...] Exynos MCPM support installed CPU1: update cpu_capacity 1535 CPU1: thread -1, cpu 0, socket 0, mpidr 8000 CPU2: update cpu_capacity 1535 CPU2: thread -1, cpu 1, socket 0, mpidr 8001 CPU3: update cpu_capacity 1535 CPU3: thread -1, cpu 2, socket 0, mpidr 8002 CPU4: update cpu_capacity 1535 CPU4: thread -1, cpu 3, socket 0, mpidr 8003 CPU5: failed to come online CPU6: update cpu_capacity 448 CPU6: thread -1, cpu 2, socket 1, mpidr 8102 CPU7: failed to come online Brought up 6 CPUs CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13) CPU: This may indicate a broken bootloader or firmware. Thanks to a tip from Abhilash, this patch gets all 8 CPUs booting again, but the warning about CPUs started in inconsistent modes remains. Also, not being terribly familiar with Exynos internals, it's not at all obvious to me why this register write (done for *all* secondaries) makes things work works for the 2 secondary CPUs that didn't come online. It's also not obvious whether this is the right general fix, since it doesn't seem to be needed on other 542x or 5800 platforms. Very interesting to see your post. I was also suffering from the same problem with my Odroid-XU3 board. With your patch 8 CPUs are brought up, but Cortex-A15 CPUs are always offline, showing low performance. heesub@odroid:~$ cat /sys/devices/system/cpu/online 0,5-7 heesub@odroid:~$ cat /sys/devices/system/cpu/offline 1-4 Any suggestion? That's probably because you have the big.LITTLE switcher enabled in your .config (which is the default when using exynos_defconfig). If you modify your .config and set CONFIG_BL_SWITCHER=n, you will see all 8 cores online. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/5] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
Hello Krzysztof, On 11/26/2014 03:24 PM, Krzysztof Kozlowski wrote: Description === This patchset tries to solve dependency between AudioSS components (clocks and GPIO) and main clock controller on Exynos platform. This solves boot failure of Peach Pi/Pit and Arndale Octa [1]. I tested and patches #2, #3, #4 solves the boot failure I was facing. So for the whole series on an Exynos5420 Peach Pit: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Thanks a lot for solving this issue. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Add arndale_rt5631 machine driver and binding
On Wed, Nov 26, 2014 at 02:53:04PM +0530, Krishna Mohan Dani wrote: Adding machine driver to instantiate I2S based realtek's ALC5631 sound card on Arndale board. Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test it...I'll try to make a
test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
Are you seeing this on Chromebook2 (Peach-Pi 5800) too ?
No, it seems that my exynos5800-peach-pi is not having this problem,
which suggests it's a bootloader setup issue.
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
The 3 boards I have access to (SMDK5420, Chromebook Peach-Pi and
Chromebook Peach-Pit) work fine with MCPM enabled.
Thanks for helping look into this.
I am not sure why
it is failing only on the above mentioned boards as there is nothing
specific to them in the MCPM back-end.
I assume that when you default to platsmp (on disabling MCPM), the
non-working boards boot all cores upto userspace without any issues ?
Nope. With MCPM disabled:
- 5420/arndale-octa: CPU0-3 come up (A15s)
- 5422/odroid-xu3: only CPU0 (A7)
- 5800/peach-pi: only CPU0 (A15)
Note that with MCPM enabled, the arndale-octa gets the same result.
Peach-pi on the other hand gets all 8 CPUs, and the odroid-xu3 only gets
6/8 CPUs (see other thread on that topic.)
Based on the timeline (problems started about 2.5 months back), there
have only been a couple of changes in the 5420 MCPM back-end. Could
you revert the following commits and check if things improve.
20fe6f9 ARM: EXYNOS: Support cluster power off on exynos5420/5800
fbb0499 ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster
using the MCPM loopback
These might not revert cleanly, so instead of the above you could also
comment the following 2 lines:
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index dc9a764..9a07188 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -152,7 +152,7 @@ static void exynos_power_down(void)
exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
- exynos_cluster_power_down(cluster);
+ //exynos_cluster_power_down(cluster);
last_man = true;
}
2 } else if (cpu_use_count[cpu][cluster] == 1) {
@@ -356,8 +356,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
- if (!ret)
- ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
+ //if (!ret)
+ //ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI
*/
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
If you still get aborts then I suspect that the problem is with the
bootloader configuration but am not sure.
Nice. With those lines commented out, the arndale-octa is not geting
imprecise aborts anymore, and this is the platform where those aborts
seem to prevent booting into a full userspace (as originally reported by
Tyler.)
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts go away.
I can't see how enabling snoops for the boot cluster is causing these
aborts. Perhaps as Krzysztof commented it has something to do with the
secure firmware/tz software on these boards ? Other than there does
not appear to be any difference between the working/non-working
setups.
Abhilash
The odroid-xu3 is still getting them, but these seem to happen whether
or not MCPM is enabled, so must a different issue related to the
bootloader setup.
I am OK with disabling
5420_MCPM in the default configuration in such a case. This would
however mean that
[PATCH v2] ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
Values stored in val[] are never bigger than a byte.
textdata bss dec hex filename
77163692 8 114162c98 arch/arm/mach-exynos/pmu.o.before
54361908 873521cb8 arch/arm/mach-exynos/pmu.o.after
Cc: Pankaj Dubey pankaj.du...@samsung.com
Cc: Amit Daniel Kachhap amit.dan...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
v2:
- rebased on top of next-20141126 branch of linux-next kernel tree
(it also applies fine to for-next branch of linux-samsung.git)
arch/arm/mach-exynos/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index ccb0120..c15761c 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -25,7 +25,7 @@
struct exynos_pmu_conf {
unsigned int offset;
- unsigned int val[NUM_SYS_POWERDOWN];
+ u8 val[NUM_SYS_POWERDOWN];
};
struct exynos_pmu_data {
--
1.8.2.3
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Re: [PATCH v2] ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
On 11/27/14 02:21, Bartlomiej Zolnierkiewicz wrote:
Values stored in val[] are never bigger than a byte.
textdata bss dec hex filename
77163692 8 114162c98 arch/arm/mach-exynos/pmu.o.before
54361908 873521cb8 arch/arm/mach-exynos/pmu.o.after
Cc: Pankaj Dubey pankaj.du...@samsung.com
Cc: Amit Daniel Kachhap amit.dan...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
v2:
- rebased on top of next-20141126 branch of linux-next kernel tree
(it also applies fine to for-next branch of linux-samsung.git)
arch/arm/mach-exynos/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index ccb0120..c15761c 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -25,7 +25,7 @@
struct exynos_pmu_conf {
unsigned int offset;
- unsigned int val[NUM_SYS_POWERDOWN];
+ u8 val[NUM_SYS_POWERDOWN];
};
struct exynos_pmu_data {
Applied, thanks.
- Kukjin
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Re: [PATCHv3 0/3] ARM: dts: add the support of Exynos3250-based Monk board
On 11/24/14 19:57, Chanwoo Choi wrote: This patchset adds the support of Exynos3250-based Monk board and Exynos-based boards compatible string and description to remove build warning. Also, this patchset includes a patch which remove unused dt node for command line in Exynos3250-based Rinato dts file. Changes from v2: - Include new patches by Chanwoo Choi with following patch[1] [1] http://www.spinics.net/lists/arm-kernel/msg368443.html Changes from v1: - Fix minor issue Chanwoo Choi (2): ARM: exynos: Add Exynos-based boards compatible string and description ARM: dts: Remove unused command line from Exynos3250-based Rinato board Youngjun Cho (1): ARM: dts: add board dts file for Exynos3250-based Monk board .../devicetree/bindings/arm/samsung-boards.txt | 19 +- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/exynos3250-monk.dts | 579 + arch/arm/boot/dts/exynos3250-rinato.dts| 4 - 4 files changed, 595 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/exynos3250-monk.dts Applied, thanks. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] thermal: cpu_cooling: check for the readiness of cpufreq layer
In this patch, the cpu_cooling code checks for the usability of cpufreq
layer before proceeding with the CPU cooling device registration. The
main reason is: CPU cooling device is not usable if cpufreq cannot
switch frequencies.
Similar checks are spread in thermal drivers. Thus, the advantage now
is to have the check in a single place: cpu cooling device registration.
For this reason, this patch also updates the existing drivers that
depend on CPU cooling to simply propagate the error code of the cpu
cooling registration call. Therefore, in case cpufreq is not ready, the
thermal drivers will still return -EPROBE_DEFER, in an attempt to try
again when cpufreq layer gets ready.
Cc: devicet...@vger.kernel.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux...@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Zhang Rui rui.zh...@intel.com
Signed-off-by: Eduardo Valentin edubez...@gmail.com
---
drivers/thermal/cpu_cooling.c | 5 +
drivers/thermal/db8500_cpufreq_cooling.c | 5 -
drivers/thermal/imx_thermal.c | 5 -
drivers/thermal/samsung/exynos_thermal_common.c| 2 +-
drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 6 --
5 files changed, 6 insertions(+), 17 deletions(-)
---
This is attempt to organize the cpu cooling vs. cpufreq boot sequencing.
The main change in this patch, as in the commit log, is to have the check
for the cpufreq layer in the cpu cooling device registration, instead of
in thermal drivers. This way, drivers don't need to bother about it, they
just need to propagate the error value.
This change was tested on top of:
(0) - Viresh's change in cpufreq layer and cpufreq-dt (up to patch 4):
https://patchwork.kernel.org/patch/5384141/
https://patchwork.kernel.org/patch/5384151/
https://patchwork.kernel.org/patch/5384161/
https://patchwork.kernel.org/patch/5384171/
(1) - fix of thermal core:
https://patchwork.kernel.org/patch/5326991/
After Viresh's changes, cpufreq-dt is properly sequenced with cpu cooling
registration. Non-of based drivers also should take advantage if these
changes, as now they do not need to check for cpufreq layer. The check is
where it belongs, in cpu cooling device registration.
BR, Eduardo Valentin
diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
index 1ab0018..9e6945b 100644
--- a/drivers/thermal/cpu_cooling.c
+++ b/drivers/thermal/cpu_cooling.c
@@ -440,6 +440,11 @@ __cpufreq_cooling_register(struct device_node *np,
int ret = 0, i;
struct cpufreq_policy policy;
+ if (!cpufreq_get_current_driver() || !cpufreq_frequency_get_table(0)) {
+ pr_err(cpu_cooling: cpufreq layer not ready! Deferring.\n);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
/* Verify that all the clip cpus have same freq_min, freq_max limit */
for_each_cpu(i, clip_cpus) {
/* continue if cpufreq policy not found and not return error */
diff --git a/drivers/thermal/db8500_cpufreq_cooling.c
b/drivers/thermal/db8500_cpufreq_cooling.c
index 786d192..1ac7ec6 100644
--- a/drivers/thermal/db8500_cpufreq_cooling.c
+++ b/drivers/thermal/db8500_cpufreq_cooling.c
@@ -18,7 +18,6 @@
*/
#include linux/cpu_cooling.h
-#include linux/cpufreq.h
#include linux/err.h
#include linux/module.h
#include linux/of.h
@@ -30,10 +29,6 @@ static int db8500_cpufreq_cooling_probe(struct
platform_device *pdev)
struct thermal_cooling_device *cdev;
struct cpumask mask_val;
- /* make sure cpufreq driver has been initialized */
- if (!cpufreq_frequency_get_table(0))
- return -EPROBE_DEFER;
-
cpumask_set_cpu(0, mask_val);
cdev = cpufreq_cooling_register(mask_val);
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 5a1f107..16405b4 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -9,7 +9,6 @@
#include linux/clk.h
#include linux/cpu_cooling.h
-#include linux/cpufreq.h
#include linux/delay.h
#include linux/device.h
#include linux/init.h
@@ -459,10 +458,6 @@ static int imx_thermal_probe(struct platform_device *pdev)
int measure_freq;
int ret;
- if (!cpufreq_get_current_driver()) {
- dev_dbg(pdev-dev, no cpufreq driver!);
- return -EPROBE_DEFER;
- }
data = devm_kzalloc(pdev-dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
diff --git a/drivers/thermal/samsung/exynos_thermal_common.c
b/drivers/thermal/samsung/exynos_thermal_common.c
index 3f5ad25..f84975e 100644
--- a/drivers/thermal/samsung/exynos_thermal_common.c
+++ b/drivers/thermal/samsung/exynos_thermal_common.c
@@ -373,7 +373,7 @@ int
Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test it...I'll try to make a
test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
Are you seeing this on Chromebook2 (Peach-Pi 5800) too ?
No, it seems that my exynos5800-peach-pi is not having this problem,
which suggests it's a bootloader setup issue.
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
The 3 boards I have access to (SMDK5420, Chromebook Peach-Pi and
Chromebook Peach-Pit) work fine with MCPM enabled.
Thanks for helping look into this.
I am not sure why
it is failing only on the above mentioned boards as there is nothing
specific to them in the MCPM back-end.
I assume that when you default to platsmp (on disabling MCPM), the
non-working boards boot all cores upto userspace without any issues ?
Nope. With MCPM disabled:
- 5420/arndale-octa: CPU0-3 come up (A15s)
- 5422/odroid-xu3: only CPU0 (A7)
- 5800/peach-pi: only CPU0 (A15)
Note that with MCPM enabled, the arndale-octa gets the same result.
Peach-pi on the other hand gets all 8 CPUs, and the odroid-xu3 only gets
6/8 CPUs (see other thread on that topic.)
Based on the timeline (problems started about 2.5 months back), there
have only been a couple of changes in the 5420 MCPM back-end. Could
you revert the following commits and check if things improve.
20fe6f9 ARM: EXYNOS: Support cluster power off on exynos5420/5800
fbb0499 ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster
using the MCPM loopback
These might not revert cleanly, so instead of the above you could also
comment the following 2 lines:
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index dc9a764..9a07188 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -152,7 +152,7 @@ static void exynos_power_down(void)
exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
- exynos_cluster_power_down(cluster);
+ //exynos_cluster_power_down(cluster);
last_man = true;
}
2 } else if (cpu_use_count[cpu][cluster] == 1) {
@@ -356,8 +356,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
- if (!ret)
- ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
+ //if (!ret)
+ //ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI
*/
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
If you still get aborts then I suspect that the problem is with the
bootloader configuration but am not sure.
Nice. With those lines commented out, the arndale-octa is not geting
imprecise aborts anymore, and this is the platform where those aborts
seem to prevent booting into a full userspace (as originally reported by
Tyler.)
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts go away.
I can't see how enabling snoops for the boot cluster is causing these
aborts. Perhaps as Krzysztof commented it has something to do with the
secure firmware/tz software on these boards ? Other than there does
not appear to be any difference between the working/non-working
setups.
Perhaps the secure firmware is preventing the CCI to be enabled by the
kernel, and that is causing the imprecise abort?
Is there a way to update/replace the BL1/BL2/TZ firmware blobs with
something that is known to be
Re: [RESEND PATCH 1/2] ARM: dts: exynos4x12: Device tree node definition for TMU on Exynos4x12
On 11/24/14 17:49, Lukasz Majewski wrote: Hi Kukjin, Lukasz Majewski wrote: + Bart, Tomasz and MLs Hi Lukasz, Please post including MLs, even resending. Will apply for v3.19, and just note that you asked me to apply this for 3.18 in personal talk but I couldn't see any requirements for fixes-3.18. If I'm missing something, please let me know. The thing is that by default Exynos 4412 (trats2) can run with modified cpufreq to support SW governed overclocking (BOOST). To provide safe BOOST operation, TMU (thermal) _must_ be configured. Configuration is not possible when trats2 DTS lacks of those patches. Well, AFAIK the BOOST mode is only available on only Samsung mobile not mainline and so I think this is not for bug fix in mainline for 3.18... - Kukjin So, yes there is a requirement to add those patches to v3.18 (if not possible please add it to v3.19). Thanks, Kukjin The TMU device tree node definition for Exynos4x12 family of SoCs. Signed-off-by: Lukasz Majewski l.majew...@samsung.com Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Reviewed-by: Tomasz Figa tomasz.f...@gmail.com --- arch/arm/boot/dts/exynos4x12.dtsi | 10 ++ 1 file changed, 10 insertions(+) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/6] drm/exynos: don't do any DPMS operation while updating planes
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
DPMS only makes sense when the mode changes, for plane update changes do
not perform any dpms operation.
This move places the win_commit() and commit() calls directly in the code
instead of calling exynos_drm_crtc_commit() thus avoiding DPMS operations.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 13c7ba5..e946b5f5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -115,6 +115,8 @@ static int exynos_drm_crtc_mode_set_commit(struct drm_crtc
*crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
+ struct exynos_drm_manager *manager = exynos_crtc-manager;
+ struct exynos_drm_plane *exynos_plane = to_exynos_plane(crtc-primary);
struct drm_framebuffer *fb = crtc-primary-fb;
unsigned int crtc_w;
unsigned int crtc_h;
@@ -134,7 +136,11 @@ static int exynos_drm_crtc_mode_set_commit(struct drm_crtc
*crtc, int x, int y,
if (ret)
return ret;
- exynos_drm_crtc_commit(crtc);
+ if (manager-ops-win_commit)
+ manager-ops-win_commit(manager, exynos_plane-zpos);
+
+ if (manager-ops-commit)
+ manager-ops-commit(manager);
return 0;
}
--
1.9.3
--
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[PATCH 5/6] drm/exynos: call exynos_update_plane() directly on page flips
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Avoid an extra call to exynos_drm_crtc_mode_set_commit() that only calls
exynos_update_plane().
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 4c8bd4d..185dabe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -176,6 +176,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
struct exynos_drm_private *dev_priv = dev-dev_private;
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
struct drm_framebuffer *old_fb = crtc-primary-fb;
+ unsigned int crtc_w, crtc_h;
int ret = -EINVAL;
/* when the page flip is requested, crtc's dpms should be on */
@@ -207,8 +208,11 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_unlock_irq(dev-event_lock);
crtc-primary-fb = fb;
- ret = exynos_drm_crtc_mode_set_commit(crtc, crtc-x, crtc-y,
- NULL);
+ crtc_w = fb-width - crtc-x;
+ crtc_h = fb-height - crtc-y;
+ ret = exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
+ crtc_w, crtc_h, crtc-x, crtc-y,
+ crtc_w, crtc_h);
if (ret) {
crtc-primary-fb = old_fb;
--
1.9.3
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[PATCH 4/6] drm/exynos: unify plane update on exynos_update_plane()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
We can safely use the exynos_update_plane() to update the plane
framebuffer for both the overlay and primary planes.
Note that this patch removes a call to manager-ops-commit() in
exynos_drm_crtc_mode_set_commit(). The commit() call is used only by the
fimd driver to set underlying timings and need only in full modeset
operations. For plane update only win_commit is needed.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 17 ++---
drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_plane.h | 5 +
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index a43e25d..4c8bd4d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -117,12 +117,9 @@ static int exynos_drm_crtc_mode_set_commit(struct drm_crtc
*crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct exynos_drm_manager *manager = exynos_crtc-manager;
- struct exynos_drm_plane *exynos_plane = to_exynos_plane(crtc-primary);
struct drm_framebuffer *fb = crtc-primary-fb;
unsigned int crtc_w;
unsigned int crtc_h;
- int ret;
/* when framebuffer changing is requested, crtc's dpms should be on */
if (exynos_crtc-dpms DRM_MODE_DPMS_ON) {
@@ -133,18 +130,8 @@ static int exynos_drm_crtc_mode_set_commit(struct drm_crtc
*crtc, int x, int y,
crtc_w = fb-width - x;
crtc_h = fb-height - y;
- ret = exynos_plane_mode_set(crtc-primary, crtc, fb, 0, 0,
- crtc_w, crtc_h, x, y, crtc_w, crtc_h);
- if (ret)
- return ret;
-
- if (manager-ops-win_commit)
- manager-ops-win_commit(manager, exynos_plane-zpos);
-
- if (manager-ops-commit)
- manager-ops-commit(manager);
-
- return 0;
+ return exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
+ crtc_w, crtc_h, x, y, crtc_w, crtc_h);
}
static int exynos_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index aa9cc9a..dadd306 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -165,7 +165,7 @@ void exynos_plane_dpms(struct drm_plane *plane, int mode)
}
}
-static int
+int
exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct drm_framebuffer *fb, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h
b/drivers/gpu/drm/exynos/exynos_drm_plane.h
index 3c23989..d25c079 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h
@@ -14,6 +14,11 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct
drm_crtc *crtc,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
+int exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
+ struct drm_framebuffer *fb, int crtc_x, int crtc_y,
+ unsigned int crtc_w, unsigned int crtc_h,
+ uint32_t src_x, uint32_t src_y,
+ uint32_t src_w, uint32_t src_h);
void exynos_plane_dpms(struct drm_plane *plane, int mode);
struct drm_plane *exynos_plane_init(struct drm_device *dev,
unsigned long possible_crtcs,
--
1.9.3
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Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
On 11/27/14 02:56, Kevin Hilman wrote:
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale,
chromebook...but smdk
which has different bootloader, I couldn't test it...I'll try to make a
test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
Are you seeing this on Chromebook2 (Peach-Pi 5800) too ?
No, it seems that my exynos5800-peach-pi is not having this problem,
which suggests it's a bootloader setup issue.
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
The 3 boards I have access to (SMDK5420, Chromebook Peach-Pi and
Chromebook Peach-Pit) work fine with MCPM enabled.
Thanks for helping look into this.
I am not sure why
it is failing only on the above mentioned boards as there is nothing
specific to them in the MCPM back-end.
I assume that when you default to platsmp (on disabling MCPM), the
non-working boards boot all cores upto userspace without any issues ?
Nope. With MCPM disabled:
- 5420/arndale-octa: CPU0-3 come up (A15s)
- 5422/odroid-xu3: only CPU0 (A7)
- 5800/peach-pi: only CPU0 (A15)
Note that with MCPM enabled, the arndale-octa gets the same result.
Peach-pi on the other hand gets all 8 CPUs, and the odroid-xu3 only gets
6/8 CPUs (see other thread on that topic.)
Based on the timeline (problems started about 2.5 months back), there
have only been a couple of changes in the 5420 MCPM back-end. Could
you revert the following commits and check if things improve.
20fe6f9 ARM: EXYNOS: Support cluster power off on exynos5420/5800
fbb0499 ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster
using the MCPM loopback
These might not revert cleanly, so instead of the above you could also
comment the following 2 lines:
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index dc9a764..9a07188 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -152,7 +152,7 @@ static void exynos_power_down(void)
exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
- exynos_cluster_power_down(cluster);
+ //exynos_cluster_power_down(cluster);
last_man = true;
}
2 } else if (cpu_use_count[cpu][cluster] == 1) {
@@ -356,8 +356,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
- if (!ret)
- ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI
*/
+ //if (!ret)
+ //ret = mcpm_loopback(exynos_cache_off); /* turn on the
CCI */
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
If you still get aborts then I suspect that the problem is with the
bootloader configuration but am not sure.
Nice. With those lines commented out, the arndale-octa is not geting
imprecise aborts anymore, and this is the platform where those aborts
seem to prevent booting into a full userspace (as originally reported by
Tyler.)
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts go away.
I can't see how enabling snoops for the boot cluster is causing these
aborts. Perhaps as Krzysztof commented it has something to do with the
secure firmware/tz software on these boards ? Other than there does
not appear to be any difference between the working/non-working
setups.
Perhaps the secure firmware is preventing the CCI to be enabled by the
kernel, and that is causing the imprecise abort?
Is there a way to update/replace the BL1/BL2/TZ
[PATCH 3/6] drm/exynos: remove exynos_plane_commit() wrapper
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
It's doing nothing but calling exynos_crtc-ops-win_commit(), so let's
call this directly to avoid extra layers of abstraction.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 4 +++-
drivers/gpu/drm/exynos/exynos_drm_plane.c | 15 +--
drivers/gpu/drm/exynos/exynos_drm_plane.h | 1 -
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index e946b5f5..a43e25d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -59,10 +59,12 @@ static void exynos_drm_crtc_commit(struct drm_crtc *crtc)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
struct exynos_drm_manager *manager = exynos_crtc-manager;
+ struct exynos_drm_plane *exynos_plane = to_exynos_plane(crtc-primary);
exynos_drm_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
- exynos_plane_commit(crtc-primary);
+ if (manager-ops-win_commit)
+ manager-ops-win_commit(manager, exynos_plane-zpos);
if (manager-ops-commit)
manager-ops-commit(manager);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 4fe3c2b..aa9cc9a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -139,15 +139,6 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct
drm_crtc *crtc,
return 0;
}
-void exynos_plane_commit(struct drm_plane *plane)
-{
- struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
- struct exynos_drm_manager *manager =
to_exynos_crtc(plane-crtc)-manager;
-
- if (manager-ops-win_commit)
- manager-ops-win_commit(manager, exynos_plane-zpos);
-}
-
void exynos_plane_dpms(struct drm_plane *plane, int mode)
{
struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
@@ -181,6 +172,9 @@ exynos_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
+
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)-manager;
+ struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
int ret;
ret = exynos_plane_mode_set(plane, crtc, fb, crtc_x, crtc_y,
@@ -189,7 +183,8 @@ exynos_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
if (ret 0)
return ret;
- exynos_plane_commit(plane);
+ if (manager-ops-win_commit)
+ manager-ops-win_commit(manager, exynos_plane-zpos);
return 0;
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h
b/drivers/gpu/drm/exynos/exynos_drm_plane.h
index 0d1986b..3c23989 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h
@@ -14,7 +14,6 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct
drm_crtc *crtc,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
-void exynos_plane_commit(struct drm_plane *plane);
void exynos_plane_dpms(struct drm_plane *plane, int mode);
struct drm_plane *exynos_plane_init(struct drm_device *dev,
unsigned long possible_crtcs,
--
1.9.3
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[PATCH 0/6] drm/exynos: unify plane update path and avoid DPMS for planes
From: Gustavo Padovan gustavo.pado...@collabora.co.uk This series is try to unify all the paths on exynos DRM that handle plane updates. Now SetPlane, PageFlip and SetCrtc (fb changed only) are all processed by the same function: exynos_update_plane(). In the unify process the DPMS operations were removed since we are not in full modeset path. This applies on top of my last cleanup[0] and is part of my ongoing cleanup work on exynos drm. [0] http://www.spinics.net/lists/linux-samsung-soc/msg39502.html Gustavo Padovan (6): drm/exynos: Don't touch DPMS when updating overlay planes drm/exynos: don't do any DPMS operation while updating planes drm/exynos: remove exynos_plane_commit() wrapper drm/exynos: unify plane update on exynos_update_plane() drm/exynos: call exynos_update_plane() directly on page flips drm/exynos: remove exynos_drm_crtc_mode_set_commit() drivers/gpu/drm/exynos/exynos_drm_crtc.c | 31 --- drivers/gpu/drm/exynos/exynos_drm_plane.c | 18 ++ drivers/gpu/drm/exynos/exynos_drm_plane.h | 6 +- 3 files changed, 23 insertions(+), 32 deletions(-) -- 1.9.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] drm/exynos: Don't touch DPMS when updating overlay planes
From: Gustavo Padovan gustavo.pado...@collabora.co.uk DPMS settings should only be changed by a full modeset. exynos_plane_update() should only care about updating the planes itself and nothing else. Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_plane.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 843f741..4fe3c2b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -190,7 +190,6 @@ exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, return ret; exynos_plane_commit(plane); - exynos_plane_dpms(plane, DRM_MODE_DPMS_ON); return 0; } -- 1.9.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/6] drm/exynos: remove exynos_drm_crtc_mode_set_commit()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
This was just as extra chain in the call stack. We just rename it to
_set_base() and let it do everything alone.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 185dabe..5b3d182 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -113,7 +113,7 @@ exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct
drm_display_mode *mode,
crtc_w, crtc_h, x, y, crtc_w, crtc_h);
}
-static int exynos_drm_crtc_mode_set_commit(struct drm_crtc *crtc, int x, int y,
+static int exynos_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
@@ -134,12 +134,6 @@ static int exynos_drm_crtc_mode_set_commit(struct drm_crtc
*crtc, int x, int y,
crtc_w, crtc_h, x, y, crtc_w, crtc_h);
}
-static int exynos_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
- struct drm_framebuffer *old_fb)
-{
- return exynos_drm_crtc_mode_set_commit(crtc, x, y, old_fb);
-}
-
static void exynos_drm_crtc_disable(struct drm_crtc *crtc)
{
struct drm_plane *plane;
--
1.9.3
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[PATCH 1/2] drm/exynos/fimd: don't initialize 'ret' variable in fimd_probe()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk We set it in the beginning of the function, thus no need to set it at initialization. Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 26f94e5..0c9def9 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -1134,7 +1134,7 @@ static int fimd_probe(struct platform_device *pdev) struct fimd_context *ctx; struct device_node *i80_if_timings; struct resource *res; - int ret = -EINVAL; + int ret; if (!dev-of_node) return -ENODEV; -- 1.9.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] drm/exynos/vidi: remove useless ops-commit()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
vidi_commit does nothing, remove it and its callers.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index ff194be..7f9ce73 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -115,17 +115,6 @@ static void vidi_apply(struct exynos_drm_manager *mgr)
if (win_data-enabled (mgr_ops mgr_ops-win_commit))
mgr_ops-win_commit(mgr, i);
}
-
- if (mgr_ops mgr_ops-commit)
- mgr_ops-commit(mgr);
-}
-
-static void vidi_commit(struct exynos_drm_manager *mgr)
-{
- struct vidi_context *ctx = manager_to_vidi(mgr);
-
- if (ctx-suspended)
- return;
}
static int vidi_enable_vblank(struct exynos_drm_manager *mgr)
@@ -320,7 +309,6 @@ static int vidi_mgr_initialize(struct exynos_drm_manager
*mgr,
static struct exynos_drm_manager_ops vidi_manager_ops = {
.dpms = vidi_dpms,
- .commit = vidi_commit,
.enable_vblank = vidi_enable_vblank,
.disable_vblank = vidi_disable_vblank,
.win_mode_set = vidi_win_mode_set,
--
1.9.3
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Re: [PATCH] ASoC: rt5631: Fixing compilation warning when DT is disabled
On Wed, Nov 26, 2014 at 02:26:07PM +0530, D Krishna Mohan wrote: Following your suggestion I have sent a patch (187024b36c635bd454c1b1587b58c9439d3a46ad on your git, branch: rt5631 ) using ifdef which you have already applied. Since there are more suggestion asking for second (__maybe_unused) method, I have sent another patch for which below is the link. You may be applying the second patch on the already applied first patch. so I request you to apply only second patch in place of first and abandon first patch. Once something is applied in git you should always send further patches as incrmental updates to that, this is much easier to manage and avoids any potential confusion to other people looking at the tree. signature.asc Description: Digital signature
Re: [PATCH v12 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Kevin Hilman khil...@kernel.org writes: Hi Thomas, Thomas Abraham thomas...@samsung.com writes: Changes since v11: - Rebased on top of git://linuxtv.org/snawrocki/samsung.git for-v3.19-exynos-clk Thanks for rebasing/reposting. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This series is based on the following branch. git://linuxtv.org/snawrocki/samsung.git for-v3.19-exynos-clk This series depends on the following patch which can be picked from git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git samsung/dt e540920cf21c (ARM: dts: add CPU nodes for Exynos4 SoCs). This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19 (http://www.spinics.net/lists/linux-samsung-soc/msg37933.html). Sylwester, could you consider to merge this in your tree? I tested this on exynos5800-peach-pi, and noticed a few things. First, since voltage scaling is not currently supported, the CPU cluster regulators (vdd_arm, and vdd_kfc) have to be set at sufficietnly high voltage to support all the OPPs, otherwise things will likely hang. I think you should include something like the patch below[1] in this series as well. Second, as with earlier versions of this series, I'm still seeing lots of wait_until_divider_stable: timeout in divider stablization messages coming out when running powertop. And, I just found another issue: On exynos5800-peach-pi, setting the cpufreq default governor to performance at compile time (CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y) makes the kernel boot hang when the cpufreq driver is initialized. However, setting the compile-time default to the userspace governor, and then setting the performance governor via sysfs after the boot finishes seems to work fine. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
On Wed, 26 Nov 2014, Kevin Hilman wrote: Abhilash Kesavan kesavan.abhil...@gmail.com writes: Hi Kevin, On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote: [...] More specifically, with only the loopback call to turn off CCI commented out, the imprecise aborts go away. I can't see how enabling snoops for the boot cluster is causing these aborts. Perhaps as Krzysztof commented it has something to do with the secure firmware/tz software on these boards ? Other than there does not appear to be any difference between the working/non-working setups. Perhaps the secure firmware is preventing the CCI to be enabled by the kernel, and that is causing the imprecise abort? That is well possible. Now.. if the bootloader/firmware does not let Linux deal with both the CCI and caches then MCPM simply has no more purpose for this board. The whole point of MCPM is actually to handle the CCI properly and the most efficient way despite all the possible races and opportunities for memory corruptions. And yes, this is a complex task. So there is actually two choices: the firmware let Linux take care of it via the MCPM layer (easy), or the firmware has to implement it all _properly_ (hard) behind an interface such as PSCI, at which point MCPM should be configured out. If the firmware does not let Linux interact with the CCI _and_ does not implement full MCPM-like services then the platform is broken and only a firmware upgrade could fix that. It might still be possible to boot all CPUs through other means, but power management would then be severely limited. Nicolas -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 1/2] i2c: s3c2410: add Sysreg phandle to i2c device nodes
On 11/24/14 17:47, Pankaj Dubey wrote: This patch adds syscon based phandle to i2c device nodes of exynos5250 and exynos5420. These phandles will be used to save restore i2c sysreg configuration register during s2r from i2c driver. CC: Rob Herring robh...@kernel.org CC: Randy Dunlap rdun...@infradead.org CC: Russell King li...@arm.linux.org.uk CC: devicet...@vger.kernel.org CC: linux-...@vger.kernel.org Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Applied with change the subject 'ARM: dts: add sysreg phandle to...' BTW I'm holding on 2nd because conflicts between pm update and cleanup branches in my tree... - Kukjin --- .../devicetree/bindings/i2c/i2c-s3c2410.txt|1 + arch/arm/boot/dts/exynos5250.dtsi |4 arch/arm/boot/dts/exynos5420.dtsi |4 3 files changed, 9 insertions(+) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 0/5] regulator: of: Add initial and suspend modes support
On Mon, Nov 10, 2014 at 02:43:50PM +0100, Javier Martinez Canillas wrote: Hello Mark, This is the sixth version of the series that adds regulator initial and suspend operating modes support. It relies on the existing work that added suspend states bindings. The opmodes are parsed by the regulator core and drivers should only define a translation function to map between hardware specific to standard modes. Applied all, thanks. signature.asc Description: Digital signature
Re: [PATCH] spi: s3c64xx: add support for exynos7 SPI controller
On Thu, Nov 06, 2014 at 03:21:49PM +0530, Padmavathi Venna wrote: Exynos7 SPI controller supports only the auto Selection of CS toggle mode and Exynos7 SoC includes six SPI controllers. Add support for these changes in Exynos7 SPI controller driver. Applied, thanks. It does seem like these controllers are getting more restricted in functionality which seems a bit of a shame. signature.asc Description: Digital signature
Re: [PATCH 2/3] regulator: max77802: Fill regulator modes translation callback
On Tue, Nov 11, 2014 at 01:04:44PM +0100, Javier Martinez Canillas wrote: The max77802 PMIC regulators output can be configured in one of two modes: Output ON (normal) and Output ON in Low Power Mode. Some of Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH 1/3] regulator: max77802: Document binding for regulator operating modes
On Tue, Nov 11, 2014 at 01:04:43PM +0100, Javier Martinez Canillas wrote: Some regulators from the max77802 PMIC support to be configured in one of two operating mode: Output ON (normal) and Output On Low Power Mode. Applied, thanks. signature.asc Description: Digital signature
[PATCH 1/6] drm/exynos: rename base object of struct exynos_drm_crtc to 'base'
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
'base' is more widely used name in the drm subsystem for the base object.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 4 ++--
drivers/gpu/drm/exynos/exynos_drm_drv.h | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 5b3d182..1cdf705 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -324,8 +324,8 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager)
goto err_plane;
}
- manager-crtc = exynos_crtc-drm_crtc;
- crtc = exynos_crtc-drm_crtc;
+ manager-crtc = exynos_crtc-base;
+ crtc = exynos_crtc-base;
private-crtc[manager-pipe] = crtc;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 187dde5..0a565f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -23,8 +23,7 @@
#define MAX_FB_BUFFER 4
#define DEFAULT_ZPOS -1
-#define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc,\
- drm_crtc)
+#define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base)
#define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base)
/* This enumerates device type. */
@@ -229,7 +228,7 @@ enum exynos_crtc_mode {
/*
* Exynos specific crtc structure.
*
- * @drm_crtc: crtc object.
+ * @base: crtc object.
* @manager: the manager associated with this crtc
* @pipe: a crtc index created at load() with a new crtc object creation
* and the crtc object would be set to private-crtc array
@@ -242,7 +241,7 @@ enum exynos_crtc_mode {
* @mode: store the crtc mode value
*/
struct exynos_drm_crtc {
- struct drm_crtc drm_crtc;
+ struct drm_crtc base;
struct exynos_drm_manager *manager;
unsigned intpipe;
unsigned intdpms;
--
1.9.3
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[PATCH 2/6] drm/exynos: add pipe param to exynos_drm_crtc_create()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Get the pipe value from a parameter instead of getting it from
manager-pipe. We are removing manager-pipe.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 2 +-
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 2 +-
drivers/gpu/drm/exynos/exynos_mixer.c| 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 1cdf705..68aae38 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -299,7 +299,7 @@ static void exynos_drm_crtc_attach_mode_property(struct
drm_crtc *crtc)
drm_object_attach_property(crtc-base, prop, 0);
}
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager)
+int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe)
{
struct exynos_drm_crtc *exynos_crtc;
struct drm_plane *plane;
@@ -316,8 +316,8 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager)
exynos_crtc-dpms = DRM_MODE_DPMS_OFF;
exynos_crtc-manager = manager;
- exynos_crtc-pipe = manager-pipe;
- plane = exynos_plane_init(manager-drm_dev, 1 manager-pipe,
+ exynos_crtc-pipe = pipe;
+ plane = exynos_plane_init(manager-drm_dev, 1 pipe,
DRM_PLANE_TYPE_PRIMARY);
if (IS_ERR(plane)) {
ret = PTR_ERR(plane);
@@ -327,7 +327,7 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager)
manager-crtc = exynos_crtc-base;
crtc = exynos_crtc-base;
- private-crtc[manager-pipe] = crtc;
+ private-crtc[pipe] = crtc;
ret = drm_crtc_init_with_planes(manager-drm_dev, crtc, plane, NULL,
exynos_crtc_funcs);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index dbd4227..f1bee84 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -17,7 +17,7 @@
#include exynos_drm_drv.h
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager);
+int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe);
int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe);
void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe);
void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 0c9def9..1f83a75 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -1102,7 +1102,7 @@ static int fimd_bind(struct device *dev, struct device
*master, void *data)
struct drm_device *drm_dev = data;
fimd_mgr_initialize(ctx-manager, drm_dev);
- exynos_drm_crtc_create(ctx-manager);
+ exynos_drm_crtc_create(ctx-manager, ctx-pipe);
if (ctx-display)
exynos_drm_create_enc_conn(drm_dev, ctx-display);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 7f9ce73..e78764f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -558,7 +558,7 @@ static int vidi_bind(struct device *dev, struct device
*master, void *data)
vidi_mgr_initialize(ctx-manager, drm_dev);
- ret = exynos_drm_crtc_create(ctx-manager);
+ ret = exynos_drm_crtc_create(ctx-manager, ctx-pipe);
if (ret) {
DRM_ERROR(failed to create crtc.\n);
return ret;
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index b64674a..9d7dcfc 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -1256,7 +1256,7 @@ static int mixer_bind(struct device *dev, struct device
*manager, void *data)
if (ret)
return ret;
- ret = exynos_drm_crtc_create(ctx-manager);
+ ret = exynos_drm_crtc_create(ctx-manager, ctx-pipe);
if (ret) {
mixer_mgr_remove(ctx-manager);
return ret;
--
1.9.3
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[PATCH 0/6] drm/exynos: remove struct exynos_drm_manager
From: Gustavo Padovan gustavo.pado...@collabora.co.uk Following the removal of struct exynos_drm_overlay we now remove the manager one as well. This remove another abstrastraction layer from exynos drm. We can now use known names like CRTC and Planes instead of manager and overlay. This patchset along with the ones I sent before[0][1] also helps clear the path for the upcoming atomic modesetting work. The patchset is based on the other 2 patchset. So be sure to apply them first or pick everything from here: https://git.kernel.org/cgit/linux/kernel/git/padovan/drm-exynos.git/log/?h=cleanup-try2 [0] http://www.spinics.net/lists/linux-samsung-soc/msg39502.html [1] http://www.spinics.net/lists/linux-samsung-soc/msg39614.html Gustavo Padovan (6): drm/exynos: rename base object of struct exynos_drm_crtc to 'base' drm/exynos: add pipe param to exynos_drm_crtc_create() drm/exynos: remove pipe member of struct exynos_drm_manager drm/exynos: move 'type' from manager to crtc struct drm/exynos: remove drm_dev from struct exynos_drm_manager drm/exynos: remove struct exynos_drm_manager drivers/gpu/drm/exynos/exynos_drm_crtc.c | 82 +-- drivers/gpu/drm/exynos/exynos_drm_crtc.h | 6 +- drivers/gpu/drm/exynos/exynos_drm_drv.h | 65 ++- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 127 ++ drivers/gpu/drm/exynos/exynos_drm_plane.c | 26 +++--- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 85 +--- drivers/gpu/drm/exynos/exynos_mixer.c | 109 - 7 files changed, 234 insertions(+), 266 deletions(-) -- 1.9.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/6] drm/exynos: remove drm_dev from struct exynos_drm_manager
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
manager-drm_dev is only accessed by exynos_drm_crtc_create() so this patch
pass drm_dev as argument on exynos_drm_crtc_create() and remove it from
struct exynos_drm_manager.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 9 +
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 3 ++-
drivers/gpu/drm/exynos/exynos_drm_drv.h | 1 -
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 4 ++--
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 4 ++--
drivers/gpu/drm/exynos/exynos_mixer.c| 4 ++--
6 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 224b9af..1eb5750 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -299,12 +299,13 @@ static void exynos_drm_crtc_attach_mode_property(struct
drm_crtc *crtc)
drm_object_attach_property(crtc-base, prop, 0);
}
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe,
+int exynos_drm_crtc_create(struct exynos_drm_manager *manager,
+ struct drm_device *drm_dev, int pipe,
enum exynos_drm_output_type type)
{
struct exynos_drm_crtc *exynos_crtc;
struct drm_plane *plane;
- struct exynos_drm_private *private = manager-drm_dev-dev_private;
+ struct exynos_drm_private *private = drm_dev-dev_private;
struct drm_crtc *crtc;
int ret;
@@ -319,7 +320,7 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager, int pipe,
exynos_crtc-manager = manager;
exynos_crtc-pipe = pipe;
exynos_crtc-type = type;
- plane = exynos_plane_init(manager-drm_dev, 1 pipe,
+ plane = exynos_plane_init(drm_dev, 1 pipe,
DRM_PLANE_TYPE_PRIMARY);
if (IS_ERR(plane)) {
ret = PTR_ERR(plane);
@@ -331,7 +332,7 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager, int pipe,
private-crtc[pipe] = crtc;
- ret = drm_crtc_init_with_planes(manager-drm_dev, crtc, plane, NULL,
+ ret = drm_crtc_init_with_planes(drm_dev, crtc, plane, NULL,
exynos_crtc_funcs);
if (ret 0)
goto err_crtc;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index a705941..d7690e9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -17,7 +17,8 @@
#include exynos_drm_drv.h
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe,
+int exynos_drm_crtc_create(struct exynos_drm_manager *manager,
+ struct drm_device *drm_dev, int pipe,
enum exynos_drm_output_type type);
int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe);
void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index a3ae95f..2d801a8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -211,7 +211,6 @@ struct exynos_drm_manager_ops {
*/
struct exynos_drm_manager {
struct list_head list;
- struct drm_device *drm_dev;
struct drm_crtc *crtc;
struct exynos_drm_manager_ops *ops;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 55154a6..3713be7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -299,7 +299,7 @@ static int fimd_mgr_initialize(struct exynos_drm_manager
*mgr,
struct exynos_drm_private *priv;
priv = drm_dev-dev_private;
- mgr-drm_dev = ctx-drm_dev = drm_dev;
+ ctx-drm_dev = drm_dev;
ctx-pipe = priv-pipe++;
/* attach this sub driver to iommu mapping if supported. */
@@ -1102,7 +1102,7 @@ static int fimd_bind(struct device *dev, struct device
*master, void *data)
struct drm_device *drm_dev = data;
fimd_mgr_initialize(ctx-manager, drm_dev);
- exynos_drm_crtc_create(ctx-manager, ctx-pipe,
+ exynos_drm_crtc_create(ctx-manager, drm_dev, ctx-pipe,
EXYNOS_DISPLAY_TYPE_LCD);
if (ctx-display)
exynos_drm_create_enc_conn(drm_dev, ctx-display);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 3cee0fd..03687db 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -301,7 +301,7 @@ static int vidi_mgr_initialize(struct exynos_drm_manager
*mgr,
struct vidi_context *ctx = manager_to_vidi(mgr);
struct exynos_drm_private *priv = drm_dev-dev_private;
- mgr-drm_dev =
[PATCH 3/6] drm/exynos: remove pipe member of struct exynos_drm_manager
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
It is not longer used. This is part of the process of removing
struct exynos_drm_manager entirely.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_drv.h | 2 --
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 2 +-
drivers/gpu/drm/exynos/exynos_mixer.c| 2 +-
5 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 68aae38..0fe981b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -436,7 +436,7 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
exynos_crtc = to_exynos_crtc(crtc);
if (exynos_crtc-manager-type == out_type)
- return exynos_crtc-manager-pipe;
+ return exynos_crtc-pipe;
}
return -EPERM;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 0a565f8..1d024c0 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -207,7 +207,6 @@ struct exynos_drm_manager_ops {
* @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI.
* @drm_dev: pointer to the drm device
* @crtc: crtc object.
- * @pipe: the pipe number for this crtc/manager
* @ops: pointer to callbacks for exynos drm specific functionality
* @ctx: A pointer to the manager's implementation specific context
*/
@@ -216,7 +215,6 @@ struct exynos_drm_manager {
enum exynos_drm_output_type type;
struct drm_device *drm_dev;
struct drm_crtc *crtc;
- int pipe;
struct exynos_drm_manager_ops *ops;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 1f83a75..6e2092d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -300,7 +300,7 @@ static int fimd_mgr_initialize(struct exynos_drm_manager
*mgr,
priv = drm_dev-dev_private;
mgr-drm_dev = ctx-drm_dev = drm_dev;
- mgr-pipe = ctx-pipe = priv-pipe++;
+ ctx-pipe = priv-pipe++;
/* attach this sub driver to iommu mapping if supported. */
if (is_drm_iommu_supported(ctx-drm_dev)) {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index e78764f..785d2fe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -302,7 +302,7 @@ static int vidi_mgr_initialize(struct exynos_drm_manager
*mgr,
struct exynos_drm_private *priv = drm_dev-dev_private;
mgr-drm_dev = ctx-drm_dev = drm_dev;
- mgr-pipe = ctx-pipe = priv-pipe++;
+ ctx-pipe = priv-pipe++;
return 0;
}
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 9d7dcfc..8301503 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -863,7 +863,7 @@ static int mixer_initialize(struct exynos_drm_manager *mgr,
priv = drm_dev-dev_private;
mgr-drm_dev = mixer_ctx-drm_dev = drm_dev;
- mgr-pipe = mixer_ctx-pipe = priv-pipe++;
+ mixer_ctx-pipe = priv-pipe++;
/* acquire resources: regs, irqs, clocks */
ret = mixer_resources_init(mixer_ctx);
--
1.9.3
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[PATCH 4/6] drm/exynos: move 'type' from manager to crtc struct
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
'type' is now part of the struct exynos_drm_crtc. This is just another
step in the struct exynos_drm_manager removal.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 6 --
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 3 ++-
drivers/gpu/drm/exynos/exynos_drm_drv.h | 4 ++--
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 +++---
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 6 +++---
drivers/gpu/drm/exynos/exynos_mixer.c| 6 +++---
6 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 0fe981b..224b9af 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -299,7 +299,8 @@ static void exynos_drm_crtc_attach_mode_property(struct
drm_crtc *crtc)
drm_object_attach_property(crtc-base, prop, 0);
}
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe)
+int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe,
+ enum exynos_drm_output_type type)
{
struct exynos_drm_crtc *exynos_crtc;
struct drm_plane *plane;
@@ -317,6 +318,7 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager, int pipe)
exynos_crtc-dpms = DRM_MODE_DPMS_OFF;
exynos_crtc-manager = manager;
exynos_crtc-pipe = pipe;
+ exynos_crtc-type = type;
plane = exynos_plane_init(manager-drm_dev, 1 pipe,
DRM_PLANE_TYPE_PRIMARY);
if (IS_ERR(plane)) {
@@ -435,7 +437,7 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
struct exynos_drm_crtc *exynos_crtc;
exynos_crtc = to_exynos_crtc(crtc);
- if (exynos_crtc-manager-type == out_type)
+ if (exynos_crtc-type == out_type)
return exynos_crtc-pipe;
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index f1bee84..a705941 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -17,7 +17,8 @@
#include exynos_drm_drv.h
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe);
+int exynos_drm_crtc_create(struct exynos_drm_manager *manager, int pipe,
+ enum exynos_drm_output_type type);
int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe);
void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe);
void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 1d024c0..a3ae95f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -204,7 +204,6 @@ struct exynos_drm_manager_ops {
* Exynos drm common manager structure, maps 1:1 with a crtc
*
* @list: the list entry for this manager
- * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI.
* @drm_dev: pointer to the drm device
* @crtc: crtc object.
* @ops: pointer to callbacks for exynos drm specific functionality
@@ -212,7 +211,6 @@ struct exynos_drm_manager_ops {
*/
struct exynos_drm_manager {
struct list_head list;
- enum exynos_drm_output_type type;
struct drm_device *drm_dev;
struct drm_crtc *crtc;
struct exynos_drm_manager_ops *ops;
@@ -228,6 +226,7 @@ enum exynos_crtc_mode {
*
* @base: crtc object.
* @manager: the manager associated with this crtc
+ * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI.
* @pipe: a crtc index created at load() with a new crtc object creation
* and the crtc object would be set to private-crtc array
* to get a crtc object corresponding to this pipe from private-crtc
@@ -241,6 +240,7 @@ enum exynos_crtc_mode {
struct exynos_drm_crtc {
struct drm_crtc base;
struct exynos_drm_manager *manager;
+ enum exynos_drm_output_type type;
unsigned intpipe;
unsigned intdpms;
enum exynos_crtc_mode mode;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 6e2092d..55154a6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -1102,7 +1102,8 @@ static int fimd_bind(struct device *dev, struct device
*master, void *data)
struct drm_device *drm_dev = data;
fimd_mgr_initialize(ctx-manager, drm_dev);
- exynos_drm_crtc_create(ctx-manager, ctx-pipe);
+ exynos_drm_crtc_create(ctx-manager, ctx-pipe,
+ EXYNOS_DISPLAY_TYPE_LCD);
if (ctx-display)
exynos_drm_create_enc_conn(drm_dev, ctx-display);
@@ -1143,11 +1144,10 @@
[PATCH 6/6] drm/exynos: remove struct exynos_drm_manager
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
exynos_drm_manager was just a redundant struct to represent the crtc as
well. In this commit we merge exynos_drm_manager into exynos_drm_crtc to
remove an unnecessary level of indirection easing the understand of the
flow on exynos.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 67 -
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 8 +-
drivers/gpu/drm/exynos/exynos_drm_drv.h | 51 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 121 ++
drivers/gpu/drm/exynos/exynos_drm_plane.c | 26 +++
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 79 +--
drivers/gpu/drm/exynos/exynos_mixer.c | 103 -
7 files changed, 211 insertions(+), 244 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 1eb5750..9e8ed5f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -23,7 +23,6 @@
static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct exynos_drm_manager *manager = exynos_crtc-manager;
DRM_DEBUG_KMS(crtc[%d] mode[%d]\n, crtc-base.id, mode);
@@ -41,8 +40,8 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
drm_crtc_vblank_off(crtc);
}
- if (manager-ops-dpms)
- manager-ops-dpms(manager, mode);
+ if (exynos_crtc-ops-dpms)
+ exynos_crtc-ops-dpms(exynos_crtc, mode);
exynos_crtc-dpms = mode;
@@ -58,16 +57,15 @@ static void exynos_drm_crtc_prepare(struct drm_crtc *crtc)
static void exynos_drm_crtc_commit(struct drm_crtc *crtc)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct exynos_drm_manager *manager = exynos_crtc-manager;
struct exynos_drm_plane *exynos_plane = to_exynos_plane(crtc-primary);
exynos_drm_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
- if (manager-ops-win_commit)
- manager-ops-win_commit(manager, exynos_plane-zpos);
+ if (exynos_crtc-ops-win_commit)
+ exynos_crtc-ops-win_commit(exynos_crtc, exynos_plane-zpos);
- if (manager-ops-commit)
- manager-ops-commit(manager);
+ if (exynos_crtc-ops-commit)
+ exynos_crtc-ops-commit(exynos_crtc);
exynos_plane_dpms(crtc-primary, DRM_MODE_DPMS_ON);
}
@@ -78,10 +76,10 @@ exynos_drm_crtc_mode_fixup(struct drm_crtc *crtc,
struct drm_display_mode *adjusted_mode)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct exynos_drm_manager *manager = exynos_crtc-manager;
- if (manager-ops-mode_fixup)
- return manager-ops-mode_fixup(manager, mode, adjusted_mode);
+ if (exynos_crtc-ops-mode_fixup)
+ return exynos_crtc-ops-mode_fixup(exynos_crtc, mode,
+ adjusted_mode);
return true;
}
@@ -92,7 +90,6 @@ exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct
drm_display_mode *mode,
struct drm_framebuffer *old_fb)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct exynos_drm_manager *manager = exynos_crtc-manager;
struct drm_framebuffer *fb = crtc-primary-fb;
unsigned int crtc_w;
unsigned int crtc_h;
@@ -106,8 +103,8 @@ exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct
drm_display_mode *mode,
crtc_w = fb-width - x;
crtc_h = fb-height - y;
- if (manager-ops-mode_set)
- manager-ops-mode_set(manager, crtc-mode);
+ if (exynos_crtc-ops-mode_set)
+ exynos_crtc-ops-mode_set(exynos_crtc, crtc-mode);
return exynos_plane_mode_set(crtc-primary, crtc, fb, 0, 0,
crtc_w, crtc_h, x, y, crtc_w, crtc_h);
@@ -299,9 +296,11 @@ static void exynos_drm_crtc_attach_mode_property(struct
drm_crtc *crtc)
drm_object_attach_property(crtc-base, prop, 0);
}
-int exynos_drm_crtc_create(struct exynos_drm_manager *manager,
- struct drm_device *drm_dev, int pipe,
- enum exynos_drm_output_type type)
+struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
+ int pipe,
+ enum exynos_drm_output_type type,
+ struct exynos_drm_crtc_ops *ops,
+ void *ctx)
{
struct exynos_drm_crtc *exynos_crtc;
struct drm_plane *plane;
@@ -311,15 +310,16 @@ int exynos_drm_crtc_create(struct exynos_drm_manager
*manager,
exynos_crtc =
Re: [PATCH 06/19] usb: dwc3: host: Pass the XHCI_DRD_SUPPORT and XHCI_NEEDS_LHC_RESET quirk
On 2014年11月25日 21:11, George Cherian wrote:
Pass the quir flag XHCI_DRD_SUPPORT from DWC3 host to xhci platform driver.
quir to quirk
Regards,
Baolu
This enables xhci driver to handle deallocation's differently while in DRD mode.
Pass the quirk flag XHCI_NEEDS_LHC_RESET from DWC3 host to xhci platform
driver. This enables to do LHRESET during xhci_reset().
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index dcb8ca0..257b5b5 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -53,6 +53,8 @@ int dwc3_host_init(struct dwc3 *dwc)
#ifdef CONFIG_DWC3_HOST_USB3_LPM_ENABLE
pdata.usb3_lpm_capable = 1;
#endif
+ pdata.usb_drd_support = 1;
+ pdata.usb_needs_lhc_reset = 1;
ret = platform_device_add_data(xhci, pdata, sizeof(pdata));
if (ret) {
--
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Re: [PATCH v6 1/2] i2c: s3c2410: add Sysreg phandle to i2c device nodes
On Thursday 27 November 2014 12:13 AM, Kukjin Kim wrote: On 11/24/14 17:47, Pankaj Dubey wrote: This patch adds syscon based phandle to i2c device nodes of exynos5250 and exynos5420. These phandles will be used to save restore i2c sysreg configuration register during s2r from i2c driver. CC: Rob Herring robh...@kernel.org CC: Randy Dunlap rdun...@infradead.org CC: Russell King li...@arm.linux.org.uk CC: devicet...@vger.kernel.org CC: linux-...@vger.kernel.org Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Applied with change the subject 'ARM: dts: add sysreg phandle to...' Thanks for correcting subject message. BTW I'm holding on 2nd because conflicts between pm update and cleanup branches in my tree... Please let me know if anything to be done from my end. Thanks, Pankaj Dubey - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] thermal: cpu_cooling: check for the readiness of cpufreq layer
Few nits..
On 26 November 2014 at 23:20, Eduardo Valentin edubez...@gmail.com wrote:
Signed-off-by: Eduardo Valentin edubez...@gmail.com
---
The normal practice is to write the non-commitable part here ...
drivers/thermal/cpu_cooling.c | 5 +
drivers/thermal/db8500_cpufreq_cooling.c | 5 -
drivers/thermal/imx_thermal.c | 5 -
drivers/thermal/samsung/exynos_thermal_common.c| 2 +-
drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 6 --
5 files changed, 6 insertions(+), 17 deletions(-)
---
But this works as well :)
This is attempt to organize the cpu cooling vs. cpufreq boot sequencing.
The main change in this patch, as in the commit log, is to have the check
for the cpufreq layer in the cpu cooling device registration, instead of
in thermal drivers. This way, drivers don't need to bother about it, they
just need to propagate the error value.
This change was tested on top of:
(0) - Viresh's change in cpufreq layer and cpufreq-dt (up to patch 4):
https://patchwork.kernel.org/patch/5384141/
https://patchwork.kernel.org/patch/5384151/
https://patchwork.kernel.org/patch/5384161/
https://patchwork.kernel.org/patch/5384171/
(1) - fix of thermal core:
https://patchwork.kernel.org/patch/5326991/
After Viresh's changes, cpufreq-dt is properly sequenced with cpu cooling
registration. Non-of based drivers also should take advantage if these
changes, as now they do not need to check for cpufreq layer. The check is
where it belongs, in cpu cooling device registration.
BR, Eduardo Valentin
diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
index 1ab0018..9e6945b 100644
--- a/drivers/thermal/cpu_cooling.c
+++ b/drivers/thermal/cpu_cooling.c
@@ -440,6 +440,11 @@ __cpufreq_cooling_register(struct device_node *np,
int ret = 0, i;
struct cpufreq_policy policy;
+ if (!cpufreq_get_current_driver() || !cpufreq_frequency_get_table(0))
{
Only !cpufreq_frequency_get_table(0) is enough here.
For rest:
Acked-by: Viresh Kumar viresh.ku...@linaro.org
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[GIT PULL 2/4] Samsung serial updates for v3.19
Hi Arnd, Olof, Kevin Please pull this branch for exynos7 SoC into arm-soc. Note Greg agreed to upstream via arm-soc tree. Thanks, Kukjin The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1: Linux 3.18-rc1 (2014-10-19 18:08:38 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-driver for you to fetch changes up to edeeec85f7145fe8f2a5ffe250a8ee6b1fe4ab28: serial: samsung: Fix serial config dependencies for exynos7 (2014-11-22 00:09:25 +0900) Samsung driver update for v3.19 - Change samsung serial dependencies for exynos7 (ARMv8) Pankaj Dubey (1): serial: samsung: Fix serial config dependencies for exynos7 drivers/tty/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL 1/4] Samsung 3rd round of PM updates for v3.19
The following changes since commit c645a598f99768e6cc82129081458dfdd0c273b7: ARM: EXYNOS: Call regulator core suspend prepare and finish functions (2014-11-21 22:49:47 +0900) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-pm-3 for you to fetch changes up to b04fa9f704aa818b87509ff4149bba810ef8bbd8: ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf (2014-11-27 02:47:05 +0900) Samsung PM 3rd updates for v3.19 - exynos3250 : add PMU support - PMU refactoring : move restart code into PMU driver : move restart code for exynos440 into clk driver - use u8 for val[] in struct exynos_pmu_conf Note that this branch is based on tags/samsung-exynos-v3.19 Bartlomiej Zolnierkiewicz (2): ARM: EXYNOS: add exynos3250 PMU support ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf Pankaj Dubey (2): clk: exynos5440: move restart code into clock driver ARM: EXYNOS: move restart code into pmu driver arch/arm/mach-exynos/common.h| 1 - arch/arm/mach-exynos/exynos.c| 23 - arch/arm/mach-exynos/pmu.c | 192 ++- arch/arm/mach-exynos/regs-pmu.h | 128 +++ drivers/clk/samsung/clk-exynos5440.c | 29 +- 5 files changed, 347 insertions(+), 26 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL 3/4] Samsung 3rd round of DT updates for v3.19
The following changes since commit a427d15062ac46a00a22d2f0b9d05093c18ff2f1: ARM: dts: Add micro SD card SDHCI node for exynos4412-trats (2014-11-07 08:28:24 +0900) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-dt-3 for you to fetch changes up to 1888eb75e68caceaab2fe0db820bd6ed574a468f: ARM: dts: add sysreg phandle to i2c device nodes for exynos (2014-11-27 03:24:45 +0900) Samsung 3rd DT updates for v3.19 - exynos3250 : remove unused bootargs on exynos3250-rinato : add new board dt file for exynos3250-monk - exynos4 : add missing clock for MFC : specify default clocks for camera - exynos4x12 : add TMU related DT nodes - exynos4412-trats2 : add max77693-haptic and pwm nodes, enable TMU support - exynos4412-odroid : specify audio clock parents and rates - exynos5250 and exynos5420 : add syscon based phandle to i2c device nodes - exynos5250-spring : add trackpad, temperature sensor and usb3505 pinctrl Note: based on previous tags/samsung-dt-2 for v3.19 Andreas Faerber (3): ARM: dts: Add usb3503 pinctrl to exynos5250-spring ARM: dts: Add temperature sensor to exynos5250-spring ARM: dts: Add trackpad to exynos5250-spring Chanwoo Choi (2): Documentation: devicetree: Add Exynos-based boards compatible string ARM: dts: Remove unused bootargs from exynos3250-rinato Jaewon Kim (2): ARM: dts: add pwm node for exynos4412-trats2 ARM: dts: Add max77693-haptic node for exynos4412-trats2 Lukasz Majewski (2): ARM: dts: Device tree node definition for TMU on exynos4x12 ARM: dts: Enable TMU support for exynos4412-trats2 Marek Szyprowski (1): ARM: dts: add missing clock to MFC device for exynos4 Pankaj Dubey (1): ARM: dts: add sysreg phandle to i2c device nodes for exynos Sylwester Nawrocki (2): ARM: dts: Specify default clocks for Exynos4 camera devices ARM: dts: Specify audio clock parents and rates for exynos4412-odroid-common Youngjun Cho (1): ARM: dts: add board dts file for Exynos3250-based Monk board .../devicetree/bindings/arm/samsung-boards.txt | 19 +- .../devicetree/bindings/i2c/i2c-s3c2410.txt| 1 + arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/exynos3250-monk.dts | 579 + arch/arm/boot/dts/exynos3250-rinato.dts| 4 - arch/arm/boot/dts/exynos4.dtsi | 4 +- arch/arm/boot/dts/exynos4210-trats.dts | 16 + arch/arm/boot/dts/exynos4210-universal_c210.dts| 16 + arch/arm/boot/dts/exynos4412-odroid-common.dtsi| 26 + arch/arm/boot/dts/exynos4412-trats2.dts| 50 +- arch/arm/boot/dts/exynos4x12.dtsi | 10 + arch/arm/boot/dts/exynos5250-spring.dts| 30 ++ arch/arm/boot/dts/exynos5250.dtsi | 4 + arch/arm/boot/dts/exynos5420.dtsi | 4 + 14 files changed, 751 insertions(+), 15 deletions(-) create mode 100644 arch/arm/boot/dts/exynos3250-monk.dts -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL 4/4] Samsung exynos7 updates for v3.19
The following changes since commit 3b1f6f3450b6a64aead53d09fc6f8bba2999c450: Merge remote-tracking branch 'arm-soc/cleanup/dts-subdirs' into v3.19-next/dt-samsung-64 (2014-11-26 16:02:13 +0900) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-dt-64 for you to fetch changes up to ab93f6ca63943d6eca9494547127fe1c337c1d83: arm64: Enable ARMv8 based exynos7 SoC support (2014-11-27 02:14:00 +0900) Samsung arch/arm64 DT updates for v3.19 - to support ARMv8 based exynos7 SoC : add initial device tree and add pinctrl, PMU, mmc, i2c, rtc, watchdog, and adc nodes for exynos7 SoC and exynos7 based espresso board. NOTE that this is including following dependencies : cleanup/dts-subdirs in arm-soc for arm64 vendor support : tags/samsung-driver for samsung serial : for-v3.19/exynos-clk in samsung-clk tree for exynos7 clk One more NOTE, for support exynos7 we need Liviu's arm64: Create link to include/dt-bindings to enable C preprocessor use in arm-soc tree and arm64 defconfig update should be handled directly. Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on exynos7 Alim Akhtar (1): arm64: Enable ARMv8 based exynos7 SoC support Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for exynos7 arm64: dts: Add initial pinctrl support to exynos7 .../devicetree/bindings/arm/samsung/pmu.txt| 1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 + arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ 7 files changed, 1226 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v5] arm64: dts: exynos7: add support for cpuidle core power down
Chander Kashyap wrote:
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.
This patch adds support for core power down idle state.
Entry latency for core power down idle state is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in a set of 10 cpuidle transactions,
with varying load.
Exit latency and min residency values are supplied as per HW team.
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Lorenzo, thanks for your ack. Will apply.
- Kukjin
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
www.spinics.net/lists/arm-kernel/msg375961.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.
Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.
Changes in v5:
- Commit message modified
arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..891eef4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x0;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x1;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x2;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x3;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
+ };
+
+ idle-states {
+ entry-method = arm,psci;
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = arm,idle-state;
+ local-timer-stop;
+ arm,psci-suspend-param = 0x001;
+ entry-latency-us = 34;
+ exit-latency-us = 150;
+ min-residency-us = 2100;
+ };
};
};
--
1.9.1
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[PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be
always on.]
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 79 +-
include/dt-bindings/clock/exynos5433.h | 34 ++-
2 files changed, 111 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index e0d71fd..11ee2d8 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -259,6 +259,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[]
__initdata = {
FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+ /* XspiCLK[4:0] input clock for SPI */
+ FRATE(0, ioclk_spi4_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi3_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi2_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi1_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi0_clk_in, NULL, CLK_IS_ROOT, 5000),
+ /* Xi2s1SCLK input clock for I2S1_BCLK */
+ FRATE(0, ioclk_i2s1_bclk_in, NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -763,6 +771,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC 0x0600
+#define DIV_STAT_PERIC 0x0700
#define ENABLE_ACLK_PERIC 0x0800
#define ENABLE_PCLK_PERIC0 0x0900
#define ENABLE_PCLK_PERIC1 0x0904
@@ -773,6 +782,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+ DIV_STAT_PERIC,
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -782,14 +792,56 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+ /* DIV_PERIC */
+ DIV(CLK_DIV_SCLK_SCI, div_sclk_sci, fin_pll, DIV_PERIC, 4, 8),
+ DIV(CLK_DIV_SCLK_SC_IN, div_sclk_sc_in, fin_pll, DIV_PERIC, 0, 4),
+};
+
static struct samsung_gate_clock peric_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIC */
+ GATE(CLK_ACLK_AHB2APB_PERIC2P, aclk_ahb2apb_peric2p, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC1P, aclk_ahb2apb_peric1p, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC0P, aclk_ahb2apb_peric0p, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERICNP_66, aclk_pericnp_66, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIC0 */
+ GATE(CLK_PCLK_SCI, pclk_sci, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 31, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_FINGER, pclk_gpio_finger, aclk_peric_66,
+ ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ESE, pclk_gpio_ese, aclk_peric_66,
+ ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PWM, pclk_pwm, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 28, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPDIF, pclk_spdif, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 26, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_PCM1, pclk_pcm1, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 25, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2S1, pclk_i2s, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI2, pclk_spi2, aclk_peric_66, ENABLE_PCLK_PERIC0,
23, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI1, pclk_spi1, aclk_peric_66, ENABLE_PCLK_PERIC0,
22, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI0, pclk_spi0, aclk_peric_66, ENABLE_PCLK_PERIC0,
21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_ADCIF, pclk_adcif, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_TOUCH, pclk_gpio_touch, aclk_peric_66,
+ ENABLE_PCLK_PERIC0, 19,
[PATCH 15/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas catalin.mari...@arm.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com Acked-by: Inki Dae inki@samsung.com --- arch/arm64/Kconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f4536e0..8a5e8a0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -152,6 +152,16 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool ARMv8 based Samsung Exynos5433 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 10/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
drivers/clk/samsung/clk-exynos5433.c | 173 +
include/dt-bindings/clock/exynos5433.h | 53 +++
3 files changed, 233 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 8d3dad4..9a6ae75 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -23,6 +23,8 @@ Required Properties:
which generates clocks for G2D/MDMA IPs.
- samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
+ - samsung,exynos5433-cmu-aud - clock controller compatible for CMU_AUD
+which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_aud: clock-controller@0x114c {
+ compatible = samsung,exynos5433-cmu-aud;
+ reg = 0x114c 0x0b04;
+ #clock-cells = 1;
+ };
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index cd48209..9f28672 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2456,3 +2456,176 @@ static void __init exynos5433_cmu_disp_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_disp, samsung,exynos5433-cmu-disp,
exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0 0x0200
+#define MUX_SEL_AUD1 0x0204
+#define MUX_ENABLE_AUD00x0300
+#define MUX_ENABLE_AUD10x0304
+#define MUX_STAT_AUD0 0x0400
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define ENABLE_ACLK_AUD0x0800
+#define ENABLE_PCLK_AUD0x0900
+#define ENABLE_SCLK_AUD0 0x0a00
+#define ENABLE_SCLK_AUD1 0x0a04
+#define ENABLE_IP_AUD0 0x0b00
+#define ENABLE_IP_AUD1 0x0b04
+
+static unsigned long aud_clk_regs[] __initdata = {
+ MUX_SEL_AUD0,
+ MUX_SEL_AUD1,
+ MUX_ENABLE_AUD0,
+ MUX_ENABLE_AUD1,
+ MUX_STAT_AUD0,
+ DIV_AUD0,
+ DIV_AUD1,
+ DIV_STAT_AUD0,
+ DIV_STAT_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD0,
+ ENABLE_SCLK_AUD1,
+ ENABLE_IP_AUD0,
+ ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p) = { fin_pll, fout_aud_pll, };
+PNAME(mout_sclk_aud_pcm_p) = { mout_aud_pll_user, ioclk_audiocdclk0,};
+PNAME(mout_sclk_aud_i2s_p) = { mout_aud_pll_user, ioclk_audiocdclk0,};
+
+static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
+ FRATE(0, ioclk_jtag_tclk, NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, ioclk_slimbus_clk, NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, ioclk_i2s_bclk, NULL, CLK_IS_ROOT, 18800),
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+ /* MUX_SEL_AUD0 */
+ MUX(CLK_MOUT_AUD_PLL_USER, mout_aud_pll_user,
+ mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+ /* MUX_SEL_AUD1 */
+ MUX(CLK_MOUT_SCLK_AUD_PCM, mout_sclk_aud_pcm, mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 8, 1),
+ MUX(CLK_MOUT_SCLK_AUD_I2S, mout_sclk_aud_i2s, mout_sclk_aud_i2s_p,
+ MUX_SEL_AUD1, 0, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+ /* DIV_AUD0 */
+ DIV(CLK_DIV_ATCLK_AUD, div_atclk_aud, div_aud_ca5, DIV_AUD0,
+ 12, 4),
+ DIV(CLK_DIV_PCLK_DBG_AUD, div_pclk_dbg_aud, div_aud_ca5, DIV_AUD0,
+ 8, 4),
+ DIV(CLK_DIV_ACLK_AUD, div_aclk_aud, div_aud_ca5, DIV_AUD0,
+ 4, 4),
+ DIV(CLK_DIV_AUD_CA5, div_aud_ca5, mout_aud_pll_user, DIV_AUD0,
+ 0, 4),
+
+ /* DIV_AUD1 */
+ DIV(CLK_DIV_SCLK_AUD_SLIMBUS, div_sclk_aud_slimbus,
+
[PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +
include/dt-bindings/clock/exynos5433.h | 42 +-
3 files changed, 193 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 72cd0ba..27dd77b 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -19,6 +19,8 @@ Required Properties:
which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- samsung,exynos5433-cmu-fsys - clock controller compatible for CMU_FSYS
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+ - samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
+which generates clocks for G2D/MDMA IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -70,6 +72,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_g2d: clock-controller@0x1246 {
+ compatible = samsung,exynos5433-cmu-g2d;
+ reg = 0x1246 0x0b08;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index b09f2cfe..dd1e6a1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -403,6 +403,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
};
static struct samsung_div_clock top_div_clks[] __initdata = {
+ /* DIV_TOP1 */
+ DIV(CLK_DIV_ACLK_GSCL_111, div_aclk_gscl_111, mout_aclk_gscl_333,
+ DIV_TOP1, 28, 3),
+ DIV(CLK_DIV_ACLK_GSCL_333, div_aclk_gscl_333, mout_aclk_gscl_333,
+ DIV_TOP1, 24, 3),
+ DIV(CLK_DIV_ACLK_HEVC_400, div_aclk_hevc_400, mout_aclk_hevc_400,
+ DIV_TOP1, 20, 3),
+ DIV(CLK_DIV_ACLK_MFC_400, div_aclk_mfc_400, mout_aclk_mfc_400_c,
+ DIV_TOP1, 12, 3),
+ DIV(CLK_DIV_ACLK_G2D_266, div_aclk_g2d_266, mout_bus_pll_user,
+ DIV_TOP1, 8, 3),
+ DIV(CLK_DIV_ACLK_G2D_400, div_aclk_g2d_400, mout_aclk_g2d_400_b,
+ DIV_TOP1, 0, 3),
+
/* DIV_TOP2 */
DIV(CLK_DIV_ACLK_FSYS_200, div_aclk_fsys_200, mout_bus_pll_user,
DIV_TOP2, 0, 3),
@@ -492,6 +506,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, aclk_fsys_200, div_aclk_fsys_200,
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_266, aclk_g2d_266, div_aclk_g2d_266,
+ ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_400, aclk_g2d_400, div_aclk_g2d_400,
+ ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
@@ -1277,3 +1295,129 @@ static void __init exynos5433_cmu_fsys_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_fsys, samsung,exynos5433-cmu-fsys,
exynos5433_cmu_fsys_init);
+
+/*
+ * Register offset definitions for CMU_G2D
+ */
+#define MUX_SEL_G2D0 0x0200
+#define MUX_SEL_ENABLE_G2D00x0300
+#define MUX_SEL_STAT_G2D0 0x0400
+#define DIV_G2D0x0600
+#define DIV_STAT_G2D 0x0700
+#define DIV_ENABLE_ACLK_G2D0x0800
+#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D0x0804
+#define DIV_ENABLE_PCLK_G2D0x0900
+#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D0x0904
+#define DIV_ENABLE_IP_G2D0 0x0b00
+#define DIV_ENABLE_IP_G2D1 0x0b04
+#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
+
+static unsigned long g2d_clk_regs[] __initdata = {
+ MUX_SEL_G2D0,
+ MUX_SEL_ENABLE_G2D0,
+ MUX_SEL_STAT_G2D0,
+ DIV_G2D,
+ DIV_STAT_G2D,
+ DIV_ENABLE_ACLK_G2D,
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_PCLK_G2D,
+
[PATCH 19/19] serial: samsung: Add the support for Exynos5433 SoC
This patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC
because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: Jiri Slaby jsl...@suse.cz
Cc: linux-ser...@vger.kernel.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/tty/serial/samsung.c | 56
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 2338ad8..6f1fb9a 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1766,32 +1766,43 @@ static struct s3c24xx_serial_drv_data
s5pv210_serial_drv_data = {
#endif
#if defined(CONFIG_ARCH_EXYNOS)
+#define EXYNOS_COMMON_SERIAL_DRV_DATA \
+ .info = (struct s3c24xx_uart_info) { \
+ .name = Samsung Exynos UART,\
+ .type = PORT_S3C6400, \
+ .has_divslot= 1,\
+ .rx_fifomask= S5PV210_UFSTAT_RXMASK,\
+ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
+ .rx_fifofull= S5PV210_UFSTAT_RXFULL,\
+ .tx_fifofull= S5PV210_UFSTAT_TXFULL,\
+ .tx_fifomask= S5PV210_UFSTAT_TXMASK,\
+ .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
+ .def_clk_sel= S3C2410_UCON_CLKSEL0, \
+ .num_clks = 1,\
+ .clksel_mask= 0,\
+ .clksel_shift = 0,\
+ }, \
+ .def_cfg = (struct s3c2410_uartcfg) { \
+ .ucon = S5PV210_UCON_DEFAULT, \
+ .ufcon = S5PV210_UFCON_DEFAULT,\
+ .has_fracval= 1,\
+ } \
+
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
- .info = (struct s3c24xx_uart_info) {
- .name = Samsung Exynos4 UART,
- .type = PORT_S3C6400,
- .has_divslot= 1,
- .rx_fifomask= S5PV210_UFSTAT_RXMASK,
- .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
- .rx_fifofull= S5PV210_UFSTAT_RXFULL,
- .tx_fifofull= S5PV210_UFSTAT_TXFULL,
- .tx_fifomask= S5PV210_UFSTAT_TXMASK,
- .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
- .def_clk_sel= S3C2410_UCON_CLKSEL0,
- .num_clks = 1,
- .clksel_mask= 0,
- .clksel_shift = 0,
- },
- .def_cfg = (struct s3c2410_uartcfg) {
- .ucon = S5PV210_UCON_DEFAULT,
- .ufcon = S5PV210_UFCON_DEFAULT,
- .has_fracval= 1,
- },
+ EXYNOS_COMMON_SERIAL_DRV_DATA,
.fifosize = { 256, 64, 16, 16 },
};
+
+static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
+ EXYNOS_COMMON_SERIAL_DRV_DATA,
+ .fifosize = { 64, 256, 16, 256 },
+};
+
#define EXYNOS4210_SERIAL_DRV_DATA
((kernel_ulong_t)exynos4210_serial_drv_data)
+#define EXYNOS5433_SERIAL_DRV_DATA
((kernel_ulong_t)exynos5433_serial_drv_data)
#else
#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
+#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
#endif
static struct platform_device_id s3c24xx_serial_driver_ids[] = {
@@ -1813,6 +1824,9 @@ static struct platform_device_id
s3c24xx_serial_driver_ids[] = {
}, {
.name = exynos4210-uart,
.driver_data= EXYNOS4210_SERIAL_DRV_DATA,
+ }, {
+ .name = exynos5433-uart,
+ .driver_data= EXYNOS5433_SERIAL_DRV_DATA,
},
{ },
};
@@ -1832,6 +1846,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[]
= {
.data = (void *)S5PV210_SERIAL_DRV_DATA },
{ .compatible = samsung,exynos4210-uart,
.data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
+ { .compatible = samsung,exynos5433-uart,
+ .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
{},
};
MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
--
1.8.5.5
--
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[PATCH 13/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 127 +
include/dt-bindings/clock/exynos5433.h | 25
3 files changed, 160 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 03ae40a..589ed93 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -28,6 +28,8 @@ Required Properties:
- samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
and samsung,exynos5433-cmu-bus2 - clock controller compatible for CMU_BUS
which generates global data buses clock and global peripheral buses clock.
+ - samsung,exynos5433-cmu-g3d - clock controller compatible for CMU_G3D
+which generates clocks for 3D Graphics Engine IP.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -115,6 +117,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_g3d: clock-controller@0x14aa {
+ compatible = samsung,exynos5433-cmu-g3d;
+ reg = 0x14aa 0x1000;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index ee26974..920bc3c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3137,3 +3137,130 @@ static void __init exynos5433_cmu_bus2_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_bus2, samsung,exynos5433-cmu-bus2,
exynos5433_cmu_bus2_init);
+
+/*
+ * Register offset definitions for CMU_G3D
+ */
+#define G3D_PLL_LOCK 0x
+#define G3D_PLL_CON0 0x0100
+#define G3D_PLL_CON1 0x0104
+#define G3D_PLL_FREQ_DET 0x010c
+#define MUX_SEL_G3D0x0200
+#define MUX_ENABLE_G3D 0x0300
+#define MUX_STAT_G3D 0x0400
+#define DIV_G3D0x0600
+#define DIV_G3D_PLL_FREQ_DET 0x0604
+#define DIV_STAT_G3D 0x0700
+#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_G3D0x0800
+#define ENABLE_PCLK_G3D0x0900
+#define ENABLE_SCLK_G3D0x0a00
+#define ENABLE_IP_G3D0 0x0b00
+#define ENABLE_IP_G3D1 0x0b04
+#define CLKOUT_CMU_G3D 0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT0x0c04
+#define CLK_STOPCTRL 0x1000
+
+static unsigned long g3d_clk_regs[] __initdata = {
+ G3D_PLL_LOCK,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_FREQ_DET,
+ MUX_SEL_G3D,
+ MUX_ENABLE_G3D,
+ MUX_STAT_G3D,
+ DIV_G3D,
+ DIV_G3D_PLL_FREQ_DET,
+ DIV_STAT_G3D,
+ DIV_STAT_G3D_PLL_FREQ_DET,
+ ENABLE_ACLK_G3D,
+ ENABLE_PCLK_G3D,
+ ENABLE_SCLK_G3D,
+ ENABLE_IP_G3D0,
+ ENABLE_IP_G3D1,
+ CLKOUT_CMU_G3D,
+ CLKOUT_CMU_G3D_DIV_STAT,
+ CLK_STOPCTRL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g3d_400_p) = { mout_g3d_pll, aclk_g3d_400, };
+PNAME(mout_g3d_pll_p) = { fin_pll, fout_g3d_pll, };
+
+static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_G3D_PLL, fout_g3d_pll, fin_pll,
+ G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
+ /* MUX_SEL_G3D */
+ MUX(CLK_MOUT_ACLK_G3D_400, mout_aclk_g3d_400, mout_aclk_g3d_400_p,
+ MUX_SEL_G3D, 8, 1),
+ MUX(CLK_MOUT_G3D_PLL, mout_g3d_pll, mout_g3d_pll_p,
+ MUX_SEL_G3D, 0, 1),
+};
+
+static struct samsung_div_clock g3d_div_clks[] __initdata = {
+ /* DIV_G3D */
+ DIV(CLK_DIV_SCLK_HPM_G3D, div_sclk_hpm_g3d, mout_g3d_pll, DIV_G3D,
+ 8, 2),
+ DIV(CLK_DIV_PCLK_G3D, div_pclk_g3d, div_aclk_g3d, DIV_G3D,
+ 4, 3),
+ DIV(CLK_DIV_ACLK_G3D, div_aclk_g3d, mout_aclk_g3d_400, DIV_G3D,
+ 0, 3),
+};
+
+static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_G3D */
+ GATE(CLK_ACLK_BTS_G3D1, aclk_bts_g3d1, div_aclk_g3d,
+ ENABLE_ACLK_G3D,
[PATCH 17/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433
From: Jaehoon Chung jh80.ch...@samsung.com
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 3d8b576..cfe3de8 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -53,6 +53,9 @@
i2c9 = hsi2c_9;
i2c10 = hsi2c_10;
i2c11 = hsi2c_11;
+ mshc0 = mshc_0;
+ mshc1 = mshc_1;
+ mshc2 = mshc_2;
};
chipid@1000 {
@@ -507,6 +510,45 @@
status = disabled;
};
+ mshc_0: mshc@1554 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 225 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1554 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC0,
+cmu_fsys CLK_SCLK_MMC0;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
+ mshc_1: mshc@1555 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 226 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1555 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC1,
+cmu_fsys CLK_SCLK_MMC1;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
+ mshc_2: mshc@1556 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 227 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1556 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC2,
+cmu_fsys CLK_SCLK_MMC2;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
timer {
compatible = arm,armv8-timer;
interrupts = 1 13 0xff01,
--
1.8.5.5
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[PATCH 12/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 285 +
include/dt-bindings/clock/exynos5433.h | 82 +-
2 files changed, 364 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index f0975e1..ee26974 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -467,6 +467,16 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_SCLK_MMC2_A, div_sclk_mmc2_a, mout_sclk_mmc2_b,
DIV_TOP_FSYS0, 0, 4),
+ /* DIV_TOP_FSYS2 */
+ DIV(CLK_DIV_SCLK_PCIE_100, div_sclk_pcie_100, mout_sclk_pcie_100,
+ DIV_TOP_FSYS2, 12, 3),
+ DIV(CLK_DIV_SCLK_USBHOST30, div_sclk_usbhost30,
+ mout_sclk_usbhost30, DIV_TOP_FSYS2, 8, 4),
+ DIV(CLK_DIV_SCLK_UFSUNIPRO, div_sclk_ufsunipro,
+ mout_sclk_ufsunipro, DIV_TOP_FSYS2, 4, 4),
+ DIV(CLK_DIV_SCLK_USBDRD30, div_sclk_usbdrd30, mout_sclk_usbdrd30,
+ DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, div_sclk_spi1_b, div_sclk_spi1_a,
DIV_TOP_PERIC0, 16, 8),
@@ -539,12 +549,20 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_PCIE_100_FSYS, sclk_pcie_100_fsys, div_sclk_pcie_100,
+ ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, sclk_mmc1_fsys, div_sclk_mmc1_b,
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, sclk_mmc0_fsys, div_sclk_mmc0_b,
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO_FSYS, sclk_ufsunipro_fsys,
+ div_sclk_ufsunipro, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBHOST30_FSYS, sclk_usbhost30_fsys,
+ div_sclk_usbhost30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBDRD30_FSYS, sclk_usbdrd30_fsys,
+ div_sclk_usbdrd30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, sclk_spi4_peric, div_sclk_spi4_b,
@@ -1821,10 +1839,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris,
samsung,exynos5433-cmu-peris,
#define ENABLE_IP_FSYS10x0b04
/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p) = { fin_pll, sclk_ufs_mphy, };
PNAME(mout_aclk_fsys_200_user_p) = { fin_pll, aclk_fsys_200, };
+PNAME(mout_sclk_pcie_100_user_p) = { fin_pll, sclk_ufsunipro_fsys,};
+PNAME(mout_sclk_ufsunipro_user_p) = { fin_pll, sclk_ufsunipro_fsys,};
PNAME(mout_sclk_mmc2_user_p) = { fin_pll, sclk_mmc2_fsys, };
PNAME(mout_sclk_mmc1_user_p) = { fin_pll, sclk_mmc1_fsys, };
PNAME(mout_sclk_mmc0_user_p) = { fin_pll, sclk_mmc0_fsys, };
+PNAME(mout_sclk_usbhost30_user_p) = { fin_pll, sclk_usbhost30_fsys,};
+PNAME(mout_sclk_usbdrd30_user_p) = { fin_pll, sclk_usbdrd30_fsys, };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+ = { fin_pll, phyclk_usbhost20_phy_hsic1_phy, };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_clk48mohci_phy, };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_freeclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+ = { fin_pll, phyclk_ufs_rx1_symbol_phy, };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+ = { fin_pll, phyclk_ufs_rx0_symbol_phy, };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+ = { fin_pll, phyclk_ufs_tx1_symbol_phy, };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+ = { fin_pll,
[PATCH 14/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 143 +
include/dt-bindings/clock/exynos5433.h | 37 +-
3 files changed, 187 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 589ed93..bf72817 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -30,6 +30,8 @@ Required Properties:
which generates global data buses clock and global peripheral buses clock.
- samsung,exynos5433-cmu-g3d - clock controller compatible for CMU_G3D
which generates clocks for 3D Graphics Engine IP.
+ - samsung,exynos5433-cmu-gscl - clock controller compatible for CMU_GSCL
+which generates clocks for GSCALER IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -123,6 +125,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_gscl: clock-controller@0x13cf {
+ compatible = samsung,exynos5433-cmu-gscl;
+ reg = 0x13cf 0x0b10;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 920bc3c..f515b95 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -543,6 +543,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, aclk_fsys_200, div_aclk_fsys_200,
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_111, aclk_gscl_111, div_aclk_gscl_111,
+ ENABLE_ACLK_TOP, 15, 0, 0),
+ GATE(CLK_ACLK_GSCL_333, aclk_gscl_333, div_aclk_gscl_333,
+ ENABLE_ACLK_TOP, 14, 0, 0),
GATE(CLK_ACLK_G2D_266, aclk_g2d_266, div_aclk_g2d_266,
ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2D_400, aclk_g2d_400, div_aclk_g2d_400,
@@ -3264,3 +3268,142 @@ static void __init exynos5433_cmu_g3d_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, samsung,exynos5433-cmu-g3d,
exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL0x0300
+#defineMUX_STAT_GSCL 0x0400
+#defineENABLE_ACLK_GSCL0x0800
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#defineENABLE_PCLK_GSCL0x0900
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#defineENABLE_IP_GSCL0 0x0b00
+#defineENABLE_IP_GSCL1 0x0b04
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL00x0b08
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL10x0b0c
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL20x0b10
+
+static unsigned long gscl_clk_regs[] __initdata = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ MUX_STAT_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p)= { fin_pll, aclk_gscl_111, };
+PNAME(aclk_gscl_333_user_p)= { fin_pll, aclk_gscl_333, };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, mout_aclk_gscl_111_user,
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER,
[PATCH 18/19] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 119 +
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index cfe3de8..a3093d4 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -56,6 +56,11 @@
mshc0 = mshc_0;
mshc1 = mshc_1;
mshc2 = mshc_2;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
+ spi3 = spi_3;
+ spi4 = spi_4;
};
chipid@1000 {
@@ -254,6 +259,35 @@
interrupts = 1 9 0xf04;
};
+ amba {
+ compatible = arm,amba-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ pdma0: pdma@1561 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1561 0x1000;
+ interrupts = 0 228 0;
+ clocks = cmu_fsys CLK_PDMA0;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@1560 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1560 0x1000;
+ interrupts = 0 246 0;
+ clocks = cmu_fsys CLK_PDMA1;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+ };
+
serial_0: serial@14C1 {
compatible = samsung,exynos5433-uart;
reg = 0x14C1 0x100;
@@ -354,6 +388,91 @@
interrupts = 0 442 0;
};
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 432 0;
+ dmas = pdma0 9, pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI0,
+cmu_top CLK_SCLK_SPI0_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ status = disabled;
+ };
+
+ spi_1: spi@14d3 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d3 0x100;
+ interrupts = 0 433 0;
+ dmas = pdma0 11, pdma0 10;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI1,
+cmu_top CLK_SCLK_SPI1_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi1_bus;
+ status = disabled;
+ };
+
+ spi_2: spi@14d4 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d4 0x100;
+ interrupts = 0 434 0;
+ dmas = pdma0 13, pdma0 12;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI2,
+cmu_top CLK_SCLK_SPI2_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names =
[PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 -
include/dt-bindings/clock/exynos5433.h | 114 -
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
+which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_disp: clock-controller@0x13b9 {
+ compatible = samsung,exynos5433-cmu-disp;
+ reg = 0x13b9 0x0c04;
+ #clock-cells = 1;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 5d7ff33..cd48209 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1,
fin_pll,
PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
mout_aud_pll_user_t,};
+PNAME(mout_sclk_hdmi_spdif_p) = { sclk_audio1, ioclk_spdif_extclk, };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
@@ -400,6 +402,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, mout_sclk_audio0, mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, mout_sclk_hdmi_spdif,
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1259,9 +1265,9 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, aclk_bus2_400, div_aclk_bus2_400,
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, aclk_disp_333, div_aclk_disp_333,
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, aclk_cpif_200, div_aclk_cpif_200,
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1336,21 +1342,30 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, sclk_dsim1_disp, div_sclk_dsim1,
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, sclk_decon_tv_vclk_disp,
- div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF, 14, 0, 0),
+ div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, sclk_dsim0_disp, div_sclk_dsim0,
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, sclk_dsd_disp, div_sclk_dsd,
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, sclk_decon_tv_eclk_disp,
- div_sclk_decon_tv_eclk, ENABLE_SCLK_MIF, 7, 0, 0),
+
[PATCH 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock control for Exynos5433 using common clk framework
This patchst is based on Exynos7 patchset[1] because Exynos5433 has similiar
feature with Exynos7. Exynos7 did already specify the dependent patchset list.
This patchset has the dependency as following list:
: The Exynos7 patchset[1] specified dependent patchset for 64-bit SoC.
So, this patchset used same dependent patchset of Exynos7 patchset and Exynos7
patchset about pinctrl patch. Additionally, SPI/MMC/PDMA patch [2-5] is used
for kernel booting and mounting rootfs.
1. [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
- [1] http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
2. [PATCH] spi: s3c64xx: add support for exynos7 SPI controller
- [2] http://www.spinics.net/lists/linux-samsung-soc/msg38607.html
3. [PATCH V7] mmc: dw_mmc: Add IDMAC 64-bit address mode support
- [3] https://lkml.org/lkml/2014/10/20/58
4. [PATCH] mmc: dw_mmc: exynos: Add support for exynos7
- [4] http://www.spinics.net/lists/linux-mmc/msg28294.html
5. [PATCH] dmaengine: pl330: Correct device assignment
- [5] https://lkml.org/lkml/2014/11/6/207
Chanwoo Choi (18):
pinctrl: exynos: Add support for Exynos5433
clk: samsung: Add binding documentation for Exynos5433 clock controller
clk: samsung: exynos5433: Add clocks using common clock framework
clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
clk: samsung: exynos5433: Add clocks for CMU_G2D domain
clk: samsung: exynos5433: Add clocks for CMU_MIF domain
clk: samsung: exynos5433: Add clocks for CMU_DISP domain
clk: samsung: exynos5433: Add clocks for CMU_AUD domain
clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
clk: samsung: exynos5433: Add clocks for CMU_G3D domain
clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
serial: samsung: Add the support for Exynos5433 SoC
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/clock/exynos5433-clock.txt | 167 +
arch/arm64/Kconfig | 10 +
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 684
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5433.c | 3409
drivers/pinctrl/samsung/pinctrl-exynos.c | 163 +
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
drivers/tty/serial/samsung.c | 56 +-
include/dt-bindings/clock/exynos5433.h | 867 +
11 files changed, 6038 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5433.c
create mode 100644 include/dt-bindings/clock/exynos5433.h
--
1.8.5.5
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[PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 146 -
include/dt-bindings/clock/exynos5433.h | 33 +++-
2 files changed, 176 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 11ee2d8..b09f2cfe 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -248,6 +248,7 @@ PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0,
fin_pll,
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
+ FFACTOR(0, oscclk_efuse_common, fin_pll, 1, 1, 0),
/* HACK: fin_pll hardcoded to xusbxti until detection is implemented */
FFACTOR(CLK_FIN_PLL, fin_pll, xusbxti, 1, 1, 0),
@@ -959,15 +960,69 @@ CLK_OF_DECLARE(exynos5433_cmu_peric,
samsung,exynos5433-cmu-peric,
/*
* Register offset definitions for CMU_PERIS
*/
-#define ENABLE_ACLK_PERIS 0x0800
-#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_ACLK_PERIS 0x0800
+#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
+#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
+#define ENABLE_PCLK_PERIS_SECURE_TOPRTC0x0910
+#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF0x0914
+#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
+#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
+#define ENABLE_SCLK_PERIS 0x0a00
+#define ENABLE_SCLK_PERIS_SECURE_SECKEY0x0a04
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0a08
+#define ENABLE_SCLK_PERIS_SECURE_TOPRTC0x0a0c
+#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
+#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
+#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
+#define ENABLE_IP_PERIS0 0x0b00
+#define ENABLE_IP_PERIS1 0x0b04
+#define ENABLE_IP_PERIS_SECURE_TZPC0x0b08
+#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
+#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
+#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
+#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE0x0b18
+#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
+#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
static unsigned long peris_clk_regs[] __initdata = {
ENABLE_ACLK_PERIS,
ENABLE_PCLK_PERIS,
+ ENABLE_PCLK_PERIS_SECURE_TZPC,
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
+ ENABLE_SCLK_PERIS,
+ ENABLE_SCLK_PERIS_SECURE_SECKEY,
+ ENABLE_SCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON,
+ ENABLE_IP_PERIS0,
+ ENABLE_IP_PERIS1,
+ ENABLE_IP_PERIS_SECURE_TZPC,
+ ENABLE_IP_PERIS_SECURE_SECKEY,
+ ENABLE_IP_PERIS_SECURE_CHIPID,
+ ENABLE_IP_PERIS_SECURE_TOPRTC,
+ ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
+ ENABLE_IP_PERIS_SECURE_OTP_CON,
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIS */
+ GATE(CLK_ACLK_AHB2APB_PERIS1P, aclk_ahb2apb_peris1p, aclk_peris_66,
+ ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIS0P, aclk_ahb2apb_peris0p, aclk_peris_66,
+ ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERISNP_66, aclk_perisnp_66, aclk_peris_66,
+ ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIS */
GATE(CLK_PCLK_HPM_APBIF, pclk_hpm_apbif, aclk_peris_66,
ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
@@ -989,6 +1044,93 @@ static struct samsung_gate_clock peris_gate_clks[]
__initdata = {
[PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590 +
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index dd1e6a1..5d7ff33 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -740,6 +740,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif,
samsung,exynos5433-cmu-cpif,
#define MFC_PLL_CON0 0x0130
#define MFC_PLL_CON1 0x0134
#define MFC_PLL_FREQ_DET 0x013c
+#define MUX_SEL_MIF0 0x0200
+#define MUX_SEL_MIF1 0x0204
+#define MUX_SEL_MIF2 0x0208
+#define MUX_SEL_MIF3 0x020c
+#define MUX_SEL_MIF4 0x0210
+#define MUX_SEL_MIF5 0x0214
+#define MUX_SEL_MIF6 0x0218
+#define MUX_SEL_MIF7 0x021c
+#define MUX_ENABLE_MIF00x0300
+#define MUX_ENABLE_MIF10x0304
+#define MUX_ENABLE_MIF20x0308
+#define MUX_ENABLE_MIF30x030c
+#define MUX_ENABLE_MIF40x0310
+#define MUX_ENABLE_MIF50x0314
+#define MUX_ENABLE_MIF60x0318
+#define MUX_ENABLE_MIF70x031c
+#define MUX_STAT_MIF0 0x0400
+#define MUX_STAT_MIF1 0x0404
+#define MUX_STAT_MIF2 0x0408
+#define MUX_STAT_MIF3 0x040c
+#define MUX_STAT_MIF4 0x0410
+#define MUX_STAT_MIF5 0x0414
+#define MUX_STAT_MIF6 0x0418
+#define MUX_STAT_MIF7 0x041c
+#define DIV_MIF1 0x0604
+#define DIV_MIF2 0x0608
+#define DIV_MIF3 0x060c
+#define DIV_MIF4 0x0610
+#define DIV_MIF5 0x0614
+#define DIV_MIF_PLL_FREQ_DET 0x0618
+#define DIV_STAT_MIF1 0x0704
+#define DIV_STAT_MIF2 0x0708
+#define DIV_STAT_MIF3 0x070c
+#define DIV_STAT_MIF4 0x0710
+#define DIV_STAT_MIF5 0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
+#define ENABLE_ACLK_MIF0 0x0800
+#define ENABLE_ACLK_MIF1 0x0804
+#define ENABLE_ACLK_MIF2 0x0808
+#define ENABLE_ACLK_MIF3 0x080c
+#define ENABLE_PCLK_MIF0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
+#define ENABLE_SCLK_MIF0x0a00
+#define ENABLE_IP_MIF0 0x0b00
+#define ENABLE_IP_MIF1 0x0b04
+#define ENABLE_IP_MIF2 0x0b08
+#define ENABLE_IP_MIF3 0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
+#define CLKOUT_CMU_MIF 0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT0x0c04
+#define DREX_FREQ_CTRL00x1000
+#define DREX_FREQ_CTRL10x1004
+#define PAUSE 0x1008
+#define DDRPHY_LOCK_CTRL 0x100c
static unsigned long mif_clk_regs[] __initdata = {
MEM0_PLL_LOCK,
@@ -758,6 +818,66 @@ static unsigned long mif_clk_regs[] __initdata = {
MFC_PLL_CON0,
MFC_PLL_CON1,
MFC_PLL_FREQ_DET,
+ MUX_SEL_MIF0,
+ MUX_SEL_MIF1,
+ MUX_SEL_MIF2,
+ MUX_SEL_MIF3,
+ MUX_SEL_MIF4,
+ MUX_SEL_MIF5,
+ MUX_SEL_MIF6,
+ MUX_SEL_MIF7,
+ MUX_ENABLE_MIF0,
+ MUX_ENABLE_MIF1,
+ MUX_ENABLE_MIF2,
+ MUX_ENABLE_MIF3,
+ MUX_ENABLE_MIF4,
+ MUX_ENABLE_MIF5,
+ MUX_ENABLE_MIF6,
+ MUX_ENABLE_MIF7,
+ MUX_STAT_MIF0,
+ MUX_STAT_MIF1,
+ MUX_STAT_MIF2,
+ MUX_STAT_MIF3,
+ MUX_STAT_MIF4,
+ MUX_STAT_MIF5,
+ MUX_STAT_MIF6,
+ MUX_STAT_MIF7,
+ DIV_MIF1,
+ DIV_MIF2,
+ DIV_MIF3,
+ DIV_MIF4,
+ DIV_MIF5,
+ DIV_MIF_PLL_FREQ_DET,
+ DIV_STAT_MIF1,
+ DIV_STAT_MIF2,
+ DIV_STAT_MIF3,
[PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for regiser accesses.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 21 ++
drivers/clk/samsung/clk-exynos5433.c | 225 -
include/dt-bindings/clock/exynos5433.h | 52 -
3 files changed, 295 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9a6ae75..03ae40a 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -25,6 +25,9 @@ Required Properties:
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- samsung,exynos5433-cmu-aud - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and samsung,exynos5433-cmu-bus2 - clock controller compatible for CMU_BUS
+which generates global data buses clock and global peripheral buses clock.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_bus0: clock-controller@0x1360 {
+ compatible = samsung,exynos5433-cmu-bus0;
+ reg = 0x1360 0x0b04;
+ #clock-cells = 1;
+ };
+
+ cmu_bus1: clock-controller@0x1480 {
+ compatible = samsung,exynos5433-cmu-bus1;
+ reg = 0x1480 0x0b04;
+ #clock-cells = 1;
+ };
+
+ cmu_bus2: clock-controller@0x1340 {
+ compatible = samsung,exynos5433-cmu-bus2;
+ reg = 0x1340 0x0b04;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 9f28672..f0975e1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -428,7 +428,7 @@ static struct samsung_div_clock top_div_clks[] __initdata =
{
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
- DIV(CLK_DIV_ACLK_IMEM_SSSX, div_aclk_imem_sssx,
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, div_aclk_imem_sssx_266,
mout_bus_pll_user, DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, div_aclk_imem_200,
mout_bus_pll_user, DIV_TOP3, 20, 3),
@@ -443,6 +443,14 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_ACLK_PERIS_66_A, div_aclk_peris_66_a,
mout_bus_pll_user, DIV_TOP3, 0, 3),
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, div_aclk_g3d_400, mout_bus_pll_user,
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, div_aclk_bus0_400, mout_aclk_bus0_400,
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, div_aclk_bus1_400, mout_bus_pll_user,
+ DIV_TOP4, 0, 3),
+
/* DIV_TOP_FSYS0 */
DIV(CLK_DIV_SCLK_MMC1_B, div_sclk_mmc1_b, div_sclk_mmc1_a,
DIV_TOP_FSYS0, 16, 8),
@@ -506,6 +514,19 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
static struct samsung_gate_clock top_gate_clks[] __initdata = {
/* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_G3D_400, aclk_g3d_400, div_aclk_g3d_400,
+ ENABLE_ACLK_TOP, 30, 0, 0),
+ GATE(CLK_ACLK_IMEM_SSX_266, aclk_imem_ssx_266,
+ div_aclk_imem_sssx_266, ENABLE_ACLK_TOP,
+ 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0_400, aclk_bus0_400, div_aclk_bus0_400,
+ ENABLE_ACLK_TOP, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1_400, aclk_bus1_400, div_aclk_bus1_400,
+ ENABLE_ACLK_TOP, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_200, aclk_imem_200, div_aclk_imem_266,
+ ENABLE_ACLK_TOP, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_266, aclk_imem_266, div_aclk_imem_200,
+ ENABLE_ACLK_TOP, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIC_66, aclk_peric_66, div_aclk_peric_66_b,
ENABLE_ACLK_TOP, 22, CLK_IGNORE_UNUSED, 0),
[PATCH 02/19] clk: samsung: Add binding documentation for Exynos5433 clock controller
This patch add binding documentation for Exynos5433 clock controller.
Exynos5433 has various clock domains So, this documentation explains
the detailed clock domains ans usage guide.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 106 +
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 000..72cd0ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,106 @@
+* Samsung Exynos5433 CMU (Clock Management Units)
+
+The Exynos5433 clock controller generates and supplies clock to various
+controllers within the Exynos5433 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - samsung,exynos5433-cmu-top - clock controller compatible for CMU_TOP
+which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
+domains and bus clocks.
+ - samsung,exynos5433-cmu-cpif - clock controller compatible for CMU_CPIF
+which generates clocks for LLI (Low Latency Interface) IP.
+ - samsung,exynos5433-cmu-mif - clock controller compatible for CMU_MIF
+which generates clocks for DRAM Memory Controller domain.
+ - samsung,exynos5433-cmu-peric - clock controller compatible for CMU_PERIC
+which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
+ - samsung,exynos5433-cmu-peris - clock controller compatible for CMU_PERIS
+which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
+ - samsung,exynos5433-cmu-fsys - clock controller compatible for CMU_FSYS
+which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5433.h header and can be used in device
+tree sources.
+
+Example 1: Examples of clock controller nodes are listed below.
+
+ cmu_top: clock-controller@0x1003 {
+ compatible = samsung,exynos5433-cmu-top;
+ reg = 0x1003 0x0c04;
+ #clock-cells = 1;
+ };
+
+ cmu_cpif: clock-controller@0x10fc {
+ compatible = samsung,exynos5433-cmu-cpif;
+ reg = 0x10fc 0x0c04;
+ #clock-cells = 1;
+ };
+
+ cmu_mif: clock-controller@0x105b {
+ compatible = samsung,exynos5433-cmu-mif;
+ reg = 0x105b 0x100c;
+ #clock-cells = 1;
+ };
+
+ cmu_peric: clock-controller@0x14c8 {
+ compatible = samsung,exynos5433-cmu-peric;
+ reg = 0x14c8 0x0b08;
+ #clock-cells = 1;
+ };
+
+ cmu_peris: clock-controller@0x1004 {
+ compatible = samsung,exynos5433-cmu-peris;
+ reg = 0x1004 0x0b20;
+ #clock-cells = 1;
+ };
+
+ cmu_fsys: clock-controller@0x156e {
+ compatible = samsung,exynos5433-cmu-fsys;
+ reg = 0x156e 0x0b04;
+ #clock-cells = 1;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller.
+
+ serial_0: serial@14C1 {
+ compatible = samsung,exynos5433-uart;
+ reg = 0x14C1 0x100;
+ interrupts = 0 421 0;
+ clocks = cmu_peric CLK_PCLK_UART0,
+cmu_peric CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ pinctrl-names = default;
+ pinctrl-0 = uart0_bus;
+ status = disabled;
+ };
+
+Example 3: SPI controller node that consumes the clock generated by the clock
+ controller.
+
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 432 0;
+ dmas = pdma0 9, pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI0,
+cmu_top CLK_SCLK_SPI0_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ status = disabled;
+ };
--
1.8.5.5
--
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[PATCH 01/19] pinctrl: exynos: Add support for Exynos5433
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 163 ++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 166 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 8e3e0c0..bd4c4ec 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1268,6 +1268,169 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
},
};
+/* pin banks of exynos5433 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos5433_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos5433 pin-controller - AUD */
+static struct samsung_pin_bank exynos5433_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos5433 pin-controller - CPIF */
+static struct samsung_pin_bank exynos5433_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(2, 0x000, gpv6, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - eSE */
+static struct samsung_pin_bank exynos5433_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj2, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FINGER */
+static struct samsung_pin_bank exynos5433_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpd5, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FSYS */
+static struct samsung_pin_bank exynos5433_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gph1, 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, gpr4, 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, gpr0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpr1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpr2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpr3, 0x14),
+};
+
+/* pin banks of exynos5433 pin-controller - IMEM */
+static struct samsung_pin_bank exynos5433_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpf0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - NFC */
+static struct samsung_pin_bank exynos5433_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - PERIC */
+static struct samsung_pin_bank exynos5433_pin_banks8[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gpv7, 0x00),
+ EXYNOS_PIN_BANK_EINTG(5, 0x020, gpb0, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpc0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x060, gpc1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x080, gpc2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpc3, 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0c0, gpg0, 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0e0, gpd0, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x100, gpd1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, gpd2, 0x24),
+ EXYNOS_PIN_BANK_EINTG(5, 0x140, gpd4, 0x28),
+ EXYNOS_PIN_BANK_EINTG(2, 0x160, gpd8, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(7, 0x180, gpd6, 0x30),
+ EXYNOS_PIN_BANK_EINTG(3, 0x1a0, gpd7, 0x34),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1c0, gpg1, 0x38),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1e0, gpg2, 0x3c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x200, gpg3, 0x40),
+};
+
+/* pin banks of exynos5433 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos5433_pin_banks9[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = exynos5433-gpio-ctrl0,
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5433_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume =
[PATCH 04/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 89 ++
include/dt-bindings/clock/exynos5433.h | 31 +++-
2 files changed, 118 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 25b447a..e0d71fd 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { fin_pll, sclk_mphy_pll,
};
PNAME(mout_mfc_pll_user_p) = { fin_pll, sclk_mfc_pll, };
PNAME(mout_bus_pll_user_p) = { fin_pll, sclk_bus_pll, };
PNAME(mout_bus_pll_user_t_p) = { fin_pll, mout_bus_pll_user, };
+PNAME(mout_mphy_pll_user_t_p) = { fin_pll, mout_mphy_pll_user, };
PNAME(mout_bus_mfc_pll_user_p) = { mout_bus_pll_user, mout_mfc_pll_user,};
PNAME(mout_mfc_bus_pll_user_p) = { mout_mfc_pll_user, mout_bus_pll_user,};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = {
mout_aclk_cam1_552_a,
mout_mfc_pll_user, };
PNAME(mout_aclk_cam1_552_a_p) = { mout_isp_pll, mout_bus_pll_user, };
+PNAME(mout_aclk_mfc_400_c_p) = { mout_aclk_mfc_400_b,
+ mout_mphy_pll_user, };
+PNAME(mout_aclk_mfc_400_b_p) = { mout_aclk_mfc_400_a,
+ mout_bus_pll_user, };
+PNAME(mout_aclk_mfc_400_a_p) = { mout_mfc_pll_user, mout_isp_pll, };
+
PNAME(mout_bus_mphy_pll_user_p)= { mout_bus_pll_user,
mout_mphy_pll_user, };
PNAME(mout_aclk_mscl_b_p) = { mout_aclk_mscl_400_a,
@@ -231,6 +238,13 @@ PNAME(mout_sclk_mmc0_d_p) = { mout_sclk_mmc0_c,
mout_isp_pll, };
PNAME(mout_sclk_mmc0_c_p) = { mout_sclk_mmc0_b, mout_mphy_pll_user,};
PNAME(mout_sclk_mmc0_b_p) = { mout_sclk_mmc0_a, mout_mfc_pll_user, };
+PNAME(mout_sclk_spdif_p) = { sclk_audio0, sclk_audio1,
+ fin_pll, ioclk_spdif_extclk, };
+PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1, fin_pll,
+ mout_aud_pll_user_t,};
+PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
+ mout_aud_pll_user_t,};
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
@@ -239,6 +253,14 @@ static struct samsung_fixed_factor_clock
top_fixed_factor_clks[] __initdata = {
FFACTOR(CLK_FIN_PLL, fin_pll, xusbxti, 1, 1, 0),
};
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, ioclk_audiocdclk1, NULL, CLK_IS_ROOT, 1),
+ FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+};
+
static struct samsung_mux_clock top_mux_clks[] __initdata = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, mout_aud_pll, mout_aud_pll_p, MUX_SEL_TOP0,
@@ -284,6 +306,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_ACLK_G2D_400_A, mout_aclk_g2d_400_a,
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, mout_aclk_mfc_400_c,
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, mout_aclk_mfc_400_b,
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, mout_aclk_mfc_400_a,
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, mout_sclk_jpeg_c, mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
@@ -292,6 +322,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_SCLK_JPEG_A, mout_sclk_jpeg_a, mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, mout_sclk_isp_sensor2,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, mout_sclk_isp_sensor1,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, mout_sclk_isp_sensor0,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, mout_sclk_isp_uart,
+ mout_bus_pll_user_t_p,
[PATCH 16/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 523 +++
2 files changed, 1221 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000..81fe925
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = gpz0-0, gpz0-1, gpz0-2, gpz0-3,
+ gpz0-4, gpz0-5, gpz0-6;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = gpz1-0, gpz1-1, gpz1-2, gpz1-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+};
+
+pinctrl_cpif {
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_ese {
+ gpj2: gpj2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_finger {
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = gpd5-0, gpd5-2, gpd5-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus {
+ samsung,pins = gpd5-3, gpd5-2;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+};
+
+pinctrl_fsys {
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpr4: gpr4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpr0: gpr0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+
[PATCH 03/19] clk: samsung: exynos5433: Add clocks using common clock framework
This patch adds the support for CMU (Clock Management Units) of Exynos5433 which is 64bit SoC and has Octa-cores. This patch supports necessary clocks for kernel boot as following: - PLL/MMC/UART/MCT/I2C/SPI Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5433.c | 971 + include/dt-bindings/clock/exynos5433.h | 200 +++ 3 files changed, 1172 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos5433.c create mode 100644 include/dt-bindings/clock/exynos5433.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 04acd70..9e8bd83 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c new file mode 100644 index 000..25b447a --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Chanwoo Choi cw00.c...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5443 SoC. + */ + +#include linux/clk.h +#include linux/clkdev.h +#include linux/clk-provider.h +#include linux/of.h + +#include dt-bindings/clock/exynos5433.h + +#include clk.h +#include clk-pll.h + +/* + * Register offset definitions for CMU_TOP + */ +#define ISP_PLL_LOCK 0x +#define AUD_PLL_LOCK 0x0004 +#define ISP_PLL_CON0 0x0100 +#define ISP_PLL_CON1 0x0104 +#define ISP_PLL_FREQ_DET 0x0108 +#define AUD_PLL_CON0 0x0110 +#define AUD_PLL_CON1 0x0114 +#define AUD_PLL_CON2 0x0118 +#define AUD_PLL_FREQ_DET 0x011c +#define MUX_SEL_TOP0 0x0200 +#define MUX_SEL_TOP1 0x0204 +#define MUX_SEL_TOP2 0x0208 +#define MUX_SEL_TOP3 0x020c +#define MUX_SEL_TOP4 0x0210 +#define MUX_SEL_TOP_MSCL 0x0220 +#define MUX_SEL_TOP_CAM1 0x0224 +#defineMUX_SEL_TOP_DISP0x0228 +#define MUX_SEL_TOP_FSYS0 0x0230 +#define MUX_SEL_TOP_FSYS1 0x0234 +#define MUX_SEL_TOP_PERIC0 0x0238 +#define MUX_SEL_TOP_PERIC1 0x023c +#define MUX_ENABLE_TOP00x0300 +#define MUX_ENABLE_TOP10x0304 +#define MUX_ENABLE_TOP20x0308 +#define MUX_ENABLE_TOP30x030c +#define MUX_ENABLE_TOP40x0310 +#define MUX_ENABLE_TOP_MSCL0x0320 +#define MUX_ENABLE_TOP_CAM10x0324 +#define MUX_ENABLE_TOP_DISP0x0328 +#define MUX_ENABLE_TOP_FSYS0 0x0330 +#define MUX_ENABLE_TOP_FSYS1 0x0334 +#define MUX_ENABLE_TOP_PERIC0 0x0338 +#define MUX_ENABLE_TOP_PERIC1 0x033c +#define MUX_STAT_TOP0 0x0400 +#define MUX_STAT_TOP1 0x0404 +#define MUX_STAT_TOP2 0x0408 +#define MUX_STAT_TOP3 0x040c +#define MUX_STAT_TOP4 0x0410 +#define MUX_STAT_TOP_MSCL 0x0420 +#define MUX_STAT_TOP_CAM1 0x0424 +#define MUX_STAT_TOP_FSYS0 0x0430 +#define MUX_STAT_TOP_FSYS1 0x0434 +#define MUX_STAT_TOP_PERIC00x0438 +#define MUX_STAT_TOP_PERIC10x043c +#define DIV_TOP0 0x0600 +#define DIV_TOP1 0x0604 +#define DIV_TOP2 0x0608 +#define DIV_TOP3 0x060c +#define DIV_TOP4 0x0610 +#define DIV_TOP_MSCL 0x0618 +#define DIV_TOP_CAM10 0x061c +#define DIV_TOP_CAM11 0x0620 +#define DIV_TOP_FSYS0 0x062c +#define DIV_TOP_FSYS1 0x0630 +#define DIV_TOP_FSYS2 0x0634 +#define DIV_TOP_PERIC0 0x0638 +#define DIV_TOP_PERIC1 0x063c +#define DIV_TOP_PERIC2 0x0640 +#define DIV_TOP_PERIC3
