Re: [PATCH V2 RESEND] arm: dts: Exynos5: Use pmu_system_controller phandle for dp phy
Hello Kukjin, On Mon, Nov 24, 2014 at 6:41 AM, Vivek Gautam gautam.vi...@samsung.com wrote: DP PHY now require pmu-system-controller to handle PMU register to control PHY's power isolation. Adding the same to dp-phy node. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com Reviewed-by: Jingoo Han jg1@samsung.com Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Cc: Kukjin Kim kg...@kernel.org Any opinions about $subject? This patch is -rc material since is needed after commit a5ec598 (phy: exynos-dp-video: Use syscon support to control pmu register) which landed in 3.18. That means that display for Exynos is currently broken in 3.18. I think it's too late for the 3.18 -rc cycle but at least it would be great to have this merged for 3.19 and backport to stable kernels to have display working again. Thierry had concerns that this change breaks DT backward compability but actually it was already been broken by a5ec598 which changed the DT binding for the phy-exynos-dp-video driver so we should either apply this patch now or revert a5ec598. Thanks a lot and best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add dts file for odroid XU3 board
On Tue, 2014-12-02 at 15:17 +0900, Heesub Shin wrote:
Hello Simons,
On 12/01/2014 09:59 PM, Sjoerd Simons wrote:
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5800.dtsi
Looking at exynos5800.dtsi, it derives from exynos5420.dtsi and seems
having differences on clock and mfc. Is it proper to include
exynos5800.dtsi here, instead of exynos5420.dtsi? It's just my curiosity
as I am not in a position to know detailed things on the soc. Only
semiconductor guys could answer this.
I would love to get a conclusive answer on this one as the exynos 5422
vs. exynos 5800 question seems to keep coming up (both on this list and
the u-boot one where XU3 support is being added as well).
As far as i understand things the Exynos 5800 is a variant of the
Exynos 5422 for chromebooks[0]. I suspect things are just being called
5800 in the kernel and u-boot as the chromebooks were the first boards
based on this SoC to reach mainline...
Which led to interesting things like:
#define EXYNOS5800_SOC_ID 0xE5422000
Iotw, the identifier for the 5800 is 0x5422, which doesn't really make
things more clear.
I'm working on the assumption that this SoC variation doesn't expose
differences to the OS. I did not yet test the MFC, but should get round
to that later this week, which should help in verifying the MFC side of
things at least.. I haven't yet seen any issues caused due to the
differences in clock setup between samsung,exynos5800-clock and
samsung,exynos5420-clock
+
+/ {
+ model = Hardkernel Odroid XU3;
+ compatible = hardkernel,odroid-xu3, samsung,exynos5800,
samsung,exynos5;
+
+ memory {
+ reg = 0x2000 0x8000;
+ };
Start address above should be 0x4000, not 0x2000.
Indeed, the Hardkernel DTS also starts at 0x4000, I missed that.
Looking at the other exynos5800/5420 based boards in the kernel they all
have their start offset at 0x2000, is this different for the XU3
because it runs with secure firmware or is there some other reason
behind this?
One more thing, having bootargs which specifies 'console=xxx' would be
better.
Hrm, i've got a dislike for chosen/bootargs as they typically seem
rather random/inconsistent (not sure who they're meant for). However, I
should indeed specify chosen/stdout-path to point to the serial console.
Thanks for your review!
0: See table at the bottom of
http://www.samsung.com/global/business/semiconductor/minisite/Exynos/w/solution.html#?v=octa_5422
--
Sjoerd Simons sjoerd.sim...@collabora.co.uk
Collabora Ltd.
smime.p7s
Description: S/MIME cryptographic signature
Re: exynos boot falures in linux-next
Hello Kukjin, On 11/20/2014 02:55 AM, Kukjin Kim wrote: Yeah, it could be a best solution at this moment. Let me revert the commit 0ef76aea7a34 (ARM: exynos_defconfig: Enable options for display panel support) from -next in samsung tree. Maybe now that all the issues with the Exynos DRM driver that were causing boot failures were found and fixed, we can enable these config options again? After all, the fact that these symbols got enabled is what made the issues to be detected in the first place so is useful to find regressions earlier. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 RESEND] arm: dts: Exynos5: Use pmu_system_controller phandle for dp phy
On Tuesday, December 02, 2014 5:17 PM, Javier Martinez Canillas wrote: Hello Kukjin, On Mon, Nov 24, 2014 at 6:41 AM, Vivek Gautam gautam.vi...@samsung.com wrote: DP PHY now require pmu-system-controller to handle PMU register to control PHY's power isolation. Adding the same to dp-phy node. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com Reviewed-by: Jingoo Han jg1@samsung.com Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Cc: Kukjin Kim kg...@kernel.org Any opinions about $subject? This patch is -rc material since is needed after commit a5ec598 (phy: exynos-dp-video: Use syscon support to control pmu register) which landed in 3.18. That means that display for Exynos is currently broken in 3.18. I think it's too late for the 3.18 -rc cycle but at least it would be great to have this merged for 3.19 and backport to stable kernels to have display working again. I agree with this suggestion. Thierry had concerns that this change breaks DT backward compability but actually it was already been broken by a5ec598 which changed the DT binding for the phy-exynos-dp-video driver so we should either apply this patch now or revert a5ec598. I think that very few people might use old properties for Exynos DP. Actually, DT backward compatibility will not be the considerable problem in my opinion. But, in order to keep the DT backward compatibility, we should revert a5ec598, and send another patch for keeping the DT backward compatibility. Best regards, Jingoo Han Thanks a lot and best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +
include/dt-bindings/clock/exynos5433.h | 37 +-
3 files changed, 188 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 589ed93..bf72817 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -30,6 +30,8 @@ Required Properties:
which generates global data buses clock and global peripheral buses clock.
- samsung,exynos5433-cmu-g3d - clock controller compatible for CMU_G3D
which generates clocks for 3D Graphics Engine IP.
+ - samsung,exynos5433-cmu-gscl - clock controller compatible for CMU_GSCL
+which generates clocks for GSCALER IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -123,6 +125,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_gscl: clock-controller@0x13cf {
+ compatible = samsung,exynos5433-cmu-gscl;
+ reg = 0x13cf 0x0b10;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index a7f5feb..00dcac3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -540,6 +540,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, aclk_fsys_200, div_aclk_fsys_200,
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_111, aclk_gscl_111, div_aclk_gscl_111,
+ ENABLE_ACLK_TOP, 15, 0, 0),
+ GATE(CLK_ACLK_GSCL_333, aclk_gscl_333, div_aclk_gscl_333,
+ ENABLE_ACLK_TOP, 14, 0, 0),
GATE(CLK_ACLK_G2D_266, aclk_g2d_266, div_aclk_g2d_266,
ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2D_400, aclk_g2d_400, div_aclk_g2d_400,
@@ -3223,3 +3227,143 @@ static void __init exynos5433_cmu_g3d_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, samsung,exynos5433-cmu-g3d,
exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL0x0300
+#defineMUX_STAT_GSCL 0x0400
+#defineENABLE_ACLK_GSCL0x0800
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#defineENABLE_PCLK_GSCL0x0900
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#defineENABLE_IP_GSCL0 0x0b00
+#defineENABLE_IP_GSCL1 0x0b04
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL00x0b08
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL10x0b0c
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL20x0b10
+
+static unsigned long gscl_clk_regs[] __initdata = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ MUX_STAT_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p)= { fin_pll, aclk_gscl_111, };
+PNAME(aclk_gscl_333_user_p)= { fin_pll, aclk_gscl_333, };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, mout_aclk_gscl_111_user,
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER,
[PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock control for Exynos5433 using common clk framework
This patchst is based on linux-samsung.git (branch: v3.19-next/dt-samsung-64)
This patchset has the dependency as following list:
: The Exynos7 patchset[1] specified dependent patchset for 64-bit SoC.
So, this patchset used same dependent patchset of Exynos7 patchset and Exynos7
patchset about pinctrl patch. Additionally, SPI/MMC/PDMA patch [2-5] is used
for kernel booting and mounting rootfs.
1. [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
- [1] http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
2. [PATCH] spi: s3c64xx: add support for exynos7 SPI controller
- [2] http://www.spinics.net/lists/linux-samsung-soc/msg38607.html
3. [PATCH V7] mmc: dw_mmc: Add IDMAC 64-bit address mode support
- [3] https://lkml.org/lkml/2014/10/20/58
4. [PATCH] mmc: dw_mmc: exynos: Add support for exynos7
- [4] http://www.spinics.net/lists/linux-mmc/msg28294.html
5. [PATCH] dmaengine: pl330: Correct device assignment
- [5] https://lkml.org/lkml/2014/11/6/207
Changes from v1:
- Merge two patches (patch2, patch3) to solve incomplete description [by Arnd]
- Exynos5433 Clock driver
: Fix wrong register and code clean by using space instead of tab [Pankaj]
: Add CLK_IGNORE_UNUSED flag to pclk_sysreg_* clock for accessing system
control register
: Remove duplicate definition on the patch for CMU_BUS{0|1|2} domain
- Exynos5433 SoC DTS
: Remove un-supported properties of arch_timer [by Marc and Mark]
: Remove 'clock-frequency' property from 'cpus' dt node
: Fix interrupt type from edge rising triggering to level high triggering
because Cortex-A53/A57 use level triggering.
: Fix defult address-size/size-celss from 1 to 2 because Exynos5433 is 64-bit
SoC
: Modify 'fin_pll' dt node to remove un-needed and ugly code
: Move 'chipid' dt node under 'soc'
: Use lowercase on all case in exynos5433.dtsi
: Add PSCI dt node for secondary cpu boot
: Add 'samsung,exynos5433' compatible to MCT dt node
- Divide pinctrl patch from this patchset
- Add new following patches:
: clocksource: exynos_mct: Add the support for Exynos 64bit SoC
: arm64: Enable Exynos5433 SoC in the defconfig
Chanwoo Choi (18):
clk: samsung: exynos5433: Add clocks using common clock framework
clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
clk: samsung: exynos5433: Add clocks for CMU_G2D domain
clk: samsung: exynos5433: Add clocks for CMU_MIF domain
clk: samsung: exynos5433: Add clocks for CMU_DISP domain
clk: samsung: exynos5433: Add clocks for CMU_AUD domain
clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
clk: samsung: exynos5433: Add clocks for CMU_G3D domain
clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
serial: samsung: Add the support for Exynos5433 SoC
clocksource: exynos_mct: Add the support for Exynos 64bit SoC
arm64: Enable Exynos5433 SoC in the defconfig
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/clock/exynos5433-clock.txt | 167 +
arch/arm64/Kconfig | 10 +
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 675
arch/arm64/configs/defconfig |1 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5433.c | 3369
drivers/clocksource/Kconfig|1 -
drivers/clocksource/exynos_mct.c |4 +
drivers/tty/serial/samsung.c | 56 +-
include/dt-bindings/clock/exynos5433.h | 843 +
11 files changed, 5804 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5433.c
create mode 100644 include/dt-bindings/clock/exynos5433.h
--
1.8.5.5
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[PATCH 18/19] clocksource: exynos_mct: Add the support for Exynos 64bit SoC
This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/clocksource/Kconfig | 1 -
drivers/clocksource/exynos_mct.c | 4
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 9042060..27ef3fa 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -134,7 +134,6 @@ config CLKSRC_METAG_GENERIC
config CLKSRC_EXYNOS_MCT
def_bool y if ARCH_EXYNOS
- depends on !ARM64
help
Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..b840ea1 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_read_count_32();
}
+#if defined(CONFIG_ARM)
static struct delay_timer exynos4_delay_timer;
static cycles_t exynos4_read_current_timer(void)
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
cycles_t needs to move to 32-bit for ARM64 usage);
return exynos4_read_count_32();
}
+#endif
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start();
+#if defined(CONFIG_ARM)
exynos4_delay_timer.read_current_timer = exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(exynos4_delay_timer);
+#endif
if (clocksource_register_hz(mct_frc, clk_rate))
panic(%s: can't register clocksource\n, mct_frc.name);
--
1.8.5.5
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[PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
drivers/clk/samsung/clk-exynos5433.c | 173 +
include/dt-bindings/clock/exynos5433.h | 53 +++
3 files changed, 233 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 8d3dad4..9a6ae75 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -23,6 +23,8 @@ Required Properties:
which generates clocks for G2D/MDMA IPs.
- samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
+ - samsung,exynos5433-cmu-aud - clock controller compatible for CMU_AUD
+which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_aud: clock-controller@0x114c {
+ compatible = samsung,exynos5433-cmu-aud;
+ reg = 0x114c 0x0b04;
+ #clock-cells = 1;
+ };
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index ec23e97..99262e0 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2454,3 +2454,176 @@ static void __init exynos5433_cmu_disp_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_disp, samsung,exynos5433-cmu-disp,
exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0 0x0200
+#define MUX_SEL_AUD1 0x0204
+#define MUX_ENABLE_AUD00x0300
+#define MUX_ENABLE_AUD10x0304
+#define MUX_STAT_AUD0 0x0400
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define ENABLE_ACLK_AUD0x0800
+#define ENABLE_PCLK_AUD0x0900
+#define ENABLE_SCLK_AUD0 0x0a00
+#define ENABLE_SCLK_AUD1 0x0a04
+#define ENABLE_IP_AUD0 0x0b00
+#define ENABLE_IP_AUD1 0x0b04
+
+static unsigned long aud_clk_regs[] __initdata = {
+ MUX_SEL_AUD0,
+ MUX_SEL_AUD1,
+ MUX_ENABLE_AUD0,
+ MUX_ENABLE_AUD1,
+ MUX_STAT_AUD0,
+ DIV_AUD0,
+ DIV_AUD1,
+ DIV_STAT_AUD0,
+ DIV_STAT_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD0,
+ ENABLE_SCLK_AUD1,
+ ENABLE_IP_AUD0,
+ ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p) = { fin_pll, fout_aud_pll, };
+PNAME(mout_sclk_aud_pcm_p) = { mout_aud_pll_user, ioclk_audiocdclk0,};
+PNAME(mout_sclk_aud_i2s_p) = { mout_aud_pll_user, ioclk_audiocdclk0,};
+
+static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
+ FRATE(0, ioclk_jtag_tclk, NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, ioclk_slimbus_clk, NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, ioclk_i2s_bclk, NULL, CLK_IS_ROOT, 18800),
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+ /* MUX_SEL_AUD0 */
+ MUX(CLK_MOUT_AUD_PLL_USER, mout_aud_pll_user,
+ mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+ /* MUX_SEL_AUD1 */
+ MUX(CLK_MOUT_SCLK_AUD_PCM, mout_sclk_aud_pcm, mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 8, 1),
+ MUX(CLK_MOUT_SCLK_AUD_I2S, mout_sclk_aud_i2s, mout_sclk_aud_i2s_p,
+ MUX_SEL_AUD1, 0, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+ /* DIV_AUD0 */
+ DIV(CLK_DIV_ATCLK_AUD, div_atclk_aud, div_aud_ca5, DIV_AUD0,
+ 12, 4),
+ DIV(CLK_DIV_PCLK_DBG_AUD, div_pclk_dbg_aud, div_aud_ca5, DIV_AUD0,
+ 8, 4),
+ DIV(CLK_DIV_ACLK_AUD, div_aclk_aud, div_aud_ca5, DIV_AUD0,
+ 4, 4),
+ DIV(CLK_DIV_AUD_CA5, div_aud_ca5, mout_aud_pll_user, DIV_AUD0,
+ 0, 4),
+
+ /* DIV_AUD1 */
+ DIV(CLK_DIV_SCLK_AUD_SLIMBUS, div_sclk_aud_slimbus,
+
[PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000..81fe925
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = gpz0-0, gpz0-1, gpz0-2, gpz0-3,
+ gpz0-4, gpz0-5, gpz0-6;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = gpz1-0, gpz1-1, gpz1-2, gpz1-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+};
+
+pinctrl_cpif {
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_ese {
+ gpj2: gpj2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_finger {
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = gpd5-0, gpd5-2, gpd5-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus {
+ samsung,pins = gpd5-3, gpd5-2;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+};
+
+pinctrl_fsys {
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpr4: gpr4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+
[PATCH 15/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433
From: Jaehoon Chung jh80.ch...@samsung.com
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 5637086..fef9bbc 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -52,6 +52,9 @@
i2c9 = hsi2c_9;
i2c10 = hsi2c_10;
i2c11 = hsi2c_11;
+ mshc0 = mshc_0;
+ mshc1 = mshc_1;
+ mshc2 = mshc_2;
};
cpus {
@@ -502,6 +505,45 @@
status = disabled;
};
+ mshc_0: mshc@1554 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 225 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1554 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC0,
+cmu_fsys CLK_SCLK_MMC0;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
+ mshc_1: mshc@1555 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 226 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1555 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC1,
+cmu_fsys CLK_SCLK_MMC1;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
+ mshc_2: mshc@1556 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 227 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1556 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC2,
+cmu_fsys CLK_SCLK_MMC2;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
timer {
compatible = arm,armv8-timer;
interrupts = 4 13 0xff01,
--
1.8.5.5
--
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[PATCH 19/19] arm64: Enable Exynos5433 SoC in the defconfig
This patch enable Exynos5433 SoC in the arm64 defconfig. Cc: Catalin Marinas catalin.mari...@arm.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c7ae5ac..7551a50 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS5433=y CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 146 -
include/dt-bindings/clock/exynos5433.h | 33 +++-
2 files changed, 176 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index a48b36c..7e4612f 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -248,6 +248,7 @@ PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0,
fin_pll,
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
+ FFACTOR(0, oscclk_efuse_common, fin_pll, 1, 1, 0),
};
static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
@@ -957,15 +958,69 @@ CLK_OF_DECLARE(exynos5433_cmu_peric,
samsung,exynos5433-cmu-peric,
/*
* Register offset definitions for CMU_PERIS
*/
-#define ENABLE_ACLK_PERIS 0x0800
-#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_ACLK_PERIS 0x0800
+#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
+#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
+#define ENABLE_PCLK_PERIS_SECURE_TOPRTC0x0910
+#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF0x0914
+#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
+#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
+#define ENABLE_SCLK_PERIS 0x0a00
+#define ENABLE_SCLK_PERIS_SECURE_SECKEY0x0a04
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0a08
+#define ENABLE_SCLK_PERIS_SECURE_TOPRTC0x0a0c
+#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
+#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
+#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
+#define ENABLE_IP_PERIS0 0x0b00
+#define ENABLE_IP_PERIS1 0x0b04
+#define ENABLE_IP_PERIS_SECURE_TZPC0x0b08
+#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
+#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
+#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
+#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE0x0b18
+#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
+#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
static unsigned long peris_clk_regs[] __initdata = {
ENABLE_ACLK_PERIS,
ENABLE_PCLK_PERIS,
+ ENABLE_PCLK_PERIS_SECURE_TZPC,
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
+ ENABLE_SCLK_PERIS,
+ ENABLE_SCLK_PERIS_SECURE_SECKEY,
+ ENABLE_SCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON,
+ ENABLE_IP_PERIS0,
+ ENABLE_IP_PERIS1,
+ ENABLE_IP_PERIS_SECURE_TZPC,
+ ENABLE_IP_PERIS_SECURE_SECKEY,
+ ENABLE_IP_PERIS_SECURE_CHIPID,
+ ENABLE_IP_PERIS_SECURE_TOPRTC,
+ ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
+ ENABLE_IP_PERIS_SECURE_OTP_CON,
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIS */
+ GATE(CLK_ACLK_AHB2APB_PERIS1P, aclk_ahb2apb_peris1p, aclk_peris_66,
+ ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIS0P, aclk_ahb2apb_peris0p, aclk_peris_66,
+ ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERISNP_66, aclk_perisnp_66, aclk_peris_66,
+ ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIS */
GATE(CLK_PCLK_HPM_APBIF, pclk_hpm_apbif, aclk_peris_66,
ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
@@ -987,6 +1042,93 @@ static struct samsung_gate_clock peris_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
[PATCH 13/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas catalin.mari...@arm.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com Acked-by: Inki Dae inki@samsung.com --- arch/arm64/Kconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fa708a0..3fa5d91 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -146,6 +146,16 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool ARMv8 based Samsung Exynos5433 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 -
include/dt-bindings/clock/exynos5433.h | 114 -
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
+which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_disp: clock-controller@0x13b9 {
+ compatible = samsung,exynos5433-cmu-disp;
+ reg = 0x13b9 0x0c04;
+ #clock-cells = 1;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 10197a1..ec23e97 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1,
fin_pll,
PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
mout_aud_pll_user_t,};
+PNAME(mout_sclk_hdmi_spdif_p) = { sclk_audio1, ioclk_spdif_extclk, };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
@@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, mout_sclk_audio0, mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, mout_sclk_hdmi_spdif,
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, aclk_bus2_400, div_aclk_bus2_400,
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, aclk_disp_333, div_aclk_disp_333,
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, aclk_cpif_200, div_aclk_cpif_200,
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, sclk_dsim1_disp, div_sclk_dsim1,
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, sclk_decon_tv_vclk_disp,
- div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF, 14, 0, 0),
+ div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, sclk_dsim0_disp, div_sclk_dsim0,
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, sclk_dsd_disp, div_sclk_dsd,
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, sclk_decon_tv_eclk_disp,
- div_sclk_decon_tv_eclk, ENABLE_SCLK_MIF, 7, 0, 0),
+
[PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 90 ++
include/dt-bindings/clock/exynos5433.h | 31 +++-
2 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 0877663..88e8cac 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { fin_pll, sclk_mphy_pll,
};
PNAME(mout_mfc_pll_user_p) = { fin_pll, sclk_mfc_pll, };
PNAME(mout_bus_pll_user_p) = { fin_pll, sclk_bus_pll, };
PNAME(mout_bus_pll_user_t_p) = { fin_pll, mout_bus_pll_user, };
+PNAME(mout_mphy_pll_user_t_p) = { fin_pll, mout_mphy_pll_user, };
PNAME(mout_bus_mfc_pll_user_p) = { mout_bus_pll_user, mout_mfc_pll_user,};
PNAME(mout_mfc_bus_pll_user_p) = { mout_mfc_pll_user, mout_bus_pll_user,};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = {
mout_aclk_cam1_552_a,
mout_mfc_pll_user, };
PNAME(mout_aclk_cam1_552_a_p) = { mout_isp_pll, mout_bus_pll_user, };
+PNAME(mout_aclk_mfc_400_c_p) = { mout_aclk_mfc_400_b,
+ mout_mphy_pll_user, };
+PNAME(mout_aclk_mfc_400_b_p) = { mout_aclk_mfc_400_a,
+ mout_bus_pll_user, };
+PNAME(mout_aclk_mfc_400_a_p) = { mout_mfc_pll_user, mout_isp_pll, };
+
PNAME(mout_bus_mphy_pll_user_p)= { mout_bus_pll_user,
mout_mphy_pll_user, };
PNAME(mout_aclk_mscl_b_p) = { mout_aclk_mscl_400_a,
@@ -231,11 +238,26 @@ PNAME(mout_sclk_mmc0_d_p) = { mout_sclk_mmc0_c,
mout_isp_pll, };
PNAME(mout_sclk_mmc0_c_p) = { mout_sclk_mmc0_b, mout_mphy_pll_user,};
PNAME(mout_sclk_mmc0_b_p) = { mout_sclk_mmc0_a, mout_mfc_pll_user, };
+PNAME(mout_sclk_spdif_p) = { sclk_audio0, sclk_audio1,
+ fin_pll, ioclk_spdif_extclk, };
+PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1, fin_pll,
+ mout_aud_pll_user_t,};
+PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
+ mout_aud_pll_user_t,};
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
};
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, ioclk_audiocdclk1, NULL, CLK_IS_ROOT, 1),
+ FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+};
+
static struct samsung_mux_clock top_mux_clks[] __initdata = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, mout_aud_pll, mout_aud_pll_p, MUX_SEL_TOP0,
@@ -281,6 +303,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_ACLK_G2D_400_A, mout_aclk_g2d_400_a,
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, mout_aclk_mfc_400_c,
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, mout_aclk_mfc_400_b,
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, mout_aclk_mfc_400_a,
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, mout_sclk_jpeg_c, mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
@@ -289,6 +319,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_SCLK_JPEG_A, mout_sclk_jpeg_a, mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, mout_sclk_isp_sensor2,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, mout_sclk_isp_sensor1,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, mout_sclk_isp_sensor0,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, mout_sclk_isp_uart,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI1, mout_sclk_isp_spi1,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
+
[PATCH 16/19] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 118 +
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index fef9bbc..22f2df8 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -55,6 +55,11 @@
mshc0 = mshc_0;
mshc1 = mshc_1;
mshc2 = mshc_2;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
+ spi3 = spi_3;
+ spi4 = spi_4;
};
cpus {
@@ -249,6 +254,34 @@
interrupts = 1 9 0xf04;
};
+ amba {
+ compatible = arm,amba-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ pdma0: pdma@1561 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1561 0x1000;
+ interrupts = 0 228 0;
+ clocks = cmu_fsys CLK_PDMA0;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@1560 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1560 0x1000;
+ interrupts = 0 246 0;
+ clocks = cmu_fsys CLK_PDMA1;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+ };
+
serial_0: serial@14c1 {
compatible = samsung,exynos5433-uart;
reg = 0x14c1 0x100;
@@ -349,6 +382,91 @@
interrupts = 0 442 0;
};
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 432 0;
+ dmas = pdma0 9, pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI0,
+cmu_top CLK_SCLK_SPI0_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ status = disabled;
+ };
+
+ spi_1: spi@14d3 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d3 0x100;
+ interrupts = 0 433 0;
+ dmas = pdma0 11, pdma0 10;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI1,
+cmu_top CLK_SCLK_SPI1_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi1_bus;
+ status = disabled;
+ };
+
+ spi_2: spi@14d4 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d4 0x100;
+ interrupts = 0 434 0;
+ dmas = pdma0 13, pdma0 12;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI2,
+cmu_top CLK_SCLK_SPI2_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names =
[PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for regiser accesses.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 21 +++
drivers/clk/samsung/clk-exynos5433.c | 185 -
include/dt-bindings/clock/exynos5433.h | 29 +++-
3 files changed, 232 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9a6ae75..03ae40a 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -25,6 +25,9 @@ Required Properties:
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- samsung,exynos5433-cmu-aud - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and samsung,exynos5433-cmu-bus2 - clock controller compatible for CMU_BUS
+which generates global data buses clock and global peripheral buses clock.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_bus0: clock-controller@0x1360 {
+ compatible = samsung,exynos5433-cmu-bus0;
+ reg = 0x1360 0x0b04;
+ #clock-cells = 1;
+ };
+
+ cmu_bus1: clock-controller@0x1480 {
+ compatible = samsung,exynos5433-cmu-bus1;
+ reg = 0x1480 0x0b04;
+ #clock-cells = 1;
+ };
+
+ cmu_bus2: clock-controller@0x1340 {
+ compatible = samsung,exynos5433-cmu-bus2;
+ reg = 0x1340 0x0b04;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 99262e0..5b4ec83 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -425,7 +425,7 @@ static struct samsung_div_clock top_div_clks[] __initdata =
{
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
- DIV(CLK_DIV_ACLK_IMEM_SSSX, div_aclk_imem_sssx,
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, div_aclk_imem_sssx_266,
mout_bus_pll_user, DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, div_aclk_imem_200,
mout_bus_pll_user, DIV_TOP3, 20, 3),
@@ -440,6 +440,14 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_ACLK_PERIS_66_A, div_aclk_peris_66_a,
mout_bus_pll_user, DIV_TOP3, 0, 3),
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, div_aclk_g3d_400, mout_bus_pll_user,
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, div_aclk_bus0_400, mout_aclk_bus0_400,
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, div_aclk_bus1_400, mout_bus_pll_user,
+ DIV_TOP4, 0, 3),
+
/* DIV_TOP_FSYS0 */
DIV(CLK_DIV_SCLK_MMC1_B, div_sclk_mmc1_b, div_sclk_mmc1_a,
DIV_TOP_FSYS0, 16, 8),
@@ -503,6 +511,19 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
static struct samsung_gate_clock top_gate_clks[] __initdata = {
/* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_G3D_400, aclk_g3d_400, div_aclk_g3d_400,
+ ENABLE_ACLK_TOP, 30, 0, 0),
+ GATE(CLK_ACLK_IMEM_SSX_266, aclk_imem_ssx_266,
+ div_aclk_imem_sssx_266, ENABLE_ACLK_TOP,
+ 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0_400, aclk_bus0_400, div_aclk_bus0_400,
+ ENABLE_ACLK_TOP, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1_400, aclk_bus1_400, div_aclk_bus1_400,
+ ENABLE_ACLK_TOP, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_200, aclk_imem_200, div_aclk_imem_266,
+ ENABLE_ACLK_TOP, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_266, aclk_imem_266, div_aclk_imem_200,
+ ENABLE_ACLK_TOP, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIC_66, aclk_peric_66, div_aclk_peric_66_b,
ENABLE_ACLK_TOP, 22,
[PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 127 +
include/dt-bindings/clock/exynos5433.h | 25
3 files changed, 160 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 03ae40a..589ed93 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -28,6 +28,8 @@ Required Properties:
- samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
and samsung,exynos5433-cmu-bus2 - clock controller compatible for CMU_BUS
which generates global data buses clock and global peripheral buses clock.
+ - samsung,exynos5433-cmu-g3d - clock controller compatible for CMU_G3D
+which generates clocks for 3D Graphics Engine IP.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -115,6 +117,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_g3d: clock-controller@0x14aa {
+ compatible = samsung,exynos5433-cmu-g3d;
+ reg = 0x14aa 0x1000;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index e2b7ea6..a7f5feb 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3096,3 +3096,130 @@ CLK_OF_DECLARE(exynos5433_cmu_bus##id,
\
exynos5433_cmu_bus_init(0);
exynos5433_cmu_bus_init(1);
exynos5433_cmu_bus_init(2);
+
+/*
+ * Register offset definitions for CMU_G3D
+ */
+#define G3D_PLL_LOCK 0x
+#define G3D_PLL_CON0 0x0100
+#define G3D_PLL_CON1 0x0104
+#define G3D_PLL_FREQ_DET 0x010c
+#define MUX_SEL_G3D0x0200
+#define MUX_ENABLE_G3D 0x0300
+#define MUX_STAT_G3D 0x0400
+#define DIV_G3D0x0600
+#define DIV_G3D_PLL_FREQ_DET 0x0604
+#define DIV_STAT_G3D 0x0700
+#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_G3D0x0800
+#define ENABLE_PCLK_G3D0x0900
+#define ENABLE_SCLK_G3D0x0a00
+#define ENABLE_IP_G3D0 0x0b00
+#define ENABLE_IP_G3D1 0x0b04
+#define CLKOUT_CMU_G3D 0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT0x0c04
+#define CLK_STOPCTRL 0x1000
+
+static unsigned long g3d_clk_regs[] __initdata = {
+ G3D_PLL_LOCK,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_FREQ_DET,
+ MUX_SEL_G3D,
+ MUX_ENABLE_G3D,
+ MUX_STAT_G3D,
+ DIV_G3D,
+ DIV_G3D_PLL_FREQ_DET,
+ DIV_STAT_G3D,
+ DIV_STAT_G3D_PLL_FREQ_DET,
+ ENABLE_ACLK_G3D,
+ ENABLE_PCLK_G3D,
+ ENABLE_SCLK_G3D,
+ ENABLE_IP_G3D0,
+ ENABLE_IP_G3D1,
+ CLKOUT_CMU_G3D,
+ CLKOUT_CMU_G3D_DIV_STAT,
+ CLK_STOPCTRL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g3d_400_p) = { mout_g3d_pll, aclk_g3d_400, };
+PNAME(mout_g3d_pll_p) = { fin_pll, fout_g3d_pll, };
+
+static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_G3D_PLL, fout_g3d_pll, fin_pll,
+ G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
+ /* MUX_SEL_G3D */
+ MUX(CLK_MOUT_ACLK_G3D_400, mout_aclk_g3d_400, mout_aclk_g3d_400_p,
+ MUX_SEL_G3D, 8, 1),
+ MUX(CLK_MOUT_G3D_PLL, mout_g3d_pll, mout_g3d_pll_p,
+ MUX_SEL_G3D, 0, 1),
+};
+
+static struct samsung_div_clock g3d_div_clks[] __initdata = {
+ /* DIV_G3D */
+ DIV(CLK_DIV_SCLK_HPM_G3D, div_sclk_hpm_g3d, mout_g3d_pll, DIV_G3D,
+ 8, 2),
+ DIV(CLK_DIV_PCLK_G3D, div_pclk_g3d, div_aclk_g3d, DIV_G3D,
+ 4, 3),
+ DIV(CLK_DIV_ACLK_G3D, div_aclk_g3d, mout_aclk_g3d_400, DIV_G3D,
+ 0, 3),
+};
+
+static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_G3D */
+ GATE(CLK_ACLK_BTS_G3D1, aclk_bts_g3d1, div_aclk_g3d,
+ ENABLE_ACLK_G3D, 7, 0, 0),
+
[PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +
include/dt-bindings/clock/exynos5433.h | 42 +-
3 files changed, 193 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 72cd0ba..27dd77b 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -19,6 +19,8 @@ Required Properties:
which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- samsung,exynos5433-cmu-fsys - clock controller compatible for CMU_FSYS
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+ - samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
+which generates clocks for G2D/MDMA IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -70,6 +72,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_g2d: clock-controller@0x1246 {
+ compatible = samsung,exynos5433-cmu-g2d;
+ reg = 0x1246 0x0b08;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 7e4612f..4dec9fc 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -400,6 +400,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
};
static struct samsung_div_clock top_div_clks[] __initdata = {
+ /* DIV_TOP1 */
+ DIV(CLK_DIV_ACLK_GSCL_111, div_aclk_gscl_111, mout_aclk_gscl_333,
+ DIV_TOP1, 28, 3),
+ DIV(CLK_DIV_ACLK_GSCL_333, div_aclk_gscl_333, mout_aclk_gscl_333,
+ DIV_TOP1, 24, 3),
+ DIV(CLK_DIV_ACLK_HEVC_400, div_aclk_hevc_400, mout_aclk_hevc_400,
+ DIV_TOP1, 20, 3),
+ DIV(CLK_DIV_ACLK_MFC_400, div_aclk_mfc_400, mout_aclk_mfc_400_c,
+ DIV_TOP1, 12, 3),
+ DIV(CLK_DIV_ACLK_G2D_266, div_aclk_g2d_266, mout_bus_pll_user,
+ DIV_TOP1, 8, 3),
+ DIV(CLK_DIV_ACLK_G2D_400, div_aclk_g2d_400, mout_aclk_g2d_400_b,
+ DIV_TOP1, 0, 3),
+
/* DIV_TOP2 */
DIV(CLK_DIV_ACLK_FSYS_200, div_aclk_fsys_200, mout_bus_pll_user,
DIV_TOP2, 0, 3),
@@ -489,6 +503,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, aclk_fsys_200, div_aclk_fsys_200,
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_266, aclk_g2d_266, div_aclk_g2d_266,
+ ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_400, aclk_g2d_400, div_aclk_g2d_400,
+ ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
@@ -1275,3 +1293,129 @@ static void __init exynos5433_cmu_fsys_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_fsys, samsung,exynos5433-cmu-fsys,
exynos5433_cmu_fsys_init);
+
+/*
+ * Register offset definitions for CMU_G2D
+ */
+#define MUX_SEL_G2D0 0x0200
+#define MUX_SEL_ENABLE_G2D00x0300
+#define MUX_SEL_STAT_G2D0 0x0400
+#define DIV_G2D0x0600
+#define DIV_STAT_G2D 0x0700
+#define DIV_ENABLE_ACLK_G2D0x0800
+#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D0x0804
+#define DIV_ENABLE_PCLK_G2D0x0900
+#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D0x0904
+#define DIV_ENABLE_IP_G2D0 0x0b00
+#define DIV_ENABLE_IP_G2D1 0x0b04
+#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
+
+static unsigned long g2d_clk_regs[] __initdata = {
+ MUX_SEL_G2D0,
+ MUX_SEL_ENABLE_G2D0,
+ MUX_SEL_STAT_G2D0,
+ DIV_G2D,
+ DIV_STAT_G2D,
+ DIV_ENABLE_ACLK_G2D,
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_PCLK_G2D,
+
[PATCH 01/19] clk: samsung: exynos5433: Add clocks using common clock framework
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5433.c | 967 +
include/dt-bindings/clock/exynos5433.h | 199 +
4 files changed, 1273 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5433.c
create mode 100644 include/dt-bindings/clock/exynos5433.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 000..72cd0ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,106 @@
+* Samsung Exynos5433 CMU (Clock Management Units)
+
+The Exynos5433 clock controller generates and supplies clock to various
+controllers within the Exynos5433 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - samsung,exynos5433-cmu-top - clock controller compatible for CMU_TOP
+which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
+domains and bus clocks.
+ - samsung,exynos5433-cmu-cpif - clock controller compatible for CMU_CPIF
+which generates clocks for LLI (Low Latency Interface) IP.
+ - samsung,exynos5433-cmu-mif - clock controller compatible for CMU_MIF
+which generates clocks for DRAM Memory Controller domain.
+ - samsung,exynos5433-cmu-peric - clock controller compatible for CMU_PERIC
+which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
+ - samsung,exynos5433-cmu-peris - clock controller compatible for CMU_PERIS
+which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
+ - samsung,exynos5433-cmu-fsys - clock controller compatible for CMU_FSYS
+which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5433.h header and can be used in device
+tree sources.
+
+Example 1: Examples of clock controller nodes are listed below.
+
+ cmu_top: clock-controller@0x1003 {
+ compatible = samsung,exynos5433-cmu-top;
+ reg = 0x1003 0x0c04;
+ #clock-cells = 1;
+ };
+
+ cmu_cpif: clock-controller@0x10fc {
+ compatible = samsung,exynos5433-cmu-cpif;
+ reg = 0x10fc 0x0c04;
+ #clock-cells = 1;
+ };
+
+ cmu_mif: clock-controller@0x105b {
+ compatible = samsung,exynos5433-cmu-mif;
+ reg = 0x105b 0x100c;
+ #clock-cells = 1;
+ };
+
+ cmu_peric: clock-controller@0x14c8 {
+ compatible = samsung,exynos5433-cmu-peric;
+ reg = 0x14c8 0x0b08;
+ #clock-cells = 1;
+ };
+
+ cmu_peris: clock-controller@0x1004 {
+ compatible = samsung,exynos5433-cmu-peris;
+ reg = 0x1004 0x0b20;
+ #clock-cells = 1;
+ };
+
+ cmu_fsys: clock-controller@0x156e {
+ compatible = samsung,exynos5433-cmu-fsys;
+ reg = 0x156e 0x0b04;
+ #clock-cells = 1;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller.
+
+ serial_0: serial@14C1 {
+ compatible = samsung,exynos5433-uart;
+ reg = 0x14C1 0x100;
+ interrupts = 0 421 0;
+ clocks = cmu_peric CLK_PCLK_UART0,
+cmu_peric CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ pinctrl-names = default;
+ pinctrl-0 = uart0_bus;
+ status = disabled;
+ };
+
+Example 3: SPI controller node that consumes the clock generated by the clock
+ controller.
+
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 432 0;
+ dmas = pdma0 9, pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+
[PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 286 +
include/dt-bindings/clock/exynos5433.h | 82 +-
2 files changed, 365 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 5b4ec83..e2b7ea6 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_SCLK_MMC2_A, div_sclk_mmc2_a, mout_sclk_mmc2_b,
DIV_TOP_FSYS1, 0, 4),
+ /* DIV_TOP_FSYS2 */
+ DIV(CLK_DIV_SCLK_PCIE_100, div_sclk_pcie_100, mout_sclk_pcie_100,
+ DIV_TOP_FSYS2, 12, 3),
+ DIV(CLK_DIV_SCLK_USBHOST30, div_sclk_usbhost30,
+ mout_sclk_usbhost30, DIV_TOP_FSYS2, 8, 4),
+ DIV(CLK_DIV_SCLK_UFSUNIPRO, div_sclk_ufsunipro,
+ mout_sclk_ufsunipro, DIV_TOP_FSYS2, 4, 4),
+ DIV(CLK_DIV_SCLK_USBDRD30, div_sclk_usbdrd30, mout_sclk_usbdrd30,
+ DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, div_sclk_spi1_b, div_sclk_spi1_a,
DIV_TOP_PERIC0, 16, 8),
@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_PCIE_100_FSYS, sclk_pcie_100_fsys, div_sclk_pcie_100,
+ ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, sclk_mmc1_fsys, div_sclk_mmc1_b,
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, sclk_mmc0_fsys, div_sclk_mmc0_b,
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO_FSYS, sclk_ufsunipro_fsys,
+ div_sclk_ufsunipro, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBHOST30_FSYS, sclk_usbhost30_fsys,
+ div_sclk_usbhost30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBDRD30_FSYS, sclk_usbdrd30_fsys,
+ div_sclk_usbdrd30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, sclk_spi4_peric, div_sclk_spi4_b,
@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris,
samsung,exynos5433-cmu-peris,
#define ENABLE_IP_FSYS10x0b04
/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p) = { fin_pll, sclk_ufs_mphy, };
PNAME(mout_aclk_fsys_200_user_p) = { fin_pll, aclk_fsys_200, };
+PNAME(mout_sclk_pcie_100_user_p) = { fin_pll, sclk_ufsunipro_fsys,};
+PNAME(mout_sclk_ufsunipro_user_p) = { fin_pll, sclk_ufsunipro_fsys,};
PNAME(mout_sclk_mmc2_user_p) = { fin_pll, sclk_mmc2_fsys, };
PNAME(mout_sclk_mmc1_user_p) = { fin_pll, sclk_mmc1_fsys, };
PNAME(mout_sclk_mmc0_user_p) = { fin_pll, sclk_mmc0_fsys, };
+PNAME(mout_sclk_usbhost30_user_p) = { fin_pll, sclk_usbhost30_fsys,};
+PNAME(mout_sclk_usbdrd30_user_p) = { fin_pll, sclk_usbdrd30_fsys, };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+ = { fin_pll, phyclk_usbhost20_phy_hsic1_phy, };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_clk48mohci_phy, };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_freeclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+ = { fin_pll, phyclk_ufs_rx1_symbol_phy, };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+ = { fin_pll, phyclk_ufs_rx0_symbol_phy, };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+ = { fin_pll, phyclk_ufs_tx1_symbol_phy, };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+ = { fin_pll,
[PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590 +
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 4dec9fc..10197a1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -737,6 +737,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif,
samsung,exynos5433-cmu-cpif,
#define MFC_PLL_CON0 0x0130
#define MFC_PLL_CON1 0x0134
#define MFC_PLL_FREQ_DET 0x013c
+#define MUX_SEL_MIF0 0x0200
+#define MUX_SEL_MIF1 0x0204
+#define MUX_SEL_MIF2 0x0208
+#define MUX_SEL_MIF3 0x020c
+#define MUX_SEL_MIF4 0x0210
+#define MUX_SEL_MIF5 0x0214
+#define MUX_SEL_MIF6 0x0218
+#define MUX_SEL_MIF7 0x021c
+#define MUX_ENABLE_MIF00x0300
+#define MUX_ENABLE_MIF10x0304
+#define MUX_ENABLE_MIF20x0308
+#define MUX_ENABLE_MIF30x030c
+#define MUX_ENABLE_MIF40x0310
+#define MUX_ENABLE_MIF50x0314
+#define MUX_ENABLE_MIF60x0318
+#define MUX_ENABLE_MIF70x031c
+#define MUX_STAT_MIF0 0x0400
+#define MUX_STAT_MIF1 0x0404
+#define MUX_STAT_MIF2 0x0408
+#define MUX_STAT_MIF3 0x040c
+#define MUX_STAT_MIF4 0x0410
+#define MUX_STAT_MIF5 0x0414
+#define MUX_STAT_MIF6 0x0418
+#define MUX_STAT_MIF7 0x041c
+#define DIV_MIF1 0x0604
+#define DIV_MIF2 0x0608
+#define DIV_MIF3 0x060c
+#define DIV_MIF4 0x0610
+#define DIV_MIF5 0x0614
+#define DIV_MIF_PLL_FREQ_DET 0x0618
+#define DIV_STAT_MIF1 0x0704
+#define DIV_STAT_MIF2 0x0708
+#define DIV_STAT_MIF3 0x070c
+#define DIV_STAT_MIF4 0x0710
+#define DIV_STAT_MIF5 0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
+#define ENABLE_ACLK_MIF0 0x0800
+#define ENABLE_ACLK_MIF1 0x0804
+#define ENABLE_ACLK_MIF2 0x0808
+#define ENABLE_ACLK_MIF3 0x080c
+#define ENABLE_PCLK_MIF0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
+#define ENABLE_SCLK_MIF0x0a00
+#define ENABLE_IP_MIF0 0x0b00
+#define ENABLE_IP_MIF1 0x0b04
+#define ENABLE_IP_MIF2 0x0b08
+#define ENABLE_IP_MIF3 0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
+#define CLKOUT_CMU_MIF 0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT0x0c04
+#define DREX_FREQ_CTRL00x1000
+#define DREX_FREQ_CTRL10x1004
+#define PAUSE 0x1008
+#define DDRPHY_LOCK_CTRL 0x100c
static unsigned long mif_clk_regs[] __initdata = {
MEM0_PLL_LOCK,
@@ -755,6 +815,66 @@ static unsigned long mif_clk_regs[] __initdata = {
MFC_PLL_CON0,
MFC_PLL_CON1,
MFC_PLL_FREQ_DET,
+ MUX_SEL_MIF0,
+ MUX_SEL_MIF1,
+ MUX_SEL_MIF2,
+ MUX_SEL_MIF3,
+ MUX_SEL_MIF4,
+ MUX_SEL_MIF5,
+ MUX_SEL_MIF6,
+ MUX_SEL_MIF7,
+ MUX_ENABLE_MIF0,
+ MUX_ENABLE_MIF1,
+ MUX_ENABLE_MIF2,
+ MUX_ENABLE_MIF3,
+ MUX_ENABLE_MIF4,
+ MUX_ENABLE_MIF5,
+ MUX_ENABLE_MIF6,
+ MUX_ENABLE_MIF7,
+ MUX_STAT_MIF0,
+ MUX_STAT_MIF1,
+ MUX_STAT_MIF2,
+ MUX_STAT_MIF3,
+ MUX_STAT_MIF4,
+ MUX_STAT_MIF5,
+ MUX_STAT_MIF6,
+ MUX_STAT_MIF7,
+ DIV_MIF1,
+ DIV_MIF2,
+ DIV_MIF3,
+ DIV_MIF4,
+ DIV_MIF5,
+ DIV_MIF_PLL_FREQ_DET,
+ DIV_STAT_MIF1,
+ DIV_STAT_MIF2,
+ DIV_STAT_MIF3,
Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem
Hey Marek, Inki, On Wed, 2014-11-19 at 12:15 +0100, Marek Szyprowski wrote: Hello Everyone, This is another attempt to finally make Exynos SYSMMU driver fully integrated with DMA-mapping subsystem. The main change from previous version is a rebase onto latest automatic DMA configuration for IOMMU masters patches from Will Deacon. Do you happen to know if anyone is working on iommu/dma-mapping patches for Exynos 5 based on this patchset? For some background to that question, We (re-)discovered yesterday that the out-of-tree exynos-reference kernel iommu patches are required to get HDMI out working on exynos 5 boards. The current situation in mainline is rather broken, HDMI output without CONFIG_DRM_EXYNOS_IOMMU results in just displaying stripes[0]. While turning on CONFIG_DRM_EXYNOS_IOMMU causes a kernel oops at boot 0: http://people.collabora.com/~sjoerd/14120001.jpg -- Sjoerd Simons sjoerd.sim...@collabora.co.uk Collabora Ltd. smime.p7s Description: S/MIME cryptographic signature
[PATCHv2] pinctrl: exynos: Add support for Exynos5433
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
Changes from v1:
- Fix the wrong number of Exynos5433 (four - ten)
- Divide pinctrl patch from following patch[1]
[1] https://lkml.org/lkml/2014/12/2/134
drivers/pinctrl/samsung/pinctrl-exynos.c | 163 ++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 166 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d5d4cfc..67da569 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1240,6 +1240,169 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[]
__initconst = {
},
};
+/* pin banks of exynos5433 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos5433_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos5433 pin-controller - AUD */
+static struct samsung_pin_bank exynos5433_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos5433 pin-controller - CPIF */
+static struct samsung_pin_bank exynos5433_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(2, 0x000, gpv6, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - eSE */
+static struct samsung_pin_bank exynos5433_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj2, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FINGER */
+static struct samsung_pin_bank exynos5433_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpd5, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FSYS */
+static struct samsung_pin_bank exynos5433_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gph1, 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, gpr4, 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, gpr0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpr1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpr2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpr3, 0x14),
+};
+
+/* pin banks of exynos5433 pin-controller - IMEM */
+static struct samsung_pin_bank exynos5433_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpf0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - NFC */
+static struct samsung_pin_bank exynos5433_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - PERIC */
+static struct samsung_pin_bank exynos5433_pin_banks8[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gpv7, 0x00),
+ EXYNOS_PIN_BANK_EINTG(5, 0x020, gpb0, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpc0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x060, gpc1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x080, gpc2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpc3, 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0c0, gpg0, 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0e0, gpd0, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x100, gpd1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, gpd2, 0x24),
+ EXYNOS_PIN_BANK_EINTG(5, 0x140, gpd4, 0x28),
+ EXYNOS_PIN_BANK_EINTG(2, 0x160, gpd8, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(7, 0x180, gpd6, 0x30),
+ EXYNOS_PIN_BANK_EINTG(3, 0x1a0, gpd7, 0x34),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1c0, gpg1, 0x38),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1e0, gpg2, 0x3c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x200, gpg3, 0x40),
+};
+
+/* pin banks of exynos5433 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos5433_pin_banks9[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * ten gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = exynos5433-gpio-ctrl0,
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5433_pin_banks1,
+ .nr_banks =
Re: [PATCH 16/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
On Mon, Dec 01, 2014 at 02:21:46AM +, Chanwoo Choi wrote:
Dear Mark,
On 11/28/2014 11:00 PM, Mark Rutland wrote:
On Fri, Nov 28, 2014 at 01:18:25PM +, Chanwoo Choi wrote:
Dear Mark,
On 11/27/2014 08:18 PM, Mark Rutland wrote:
On Thu, Nov 27, 2014 at 07:35:13AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
+
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 523 +++
2 files changed, 1221 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
+
+ cpu0: cpu@100 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
While the CPU nodes have enable-methods, I didn't spot a PSCI node
anywhere, so this dts cannot possibly have been used to bring up an SMP
system.
How has this dts been tested?
What PSCI revision have you implemented? Have have you tested it?
My mistake,
Exynos5433 supports PSCI v0.1. I'll add following PSCI nodes:
I tested the boot of secondary cpu.
psci {
compatible = arm,psci;
method = smc;
cpu_off = 0x8402;
cpu_on = 0xC403;
};
Ok. I take it _any_ CPU may be hotplugged (including CPU0), given that
you don't have MIGRATE_INFO_TYPE from PSCI 0.2 to tell you that this is
not possible? If not, attempting to hotplug CPU0 will result in a BUG()
and the kernel will explode.
Has that been tested?
I just tested secondary CPU on during kernel booting after added 'psci' dt
node.
So, I got the ON state of Octa CPUs.
Maybe I need more time to implement CPU0 and secondary cpu hotplugged
dynamically on runtime.
So currently PSCI CPU_OFF is not implemented at all?
Do all CPUs enter the kernel at EL2?
I didn't consider EL2 for hypervisor mode.
First role of this job, I'll implement CPU on/off and suspend by using PSCI.
Is there any reason not to enter the kernel at EL2?
PSCI 0.2 mandates entering at EL2 if present (and not under a
hypervisor), and it gives the kernel a lot more flexibility to fix
things up (and there's less for FW to restore) even when a hypervisor is
not in use.
Implementing all that to EL2 is _simpler_ than implementing it to EL1.
The kernel will restore what it needs to.
Thanks,
Mark.
--
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Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
+
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu0: cpu@100 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x100;
+ };
+
+ cpu1: cpu@101 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x101;
+ };
+
+ cpu2: cpu@102 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x0 0x102;
+ };
+
+ cpu3: cpu@103 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x103;
+ };
+
+ cpu4: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu5: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu6: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu7: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
Where the final cell is a sufficiently large value to cover all
addresses in the soc node.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
[...]
+ pinctrl_alive: pinctrl@1058 {
+ compatible = samsung,exynos5433-pinctrl;
+ reg = 0x1058 0x1000;
+
+ wakeup-interrupt-controller {
+ compatible = samsung,exynos7-wakeup-eint;
+ interrupts = 0 16 0;
+ };
+ };
How exactly does the wakeup interrupt controller interact with the GIC?
Surely the relationship between the two should be described?
Is it a subcomponent of the
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Dear Mark,
On 12/02/2014 08:09 PM, Mark Rutland wrote:
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433
supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
+
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu0: cpu@100 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x100;
+ };
+
+ cpu1: cpu@101 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x101;
+ };
+
+ cpu2: cpu@102 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x0 0x102;
+ };
+
+ cpu3: cpu@103 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x103;
+ };
+
+ cpu4: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu5: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu6: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu7: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
At current version,
CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of
CPU_OFF fail.
(I got CPU_ON of Exynos5433 all cores.)
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
I'll fix it after checking correct spec.
Where the final cell is a sufficiently large value to cover all
addresses in the soc node.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = 0x11001000 0x1000,
0x11002000 0x2000,- I changed the the range of
GICC.
0x11004000 0x2000,
0x11006000 0x2000;
[...]
+
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
At current version,
CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of
CPU_OFF fail.
(I got CPU_ON of Exynos5433 all cores.)
CPU_OFF should not be described in the DT unless it works.
[...]
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
I'll fix it after checking correct spec.
Thanks.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = 0x11001000 0x1000,
0x11002000 0x2000,- I changed the the range of
GICC.
0x11004000 0x2000,
0x11006000 0x2000;
Yes.
[...]
+ pinctrl_alive: pinctrl@1058 {
+ compatible = samsung,exynos5433-pinctrl;
+ reg = 0x1058 0x1000;
+
+ wakeup-interrupt-controller {
+ compatible = samsung,exynos7-wakeup-eint;
+ interrupts = 0 16 0;
+ };
+ };
How exactly does the wakeup interrupt controller interact with the GIC?
Surely the relationship between the two should be described?
The pinctrl_alive contains the alive part of GPIO PAD (gpa0~gpa3).
The each GPA0/GPA1 of pinctrl_alive pad did map to unique SPI number of GIC
amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
gpa0-0 - SPI[0]
gpa0-1 - SPI[1]
gpa0-2 - SPI[2]
gpa0-3 - SPI[3]
gpa0-4 - SPI[4]
gpa0-5 - SPI[5]
gpa0-6 - SPI[6]
gpa0-7 - SPI[7]
gpa1-0 - SPI[8]
gpa1-1 - SPI[9]
gpa1-2 - SPI[10]
gpa1-3 - SPI[11]
gpa1-4 - SPI[12]
gpa1-5 - SPI[13]
gpa1-6 - SPI[14]
gpa1-7 - SPI[15]
GPA2/GPA3 use only one interrupt (SPI[16]).
The pinctrl-exynos.c driver initialized external wakeup interrupt
(e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) in exynos_eint_wkup_init() function.
Following patch[1] adds the control for Exynos5433 wakeup irq.The
exynos5433_pin_ctrl structure
includes '.eint_wkup_init = exynos_eint_wkup_init;' fields to handle wakeup
interrupt of Exynos SoC.
[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = exynos5433-gpio-ctrl0,
+ }, {
And,
'struct exynos_irq_chip
[PATCH] mfd: max77686: Fix parent of rtc device
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
driver max77686-pmic modalias power uevent
max77686-clk max77686-rtc name subsystem
After applying patch :
driver/modalias power/ uevent
max77686-rtc/ name subsystem/
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
Or Can we follow another (exhaustive but more cleaner) approach, which will
be more like code refactoring and cleanup rather than only fix:
Since rtc uses i2c client, which gets created using i2c_new_dummy() and is not
shared by any other cell of max77686. So we can covert rtc platform driver
itself to i2c client driver. It will also allow to expilicitly describe
max77686-rtc in DT which we can't do now.
It can be applicable to some other existing and new mfd pmic drivers.
Any suggestion/comments ?
---
drivers/mfd/max77686.c | 22 --
1 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 929795e..22c0948 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -39,10 +39,13 @@
static const struct mfd_cell max77686_devs[] = {
{ .name = max77686-pmic, },
- { .name = max77686-rtc, },
{ .name = max77686-clk, },
};
+static const struct mfd_cell max77686_rtc_dev[] = {
+ { .name = max77686-rtc, },
+};
+
static const struct mfd_cell max77802_devs[] = {
{ .name = max77802-pmic, },
{ .name = max77802-clk, },
@@ -332,14 +335,27 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
goto err_del_irqc;
}
+ if (max77686-type == TYPE_MAX77686) {
+ ret = mfd_add_devices(max77686-rtc-dev, -1, max77686_rtc_dev,
+ 1, NULL, 0, NULL);
+ if (ret 0) {
+ dev_err(max77686-rtc-dev,
+ failed to add RTC device %d\n, ret);
+ goto err_del_rtc_irqc;
+ }
+ }
+
ret = mfd_add_devices(max77686-dev, -1, cells, n_devs, NULL, 0, NULL);
if (ret 0) {
dev_err(i2c-dev, failed to add MFD devices: %d\n, ret);
- goto err_del_rtc_irqc;
+ goto err_del_rtc_dev;
}
return 0;
+err_del_rtc_dev:
+ if (max77686-type == TYPE_MAX77686)
+ mfd_remove_devices(max77686-rtc-dev);
err_del_rtc_irqc:
regmap_del_irq_chip(max77686-irq, max77686-rtc_irq_data);
err_del_irqc:
@@ -356,6 +372,8 @@ static int max77686_i2c_remove(struct i2c_client *i2c)
struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
mfd_remove_devices(max77686-dev);
+ if (max77686-type == TYPE_MAX77686)
+ mfd_remove_devices(max77686-rtc-dev);
regmap_del_irq_chip(max77686-irq, max77686-rtc_irq_data);
regmap_del_irq_chip(max77686-irq, max77686-irq_data);
--
1.7.0.4
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Re: [PATCH 0/4] removal of extra abstraction layers
Hi Inki, Can you please review this? I also have sent other two patch sets that sits on top of this one. Thanks. Gustavo 2014-11-24 Gustavo Padovan gust...@padovan.org: From: Gustavo Padovan gustavo.pado...@collabora.co.uk Hi Inki, In this series I've removed some level of indirection from the exynos_drm_code. There two moves in these patches, first we remove all exynos_drm_crtc_plane_*() wrappers and call the manager specific functions directly. The other change is the removal of struct exynos_drm_overlay(). In my understanding the overlay struct was just storing plane data in a 1:1 relationship so it made sense to merge its fields in struct exynos_drm_plane and remove another abstraction from the driver. Next steps: During our initial investigation on the Exynos DRM driver we've spoted a few abstractions that could be removed to get a more clean and less abstract code. - struct exynos_drm_manager: this is just a helper of struct exynos_drm_crtc, I suggest we could merge them both. - struct *_win_data: Most of the share common fields and could be merged int struct exynos_drm_plane. - some more function wrapper can be removed as well. After these changes intead of looking to manager and win_data we will look into crtc and planes. The new names give us more clue about what a piece of code is doing since they are already defined and used by the whole DRM ecossytem. What your thoughts on this? I've seen that you pushed some patches to remove static usage of managers so I would like to check with you which direction are you planning to go with this. I've done some code[0] around this but now it needs a rebase against you exynos-drm-next. [0] https://git.kernel.org/cgit/linux/kernel/git/padovan/drm-exynos.git/log/?h=cleanup Gustavo Padovan (4): drm/exynos: move to_exynos_crtc() macro to main header drm/exynos: expose struct exynos_drm_crtc drm/exynos: remove exynos_drm_crtc_plane_* wrappers drm/exynos: remove struct exynos_drm_overlay drivers/gpu/drm/exynos/exynos_drm_crtc.c | 66 - drivers/gpu/drm/exynos/exynos_drm_crtc.h | 2 +- drivers/gpu/drm/exynos/exynos_drm_drv.h | 43 +- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 44 +++--- drivers/gpu/drm/exynos/exynos_drm_plane.c | 96 +++ drivers/gpu/drm/exynos/exynos_drm_vidi.c | 38 ++-- drivers/gpu/drm/exynos/exynos_mixer.c | 50 7 files changed, 156 insertions(+), 183 deletions(-) -- 1.9.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] mfd: max77686: Fix parent of rtc device
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
# ls /sys/class/i2c-adapter/i2c-0/0-0009/
driver max77686-pmic modalias power uevent
max77686-clk max77686-rtc name subsystem
After applying patch :
# ls /sys/class/i2c-adapter/i2c-0/0-0006/
driver/modalias power/ uevent
max77686-rtc/ name subsystem/
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
Or Can we follow another (exhaustive but more cleaner) approach, which will
be more like code refactoring and cleanup rather than only fix:
Since rtc uses i2c client, which gets created using i2c_new_dummy() and is not
shared by any other cell of max77686. So we can covert rtc platform driver
itself to i2c client driver. It will also allow to expilicitly describe
max77686-rtc in DT which we can't do now.
It can be applicable to some other existing and new mfd pmic drivers.
Any suggestion/comments ?
---
drivers/mfd/max77686.c | 22 --
1 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 929795e..22c0948 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -39,10 +39,13 @@
static const struct mfd_cell max77686_devs[] = {
{ .name = max77686-pmic, },
- { .name = max77686-rtc, },
{ .name = max77686-clk, },
};
+static const struct mfd_cell max77686_rtc_dev[] = {
+ { .name = max77686-rtc, },
+};
+
static const struct mfd_cell max77802_devs[] = {
{ .name = max77802-pmic, },
{ .name = max77802-clk, },
@@ -332,14 +335,27 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
goto err_del_irqc;
}
+ if (max77686-type == TYPE_MAX77686) {
+ ret = mfd_add_devices(max77686-rtc-dev, -1, max77686_rtc_dev,
+ 1, NULL, 0, NULL);
+ if (ret 0) {
+ dev_err(max77686-rtc-dev,
+ failed to add RTC device %d\n, ret);
+ goto err_del_rtc_irqc;
+ }
+ }
+
ret = mfd_add_devices(max77686-dev, -1, cells, n_devs, NULL, 0, NULL);
if (ret 0) {
dev_err(i2c-dev, failed to add MFD devices: %d\n, ret);
- goto err_del_rtc_irqc;
+ goto err_del_rtc_dev;
}
return 0;
+err_del_rtc_dev:
+ if (max77686-type == TYPE_MAX77686)
+ mfd_remove_devices(max77686-rtc-dev);
err_del_rtc_irqc:
regmap_del_irq_chip(max77686-irq, max77686-rtc_irq_data);
err_del_irqc:
@@ -356,6 +372,8 @@ static int max77686_i2c_remove(struct i2c_client *i2c)
struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
mfd_remove_devices(max77686-dev);
+ if (max77686-type == TYPE_MAX77686)
+ mfd_remove_devices(max77686-rtc-dev);
regmap_del_irq_chip(max77686-irq, max77686-rtc_irq_data);
regmap_del_irq_chip(max77686-irq, max77686-irq_data);
--
1.7.0.4
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Re: [PATCH] mfd: max77686: Fix parent of rtc device
On 02.12.2014 13:45, Yadwinder Singh Brar wrote:
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs
also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
# ls /sys/class/i2c-adapter/i2c-0/0-0009/
driver max77686-pmic modalias power uevent
max77686-clk max77686-rtc name subsystem
After applying patch :
# ls /sys/class/i2c-adapter/i2c-0/0-0006/
driver/modalias power/ uevent
max77686-rtc/ name subsystem/
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
Or Can we follow another (exhaustive but more cleaner) approach, which will
be more like code refactoring and cleanup rather than only fix:
Since rtc uses i2c client, which gets created using i2c_new_dummy() and is not
shared by any other cell of max77686. So we can covert rtc platform driver
itself to i2c client driver. It will also allow to expilicitly describe
max77686-rtc in DT which we can't do now.
It can be applicable to some other existing and new mfd pmic drivers.
Any suggestion/comments ?
Hi,
What kind of problem is solved by this patch?
Best regards,
Krzysztof
---
drivers/mfd/max77686.c | 22 --
1 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 929795e..22c0948 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -39,10 +39,13 @@
static const struct mfd_cell max77686_devs[] = {
{ .name = max77686-pmic, },
- { .name = max77686-rtc, },
{ .name = max77686-clk, },
};
+static const struct mfd_cell max77686_rtc_dev[] = {
+ { .name = max77686-rtc, },
+};
+
static const struct mfd_cell max77802_devs[] = {
{ .name = max77802-pmic, },
{ .name = max77802-clk, },
@@ -332,14 +335,27 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
goto err_del_irqc;
}
+ if (max77686-type == TYPE_MAX77686) {
+ ret = mfd_add_devices(max77686-rtc-dev, -1, max77686_rtc_dev,
+ 1, NULL, 0, NULL);
+ if (ret 0) {
+ dev_err(max77686-rtc-dev,
+ failed to add RTC device %d\n, ret);
+ goto err_del_rtc_irqc;
+ }
+ }
+
ret = mfd_add_devices(max77686-dev, -1, cells, n_devs, NULL, 0, NULL);
if (ret 0) {
dev_err(i2c-dev, failed to add MFD devices: %d\n, ret);
- goto err_del_rtc_irqc;
+ goto err_del_rtc_dev;
}
return 0;
+err_del_rtc_dev:
+ if (max77686-type == TYPE_MAX77686)
+ mfd_remove_devices(max77686-rtc-dev);
err_del_rtc_irqc:
regmap_del_irq_chip(max77686-irq, max77686-rtc_irq_data);
err_del_irqc:
@@ -356,6 +372,8 @@ static int max77686_i2c_remove(struct i2c_client *i2c)
struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
mfd_remove_devices(max77686-dev);
+ if (max77686-type == TYPE_MAX77686)
+ mfd_remove_devices(max77686-rtc-dev);
regmap_del_irq_chip(max77686-irq, max77686-rtc_irq_data);
regmap_del_irq_chip(max77686-irq, max77686-irq_data);
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Re: [PATCH] clocksource: exynos_mct: fix exynos4_mct_write
On 11/29/2014 11:18 PM, Kukjin Kim wrote:
Tobias Jakobi wrote:
EXYNOS4_MCT_L_MASK is defined as 0xff00, so applying this bitmask
produces a number outside the range 0x00 to 0xff, which always results
in execution of the default switch statement.
Obviously this is wrong and git history shows that the bitmask inversion
was incorrectly set during a refactoring of the MCT code.
Fix this by putting the inversion at the correct position again.
Reported-by: GP Orcullo kinsama...@gmail.com
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
+ Daniel, Thomas,
adding Doug's review tag from previous his reply.
Reviewed-by: Doug Anderson diand...@chromium.org
And
Acked-by: Kukjin Kim kgene@samsung.com
Daniel,
Since this is obvious fix, can you please pick into your tree?
If any problem, please kindly let me know.
Hi Kukjin,
the patch is my tree for a 3.18 fix.
Added the stable@ also in the Cc list.
Thanks
-- Daniel
---
drivers/clocksource/exynos_mct.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..83564c9 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -97,8 +97,8 @@ static void exynos4_mct_write(unsigned int value, unsigned
long offset)
writel_relaxed(value, reg_base + offset);
if (likely(offset = EXYNOS4_MCT_L_BASE(0))) {
- stat_addr = (offset ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
- switch (offset EXYNOS4_MCT_L_MASK) {
+ stat_addr = (offset EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+ switch (offset ~EXYNOS4_MCT_L_MASK) {
case MCT_L_TCON_OFFSET:
mask = 1 3;/* L_TCON write status */
break;
--
2.0.4
--
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Re: [PATCH 3/3] clk: samsung: remove unnecessary inclusion of header files from clk.h
Hi Pankaj, On 27/09/14 07:41, Pankaj Dubey wrote: Let's remove unnecessary include of header files from clk.h and add required one in clk.c Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com --- drivers/clk/samsung/clk.c |3 ++- drivers/clk/samsung/clk.h |4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 31bf391..952f9ec 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -11,7 +11,8 @@ * clock framework for Samsung platforms. */ -#include linux/syscore_ops.h I've dropped this change when applying since it causes a build break: drivers/clk/samsung/clk.c:338:15: error: variable ‘samsung_clk_syscore_ops’ has initializer but incomplete type drivers/clk/samsung/clk.c:339:2: error: unknown field ‘suspend’ specified in initializer drivers/clk/samsung/clk.c:339:2: warning: excess elements in struct initializer [enabled by default] drivers/clk/samsung/clk.c:339:2: warning: (near initialization for ‘samsung_clk_syscore_ops’) [enabled by default] drivers/clk/samsung/clk.c:340:2: error: unknown field ‘resume’ specified in initializer drivers/clk/samsung/clk.c:340:2: warning: excess elements in struct initializer [enabled by default] drivers/clk/samsung/clk.c:340:2: warning: (near initialization for ‘samsung_clk_syscore_ops’) [enabled by default] CC drivers/dma/virt-dma.o drivers/clk/samsung/clk.c: In function ‘samsung_clk_sleep_init’: drivers/clk/samsung/clk.c:359:3: error: implicit declaration of function ‘register_syscore_ops’ [-Werror=implicit-function-declaration] Please make sure there is no build breaks with various configs when sending patches. -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] cpuidle: add MAINTAINERS entry for ARM Exynos cpuidle driver
Since there has been quite a lot of development going on for ARM Exynos cpuidle driver recently I would like to add separate MAINTAINERS entry for it and add myself as the primary maintainer. The merging process would remain (almost) unchanged with patches going (with my Ack) through Daniel's or Kukjin's tree. Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) Index: b/MAINTAINERS === --- a/MAINTAINERS 2014-11-27 18:02:51.988225868 +0100 +++ b/MAINTAINERS 2014-12-02 15:56:52.792997513 +0100 @@ -2701,6 +2701,16 @@ T: git git://git.kernel.org/pub/scm/linu S: Maintained F: drivers/cpuidle/cpuidle-big_little.c +CPUIDLE DRIVER - ARM EXYNOS +M: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com +M: Daniel Lezcano daniel.lezc...@linaro.org +M: Kukjin Kim kg...@kernel.org +L: linux...@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: drivers/cpuidle/cpuidle-exynos.c +F: arch/arm/mach-exynos/pm.c + CPUIDLE DRIVERS M: Rafael J. Wysocki r...@rjwysocki.net M: Daniel Lezcano daniel.lezc...@linaro.org -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Dear Mark,
On Tue, Dec 2, 2014 at 9:13 PM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
At current version,
CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of
CPU_OFF fail.
(I got CPU_ON of Exynos5433 all cores.)
CPU_OFF should not be described in the DT unless it works.
OK, I'll drop 'cpu_off property on next patchset. After fixing it,
I'll re-send separate patch.
[...]
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
I'll fix it after checking correct spec.
Thanks.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = 0x11001000 0x1000,
0x11002000 0x2000,- I changed the the range
of GICC.
0x11004000 0x2000,
0x11006000 0x2000;
Yes.
OK. I'll fix it.
[...]
+ pinctrl_alive: pinctrl@1058 {
+ compatible = samsung,exynos5433-pinctrl;
+ reg = 0x1058 0x1000;
+
+ wakeup-interrupt-controller {
+ compatible =
samsung,exynos7-wakeup-eint;
+ interrupts = 0 16 0;
+ };
+ };
How exactly does the wakeup interrupt controller interact with the GIC?
Surely the relationship between the two should be described?
The pinctrl_alive contains the alive part of GPIO PAD (gpa0~gpa3).
The each GPA0/GPA1 of pinctrl_alive pad did map to unique SPI number of GIC
amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
gpa0-0 - SPI[0]
gpa0-1 - SPI[1]
gpa0-2 - SPI[2]
gpa0-3 - SPI[3]
gpa0-4 - SPI[4]
gpa0-5 - SPI[5]
gpa0-6 - SPI[6]
gpa0-7 - SPI[7]
gpa1-0 - SPI[8]
gpa1-1 - SPI[9]
gpa1-2 - SPI[10]
gpa1-3 - SPI[11]
gpa1-4 - SPI[12]
gpa1-5 - SPI[13]
gpa1-6 - SPI[14]
gpa1-7 - SPI[15]
GPA2/GPA3 use only one interrupt (SPI[16]).
The pinctrl-exynos.c driver initialized external wakeup interrupt
(e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) in exynos_eint_wkup_init()
function.
Following patch[1] adds the control for Exynos5433 wakeup irq.The
exynos5433_pin_ctrl structure
includes '.eint_wkup_init = exynos_eint_wkup_init;' fields to handle wakeup
interrupt of Exynos SoC.
[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend=
Re: [PATCH] dmaengine: pl330: Set residue in tx_status callback
On 12/02/2014 06:38 AM, Padma Venkat wrote:
Hi Vinod/Lars,
On 11/26/14, Padmavathi Venna padm...@samsung.com wrote:
Fill txstate.residue with the amount of bytes remaining in the current
transfer if the transfer is not complete. This will be of particular
use to i2s DMA transfers, providing more accurate hw_ptr values to ASoC.
I had taken the code from Dylan Reid dgr...@chromium.org patch from the
below link and modified according to the current dmaengine framework.
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/23007
Cc: Dylan Reid dgr...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This patch has been tested for audio playback on exynos5420 peach-pit.
drivers/dma/pl330.c | 67
+-
1 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index b7493d2..db880ae 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2182,11 +2182,74 @@ static void pl330_free_chan_resources(struct
dma_chan *chan)
pm_runtime_put_autosuspend(pch-dmac-ddma.dev);
}
+static inline int
+pl330_src_addr_in_desc(struct dma_pl330_desc *desc, unsigned int sar)
+{
+ return ((desc-px.src_addr = sar)
+ (sar = (desc-px.src_addr + desc-px.bytes)));
+}
+
+static inline int
+pl330_dst_addr_in_desc(struct dma_pl330_desc *desc, unsigned int dar)
+{
+ return ((desc-px.dst_addr = dar)
+ (dar = (desc-px.dst_addr + desc-px.bytes)));
+}
+
static enum dma_status
pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
- return dma_cookie_status(chan, cookie, txstate);
+ dma_addr_t sar, dar;
+ struct dma_pl330_chan *pch = to_pchan(chan);
+ void __iomem *regs = pch-dmac-base;
+ struct pl330_thread *thrd = pch-thread;
+ struct dma_pl330_desc *desc;
+ unsigned int residue = 0;
+ unsigned long flags;
+ bool first = true;
+ dma_cookie_t first_c, current_c;
+ dma_cookie_t used;
+ enum dma_status ret;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+ list_for_each_entry(desc, pch-work_list, node) {
+ if (desc-status == BUSY) {
+ current_c = desc-txd.cookie;
+ if (first) {
+ first_c = desc-txd.cookie;
+ first = false;
+ }
+
+ if (first_c current_c)
+ residue += desc-px.bytes;
+ else {
+ if (desc-rqcfg.src_inc
pl330_src_addr_in_desc(desc, sar)) {
+ residue += desc-px.bytes;
+ residue -= sar - desc-px.src_addr;
+ } else if (desc-rqcfg.dst_inc
pl330_dst_addr_in_desc(desc, dar)) {
+ residue += desc-px.bytes;
+ residue -= dar - desc-px.dst_addr;
+ }
+ }
+ } else if (desc-status == PREP)
+ residue += desc-px.bytes;
+
+ if (desc-txd.cookie == used)
+ break;
+ }
+ spin_unlock_irqrestore(pch-lock, flags);
+ dma_set_residue(txstate, residue);
+ return ret;
}
static void pl330_issue_pending(struct dma_chan *chan)
@@ -2631,7 +2694,7 @@ static int pl330_dma_device_slave_caps(struct dma_chan
*dchan,
caps-directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
caps-cmd_pause = false;
caps-cmd_terminate = true;
- caps-residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ caps-residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
return 0;
}
Any comment on this patch?
Well it doesn't break audio, but I don't think it has the correct haviour
for all cases yet.
Again, the semantics are that it should return the progress of the transfer
for which the allocation function returned the cookie that is passe to this
function. You have to consider that there might be multiple different
descriptors submitted and in the work list, not just the one we want to know
the status of. The big problem with the pl330 driver is that the current
structure of the driver makes it not so easy to implement the residue
reporting correctly.
- Lars
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Re: [PATCH] cpuidle: add MAINTAINERS entry for ARM Exynos cpuidle driver
On Tuesday, December 02, 2014 04:41:35 PM Bartlomiej Zolnierkiewicz wrote: Since there has been quite a lot of development going on for ARM Exynos cpuidle driver recently I would like to add separate MAINTAINERS entry for it and add myself as the primary maintainer. The merging process would remain (almost) unchanged with patches going (with my Ack) through Daniel's or Kukjin's tree. Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com Daniel, do you want me to apply this, or are you going to do that? --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) Index: b/MAINTAINERS === --- a/MAINTAINERS 2014-11-27 18:02:51.988225868 +0100 +++ b/MAINTAINERS 2014-12-02 15:56:52.792997513 +0100 @@ -2701,6 +2701,16 @@ T: git git://git.kernel.org/pub/scm/linu S: Maintained F: drivers/cpuidle/cpuidle-big_little.c +CPUIDLE DRIVER - ARM EXYNOS +M: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com +M: Daniel Lezcano daniel.lezc...@linaro.org +M: Kukjin Kim kg...@kernel.org +L: linux...@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: drivers/cpuidle/cpuidle-exynos.c +F: arch/arm/mach-exynos/pm.c + CPUIDLE DRIVERS M: Rafael J. Wysocki r...@rjwysocki.net M: Daniel Lezcano daniel.lezc...@linaro.org -- To unsubscribe from this list: send the line unsubscribe linux-pm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- I speak only for myself. Rafael J. Wysocki, Intel Open Source Technology Center. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] hwrandom / exynos / PM: Use CONFIG_PM in #ifdef
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
CONFIG_PM is defined as the alternative of CONFIG_PM_RUNTIME and
CONFIG_PM_SLEEP, so it can be used instead of that.
Besides, after commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if
PM_SLEEP is selected) PM_RUNTIME is always set if PM is set, so
using the alternative isn't even necessary.
Use CONFIG_PM instead of it in drivers/char/hw_random/exynos-rng.c.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
---
Please let me know if it is OK to take this one into linux-pm.
---
drivers/char/hw_random/exynos-rng.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux-pm/drivers/char/hw_random/exynos-rng.c
===
--- linux-pm.orig/drivers/char/hw_random/exynos-rng.c
+++ linux-pm/drivers/char/hw_random/exynos-rng.c
@@ -143,7 +143,7 @@ static int exynos_rng_remove(struct plat
return 0;
}
-#if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM_RUNTIME)
+#ifdef CONFIG_PM
static int exynos_rng_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
--
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[PATCH] drm / exynos / PM: Replace CONFIG_PM_RUNTIME with CONFIG_PM
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
Replace CONFIG_PM_RUNTIME with CONFIG_PM in 4 files under
gpu/drm/exynos/.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
---
Note: This depends on commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if
PM_SLEEP is selected) which is only in linux-next at the moment (via the
linux-pm tree).
Please let me know if it is OK to take this one into linux-pm.
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c|2 +-
drivers/gpu/drm/exynos/exynos_drm_g2d.c |2 +-
drivers/gpu/drm/exynos/exynos_drm_gsc.c |2 +-
drivers/gpu/drm/exynos/exynos_drm_rotator.c |2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_fimc.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -1817,7 +1817,7 @@ static int fimc_resume(struct device *de
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int fimc_runtime_suspend(struct device *dev)
{
struct fimc_context *ctx = get_fimc_context(dev);
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_gsc.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -1764,7 +1764,7 @@ static int gsc_resume(struct device *dev
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int gsc_runtime_suspend(struct device *dev)
{
struct gsc_context *ctx = get_gsc_context(dev);
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_rotator.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_rotator.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_rotator.c
@@ -822,7 +822,7 @@ static int rotator_resume(struct device
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int rotator_runtime_suspend(struct device *dev)
{
struct rot_context *rot = dev_get_drvdata(dev);
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_g2d.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -1540,7 +1540,7 @@ static int g2d_resume(struct device *dev
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int g2d_runtime_suspend(struct device *dev)
{
struct g2d_data *g2d = dev_get_drvdata(dev);
--
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Re: [PATCH] drm / exynos / PM: Replace CONFIG_PM_RUNTIME with CONFIG_PM
On Wednesday, December 03, 2014 10:54 AM, Rafael J. Wysocki wrote:
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
Replace CONFIG_PM_RUNTIME with CONFIG_PM in 4 files under
gpu/drm/exynos/.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
Reviewed-by: Jingoo Han jg1@samsung.com
Best regards,
Jingoo Han
---
Note: This depends on commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if
PM_SLEEP is selected) which is only in linux-next at the moment (via the
linux-pm tree).
Please let me know if it is OK to take this one into linux-pm.
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c|2 +-
drivers/gpu/drm/exynos/exynos_drm_g2d.c |2 +-
drivers/gpu/drm/exynos/exynos_drm_gsc.c |2 +-
drivers/gpu/drm/exynos/exynos_drm_rotator.c |2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_fimc.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -1817,7 +1817,7 @@ static int fimc_resume(struct device *de
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int fimc_runtime_suspend(struct device *dev)
{
struct fimc_context *ctx = get_fimc_context(dev);
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_gsc.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -1764,7 +1764,7 @@ static int gsc_resume(struct device *dev
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int gsc_runtime_suspend(struct device *dev)
{
struct gsc_context *ctx = get_gsc_context(dev);
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_rotator.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_rotator.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_rotator.c
@@ -822,7 +822,7 @@ static int rotator_resume(struct device
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int rotator_runtime_suspend(struct device *dev)
{
struct rot_context *rot = dev_get_drvdata(dev);
Index: linux-pm/drivers/gpu/drm/exynos/exynos_drm_g2d.c
===
--- linux-pm.orig/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ linux-pm/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -1540,7 +1540,7 @@ static int g2d_resume(struct device *dev
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int g2d_runtime_suspend(struct device *dev)
{
struct g2d_data *g2d = dev_get_drvdata(dev);
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[PATCH] media / PM: Replace CONFIG_PM_RUNTIME with CONFIG_PM
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
The alternative of CONFIG_PM_SLEEP and CONFIG_PM_RUNTIME may be
replaced with CONFIG_PM too.
Make these changes everywhere under drivers/media/.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
---
Note: This depends on commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if
PM_SLEEP is selected) which is only in linux-next at the moment (via the
linux-pm tree).
Please let me know if it is OK to take this one into linux-pm.
---
drivers/media/platform/coda/coda-common.c |4 ++--
drivers/media/platform/exynos4-is/fimc-core.c |6 +++---
drivers/media/platform/exynos4-is/fimc-is-i2c.c |2 +-
drivers/media/platform/exynos4-is/fimc-lite.c |2 +-
drivers/media/platform/exynos4-is/mipi-csis.c |2 +-
drivers/media/platform/s5p-jpeg/jpeg-core.c |4 ++--
drivers/media/platform/s5p-mfc/s5p_mfc.c|2 +-
drivers/media/platform/s5p-mfc/s5p_mfc_pm.c | 10 --
8 files changed, 15 insertions(+), 17 deletions(-)
Index: linux-pm/drivers/media/platform/s5p-jpeg/jpeg-core.c
===
--- linux-pm.orig/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ linux-pm/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -2632,7 +2632,7 @@ static int s5p_jpeg_remove(struct platfo
return 0;
}
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#ifdef CONFIG_PM
static int s5p_jpeg_runtime_suspend(struct device *dev)
{
struct s5p_jpeg *jpeg = dev_get_drvdata(dev);
@@ -2682,7 +2682,7 @@ static int s5p_jpeg_runtime_resume(struc
return 0;
}
-#endif /* CONFIG_PM_RUNTIME || CONFIG_PM_SLEEP */
+#endif /* CONFIG_PM */
#ifdef CONFIG_PM_SLEEP
static int s5p_jpeg_suspend(struct device *dev)
Index: linux-pm/drivers/media/platform/s5p-mfc/s5p_mfc.c
===
--- linux-pm.orig/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ linux-pm/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -1302,7 +1302,7 @@ static int s5p_mfc_resume(struct device
}
#endif
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int s5p_mfc_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
Index: linux-pm/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
===
--- linux-pm.orig/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
+++ linux-pm/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
@@ -13,9 +13,7 @@
#include linux/clk.h
#include linux/err.h
#include linux/platform_device.h
-#ifdef CONFIG_PM_RUNTIME
#include linux/pm_runtime.h
-#endif
#include s5p_mfc_common.h
#include s5p_mfc_debug.h
#include s5p_mfc_pm.h
@@ -67,7 +65,7 @@ int s5p_mfc_init_pm(struct s5p_mfc_dev *
}
atomic_set(pm-power, 0);
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
pm-device = dev-plat_dev-dev;
pm_runtime_enable(pm-device);
#endif
@@ -93,7 +91,7 @@ void s5p_mfc_final_pm(struct s5p_mfc_dev
}
clk_unprepare(pm-clock_gate);
clk_put(pm-clock_gate);
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
pm_runtime_disable(pm-device);
#endif
}
@@ -120,7 +118,7 @@ void s5p_mfc_clock_off(void)
int s5p_mfc_power_on(void)
{
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
return pm_runtime_get_sync(pm-device);
#else
atomic_set(pm-power, 1);
@@ -130,7 +128,7 @@ int s5p_mfc_power_on(void)
int s5p_mfc_power_off(void)
{
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
return pm_runtime_put_sync(pm-device);
#else
atomic_set(pm-power, 0);
Index: linux-pm/drivers/media/platform/exynos4-is/fimc-is-i2c.c
===
--- linux-pm.orig/drivers/media/platform/exynos4-is/fimc-is-i2c.c
+++ linux-pm/drivers/media/platform/exynos4-is/fimc-is-i2c.c
@@ -81,7 +81,7 @@ static int fimc_is_i2c_remove(struct pla
return 0;
}
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#ifdef CONFIG_PM
static int fimc_is_i2c_runtime_suspend(struct device *dev)
{
struct fimc_is_i2c *isp_i2c = dev_get_drvdata(dev);
Index: linux-pm/drivers/media/platform/exynos4-is/fimc-lite.c
===
--- linux-pm.orig/drivers/media/platform/exynos4-is/fimc-lite.c
+++ linux-pm/drivers/media/platform/exynos4-is/fimc-lite.c
@@ -1588,7 +1588,7 @@ err_clk_put:
return ret;
}
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int fimc_lite_runtime_resume(struct device *dev)
{
struct fimc_lite *fimc = dev_get_drvdata(dev);
Index: linux-pm/drivers/media/platform/exynos4-is/mipi-csis.c
Re: [PATCH] hwrandom / exynos / PM: Use CONFIG_PM in #ifdef
On Wed, Dec 03, 2014 at 02:40:35AM +0100, Rafael J. Wysocki wrote: From: Rafael J. Wysocki rafael.j.wyso...@intel.com CONFIG_PM is defined as the alternative of CONFIG_PM_RUNTIME and CONFIG_PM_SLEEP, so it can be used instead of that. Besides, after commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is selected) PM_RUNTIME is always set if PM is set, so using the alternative isn't even necessary. Use CONFIG_PM instead of it in drivers/char/hw_random/exynos-rng.c. Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com Acked-by: Herbert Xu herb...@gondor.apana.org.au Please let me know if it is OK to take this one into linux-pm. Sure. -- Email: Herbert Xu herb...@gondor.apana.org.au Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: pl330: Set residue in tx_status callback
Hi Lars,
[snip]
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+ list_for_each_entry(desc, pch-work_list, node) {
+ if (desc-status == BUSY) {
+ current_c = desc-txd.cookie;
+ if (first) {
+ first_c = desc-txd.cookie;
+ first = false;
+ }
+
+ if (first_c current_c)
+ residue += desc-px.bytes;
+ else {
+ if (desc-rqcfg.src_inc
pl330_src_addr_in_desc(desc, sar)) {
+ residue += desc-px.bytes;
+ residue -= sar - desc-px.src_addr;
+ } else if (desc-rqcfg.dst_inc
pl330_dst_addr_in_desc(desc, dar))
{
+ residue += desc-px.bytes;
+ residue -= dar - desc-px.dst_addr;
+ }
+ }
+ } else if (desc-status == PREP)
+ residue += desc-px.bytes;
+
+ if (desc-txd.cookie == used)
+ break;
+ }
+ spin_unlock_irqrestore(pch-lock, flags);
+ dma_set_residue(txstate, residue);
+ return ret;
}
[snip]
Any comment on this patch?
Well it doesn't break audio, but I don't think it has the correct haviour
for all cases yet.
OK. Any way of testing other cases like scatter-gather and memcopy. I
verified memcopy in dmatest but it seems not doing anything with
residue bytes.
Again, the semantics are that it should return the progress of the transfer
for which the allocation function returned the cookie that is passe to this
May be my understanding is wrong. For clarification..In the
snd_dmaengine_pcm_pointer it is subtracting the residue bytes from the
total buffer bytes not from period bytes. So how it expects
the progress of the transfer of the passed cookie which just holds period bytes?
function. You have to consider that there might be multiple different
descriptors submitted and in the work list, not just the one we want to know
Even though there are multiple descriptors in the work list, at a time
only two descriptors are in busy state(as per the documentation in the
driver) and all the descriptors cookie number is in incremental order.
Not sure for other cases how it will be.
the status of. The big problem with the pl330 driver is that the current
structure of the driver makes it not so easy to implement the residue
reporting correctly.
- Lars
Thanks
Padma
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Re: [PATCH] soc: samsung: pmu: split up SoC specific PMU data
On 2014년 12월 01일 01:16, Pankaj Dubey wrote: This patch splits up exynos-pmu.c file, and moves PMU configuration data and functions handing those data into SoC specific PMU files, keeping driver structure and common functionality into exynos-pmu.c. At the same time it also separates compilation of these different SoC PMU files based on CONFIG_ARM64 and CONFIG_ARM. This way we can reduce overhead of ARM64 SoC's PMU getting compiled when kernel is built for ARM and vice-versa. This patch also removes .owner field from exynos-pmu.c as it's redundant for drivers calling platform_driver_register to register platform_driver. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com --- This patch is prepared on top of kgene/for-next and following patch [1] from Amit Daniel. [1]: http://www.spinics.net/lists/linux-samsung-soc/msg39797.html This patch tries to address some of concerns raised for using exynos-pmu.c for ARM and ARM64 based SoC at these threads [2], [3]. [2]: http://www.spinics.net/lists/linux-samsung-soc/msg39809.html [3]: https://lkml.org/lkml/2014/11/24/322 Since Exynos SoC's has similar PMU IP, and already existing bindings can be used, it makes sense to keep single driver for both ARM and ARM64 based SoCs. All common functionalties are in exynos-pmu.c whereas SoC specific data and handling are moved into SoC specific exynos-pmu files. All changes are compiled tested only. Any improvements/suggestions are most welcome. drivers/soc/samsung/Makefile |9 +- drivers/soc/samsung/exynos-pmu.c | 1293 +- drivers/soc/samsung/exynos-pmu.h | 63 ++ drivers/soc/samsung/exynos3250-pmu.c | 176 + drivers/soc/samsung/exynos4-pmu.c| 223 ++ drivers/soc/samsung/exynos5250-pmu.c | 196 ++ drivers/soc/samsung/exynos5420-pmu.c | 298 drivers/soc/samsung/exynos7-pmu.c| 441 8 files changed, 1412 insertions(+), 1287 deletions(-) create mode 100644 drivers/soc/samsung/exynos-pmu.h create mode 100644 drivers/soc/samsung/exynos3250-pmu.c create mode 100644 drivers/soc/samsung/exynos4-pmu.c create mode 100644 drivers/soc/samsung/exynos5250-pmu.c create mode 100644 drivers/soc/samsung/exynos5420-pmu.c create mode 100644 drivers/soc/samsung/exynos7-pmu.c ... diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h new file mode 100644 index 000..4adc5a3 --- /dev/null +++ b/drivers/soc/samsung/exynos-pmu.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header for EXYNOS PMU Driver support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __EXYNOSPMU_H +#define __EXYNOSPMU_H + +#include linux/io.h + +#define PMU_TABLE_END(-1U) + +static void __iomem *pmu_base_addr; + AFAIK, static variable in header file can't be used globally. It would be placed in exynos-pmu.c or elsewhere and then only extern declaration is allowed here. If I'm wrong, please let me know. Thanks. Jonghwa -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/2] Input: add regulator haptic driver
Hi Jaewon,
On Mon, Dec 01, 2014 at 11:11:12AM +0900, Jaewon Kim wrote:
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
---
.../devicetree/bindings/input/regulator-haptic.txt | 21 ++
drivers/input/misc/Kconfig | 11 +
drivers/input/misc/Makefile|1 +
drivers/input/misc/regulator-haptic.c | 247
include/linux/input/regulator-haptic.h | 31 +++
5 files changed, 311 insertions(+)
create mode 100644
Documentation/devicetree/bindings/input/regulator-haptic.txt
create mode 100644 drivers/input/misc/regulator-haptic.c
create mode 100644 include/linux/input/regulator-haptic.h
diff --git a/Documentation/devicetree/bindings/input/regulator-haptic.txt
b/Documentation/devicetree/bindings/input/regulator-haptic.txt
new file mode 100644
index 000..3ed1c7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/regulator-haptic.txt
@@ -0,0 +1,21 @@
+* Regulator Haptic Device Tree Bindings
+
+Required Properties:
+ - compatible : Should be regulator-haptic
+ - haptic-supply : Power supply to the haptic motor.
+ [*] refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+ - max-microvolt : The maximum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+ - min-microvolt : The minimum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+Example:
+
+ haptics {
+ compatible = regulator-haptic;
+ haptic-supply = motor_regulator;
+ max-microvolt = 270;
+ min-microvolt = 110;
+ };
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 23297ab..e5e556d 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -394,6 +394,17 @@ config INPUT_CM109
To compile this driver as a module, choose M here: the module will be
called cm109.
+config INPUT_REGULATOR_HAPTIC
+ tristate regulator haptics support
+ select INPUT_FF_MEMLESS
+ help
+ This option enables device driver support for the haptic controlled
+ by regulator. This driver supports ff-memless interface
+ from input framework.
+
+ To compile this driver as a module, choose M here: the
+ module will be called regulator-haptic.
+
config INPUT_RETU_PWRBUTTON
tristate Retu Power button Driver
depends on MFD_RETU
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 19c7603..1f135af 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o
obj-$(CONFIG_INPUT_POWERMATE)+= powermate.o
obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o
obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o
+obj-$(CONFIG_INPUT_REGULATOR_HAPTIC) += regulator-haptic.o
obj-$(CONFIG_INPUT_RETU_PWRBUTTON) += retu-pwrbutton.o
obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER) += rotary_encoder.o
obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o
diff --git a/drivers/input/misc/regulator-haptic.c
b/drivers/input/misc/regulator-haptic.c
new file mode 100644
index 000..6bc8e45
--- /dev/null
+++ b/drivers/input/misc/regulator-haptic.c
@@ -0,0 +1,247 @@
+/*
+ * Regulator haptic driver
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Jaewon Kim jaewon02@samsung.com
+ * Author: Hyunhee Kim hyunhee@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/input.h
+#include linux/input/regulator-haptic.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+
+#define MAX_MAGNITUDE_SHIFT 16
+
+struct regulator_haptic {
+ struct device *dev;
+ struct input_dev *input_dev;
+ struct regulator *regulator;
+ struct work_struct work;
+
+ bool enabled;
+ bool suspend_state;
+ unsigned int max_volt;
+ unsigned int min_volt;
+ unsigned int intensity;
+ unsigned int magnitude;
+};
+
+static void regulator_haptic_enable(struct regulator_haptic *haptic, bool
state)
+{
+ int error;
+
+ if (haptic-enabled == state)
+ return;
+
Re: [PATCH v4 1/2] Input: add regulator haptic driver
Hi Dmitry,
2014년 12월 03일 15:02에 Dmitry Torokhov 이(가) 쓴 글:
Hi Jaewon,
On Mon, Dec 01, 2014 at 11:11:12AM +0900, Jaewon Kim wrote:
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
---
.../devicetree/bindings/input/regulator-haptic.txt | 21 ++
drivers/input/misc/Kconfig | 11 +
drivers/input/misc/Makefile|1 +
drivers/input/misc/regulator-haptic.c | 247
include/linux/input/regulator-haptic.h | 31 +++
5 files changed, 311 insertions(+)
create mode 100644
Documentation/devicetree/bindings/input/regulator-haptic.txt
create mode 100644 drivers/input/misc/regulator-haptic.c
create mode 100644 include/linux/input/regulator-haptic.h
diff --git a/Documentation/devicetree/bindings/input/regulator-haptic.txt
b/Documentation/devicetree/bindings/input/regulator-haptic.txt
new file mode 100644
index 000..3ed1c7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/regulator-haptic.txt
@@ -0,0 +1,21 @@
+* Regulator Haptic Device Tree Bindings
+
+Required Properties:
+ - compatible : Should be regulator-haptic
+ - haptic-supply : Power supply to the haptic motor.
+ [*] refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+ - max-microvolt : The maximum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+ - min-microvolt : The minimum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+Example:
+
+ haptics {
+ compatible = regulator-haptic;
+ haptic-supply = motor_regulator;
+ max-microvolt = 270;
+ min-microvolt = 110;
+ };
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 23297ab..e5e556d 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -394,6 +394,17 @@ config INPUT_CM109
To compile this driver as a module, choose M here: the module will be
called cm109.
+config INPUT_REGULATOR_HAPTIC
+ tristate regulator haptics support
+ select INPUT_FF_MEMLESS
+ help
+ This option enables device driver support for the haptic controlled
+ by regulator. This driver supports ff-memless interface
+ from input framework.
+
+ To compile this driver as a module, choose M here: the
+ module will be called regulator-haptic.
+
config INPUT_RETU_PWRBUTTON
tristate Retu Power button Driver
depends on MFD_RETU
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 19c7603..1f135af 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o
obj-$(CONFIG_INPUT_POWERMATE) += powermate.o
obj-$(CONFIG_INPUT_PWM_BEEPER)+= pwm-beeper.o
obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o
+obj-$(CONFIG_INPUT_REGULATOR_HAPTIC) += regulator-haptic.o
obj-$(CONFIG_INPUT_RETU_PWRBUTTON)+= retu-pwrbutton.o
obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER) += rotary_encoder.o
obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o
diff --git a/drivers/input/misc/regulator-haptic.c
b/drivers/input/misc/regulator-haptic.c
new file mode 100644
index 000..6bc8e45
--- /dev/null
+++ b/drivers/input/misc/regulator-haptic.c
@@ -0,0 +1,247 @@
+/*
+ * Regulator haptic driver
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Jaewon Kim jaewon02@samsung.com
+ * Author: Hyunhee Kim hyunhee@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/input.h
+#include linux/input/regulator-haptic.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+
+#define MAX_MAGNITUDE_SHIFT16
+
+struct regulator_haptic {
+ struct device *dev;
+ struct input_dev *input_dev;
+ struct regulator *regulator;
+ struct work_struct work;
+
+ bool enabled;
+ bool suspend_state;
+ unsigned int max_volt;
+ unsigned int min_volt;
+ unsigned int intensity;
+ unsigned int magnitude;
+};
+
+static void regulator_haptic_enable(struct regulator_haptic *haptic, bool
state)
+{
+ int error;
+
+ if (haptic-enabled == state)
+
Re: [PATCHv3 1/1] thermal: cpu_cooling: check for the readiness of cpufreq layer
On 28 November 2014 at 20:23, Eduardo Valentin edubez...@gmail.com wrote: diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c index 1ab0018..88d2775 100644 --- a/drivers/thermal/cpu_cooling.c +++ b/drivers/thermal/cpu_cooling.c @@ -440,6 +440,9 @@ __cpufreq_cooling_register(struct device_node *np, int ret = 0, i; struct cpufreq_policy policy; + if (!cpufreq_frequency_get_table(0)) Please add a pr_debug() here, that will be quite useful while debugging. Also, you can't simply pass 0 to get_table() above. We might be registering the cooling device for some other cluster as well.. This is what I have done in my patch earlier. cpufreq_frequency_get_table(cpumask_first(clip_cpus)); And this will work for all cases. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: pl330: Set residue in tx_status callback
On 3 December 2014 at 10:17, Padma Venkat padma@gmail.com wrote:
Hi Lars,
[snip]
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+ list_for_each_entry(desc, pch-work_list, node) {
+ if (desc-status == BUSY) {
+ current_c = desc-txd.cookie;
+ if (first) {
+ first_c = desc-txd.cookie;
+ first = false;
+ }
+
+ if (first_c current_c)
+ residue += desc-px.bytes;
+ else {
+ if (desc-rqcfg.src_inc
pl330_src_addr_in_desc(desc, sar)) {
+ residue += desc-px.bytes;
+ residue -= sar - desc-px.src_addr;
+ } else if (desc-rqcfg.dst_inc
pl330_dst_addr_in_desc(desc, dar))
{
+ residue += desc-px.bytes;
+ residue -= dar - desc-px.dst_addr;
+ }
+ }
+ } else if (desc-status == PREP)
+ residue += desc-px.bytes;
+
+ if (desc-txd.cookie == used)
+ break;
+ }
+ spin_unlock_irqrestore(pch-lock, flags);
+ dma_set_residue(txstate, residue);
+ return ret;
}
[snip]
Any comment on this patch?
Well it doesn't break audio, but I don't think it has the correct haviour
for all cases yet.
OK. Any way of testing other cases like scatter-gather and memcopy. I
verified memcopy in dmatest but it seems not doing anything with
residue bytes.
Again, the semantics are that it should return the progress of the transfer
for which the allocation function returned the cookie that is passe to this
May be my understanding is wrong. For clarification..In the
snd_dmaengine_pcm_pointer it is subtracting the residue bytes from the
total buffer bytes not from period bytes. So how it expects
the progress of the transfer of the passed cookie which just holds period
bytes?
function. You have to consider that there might be multiple different
descriptors submitted and in the work list, not just the one we want to know
Even though there are multiple descriptors in the work list, at a time
only two descriptors are in busy state(as per the documentation in the
driver) and all the descriptors cookie number is in incremental order.
Not sure for other cases how it will be.
Yes.
Tracing the history ... I think we could have done without
04abf5daf7d dma: pl330: Differentiate between submitted and issued descriptors
The pl330 dmaengine driver currently does not differentiate
between submitted
and issued descriptors. It won't start transferring a newly submitted
descriptor until issue_pending() is called, but only if it is idle. If it is
active and a new descriptor is submitted before it goes idle it will happily
start the newly submitted descriptor once all earlier submitted
descriptors have
been completed. This is not a 100% correct with regards to the dmaengine
interface semantics. A descriptor is not supposed to be started
until the next
issue_pending() call after the descriptor has been submitted.
because the reasoning above seems incorrect considering the following
documentation...
Documentation/crypto/async-tx-api.txt says
Once a driver-specific threshold is met the driver
automatically issues pending operations. An application can force this
event by calling async_tx_issue_pending_all().
And
include/linux/dmaengine.h says
dma_async_tx_descriptor.tx_submit(): set the prepared descriptor(s)
to be executed by the engine
so theoretically a driver, not starting transfer until
issue_pending(), is broken.
At best the patch@04abf5daf7d makes the driver slightly more
complicated and the reason behind confusion such as in this thread.
-jassi
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[PATCH] ARM: samsung: add exynos-chipid binding information
Exynos SoC's DT files are using Chipid device nodes, but it's binding
information is missing. This patch adds exynos-chipid binding information.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
.../bindings/arm/samsung/exynos-chipid.txt | 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
new file mode 100644
index 000..85c5dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
@@ -0,0 +1,12 @@
+SAMSUNG Exynos SoCs Chipid driver.
+
+Required properties:
+- compatible : Should at least contain samsung,exynos4210-chipid.
+
+- reg: offset and length of the register set
+
+Example:
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
--
1.7.9.5
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[PATCH v5 2/2] ARM: dts: Add haptics node for exynos3250-rinato
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 84380fa..da03005 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -104,6 +104,13 @@
};
};
};
+
+ haptics {
+ compatible = regulator-haptic;
+ haptic-supply = motor_reg;
+ min-microvolt = 110;
+ max-microvolt = 270;
+ };
};
adc {
--
1.7.9.5
--
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[PATCH v5 1/2] Input: add regulator haptic driver
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
---
.../devicetree/bindings/input/regulator-haptic.txt | 21 ++
drivers/input/misc/Kconfig | 11 +
drivers/input/misc/Makefile|1 +
drivers/input/misc/regulator-haptic.c | 246
include/linux/input/regulator-haptic.h | 31 +++
5 files changed, 310 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/regulator-haptic.txt
create mode 100644 drivers/input/misc/regulator-haptic.c
create mode 100644 include/linux/input/regulator-haptic.h
diff --git a/Documentation/devicetree/bindings/input/regulator-haptic.txt
b/Documentation/devicetree/bindings/input/regulator-haptic.txt
new file mode 100644
index 000..3ed1c7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/regulator-haptic.txt
@@ -0,0 +1,21 @@
+* Regulator Haptic Device Tree Bindings
+
+Required Properties:
+ - compatible : Should be regulator-haptic
+ - haptic-supply : Power supply to the haptic motor.
+ [*] refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+ - max-microvolt : The maximum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+ - min-microvolt : The minimum voltage value supplied to the haptic motor.
+ [The unit of the voltage is a micro]
+
+Example:
+
+ haptics {
+ compatible = regulator-haptic;
+ haptic-supply = motor_regulator;
+ max-microvolt = 270;
+ min-microvolt = 110;
+ };
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 23297ab..e5e556d 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -394,6 +394,17 @@ config INPUT_CM109
To compile this driver as a module, choose M here: the module will be
called cm109.
+config INPUT_REGULATOR_HAPTIC
+ tristate regulator haptics support
+ select INPUT_FF_MEMLESS
+ help
+ This option enables device driver support for the haptic controlled
+ by regulator. This driver supports ff-memless interface
+ from input framework.
+
+ To compile this driver as a module, choose M here: the
+ module will be called regulator-haptic.
+
config INPUT_RETU_PWRBUTTON
tristate Retu Power button Driver
depends on MFD_RETU
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 19c7603..1f135af 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o
obj-$(CONFIG_INPUT_POWERMATE) += powermate.o
obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o
obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o
+obj-$(CONFIG_INPUT_REGULATOR_HAPTIC) += regulator-haptic.o
obj-$(CONFIG_INPUT_RETU_PWRBUTTON) += retu-pwrbutton.o
obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER)+= rotary_encoder.o
obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o
diff --git a/drivers/input/misc/regulator-haptic.c
b/drivers/input/misc/regulator-haptic.c
new file mode 100644
index 000..c355942
--- /dev/null
+++ b/drivers/input/misc/regulator-haptic.c
@@ -0,0 +1,246 @@
+/*
+ * Regulator haptic driver
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Jaewon Kim jaewon02@samsung.com
+ * Author: Hyunhee Kim hyunhee@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/input.h
+#include linux/input/regulator-haptic.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+
+#define MAX_MAGNITUDE_SHIFT16
+
+struct regulator_haptic {
+ struct device *dev;
+ struct input_dev *input_dev;
+ struct regulator *regulator;
+ struct work_struct work;
+
+ bool enabled;
+ bool suspend_state;
+ unsigned int max_volt;
+ unsigned int min_volt;
+ unsigned int intensity;
+ unsigned int magnitude;
+};
+
+static void regulator_haptic_enable(struct regulator_haptic *haptic, bool
state)
+{
+ int error;
+
+ if (haptic-enabled == state)
+ return;
+
+ if (state)
+ error = regulator_enable(haptic-regulator);
+ else
+ error =
