RE: [PATCH] clk: samsung: exynos7: Add clocks for MSCL block
Hi Sylwester, On Monday, December 22, 2014 8:28 PM Sylwester Nawrocki, [snip] I've queued this patch for 3.20. Would be nice to have a Reviewed-by tag from someone else who has access to the SoC documentation though. Pankaj Dubey has reviewed this patch [1]. He has pointed out that there is an extra tab space in the patch. You want me to send a revised version of this patch? [1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg40329.html Is Exynos7420 User Manual applicable to this? Exynos 7 (Octa?) seems like a marketing name to me. In technical documents there are usually more specific names used, like exynos7410 or exynos7420. -- Regards, Sylwester Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
3.19-rc1: peach*: display not working (missing patches)
Hi, 3.19-rc1 still misses these two patches: 156823e arm: dts: Exynos5: Use pmu_system_controller phandle for dp phy 03c16e7 ARM: exynos_defconfig: Enable options for display panel support156823e and without them, the display doesn't turn on on my peachpi: can we have them queued for rc2? -- bye, p. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 6/8] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
From: Tomasz Figa t.f...@samsung.com
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec and .configure callbacks is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[added comment and reworked unconditional call to SMC_CMD_L2X0INVALL]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Kukjin Kim kgene@samsung.com
---
arch/arm/mach-exynos/firmware.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 766f57d2f029..dc5ae53aa317 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
#include asm/cacheflush.h
#include asm/cputype.h
#include asm/firmware.h
+#include asm/hardware/cache-l2x0.h
#include asm/suspend.h
#include mach/map.h
@@ -136,6 +137,43 @@ static const struct firmware_ops exynos_firmware_ops = {
.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_resume : NULL,
};
+static void exynos_l2_write_sec(unsigned long val, unsigned reg)
+{
+ static int l2cache_enabled;
+
+ switch (reg) {
+ case L2X0_CTRL:
+ if (val L2X0_CTRL_EN) {
+ /*
+* Before the cache can be enabled, due to firmware
+* design, SMC_CMD_L2X0INVALL must be called.
+*/
+ if (!l2cache_enabled) {
+ exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+ l2cache_enabled = 1;
+ }
+ } else {
+ l2cache_enabled = 0;
+ }
+ exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
+ break;
+
+ case L2X0_DEBUG_CTRL:
+ exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
+ break;
+
+ default:
+ WARN_ONCE(1, %s: ignoring write to reg 0x%x\n, __func__, reg);
+ }
+}
+
+static void exynos_l2_configure(const struct l2x0_regs *regs)
+{
+ exynos_smc(SMC_CMD_L2X0SETUP1, regs-tag_latency, regs-data_latency,
+ regs-prefetch_ctrl);
+ exynos_smc(SMC_CMD_L2X0SETUP2, regs-pwr_ctrl, regs-aux_ctrl, 0);
+}
+
void __init exynos_firmware_init(void)
{
struct device_node *nd;
@@ -155,4 +193,16 @@ void __init exynos_firmware_init(void)
pr_info(Running under secure firmware.\n);
register_firmware_ops(exynos_firmware_ops);
+
+ /*
+* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
+* running under secure firmware, require certain registers of L2
+* cache controller to be written in secure mode. Here .write_sec
+* callback is provided to perform necessary SMC calls.
+*/
+ if (IS_ENABLED(CONFIG_CACHE_L2X0)
+read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+ outer_cache.write_sec = exynos_l2_write_sec;
+ outer_cache.configure = exynos_l2_configure;
+ }
}
--
1.9.2
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[PATCH v10 7/8] ARM: EXYNOS: Add support for non-secure L2X0 resume
From: Tomasz Figa t.f...@samsung.com On Exynos SoCs it is necessary to resume operation of L2C early in assembly code, because otherwise certain systems will crash. This patch adds necessary code to non-secure resume handler. Signed-off-by: Tomasz Figa t.f...@samsung.com [rewrote the code accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe..31d25834b9c4 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -16,6 +16,8 @@ */ #include linux/linkage.h +#include asm/asm-offsets.h +#include asm/hardware/cache-l2x0.h #include smc.h #define CPU_MASK 0xff00 @@ -74,6 +76,45 @@ ENTRY(exynos_cpu_resume_ns) mov r0, #SMC_CMD_C15RESUME dsb smc #0 +#ifdef CONFIG_CACHE_L2X0 + adr r0, 1f + ldr r2, [r0] + add r0, r2, r0 + + /* Check that the address has been initialised. */ + ldr r1, [r0, #L2X0_R_PHY_BASE] + teq r1, #0 + beq skip_l2x0 + + /* Check if controller has been enabled. */ + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne skip_l2x0 + + ldr r1, [r0, #L2X0_R_TAG_LATENCY] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + ldr r3, [r0, #L2X0_R_PREFETCH_CTRL] + mov r0, #SMC_CMD_L2X0SETUP1 + smc #0 + + /* Reload saved regs pointer because smc corrupts registers. */ + adr r0, 1f + ldr r2, [r0] + add r0, r2, r0 + + ldr r1, [r0, #L2X0_R_PWR_CTRL] + ldr r2, [r0, #L2X0_R_AUX_CTRL] + mov r0, #SMC_CMD_L2X0SETUP2 + smc #0 + + mov r0, #SMC_CMD_L2X0INVALL + smc #0 + + mov r1, #1 + mov r0, #SMC_CMD_L2X0CTRL + smc #0 +skip_l2x0: +#endif /* CONFIG_CACHE_L2X0 */ skip_cp15: b cpu_resume ENDPROC(exynos_cpu_resume_ns) @@ -83,3 +124,8 @@ cp15_save_diag: .globl cp15_save_power cp15_save_power: .long 0 @ cp15 power control + +#ifdef CONFIG_CACHE_L2X0 + .align +1: .long l2x0_saved_regs - . +#endif /* CONFIG_CACHE_L2X0 */ -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 0/8] Enable L2 cache support on Exynos4210/4x12 SoCs
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+ platforms by moving l2cache initialization to
common code. This will resolve too early call to l2cache init, what might
cause kmalloc failure in code added in next patches.
Next four patches extend existing support for secure write in L2C driver
to account for design of secure firmware running on Exynos. Namely:
1) direct read access to certain registers is needed on Exynos, because
secure firmware calls set several registers at once,
2) not all boards are running secure firmware, so .write_sec callback
needs to be installed in Exynos firmware ops initialization code,
3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
is not allowed and so must use l2c_write_sec as well,
4) on certain boards, default value of prefetch register is incorrect
and must be overridden at L2C initialization.
For boards running with firmware that provides access to individual
L2C registers this series should introduce no functional changes. However
since the driver is widely used on other platforms I'd like to kindly ask
any interested people for testing.
Further three patches add implementation of .write_sec and .configure
callbacks for Exynos secure firmware and necessary DT nodes to enable
L2 cache.
Changes in this version tested on Exynos4412-based TRATS2 and OdroidU3+
boards (both with secure firmware). There should be no functional change
for Exynos boards running without secure firmware. I do not have access
to affected non-Exynos boards, so I could not test on them.
Omap related changes were only compile time tested.
Depends on:
- v3.19-rc1
Changelog:
Changes since v9:
(https://lkml.org/lkml/2014/11/17/217)
- Rebased onto vanilla v3.19-rc1
- Added patch for Omap2+ (move l2cache initialization to common code), what
fixes too early initialization (kmalloc failure)
Changes since v8:
(http://lkml.org/lkml/2014/11/13/263)
- Rebased onto vanilla v3.18-rc3 and added required includes, which were
previously added by other patches
- Added Acked-by tags for Exynos part
Changes since v7:
(https://lkml.org/lkml/2014/10/29/158)
- rebased onto arm-soc/for-next kernel tree (depends on patches merged to
v3.18-rc3 and arm-soc/samsung/pm2 branch)
- removed 'ARM: l2c: unify L2C-310 OF initialization error messages' patch
(no longer needed)
Changes since v6:
(https://lkml.org/lkml/2014/10/27/233)
- changed PL310 to L2C-310 prefix in error messages
- added patch shortening the error message about incorrect associativity
Changes since v5:
(https://lkml.org/lkml/2014/9/24/364)
- rebased onto v3.18-rc2
- added error message about missing properties values
Changes since v4:
(https://lkml.org/lkml/2014/8/26/461)
- rewrote the code accessing l2x0_saved_regs from assembly code
- added comment and reworked unconditional call to SMC_CMD_L2X0INVALL
Patch summary:
Marek Szyprowski (1):
ARM: OMAP2+: use common l2cache initialization code
Tomasz Figa (7):
ARM: l2c: Refactor the driver to use commit-like interface
ARM: l2c: Add interface to ask hypervisor to configure L2C
ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
not NULL
ARM: l2c: Add support for overriding prefetch settings
ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
ARM: EXYNOS: Add support for non-secure L2X0 resume
ARM: dts: exynos4: Add nodes for L2 cache controller
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
arch/arm/include/asm/outercache.h | 3 +
arch/arm/kernel/irq.c | 3 +-
arch/arm/mach-exynos/firmware.c| 50 +
arch/arm/mach-exynos/sleep.S | 46 +
arch/arm/mach-omap2/board-generic.c| 6 +
arch/arm/mach-omap2/common.h | 7 +
arch/arm/mach-omap2/omap4-common.c | 16 +-
arch/arm/mm/cache-l2x0.c | 270 -
11 files changed, 323 insertions(+), 111 deletions(-)
--
1.9.2
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[PATCH v10 8/8] ARM: dts: exynos4: Add nodes for L2 cache controller
From: Tomasz Figa t.f...@samsung.com
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Kukjin Kim kgene@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63c8070..8e45ea44317e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -81,6 +81,15 @@
reg = 0x10023CA0 0x20;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = arm,pl310-cache;
+ reg = 0x10502000 0x1000;
+ cache-unified;
+ cache-level = 2;
+ arm,tag-latency = 2 2 1;
+ arm,data-latency = 2 2 1;
+ };
+
gic: interrupt-controller@1049 {
cpu-offset = 0x8000;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b70402e943..8bc97c415c9a 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -54,6 +54,20 @@
reg = 0x10023CA0 0x20;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = arm,pl310-cache;
+ reg = 0x10502000 0x1000;
+ cache-unified;
+ cache-level = 2;
+ arm,tag-latency = 2 2 1;
+ arm,data-latency = 3 2 1;
+ arm,double-linefill = 1;
+ arm,double-linefill-incr = 0;
+ arm,double-linefill-wrap = 1;
+ arm,prefetch-drop = 1;
+ arm,prefetch-offset = 7;
+ };
+
clock: clock-controller@1003 {
compatible = samsung,exynos4412-clock;
reg = 0x1003 0x2;
--
1.9.2
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[PATCH v10 5/8] ARM: l2c: Add support for overriding prefetch settings
From: Tomasz Figa t.f...@samsung.com
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in the
driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[mszyprow: rebased onto v3.18-rc1, added error message when prefetch related
dt property has been provided without any value]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/mm/cache-l2x0.c | 54 ++
2 files changed, 64 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b/Documentation/devicetree/bindings/arm/l2cc.txt
index 292ef7ca3058..0dbabe9a6b0a 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -57,6 +57,16 @@ Optional properties:
- cache-id-part: cache id part number to be used if it is not present
on hardware
- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if
non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
Example:
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index d214be207517..6f9d5a02d053 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1169,6 +1169,8 @@ static void __init l2c310_of_parse(const struct
device_node *np,
u32 tag[3] = { 0, 0, 0 };
u32 filter[2] = { 0, 0 };
u32 assoc;
+ u32 prefetch;
+ u32 val;
int ret;
of_property_read_u32_array(np, arm,tag-latency, tag, ARRAY_SIZE(tag));
@@ -1214,6 +1216,58 @@ static void __init l2c310_of_parse(const struct
device_node *np,
assoc);
break;
}
+
+ prefetch = l2x0_saved_regs.prefetch_ctrl;
+
+ ret = of_property_read_u32(np, arm,double-linefill, val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,double-linefill property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,double-linefill-incr, val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,double-linefill-incr property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,double-linefill-wrap, val);
+ if (ret == 0) {
+ if (!val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,double-linefill-wrap property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,prefetch-drop, val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_PREFETCH_DROP;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,prefetch-drop property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,prefetch-offset, val);
+ if (ret == 0) {
+ prefetch = ~L310_PREFETCH_CTRL_OFFSET_MASK;
+ prefetch |= val L310_PREFETCH_CTRL_OFFSET_MASK;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,prefetch-offset property value is
missing\n);
+ }
+
+ l2x0_saved_regs.prefetch_ctrl = prefetch;
}
static const struct l2c_init_data of_l2c310_data __initconst = {
--
1.9.2
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[PATCH v10 4/8] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL
From: Tomasz Figa t.f...@samsung.com
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index ad857bada96c..350f188c92d2 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -109,7 +109,8 @@ void __init init_IRQ(void)
if (IS_ENABLED(CONFIG_OF) IS_ENABLED(CONFIG_CACHE_L2X0)
(machine_desc-l2c_aux_mask || machine_desc-l2c_aux_val)) {
- outer_cache.write_sec = machine_desc-l2c_write_sec;
+ if (!outer_cache.write_sec)
+ outer_cache.write_sec = machine_desc-l2c_write_sec;
ret = l2x0_of_init(machine_desc-l2c_aux_val,
machine_desc-l2c_aux_mask);
if (ret)
--
1.9.2
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[PATCH v10 2/8] ARM: l2c: Refactor the driver to use commit-like interface
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 210 ++-
1 file changed, 115 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5e65ca8dea62..e5948c5adaa7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -41,12 +41,14 @@ struct l2c_init_data {
void (*enable)(void __iomem *, u32, unsigned);
void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
void (*save)(void __iomem *);
+ void (*configure)(void __iomem *);
struct outer_cache_fns outer_cache;
};
#define CACHE_LINE_SIZE32
static void __iomem *l2x0_base;
+static const struct l2c_init_data *l2x0_data;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
@@ -106,6 +108,14 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
}
}
+static void l2c_configure(void __iomem *base)
+{
+ if (l2x0_data-configure)
+ l2x0_data-configure(base);
+
+ l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+}
+
/*
* Enable the L2 cache controller. This function must only be
* called when the cache controller is known to be disabled.
@@ -114,7 +124,12 @@ static void l2c_enable(void __iomem *base, u32 aux,
unsigned num_lock)
{
unsigned long flags;
- l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+ /* Do not touch the controller if already enabled. */
+ if (readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)
+ return;
+
+ l2x0_saved_regs.aux_ctrl = aux;
+ l2c_configure(base);
l2c_unlock(base, num_lock);
@@ -208,6 +223,11 @@ static void l2c_save(void __iomem *base)
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
}
+static void l2c_resume(void)
+{
+ l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data-num_lock);
+}
+
/*
* L2C-210 specific code.
*
@@ -288,14 +308,6 @@ static void l2c210_sync(void)
__l2c210_cache_sync(l2x0_base);
}
-static void l2c210_resume(void)
-{
- void __iomem *base = l2x0_base;
-
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN))
- l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
-}
-
static const struct l2c_init_data l2c210_data __initconst = {
.type = L2C-210,
.way_size_0 = SZ_8K,
@@ -309,7 +321,7 @@ static const struct l2c_init_data l2c210_data __initconst =
{
.flush_all = l2c210_flush_all,
.disable = l2c_disable,
.sync = l2c210_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -466,7 +478,7 @@ static const struct l2c_init_data l2c220_data = {
.flush_all = l2c220_flush_all,
.disable = l2c_disable,
.sync = l2c220_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -615,39 +627,29 @@ static void __init l2c310_save(void __iomem *base)
L310_POWER_CTRL);
}
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)) {
- unsigned revision;
-
- /* restore pl310 setup */
- writel_relaxed(l2x0_saved_regs.tag_latency,
- base + L310_TAG_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.data_latency,
- base + L310_DATA_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.filter_end,
- base + L310_ADDR_FILTER_END);
- writel_relaxed(l2x0_saved_regs.filter_start,
- base + L310_ADDR_FILTER_START);
-
- revision = readl_relaxed(base + L2X0_CACHE_ID)
- L2X0_CACHE_ID_RTL_MASK;
-
- if (revision = L310_CACHE_ID_RTL_R2P0)
- l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
-
[PATCH v10 3/8] ARM: l2c: Add interface to ask hypervisor to configure L2C
From: Tomasz Figa t.f...@samsung.com
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware according to
specified parameters. This patch adds such.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/include/asm/outercache.h | 3 +++
arch/arm/mm/cache-l2x0.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 891a56b35bcf..563b92fc2f41 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -23,6 +23,8 @@
#include linux/types.h
+struct l2x0_regs;
+
struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
@@ -36,6 +38,7 @@ struct outer_cache_fns {
/* This is an ARM L2C thing */
void (*write_sec)(unsigned long, unsigned);
+ void (*configure)(const struct l2x0_regs *);
};
extern struct outer_cache_fns outer_cache;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index e5948c5adaa7..d214be207517 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -110,6 +110,11 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
static void l2c_configure(void __iomem *base)
{
+ if (outer_cache.configure) {
+ outer_cache.configure(l2x0_saved_regs);
+ return;
+ }
+
if (l2x0_data-configure)
l2x0_data-configure(base);
@@ -910,6 +915,7 @@ static int __init __l2c_init(const struct l2c_init_data
*data,
fns = data-outer_cache;
fns.write_sec = outer_cache.write_sec;
+ fns.configure = outer_cache.configure;
if (data-fixup)
data-fixup(l2x0_base, cache_id, fns);
--
1.9.2
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[PATCH v10 1/8] ARM: OMAP2+: use common l2cache initialization code
This patch implements generic DT L2C initialisation (the one from
init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mach-omap2/board-generic.c | 6 ++
arch/arm/mach-omap2/common.h| 7 +++
arch/arm/mach-omap2/omap4-common.c | 16 +---
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..c5c480b76da5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -171,6 +171,9 @@ static const char *const omap4_boards_compat[] __initconst
= {
};
DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec = omap4_l2c310_write_sec,
.reserve= omap_reserve,
.smp= smp_ops(omap4_smp_ops),
.map_io = omap4_map_io,
@@ -214,6 +217,9 @@ static const char *const am43_boards_compat[] __initconst =
{
};
DT_MACHINE_START(AM43_DT, Generic AM43 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec = omap4_l2c310_write_sec,
.map_io = am33xx_map_io,
.init_early = am43xx_init_early,
.init_late = am43xx_init_late,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..19c9144d8b38 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -35,6 +35,7 @@
#include linux/irqchip/irq-omap-intc.h
#include asm/proc-fns.h
+#include asm/hardware/cache-l2x0.h
#include i2c.h
#include serial.h
@@ -94,11 +95,17 @@ extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);
#ifdef CONFIG_CACHE_L2X0
int omap_l2_cache_init(void);
+#define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \
+L310_AUX_CTRL_DATA_PREFETCH | \
+L310_AUX_CTRL_INSTR_PREFETCH)
+void omap4_l2c310_write_sec(unsigned long val, unsigned reg);
#else
static inline int omap_l2_cache_init(void)
{
return 0;
}
+#define OMAP_L2C_AUX_CTRL 0
+#define omap4_l2c310_write_sec NULL
#endif
extern void omap5_realtime_timer_init(void);
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44abe49b..fe99ceff2e2d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -166,7 +166,7 @@ void __iomem *omap4_get_l2cache_base(void)
return l2cache_base;
}
-static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
+void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
{
unsigned smc_op;
@@ -201,24 +201,10 @@ static void omap4_l2c310_write_sec(unsigned long val,
unsigned reg)
int __init omap_l2_cache_init(void)
{
- u32 aux_ctrl;
-
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
if (WARN_ON(!l2cache_base))
return -ENOMEM;
-
- /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
- aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
- L310_AUX_CTRL_DATA_PREFETCH |
- L310_AUX_CTRL_INSTR_PREFETCH;
-
- outer_cache.write_sec = omap4_l2c310_write_sec;
- if (of_have_populated_dt())
- l2x0_of_init(aux_ctrl, 0xcf9f);
- else
- l2x0_init(l2cache_base, aux_ctrl, 0xcf9f);
-
return 0;
}
#endif
--
1.9.2
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Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
Hello, On 2014-12-22 18:28, Russell King - ARM Linux wrote: On Mon, Dec 22, 2014 at 11:12:42AM -0600, Nishanth Menon wrote: On Mon, Dec 22, 2014 at 11:04 AM, Russell King - ARM Linux li...@arm.linux.org.uk wrote: That only leaves the non-DT stuff to worry about this, and from what I understand, that's going to be removed soon. If we're going to keep the non-DT stuff, we should implement a new machine_desc hook for it instead of hijacking one of the existing callbacks. none of the PL310 support requires non-DT. PL310 is needed for OMAP4 and AM437x both of which are DT only. Right, so the simple answer for the time being is to kill most of omap_l2_cache_init(), leaving just the ioremap() behind. Everything else can go into the machine_desc structures, and OMAP4 and AM437x can both benefit from initialising the L2 cache at exactly the same point as most other platforms. I hope I did it right: https://lkml.org/lkml/2014/12/23/158 Please test, because I have no access to Omap hardware. Best regards -- Marek Szyprowski, PhD Samsung RD Institute Poland -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
On Tue, Dec 23, 2014 at 12:00:00PM +0100, Marek Szyprowski wrote: I hope I did it right: https://lkml.org/lkml/2014/12/23/158 Please test, because I have no access to Omap hardware. Patch 1/8 looks like I'd expect it to. Nishanth, please test with your failing scenario, thanks. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 4/4] ARM: dts: Add memory bus node for Exynos3250-based Rinato board
This patch adds the exynos memory-bus node which includes the regulator and
devfreq-event phandle. The devfreq-event phandle is used for the governor
of devfreq device and provide the current usage state of DMC/Internal
memory bus group.
Cc: Kukjin Kim kgene@samsung.com
Cc: Myungjoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 60948ae..6722555 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -564,6 +564,18 @@
};
};
+memory_bus_mif {
+ devfreq-events = ppmu_dmc0_3, ppmu_dmc1_3;
+ vdd-mem-supply = buck1_reg;
+ status = okay;
+};
+
+memory_bus_int {
+ devfreq-events = ppmu_leftbus_3, ppmu_rightbus_3;
+ vdd-mem-supply = buck3_reg;
+ status = okay;
+};
+
xusbxti {
clock-frequency = 2400;
};
--
1.8.5.5
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[RFC PATCH 3/4] ARM: dts: Add memory bus node for Exynos3250
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Cc: Kukjin Kim kgene@samsung.com
Cc: Myungjoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 137 ++
1 file changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 9ed1260..7f20039 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -99,6 +99,143 @@
};
};
+ memory_bus_mif: memory_bus@0 {
+ compatible = samsung,exynos-memory-bus;
+
+ operating-points =
+ 40 875000
+ 20 80
+ 133000 80
+ 10 80
+ 5 80;
+ status = disabled;
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = cmu_dmc CLK_DIV_DMC;
+ clock-names = memory-bus;
+ frequency =
+ 40
+ 20
+ 133000
+ 10
+ 5;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = samsung,exynos-memory-bus;
+
+ operating-points =
+ 40 95
+ 20 95
+ 133000 925000
+ 10 85
+ 8 85
+ 5 85;
+
+ status = disabled;
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = cmu CLK_DIV_ACLK_100;
+ clock-names = memory-bus;
+ frequency =
+ 10
+ 10
+ 10
+ 10
+ 5
+ 5;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = cmu CLK_DIV_ACLK_160;
+ clock-names = memory-bus;
+ frequency =
+ 20
+ 16
+ 10
+ 8
+ 8
+ 5;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = cmu CLK_DIV_ACLK_200;
+ clock-names = memory-bus;
+ frequency =
+ 20
+ 20
+ 10
+ 8
+ 5
+ 5;
+ };
+
+ gps_block: memory_bus_block4 {
+ clocks = cmu CLK_DIV_ACLK_266;
+ clock-names = memory-bus;
+ frequency =
+ 30
+ 20
+ 133000
+ 10
+ 5
+ 5;
+ };
+
+ mcuisp_block: memory_bus_block5 {
+ clocks = cmu CLK_DIV_ACLK_400_MCUISP;
+
[RFC PATCH 1/4] devfreq: exynos: Add generic exynos memory bus frequency driver
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus block has a clock for memory bus speed and frequency
table which is changed according to the utilization of memory bus on runtime.
And then each memory bus group has the one more memory bus blocks and
OPP table (including frequency and voltage), regulator, devfreq-event
devices.
There are a little difference about the number of memory bus because each Exynos
SoC have the different sub-IP and different memory bus speed. In spite of this
difference among Exynos SoCs, we can support almost Exynos SoC by adding
unique data of memory bus to devicetree file.
Cc: Myungjoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/devfreq/Kconfig | 15 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/exynos-busfreq.c | 586 +++
3 files changed, 602 insertions(+)
create mode 100644 drivers/devfreq/exynos-busfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 21f8f17..f1003eb 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -65,6 +65,21 @@ config DEVFREQ_GOV_USERSPACE
comment DEVFREQ Drivers
+config ARM_EXYNOS_BUS_DEVFREQ
+ bool EXYNOS Memory Bus DEVFREQ Driver
+ depends on ARCH_EXYNOS
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_EVENT_EXYNOS_PPMU
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+ Memory bus has one more group of memory bus (e.g, MIF and INT block).
+ Each memory bus group could contain many memoby bus block. It reads
+ PPMU counters of memory controllers by using DEVFREQ-event device
+ and adjusts the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
config ARM_EXYNOS4_BUS_DEVFREQ
bool ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver
depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412)
!ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index c449336..2b82a4c 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
# DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS) += exynos-busfreq.o
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
diff --git a/drivers/devfreq/exynos-busfreq.c b/drivers/devfreq/exynos-busfreq.c
new file mode 100644
index 000..a693e62
--- /dev/null
+++ b/drivers/devfreq/exynos-busfreq.c
@@ -0,0 +1,586 @@
+/*
+ * Generic Exynos Memory Bus Frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi cw00.c...@samsung.com
+ *
+ * This driver is based on exynos4_bus.c, which was written
+ * by MyungJoo Ham myungjoo@samsung.com, Samsung Electronics.
+ *
+ * This driver support Exynos Memory Bus frequency feature by using in DEVFREQ
+ * framework. This version supprots Exynos3250/Exynos4 series/Exynos5260 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/devfreq.h
+#include linux/devfreq-event.h
+#include linux/device.h
+#include linux/export.h
+#include linux/module.h
+#include linux/of_device.h
+#include linux/pm_opp.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+
+#define BUS_SATURATION_RATIO 40
+#define SAFEVOLT 5
+
+struct exynos_memory_bus_opp_info {
+ unsigned long rate;
+ unsigned long volt;
+};
+
+struct exynos_memory_bus_block {
+ struct clk *clk;
+ struct exynos_memory_bus_opp_info *freq_table;
+};
+
+struct exynos_memory_bus_data {
+ /* devfreq device to monitor and control memory bus group */
+ struct device *dev;
+ struct devfreq *devfreq;
+
+ struct exynos_memory_bus_opp_info *freq_table;
+ unsigned int freq_count;
+ struct regulator *regulator;
+ struct mutex lock;
+
+ struct exynos_memory_bus_opp_info curr_opp;
+
+ struct exynos_memory_bus_block *block;
+ unsigned int block_count;
+
+ /* devfreq-event device to get current state of memory bus group */
+ struct devfreq_event_dev **edev;
+ unsigned int edev_count;
+};
+
+/*
+ * Initialize the memory bus group/block by
[RFC PATCH 0/4] devfreq: Add generic exynos memory-bus frequency driver
These patch-set adds the generic exynos bus frequency driver for memory bus with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can support the memory bus frequency driver for Exynos SoCs. Each memory bus block has a clock for memory bus speed and frequency table which is changed according to the utilization of memory bus on runtime. And then each memory bus group has the one more memory bus blocks and OPP table (including frequency and voltage), regulator, devfreq-event devices. There are a little difference about the number of memory bus because each Exynos SoC have the different sub-IP and different memory bus speed. In spite of this difference among Exynos SoCs, we can support almost Exynos SoC by adding unique data of memory bus to devicetree file. Chanwoo Choi (4): devfreq: exynos: Add generic exynos memory bus frequency driver devfreq: exynos: Add documentation for generic exynos memory bus frequency driver ARM: dts: Add memory bus node for Exynos3250 ARM: dts: Add memory bus node for Exynos3250-based Rinato board .../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +++ arch/arm/boot/dts/exynos3250-rinato.dts| 12 + arch/arm/boot/dts/exynos3250.dtsi | 137 + drivers/devfreq/Kconfig| 15 + drivers/devfreq/Makefile | 1 + drivers/devfreq/exynos-busfreq.c | 586 + 6 files changed, 935 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt create mode 100644 drivers/devfreq/exynos-busfreq.c -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 2/4] devfreq: exynos: Add documentation for generic exynos memory bus frequency driver
This patch adds the documentation for generic exynos memory bus frequency
driver.
Cc: MyungJoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +
1 file changed, 184 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
new file mode 100644
index 000..c601e88
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
@@ -0,0 +1,184 @@
+
+* Generic Exynos Memory Bus device
+
+The Samsung Exynos SoCs have many memory buses for data transfer between DRAM
+memory and MMC/sub-IP in SoC. Almost Exynos SoCs have the common architecture
+for memory buses. Generally, Exynos SoC express the memory bus by using memory
+bus group and block. The memory bus group has one more memory bus blocks and
+OPP table (including frequency and voltage for DVFS), regulator, devfreq-event
+devices. Each memory bus block has a clock for own memory bus speen and
+frequency table for DVFS. There are a little different among Exynos SoCs
+because each Exynos SoC has the different sub-IP and differnt memory bus.
+So, this difference should be specified in devicetree file.
+
+Required properties for memory bus group:
+- compatible: Should be samsung,exynos-memory-bus.
+- operating-points: the OPP table including frequency/voltage information to
+ support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- devfreq-events: the devfreq-event device to monitor the curret state of
+ memory bus group.
+- vdd-mem-supply: the regulator to provide memory bus group with the voltage.
+
+Required properties for memory bus block:
+- clock-names : the name of clock used by the memory bus, memory-bus.
+- clocks : phandles for clock specified in clock-names property.
+- #clock-cells: should be 1.
+- frequency: the frequency table to support DVFS feature.
+
+Example1 : Memory bus group/block in exynos3250.dtsi are listed below.
+ Exynos3250 has two memory bus group (MIF, INT group). MIF memory bus
+ group includes one memory bus block between DRAM and eMMC. Also, INT
+ memory bus group includes eight memory bus blocks which support each
+ sub-IPs between DRAM and sub-IPs.
+
+ memory_bus_mif: memory_bus@0 {
+ compatible = samsung,exynos-memory-bus;
+
+ operating-points =
+ 40 875000
+ 20 80
+ 133000 80
+ 10 80
+ 5 80;
+ status = disabled;
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = cmu_dmc CLK_DIV_DMC;
+ clock-names = memory-bus;
+ frequency =
+ 40
+ 20
+ 133000
+ 10
+ 5;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = samsung,exynos-memory-bus;
+
+ operating-points =
+ 40 95
+ 20 95
+ 133000 925000
+ 10 85
+ 8 85
+ 5 85;
+
+ status = disabled;
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = cmu CLK_DIV_ACLK_100;
+ clock-names = memory-bus;
+ frequency =
+ 10
+ 10
+ 10
+ 10
+ 5
+ 5;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = cmu CLK_DIV_ACLK_160;
+ clock-names = memory-bus;
+ frequency =
+ 20
+ 16
+ 10
+ 8
+ 8
+ 5;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = cmu CLK_DIV_ACLK_200;
+
Re: clk: samsung: exynos7: Add clocks for MSCL block
Hi Pankaj, On 23/12/14 05:59, Pankaj Dubey wrote: diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index a79bf23..95c1160 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -34,6 +34,7 @@ #define DIV_TOPC00x0600 #define DIV_TOPC10x0604 #define DIV_TOPC30x060C +#define ENABLE_ACLK_TOPC1 0x0804 nit: Tab space between #define and ENABLE_ACLK_TOPC1, should be removed. I verified register settings and clock relationships are as per UM I have with me. So other than above nit, everything looks fine. Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks for you review, I have already fixed the whitespace issue when applying. -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] ARM: dts: Enable USB node for exynos3250-monk
This patch adds device tree node for hsotg to control USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250-monk.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 24822aa..0c1d85d 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -134,6 +134,16 @@
};
};
+exynos_usbphy {
+ status = okay;
+};
+
+hsotg {
+ vusb_d-supply = ldo15_reg;
+ vusb_a-supply = ldo12_reg;
+ status = okay;
+};
+
i2c_0 {
#address-cells = 1;
#size-cells = 0;
--
1.7.9.5
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[PATCH 2/4] ARM: dts: Add hsotg node for exynos3250
This patch adds device tree node for hsotg to control USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index d976007..e5c891a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -255,6 +255,17 @@
status = disabled;
};
+ hsotg: hsotg@1248 {
+ compatible = snps,dwc2;
+ reg = 0x1248 0x2;
+ interrupts = 0 141 0;
+ clocks = cmu CLK_USBOTG;
+ clock-names = otg;
+ phys = exynos_usbphy 0;
+ phy-names = usb2-phy;
+ status = disabled;
+ };
+
mshc_0: mshc@1251 {
compatible = samsung,exynos5250-dw-mshc;
reg = 0x1251 0x1000;
--
1.7.9.5
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[PATCH 3/4] ARM: dts: Enable USB node for exynos3250-rinato
This patch enables hsotg and usbphy node to use USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 80aa8b4..bf4c17b 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -125,6 +125,16 @@
};
};
+exynos_usbphy {
+ status = okay;
+};
+
+hsotg {
+ vusb_d-supply = ldo15_reg;
+ vusb_a-supply = ldo12_reg;
+ status = okay;
+};
+
i2c_0 {
#address-cells = 1;
#size-cells = 0;
--
1.7.9.5
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[PATCH 0/4] ARM: dts: Add USB node for exynos3250 SoC boards
This patch series adds USB device node and phy for exynos3250 SoC. And enables for rinato and monk boards. Jaewon Kim (4): ARM: dts: Add exynos_usbphy node for exynos3250 ARM: dts: Add hsotg node for exynos3250 ARM: dts: Enable USB node for exynos3250-rinato ARM: dts: Enable USB node for exynos3250-monk arch/arm/boot/dts/exynos3250-monk.dts | 10 ++ arch/arm/boot/dts/exynos3250-rinato.dts | 10 ++ arch/arm/boot/dts/exynos3250.dtsi | 22 ++ 3 files changed, 42 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: dts: Add exynos_usbphy node for exynos3250
This patch adds device tree node for exynos_usbphy to use USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2246549..d976007 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -279,6 +279,17 @@
status = disabled;
};
+ exynos_usbphy: exynos-usbphy@125B {
+ compatible = samsung,exynos3250-usb2-phy;
+ reg = 0x125B 0x100;
+ samsung,pmureg-phandle = pmu_system_controller;
+ samsung,sysreg-phandle = sys_reg;
+ clocks = cmu CLK_USBOTG, xusbxti;
+ clock-names = phy, ref;
+ #phy-cells = 1;
+ status = disabled;
+ };
+
amba {
compatible = arm,amba-bus;
#address-cells = 1;
--
1.7.9.5
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Re: [PATCH 0/3] clk: samsung: Use samsung_cmu_register_one() to simplify code
Hi Chanwoo, On 23/12/14 08:40, Chanwoo Choi wrote: This patch-set uses the samsung_cmu_register_one() function to simplify the clock driver for Exynos3250/Exynos4415 SoC and change return value of samsung_cmu_register_one() because some clock driver may need the instance of samsung_clk_provider structure. Chanwoo Choi (3): clk: samsung: Changes the return value of samsung_cmu_register_one() clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code drivers/clk/samsung/clk-exynos3250.c | 217 --- drivers/clk/samsung/clk-exynos4415.c | 216 -- drivers/clk/samsung/clk.c| 13 ++- drivers/clk/samsung/clk.h| 3 +- 4 files changed, 107 insertions(+), 342 deletions(-) Thanks for the cleanup, I've queued that for 3.20. And fixed a minor checkpatch warning when applying: ERROR: foo* __init bar should be foo * __init bar #29: FILE: drivers/clk/samsung/clk.c:377: +struct samsung_clk_provider* __init samsung_cmu_register_one( total: 1 errors, 0 warnings, 42 lines checked 0001-clk-samsung-Changes-the-return-value-of-samsung_cmu_.patch has style problems, please review. -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] clk: samsung: Use samsung_cmu_register_one() to simplify code
Hi Sylwester, On Tue, Dec 23, 2014 at 10:41 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: Hi Chanwoo, On 23/12/14 08:40, Chanwoo Choi wrote: This patch-set uses the samsung_cmu_register_one() function to simplify the clock driver for Exynos3250/Exynos4415 SoC and change return value of samsung_cmu_register_one() because some clock driver may need the instance of samsung_clk_provider structure. Chanwoo Choi (3): clk: samsung: Changes the return value of samsung_cmu_register_one() clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code drivers/clk/samsung/clk-exynos3250.c | 217 --- drivers/clk/samsung/clk-exynos4415.c | 216 -- drivers/clk/samsung/clk.c| 13 ++- drivers/clk/samsung/clk.h| 3 +- 4 files changed, 107 insertions(+), 342 deletions(-) Thanks for the cleanup, I've queued that for 3.20. And fixed a minor checkpatch warning when applying: ERROR: foo* __init bar should be foo * __init bar #29: FILE: drivers/clk/samsung/clk.c:377: +struct samsung_clk_provider* __init samsung_cmu_register_one( total: 1 errors, 0 warnings, 42 lines checked 0001-clk-samsung-Changes-the-return-value-of-samsung_cmu_.patch has style problems, please review. I'll fix it and re-send these patch-set. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] clk: samsung: Use samsung_cmu_register_one() to simplify code
On 23/12/14 15:57, Chanwoo Choi wrote: I'll fix it and re-send these patch-set. There is no need, I already corrected it. The patches are already queued in this branch: http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/log/?h=for-v3.20/clk/next -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] clk: samsung: Use samsung_cmu_register_one() to simplify code
On Wed, Dec 24, 2014 at 12:05 AM, Sylwester Nawrocki s.nawro...@samsung.com wrote: On 23/12/14 15:57, Chanwoo Choi wrote: I'll fix it and re-send these patch-set. There is no need, I already corrected it. The patches are already queued in this branch: http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/log/?h=for-v3.20/clk/next OK, thanks for your fixup. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/17] thermal: exynos: Thermal code rework to use device tree
Hi Lukasz, On Mon, Dec 22, 2014 at 9:51 PM, Lukasz Majewski l.majew...@samsung.com wrote: Hi Abhilash, Hi Lukasz and Eduardo, [...] Although, this shouldn't be a problem. That is why we had the cycle with cpufreq folks, remember? (I will have a look in your patches) It would be great if those patches could find their way to therma -next. Then also Abhilash could benefit from them. I have a couple of 5420/5800 based chromebooks that I will test this series on. Is it OK for me to start basing my Exynos7 TMU support on this series ? Please let me know if I can help in any other way with this. I'm fine if you rebase on top of my patches. However, it is up to Eduardo when he decides to pull them to -next branch. I hope that it will happen soon. I tested a Peach Pit (5420 based chromebook) with your patches and they work well (temperatures and software tripping). However, my earlier comments with regards to duplicate exynos_tmu_initialize() and the thermal zone showing as disabled in sysfs . Also, I think the documentation for the dt properties are missing ? I will post my exynos7 work based on your patches soon. Please take a look. Regards, Abhilash Regards, Abhilash -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
On 12/23/2014 05:10 AM, Russell King - ARM Linux wrote: On Tue, Dec 23, 2014 at 12:00:00PM +0100, Marek Szyprowski wrote: I hope I did it right: https://lkml.org/lkml/2014/12/23/158 Please test, because I have no access to Omap hardware. Patch 1/8 looks like I'd expect it to. Nishanth, please test with your failing scenario, thanks. 3.19-rc1 1: am437x-sk: BOOT: PASS: http://slexy.org/raw/s2ARFeCcDp 2:am43xx-epos: BOOT: PASS: http://slexy.org/raw/s2Kzli0GYS 3: am43xx-gpevm: BOOT: PASS: http://slexy.org/raw/s2DMkJGmdF 4: pandaboard-es: BOOT: PASS: http://slexy.org/raw/s204jfptrr 5: pandaboard-vanilla: BOOT: PASS: http://slexy.org/raw/s2cbd82pMI 6:sdp4430: BOOT: PASS: http://slexy.org/raw/s21bzlzUNr TOTAL = 6 boards, Booted Boards = 6, No Boot boards = 0 against the patch series: (all am437x platforms fail) testing 1: am437x-sk: BOOT: FAIL: http://slexy.org/raw/s2yhDXyF7o 2:am43xx-epos: BOOT: FAIL: http://slexy.org/raw/s2m9cSdt55 3: am43xx-gpevm: BOOT: FAIL: http://slexy.org/raw/s2MqFFBuIl 4: pandaboard-es: BOOT: PASS: http://slexy.org/raw/s2XwggyB0a 5: pandaboard-vanilla: BOOT: PASS: http://slexy.org/raw/s25WDvtbob 6:sdp4430: BOOT: PASS: http://slexy.org/raw/s2gjynR1Co TOTAL = 6 boards, Booted Boards = 3, No Boot boards = 3 I am trying to understand what is different in AM437x except that it is a single A9 instead of OMAP4 style dual A9s. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 2/8] ARM: l2c: Refactor the driver to use commit-like interface
* Marek Szyprowski m.szyprow...@samsung.com [141223 02:51]: From: Tomasz Figa t.f...@samsung.com Certain implementations of secure hypervisors (namely the one found on Samsung Exynos-based boards) do not provide access to individual L2C registers. This makes the .write_sec()-based interface insufficient and provoking ugly hacks. This patch is first step to make the driver not rely on availability of writes to individual registers. This is achieved by refactoring the driver to use a commit-like operation scheme: all register values are prepared first and stored in an instance of l2x0_regs struct and then a single callback is responsible to flush those values to the hardware. The first patch of the series applied things boot with no problem. But after applying this one I get the following on am437x: Unhandled fault: imprecise external abort (0xc06) at 0xb6f33884 Probably the same issue Nishanth mentioned. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 2/8] ARM: l2c: Refactor the driver to use commit-like interface
On 12/23/2014 11:06 AM, Tony Lindgren wrote: * Marek Szyprowski m.szyprow...@samsung.com [141223 02:51]: From: Tomasz Figa t.f...@samsung.com Certain implementations of secure hypervisors (namely the one found on Samsung Exynos-based boards) do not provide access to individual L2C registers. This makes the .write_sec()-based interface insufficient and provoking ugly hacks. This patch is first step to make the driver not rely on availability of writes to individual registers. This is achieved by refactoring the driver to use a commit-like operation scheme: all register values are prepared first and stored in an instance of l2x0_regs struct and then a single callback is responsible to flush those values to the hardware. The first patch of the series applied things boot with no problem. But after applying this one I get the following on am437x: Unhandled fault: imprecise external abort (0xc06) at 0xb6f33884 Probably the same issue Nishanth mentioned. yep - just finished the bisect... came to the same conclusion.. c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f is the first bad commit commit c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f Author: Tomasz Figa t.f...@samsung.com Date: Tue Dec 23 11:48:30 2014 +0100 ARM: l2c: Refactor the driver to use commit-like interface Certain implementations of secure hypervisors (namely the one found on Samsung Exynos-based boards) do not provide access to individual L2C registers. This makes the .write_sec()-based interface insufficient and provoking ugly hacks. This patch is first step to make the driver not rely on availability of writes to individual registers. This is achieved by refactoring the driver to use a commit-like operation scheme: all register values are prepared first and stored in an instance of l2x0_regs struct and then a single callback is responsible to flush those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com :04 04 74c6c74a0dc0612d124cd759951adf2a1e4124ee 8082aabb474f8659231de744d87cd8dbd6dd79bb M arch $ git bisect log git bisect start # good: [97bf6af1f928216fd6c5a66e8a57bfa95a659672] Linux 3.19-rc1 git bisect good 97bf6af1f928216fd6c5a66e8a57bfa95a659672 # bad: [9afe195db6558621bd8bac379ed65ef121930684] ARM: dts: exynos4: Add nodes for L2 cache controller git bisect bad 9afe195db6558621bd8bac379ed65ef121930684 # bad: [0a89ef4dd870bbf692e30fef6c8182d7b8b42e17] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL git bisect bad 0a89ef4dd870bbf692e30fef6c8182d7b8b42e17 # bad: [c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f] ARM: l2c: Refactor the driver to use commit-like interface git bisect bad c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f # good: [080ab387c653b8655dc1ee790658b618399db2aa] ARM: OMAP2+: use common l2cache initialization code git bisect good 080ab387c653b8655dc1ee790658b618399db2aa -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: EXYNOS: Add exynos3250 suspend-to-ram support
This patch adds the support for suspend-to-ram feature of Exynos3250 SoC.
Exynos3250 don't contain the L2 cache.
The measured power-consumption in suspend state:
- before entering suspend : 31mA
- in suspend state : 16mA
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
This patch is based on v3.19-rc1 and is tested on Exynos3250-based Rinato board.
arch/arm/mach-exynos/regs-pmu.h | 3 ++
arch/arm/mach-exynos/suspend.c | 77 +
2 files changed, 80 insertions(+)
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index b5f4406..eb461e1 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -160,12 +160,14 @@
#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3)
#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
+#define S5P_PAD_RET_MMC2_OPTION0x30c8
#define S5P_PAD_RET_GPIO_OPTION0x3108
#define S5P_PAD_RET_UART_OPTION0x3128
#define S5P_PAD_RET_MMCA_OPTION0x3148
#define S5P_PAD_RET_MMCB_OPTION0x3168
#define S5P_PAD_RET_EBIA_OPTION0x3188
#define S5P_PAD_RET_EBIB_OPTION0x31A8
+#define S5P_PAD_RET_SPI_OPTION 0x31c8
#define S5P_PS_HOLD_CONTROL0x330C
#define S5P_PS_HOLD_EN (1 31)
@@ -326,6 +328,7 @@
(EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
#define EXYNOS3_ARM_COMMON_OPTION 0x2408
+#define EXYNOS3_ARM_L2_OPTION 0x2608
#define EXYNOS3_TOP_PWR_OPTION 0x2C48
#define EXYNOS3_CORE_TOP_PWR_OPTION0x2CA8
#define EXYNOS3_XUSBXTI_DURATION 0x341C
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..d6feef3 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -91,6 +91,12 @@ static unsigned int exynos_pmu_spare3;
static u32 exynos_irqwake_intmask = 0x;
+static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
+ { 73, BIT(1) }, /* RTC alarm */
+ { 74, BIT(2) }, /* RTC tick */
+ { /* sentinel */ },
+};
+
static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
{ 76, BIT(1) }, /* RTC alarm */
{ 77, BIT(2) }, /* RTC tick */
@@ -114,6 +120,19 @@ unsigned int exynos_release_ret_regs[] = {
REG_TABLE_END,
};
+unsigned int exynos3250_release_ret_regs[] = {
+ S5P_PAD_RET_MAUDIO_OPTION,
+ S5P_PAD_RET_GPIO_OPTION,
+ S5P_PAD_RET_UART_OPTION,
+ S5P_PAD_RET_MMCA_OPTION,
+ S5P_PAD_RET_MMCB_OPTION,
+ S5P_PAD_RET_EBIA_OPTION,
+ S5P_PAD_RET_EBIB_OPTION,
+ S5P_PAD_RET_MMC2_OPTION,
+ S5P_PAD_RET_SPI_OPTION,
+ REG_TABLE_END,
+};
+
unsigned int exynos5420_release_ret_regs[] = {
EXYNOS_PAD_RET_DRAM_OPTION,
EXYNOS_PAD_RET_MAUDIO_OPTION,
@@ -173,6 +192,12 @@ static int exynos_cpu_suspend(unsigned long arg)
return exynos_cpu_do_idle();
}
+static int exynos3250_cpu_suspend(unsigned long arg)
+{
+ flush_cache_all();
+ return exynos_cpu_do_idle();
+}
+
static int exynos5420_cpu_suspend(unsigned long arg)
{
/* MCPM works with HW CPU identifiers */
@@ -230,6 +255,23 @@ static void exynos_pm_prepare(void)
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
+static void exynos3250_pm_prepare(void)
+{
+ unsigned int tmp;
+
+ /* Set wake-up mask registers */
+ exynos_pm_set_wakeup_mask();
+
+ tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
+ tmp = ~EXYNOS5_OPTION_USE_RETENTION;
+ pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
+
+ exynos_pm_enter_sleep_mode();
+
+ /* ensure at least INFORM0 has the resume address */
+ pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+}
+
static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
@@ -344,6 +386,28 @@ early_wakeup:
pmu_raw_writel(0x0, S5P_INFORM1);
}
+static void exynos3250_pm_resume(void)
+{
+ u32 cpuid = read_cpuid_part();
+
+ if (exynos_pm_central_resume())
+ goto early_wakeup;
+
+ /* For release retention */
+ exynos_pm_release_retention();
+
+ pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
+
+ if (call_firmware_op(resume) == -ENOSYS
+cpuid == ARM_CPU_PART_CORTEX_A9)
+ exynos_cpu_restore_register();
+
+early_wakeup:
+
+ /* Clear SLEEP mode set in INFORM1 */
+ pmu_raw_writel(0x0, S5P_INFORM1);
+}
+
static void exynos5420_prepare_pm_resume(void)
{
if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
@@ -483,6 +547,16 @@ static const struct platform_suspend_ops
exynos_suspend_ops = {
[PATCH v2 0/4] ARM: dts: Add USB node for exynos3250 SoC boards
This patch series adds USB device node and phy for exynos3250 SoC. And enables for rinato and monk boards. Changes in v2: - remove unnessasary property samsung,sysreg-phandle - change xusbxti clock to CLK_SCLK_UPLL Jaewon Kim (4): ARM: dts: Add exynos_usbphy node for exynos3250 ARM: dts: Add hsotg node for exynos3250 ARM: dts: Enable USB node for exynos3250-rinato ARM: dts: Enable USB node for exynos3250-monk arch/arm/boot/dts/exynos3250-monk.dts | 10 ++ arch/arm/boot/dts/exynos3250-rinato.dts | 10 ++ arch/arm/boot/dts/exynos3250.dtsi | 21 + 3 files changed, 41 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/4] ARM: dts: Add hsotg node for exynos3250
This patch adds device tree node for hsotg to control USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 27d385f..204a84b 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -255,6 +255,17 @@
status = disabled;
};
+ hsotg: hsotg@1248 {
+ compatible = snps,dwc2;
+ reg = 0x1248 0x2;
+ interrupts = 0 141 0;
+ clocks = cmu CLK_USBOTG;
+ clock-names = otg;
+ phys = exynos_usbphy 0;
+ phy-names = usb2-phy;
+ status = disabled;
+ };
+
mshc_0: mshc@1251 {
compatible = samsung,exynos5250-dw-mshc;
reg = 0x1251 0x1000;
--
1.7.9.5
--
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[PATCH v2 3/4] ARM: dts: Enable USB node for exynos3250-rinato
This patch enables hsotg and usbphy node to use USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 80aa8b4..bf4c17b 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -125,6 +125,16 @@
};
};
+exynos_usbphy {
+ status = okay;
+};
+
+hsotg {
+ vusb_d-supply = ldo15_reg;
+ vusb_a-supply = ldo12_reg;
+ status = okay;
+};
+
i2c_0 {
#address-cells = 1;
#size-cells = 0;
--
1.7.9.5
--
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[PATCH v2 4/4] ARM: dts: Enable USB node for exynos3250-monk
This patch adds device tree node for hsotg to control USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250-monk.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 24822aa..0c1d85d 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -134,6 +134,16 @@
};
};
+exynos_usbphy {
+ status = okay;
+};
+
+hsotg {
+ vusb_d-supply = ldo15_reg;
+ vusb_a-supply = ldo12_reg;
+ status = okay;
+};
+
i2c_0 {
#address-cells = 1;
#size-cells = 0;
--
1.7.9.5
--
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[PATCH v2 1/4] ARM: dts: Add exynos_usbphy node for exynos3250
This patch adds device tree node for exynos_usbphy to use USB 2.0 Device.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2246549..27d385f 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -279,6 +279,16 @@
status = disabled;
};
+ exynos_usbphy: exynos-usbphy@125B {
+ compatible = samsung,exynos3250-usb2-phy;
+ reg = 0x125B 0x100;
+ samsung,pmureg-phandle = pmu_system_controller;
+ clocks = cmu CLK_USBOTG, cmu CLK_SCLK_UPLL;
+ clock-names = phy, ref;
+ #phy-cells = 1;
+ status = disabled;
+ };
+
amba {
compatible = arm,amba-bus;
#address-cells = 1;
--
1.7.9.5
--
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