[PATCH 2/2] arm: dts: disable CCI on exynos420 based arndale-octa
The arndale-octa board was giving imprecise external aborts during
boot-up with MCPM enabled. CCI enablement of the boot cluster was found
to be the cause of these aborts (possibly because the secure f/w was not
allowing it). Hence, disable CCI for the arndale-octa board.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Tested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Tested-by: Kevin Hilman khil...@linaro.org
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index aa7a7d7..db2c1c4 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -372,3 +372,7 @@
usbdrd_dwc3_1 {
dr_mode = host;
};
+
+cci {
+ status = disabled;
+};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..0a82ae7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -120,7 +120,7 @@
};
};
- cci@10d2 {
+ cci: cci@10d2 {
compatible = arm,cci-400;
#address-cells = 1;
#size-cells = 1;
--
2.2.0
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[PATCH 1/2] drivers: bus: check cci device tree node status
The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Acked-by: Sudeep Holla sudeep.ho...@arm.com Acked-by: Nicolas Pitre n...@linaro.org Tested-by: Sudeep Holla sudeep.ho...@arm.com Tested-by: Kevin Hilman khil...@linaro.org --- Changes: - Re-sending without the RFT tags drivers/bus/arm-cci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 860da40..0ce5e2d 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1312,6 +1312,9 @@ static int cci_probe(void) if (!np) return -ENODEV; + if (!of_device_is_available(np)) + return -ENODEV; + cci_config = of_match_node(arm_cci_matches, np)-data; if (!cci_config) return -ENODEV; -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Hi Kevin, On Sat, Jan 10, 2015 at 2:39 AM, Kevin Hilman khil...@kernel.org wrote: Abhilash Kesavan kesavan.abhil...@gmail.com writes: Hi Arnd/Olof, On Fri, Jan 9, 2015 at 10:40 AM, Sudeep Holla sudeep.ho...@arm.com wrote: On Thursday 08 January 2015 08:57 PM, Abhilash Kesavan wrote: Hi Sudeep, On Thu, Jan 8, 2015 at 12:15 PM, Sudeep Holla sudeep.ho...@arm.com wrote: Hi Abhilash, [...] What's the status of this patch. It was useful for me on vexpress for some testing. Please feel free to add Tested-by: Sudeep Holla sudeep.ho...@arm.com if this is not yet queued. Thanks for the tested-by. This patch has not been merged yet; I am not quite sure who is supposed to pick this up. So far, most of the CCI patches are merged through arm-soc. Would you be OK picking this up as is or do you want me to re-send this with the RFT tag dropped ? Please resend without the RFT, and collect the Tested-by tags you can add mine: Tested-by: Kevin Hilman khil...@linaro.org Please send to a...@kernel.org where patches targeted for the arm-soc tree are collected. I have done as suggested. Kindly check. Regards, Abhilash Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Exynos IOMMU driver doesn't work?
[adding Marek, Sjoerd and Joonyoung that were discussing about iommu support in another thread] Hello Hongbo, On Fri, Jan 9, 2015 at 8:31 AM, Hongbo Zhang hongbo.zh...@linaro.org wrote: Add linux-samsung-soc@vger.kernel.org mailing list. On 7 January 2015 at 18:31, Hongbo Zhang hongbo.zh...@linaro.org wrote: Hi Cho KyongHo, Joerg et al, I found the latest Exynos IOMMU driver doesn't work, the line 481: BUG_ON(!has_sysmmu(dev)); in function __exynos_sysmmu_enable() in file exynos-iommu.c triggers kernel panic. Then I found the dev-archdata.iommu isn't initialized at all, it should be the root cause. That's correct, I found the same the other day since and thought about posting a patch to return -ENODEV if !has_sysmmu(dev) instead to avoid the driver to panic the kernel. But then I realized this is already fixed in Marek's [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem series [0]. Another problem is this driver is added support of device tree, but there is no device tree nodes in the dts file, so I had to search from internet and added those nodes manually. I've found these links of v12 and v13 patches https://lkml.org/lkml/2014/4/27/171 https://lkml.org/lkml/2014/5/12/34 patch v13 was merged into mainline kernel, but as a part of v12, it isn't complete and doesn't work alone, eg dts nodes are missing. (I didn't research much dev-archdata.iommu initialization error is introduced by which patch, but it seems in very old codes there is no such problem) Yes, please take a look to Marek series [0]. Keep in mind that the series does not support all sysmmu revisions so IOMMU is not supported for some SoCs (e.g: Exynos5). Support for that is planned once that series land into mainline though [1]. May I ask why are you interested in IOMMU support on Exynos? I'm asking because the reason why I tried to enable IOMMU support (and hit the same issue) was to try using the Exynos DRM HDMI driver with IOMMU since I found that HDMI is working on the downstream Samsung kernel [2] that has IOMMU support, but is not working on mainline. At the end the HDMI problem seems to not be IOMMU related but something with the power domains and clocking but in case you are facing the same issue, you may be interested in that discussion [3]. Best regards, Javier [0]: http://www.spinics.net/lists/linux-samsung-soc/msg39168.html [1]: http://www.spinics.net/lists/linux-samsung-soc/msg39980.html [2]: g...@github.com:exynos-reference/kernel.git [3]: http://www.spinics.net/lists/linux-samsung-soc/msg40828.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Hi Arnd/Olof, On Fri, Jan 9, 2015 at 10:40 AM, Sudeep Holla sudeep.ho...@arm.com wrote: On Thursday 08 January 2015 08:57 PM, Abhilash Kesavan wrote: Hi Sudeep, On Thu, Jan 8, 2015 at 12:15 PM, Sudeep Holla sudeep.ho...@arm.com wrote: Hi Abhilash, [...] What's the status of this patch. It was useful for me on vexpress for some testing. Please feel free to add Tested-by: Sudeep Holla sudeep.ho...@arm.com if this is not yet queued. Thanks for the tested-by. This patch has not been merged yet; I am not quite sure who is supposed to pick this up. So far, most of the CCI patches are merged through arm-soc. Would you be OK picking this up as is or do you want me to re-send this with the RFT tag dropped ? Regards, Abhilash Regards, Sudeep -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 5/5] ARM: dts: exynos4412-trats: Switch max77686 regulators to GPIO control
Hi Kukjin,
Mark Brown pulled regulator changes and documentation for bindings [1].
Could you pick up this patch?
[1] http://www.spinics.net/lists/linux-samsung-soc/msg40834.html
Best regards,
Krzysztof
On pon, 2015-01-05 at 12:48 +0100, Krzysztof Kozlowski wrote:
Remove fixed regulators (duplicating what max77686 provides) and
add GPIO enable control to max77686 regulators.
This gives the system full control over those regulators. Previously
the state of such regulators was a mixture of what max77686 driver set
over I2C and what regulator-fixed set through GPIO.
Removal of 'regulator-always-on' from CAM_ISP_CORE_1.2V (buck9) allows
disabling it when it is not used. Previously this regulator was always
enabled because its enable state is a OR of:
- ENB9 GPIO (turned always on by regulator-fixed),
- BUCK9EN field in BUCK9CTRL register (off by max77686 through I2C).
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/boot/dts/exynos4412-trats2.dts | 25 +
1 file changed, 5 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 405d4f337e89..186c210680c1 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -58,15 +58,6 @@
#address-cells = 1;
#size-cells = 0;
- vemmc_reg: regulator-0 {
- compatible = regulator-fixed;
- regulator-name = VMEM_VDD_2.8V;
- regulator-min-microvolt = 280;
- regulator-max-microvolt = 280;
- gpio = gpk0 2 0;
- enable-active-high;
- };
-
cam_io_reg: voltage-regulator-1 {
compatible = regulator-fixed;
regulator-name = CAM_SENSOR_A;
@@ -94,16 +85,6 @@
enable-active-high;
};
- cam_isp_core_reg: voltage-regulator-4 {
- compatible = regulator-fixed;
- regulator-name = CAM_ISP_CORE_1.2V_EN;
- regulator-min-microvolt = 120;
- regulator-max-microvolt = 120;
- gpio = gpm0 3 0;
- enable-active-high;
- regulator-always-on;
- };
-
ps_als_reg: voltage-regulator-5 {
compatible = regulator-fixed;
regulator-name = LED_A_3.0V;
@@ -405,6 +386,7 @@
regulator-name = VTF_2.8V;
regulator-min-microvolt = 280;
regulator-max-microvolt = 280;
+ maxim,ena-gpios = gpy2 0
GPIO_ACTIVE_HIGH;
};
ldo22_reg: ldo22 {
@@ -412,6 +394,7 @@
regulator-name = VMEM_VDD_2.8V;
regulator-min-microvolt = 280;
regulator-max-microvolt = 280;
+ maxim,ena-gpios = gpk0 2
GPIO_ACTIVE_HIGH;
};
ldo23_reg: ldo23 {
@@ -518,6 +501,7 @@
regulator-name = VMEM_VDDF_3.0V;
regulator-min-microvolt = 285;
regulator-max-microvolt = 285;
+ maxim,ena-gpios = gpk0 2
GPIO_ACTIVE_HIGH;
};
buck9_reg: buck9 {
@@ -525,6 +509,7 @@
regulator-name = CAM_ISP_CORE_1.2V;
regulator-min-microvolt = 100;
regulator-max-microvolt = 120;
+ maxim,ena-gpios = gpm0 3
GPIO_ACTIVE_HIGH;
};
};
};
@@ -587,7 +572,7 @@
broken-cd;
non-removable;
card-detect-delay = 200;
- vmmc-supply = vemmc_reg;
+ vmmc-supply = ldo22_reg;
clock-frequency = 4;
samsung,dw-mshc-ciu-div = 0;
samsung,dw-mshc-sdr-timing = 2 3;
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Re: [PATCH v3] ARM: dts: Add dts file for odroid XU3 board
Sjoerd Simons sjoerd.sim...@collabora.co.uk writes: Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the same as the vendors naming, which means it's prefixed with exynos5422 instead of exynos5800 as the SoC name even though it includes the exyno5800 dtsi. Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Boot tested on top of next-20150109 (with and without my hack for bringing up 8 cores.) Tested-by: Kevin Hilman khil...@linaro.org Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 14/21] ARM: imx6: convert GPC to stacked domains
Hi Marc,
On 2015-01-07 18:42, Marc Zyngier wrote:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 +-
arch/arm/boot/dts/imx6sl.dtsi | 5 +-
arch/arm/boot/dts/imx6sx.dtsi | 5 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 116 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..c16d428 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+ interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
@@ -694,8 +696,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
#interrupt-cells = 3; is missing here.
I tested the patchset on a Colibri iMX6, but the module stopped booting
at some point. No error, no warn, but it looked like IRQ's are not
working:
[1.623939] platform sound: Driver imx-sgtl5000 requests probe
deferral
[1.630677] backlight supply power not found, using dummy regulator
[1.637067] pwm-backlight backlight: unable to request PWM, trying
legacy API
[1.644271] pwm-backlight backlight: unable to request legacy PWM
[1.650534] platform backlight: Driver pwm-backlight requests probe
deferral
[1.658080] platform 2028000.ssi: Driver fsl-ssi-dai requests probe
deferral
[1.665441] fec 2188000.ethernet eth0: Freescale FEC PHY driver
[Micrel KSZ8041] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
[1.677157] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[freeze]
I figured out that the GPC code did not get called. After digging
through the parsing code, I found the reason: irq_find_host always opted
to intc because this was missing... So, interrupt-cells mandatory for
all interrupt-controller? Maybe we could add a warn somewhere..?
With that in place, it worked fine:
Tested-by: Stefan Agner ste...@agner.ch
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..c476e67 100644
---
[RESEND PATCH] ARM: EXYNOS: Add missing static to file-scope declarations
The 'pm_data', 'exynos_release_ret_regs' and
'exynos5420_release_ret_regs' are not exported nor used outside of
suspend.c file. Make them static.
This fixes following sparse warnings:
arch/arm/mach-exynos/suspend.c:83:23: warning: symbol 'pm_data' was not
declared. Should it be static?
arch/arm/mach-exynos/suspend.c:106:14: warning: symbol
'exynos_release_ret_regs' was not declared. Should it be static?
arch/arm/mach-exynos/suspend.c:117:14: warning: symbol
'exynos5420_release_ret_regs' was not declared. Should it be static?
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/suspend.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 342797b9bf3b..fef091f8e59f 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -75,7 +75,7 @@ struct exynos_pm_data {
int (*cpu_suspend)(unsigned long);
};
-struct exynos_pm_data *pm_data;
+static struct exynos_pm_data *pm_data;
static int exynos5420_cpu_state;
static unsigned int exynos_pmu_spare3;
@@ -98,7 +98,7 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
{ /* sentinel */ },
};
-unsigned int exynos_release_ret_regs[] = {
+static unsigned int exynos_release_ret_regs[] = {
S5P_PAD_RET_MAUDIO_OPTION,
S5P_PAD_RET_GPIO_OPTION,
S5P_PAD_RET_UART_OPTION,
@@ -109,7 +109,7 @@ unsigned int exynos_release_ret_regs[] = {
REG_TABLE_END,
};
-unsigned int exynos5420_release_ret_regs[] = {
+static unsigned int exynos5420_release_ret_regs[] = {
EXYNOS_PAD_RET_DRAM_OPTION,
EXYNOS_PAD_RET_MAUDIO_OPTION,
EXYNOS_PAD_RET_JTAG_OPTION,
--
1.9.1
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RE: [PATCH v3 00/30] usb: updates for dwc2 gadget driver
CCing more of the Samsung folks and linux-kernel. Robert, Marek, can you test this series on your platform, please? If I don't hear from you soon, I'll just ack it and we can deal with any breakage later. -- Paul From: Mian Yousaf Kaukab [mailto:yousaf.kau...@intel.com] Sent: Friday, January 09, 2015 4:39 AM Hi, This patchset consists of various bug fixes and feature enhancements for the dwc2 gadget driver. All the patches are verified on dwc2 v3.0a with dedicated fifos. Main focus of testing was with dma enabled. Although basic testing without dma was also done. It is based on testing/next branch in Felipe's git and Tested-by: Dinh Nguyen dingu...@opensource.altera.com Thank you, Best regards, Yousaf History: v3: - Fixed comment from Sergei Shtylyov - Updated usb: dwc2: gadget: don't process XferCompl on setup packet to apply the check on endpoint 0 only. - Fixed regression in usb: dwc2: gadget: manage ep0 state in software for dwc2 ip v2.93a, found by Dinh Nguyen. v2: - Rebased to Felipe's testing/next with https://lkml.org/lkml/2014/12/16/135 applied on top. - Fixed comments from Robert Baldyga - Some cosmetic changes - Replaced usb: dwc2: gadget: process setup packet on transfer complete with usb: dwc2: gadget: don't process XferCompl on setup packet - Updated usb: dwc2: gadget: provide gadget handle to the phy so that otg_set_peripheral is called in both udc_start and udc_stop. v1: - Addressed comments from Sergei Shtylyov Gregory Herrero (13): usb: dwc2: gadget: register gadget handle to the phy usb: dwc2: gadget: write correct value in ahbcfg register usb: dwc2: gadget: don't erase gahbcfg register when enabling dma usb: dwc2: gadget: add device tree property to enable dma Documentation: dt-bindings: add dt binding info for dwc2 g-use-dma usb: dwc2: gadget: configure fifos from device tree Documentation: dt-bindings: add dt binding info for dwc2 fifo resizing usb: dwc2: gadget: don't block after fifo flush timeout usb: dwc2: gadget: add vbus_session support usb: dwc2: gadget: reset fifo_map when initializing fifos usb: dwc2: gadget: fix pullup handling usb: dwc2: gadget: add vbus_draw support usb: dwc2: gadget: force gadget initialization in dev mode Mian Yousaf Kaukab (17): usb: dwc2: gadget: mask fifo empty irq with dma usb: dwc2: gadget: don't process XferCompl on setup packet usb: dwc2: gadget: don't embed ep0 buffers usb: dwc2: gadget: fix error path in dwc2_gadget_init usb: dwc2: gadget: add bi-directional endpoint support usb: dwc2: gadget: check interrupts for all endpoints usb: dwc2: gadget: remove unused members from hsotg_req usb: dwc2: gadget: fix debug loop limits usb: dwc2: gadget: consider all tx fifos usb: dwc2: gadget: kill requests after disabling ep usb: dwc2: gadget: manage ep0 state in software usb: dwc2: gadget: fix zero length packet transfers usb: dwc2: gadget: dont warn if endpoint is not enabled usb: dwc2: gadget: rename sent_zlp to send_zlp usb: dwc2: gadget: pick smallest acceptable fifo usb: dwc2: gadget: fix fifo allocation leak usb: dwc2: gadget: report disconnection after reset Documentation/devicetree/bindings/usb/dwc2.txt | 4 + drivers/usb/dwc2/core.h| 46 +- drivers/usb/dwc2/gadget.c | 792 - drivers/usb/dwc2/hw.h | 1 + 4 files changed, 556 insertions(+), 287 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board
Sjoerd Simons sjoerd.sim...@collabora.co.uk writes: On Wed, 2015-01-07 at 23:49 +, Jonathan Stone -SISA wrote: On On Wed, 2015-01-07 at 18:37 +, Sjoerd Simons writes wrote: On Wed, 2015-01-07 at 18:37 +, Anand Moon wrote: [...] Only 4 core cpu's are on my board. Also CpuFreq is not working. Can you share some point on this. The defconfig is using the bL switcher, which pairs up big and little cores to make them appear as one core.. So for 8 real cores, you'll get 4 virtual cores. That configuration is appropriate for the 5420, which allegedly has a hardware bug in the cache-coherence between the Cortex-A7 block and the Cortex-A15 block. Newer Exynos 5 SoCs -- 5422/5800, 5620, etc -- don't have that bug. The scheduler should configured to do HMP on all 8 (or 6) cores. I don't have a 5410, but I assume it has the same bug as the 5420. Yes the kernel/scheduler could be configured like that, but exynos_defconfig turns on bL rather then HMP. Now it's not unthinkable to add code/dts properties to select the right/preferred scheduling strategy depending on the board (HMP vs. bL). But proper HMP scheduling is still a work in progress in mainline Yes, HMP scheduling is not yet ready for mainline, which is why the switcher is enabled by default. If you turn the switcher off, you will indeed get all 8 cores, but you may get some rather strange and sub-optimal results with performance since from the scheduler perspective, it will balance tasks across all 8 CPUs as if they were identical. and iirc specifically on the XU3 there are open issue wrt. MCPM and its secure firmware. I've added Kevin to the CC as he's been working on this topic so should know the status a lot better then i do. The broken firmware issues don't affect scheduling directly, but affect the low-power states that are available to the kernel. Since the firwmware doesn't allow proper access to CCI, low-power states that require MCPM are not available, which, among other things, means the clusters can not be powered down. The XU3 kernel supplied by HardKernel shows all 8 cores, and does HMP scheduling across all 8. Yes, that's independant of the dts though as mentioned above. Also there are still opne issues to booting up all cores on an XU3 afaik. See http://www.spinics.net/lists/linux-samsung-soc/msg39523.html I haven't looked closely at the hardkernel tree to see what HMP scheduling patches they're using, but it must be something out of tree. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Abhilash Kesavan kesavan.abhil...@gmail.com writes: Hi Arnd/Olof, On Fri, Jan 9, 2015 at 10:40 AM, Sudeep Holla sudeep.ho...@arm.com wrote: On Thursday 08 January 2015 08:57 PM, Abhilash Kesavan wrote: Hi Sudeep, On Thu, Jan 8, 2015 at 12:15 PM, Sudeep Holla sudeep.ho...@arm.com wrote: Hi Abhilash, [...] What's the status of this patch. It was useful for me on vexpress for some testing. Please feel free to add Tested-by: Sudeep Holla sudeep.ho...@arm.com if this is not yet queued. Thanks for the tested-by. This patch has not been merged yet; I am not quite sure who is supposed to pick this up. So far, most of the CCI patches are merged through arm-soc. Would you be OK picking this up as is or do you want me to re-send this with the RFT tag dropped ? Please resend without the RFT, and collect the Tested-by tags you can add mine: Tested-by: Kevin Hilman khil...@linaro.org Please send to a...@kernel.org where patches targeted for the arm-soc tree are collected. Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] arm64: dts: exynos7: Fix wrong base address of i2c7 bus
Hi Padma,
On Fri, Dec 19, 2014 at 7:03 PM, Padmavathi Venna padm...@samsung.com wrote:
I2C7 base address corrected.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Verified from Exynos7 datasheet. LGTM.
Reviewed-by: Vivek Gautam gautam.vi...@samsung.com
arch/arm64/boot/dts/exynos/exynos7.dtsi |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index db7058a..84a57c8 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -386,9 +386,9 @@
status = disabled;
};
- hsi2c_7: hsi2c@13e1 {
+ hsi2c_7: hsi2c@14e1 {
compatible = samsung,exynos7-hsi2c;
- reg = 0x13e1 0x1000;
+ reg = 0x14e1 0x1000;
interrupts = 0 462 0;
#address-cells = 1;
#size-cells = 0;
--
1.7.4.4
--
Best Regards
Vivek Gautam
Samsung RD Institute, Bangalore
India
--
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Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
Hi Padma,
On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com wrote:
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 73
+++
include/dt-bindings/clock/exynos7-clk.h | 22 -
2 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 954f9a0..cf5e50e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc,
samsung,exynos7-clock-topc,
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC10x0234
+#define MUX_SEL_TOP0_PERIC20x0238
#define MUX_SEL_TOP0_PERIC30x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC10x0634
+#define DIV_TOP0_PERIC20x0638
#define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC10x0A34
+#define ENABLE_SCLK_TOP0_PERIC20x0A38
#define ENABLE_SCLK_TOP0_PERIC30x0A3C
/* List of parent clocks for Muxes in CMU_TOP0 */
@@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC1,
+ MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+ DIV_TOP0_PERIC1,
+ DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC1,
+ ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
@@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[]
__initdata = {
MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+ MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+ MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20,
2),
+
+ MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+ MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20,
2),
MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4,
2),
MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8,
2),
MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12,
2),
MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16,
2),
+ MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20,
2),
};
static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[]
__initdata = {
DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
DIV_TOP03, 20, 6),
+ DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
+ DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
+
+ DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
+ DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
+ DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
};
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+ GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
+ ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
+ ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
+ ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
+ ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, sclk_uart2, dout_sclk_uart2,
@@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[]
__initdata = {
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
GATE(CLK_SCLK_UART0, sclk_uart0, dout_sclk_uart0,
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+ GATE(CLK_SCLK_SPI4, sclk_spi4, dout_sclk_spi4,
+ ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
};
static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata
= {
@@ -520,6 +556,7 @@ static
Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
On Fri, Jan 9, 2015 at 5:18 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
Hi Padma,
On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com wrote:
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 73
+++
include/dt-bindings/clock/exynos7-clk.h | 22 -
2 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 954f9a0..cf5e50e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc,
samsung,exynos7-clock-topc,
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC10x0234
+#define MUX_SEL_TOP0_PERIC20x0238
#define MUX_SEL_TOP0_PERIC30x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC10x0634
+#define DIV_TOP0_PERIC20x0638
#define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC10x0A34
+#define ENABLE_SCLK_TOP0_PERIC20x0A38
#define ENABLE_SCLK_TOP0_PERIC30x0A3C
/* List of parent clocks for Muxes in CMU_TOP0 */
@@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC1,
+ MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+ DIV_TOP0_PERIC1,
+ DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC1,
+ ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
@@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[]
__initdata = {
MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12,
2),
MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20,
2),
+ MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8,
2),
+ MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20,
2),
+
+ MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8,
2),
+ MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20,
2),
MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4,
2),
MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8,
2),
MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12,
2),
MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16,
2),
+ MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20,
2),
};
static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[]
__initdata = {
DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
DIV_TOP03, 20, 6),
+ DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
+ DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
+
+ DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
+ DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
+ DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
};
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+ GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
+ ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
+ ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
+ ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
+ ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, sclk_uart2, dout_sclk_uart2,
@@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[]
__initdata = {
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
GATE(CLK_SCLK_UART0, sclk_uart0, dout_sclk_uart0,
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+ GATE(CLK_SCLK_SPI4, sclk_spi4, dout_sclk_spi4,
+ ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
};
static struct
