Re: [PATCH v2 14/21] ARM: imx6: convert GPC to stacked domains
On 2015-01-10 14:34, Marc Zyngier wrote:
On 2015-01-09 17:40, Stefan Agner wrote:
Hi Marc,
On 2015-01-07 18:42, Marc Zyngier wrote:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 +-
arch/arm/boot/dts/imx6sl.dtsi | 5 +-
arch/arm/boot/dts/imx6sx.dtsi | 5 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 116 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..c16d428 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+ interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
@@ -694,8 +696,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
#interrupt-cells = 3; is missing here.
Ah, nice catch!
I tested the patchset on a Colibri iMX6, but the module stopped booting
at some point. No error, no warn, but it looked like IRQ's are not
working:
[1.623939] platform sound: Driver imx-sgtl5000 requests probe
deferral
[1.630677] backlight supply power not found, using dummy regulator
[1.637067] pwm-backlight backlight: unable to request PWM, trying
legacy API
[1.644271] pwm-backlight backlight: unable to request legacy PWM
[1.650534] platform backlight: Driver pwm-backlight requests probe
deferral
[1.658080] platform 2028000.ssi: Driver fsl-ssi-dai requests probe
deferral
[1.665441] fec 2188000.ethernet eth0: Freescale FEC PHY driver
[Micrel KSZ8041] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
[1.677157] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[freeze]
I figured out that the GPC code did not get called. After digging
through the parsing code, I found the reason: irq_find_host always opted
to intc because this was missing... So, interrupt-cells mandatory for
all interrupt-controller? Maybe we could add a warn somewhere..?
interrupt-cells has a default of 1, I believe. I suppose I could add a
WARN_ON in the xlate/alloc functions...
I think the problem was in of_irq_find_parent (of drivers/of/irq.c). In
that while, interrupt-controller without interrupt-cells just get
ignored.
With that in place, it worked fine:
Tested-by: Stefan Agner ste...@agner.ch
Thanks!
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
Re: [PATCH v2 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
On 2015-01-08 10:41, Thierry Reding wrote:
On Wed, Jan 07, 2015 at 05:42:39PM +, Marc Zyngier wrote:
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
I've updated the patch to reflect the requested changes. See below for
the few contentious points:
[...]
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
Is this allowed? It makes the GIC its own parent. I guess we need it
to
stop a loop from GIC - LIC - GIC, but it doesn't look quite right.
This seems to be the expected construct to override a parent interrupt
controller. Actually, this is already what happens when you have a
single interrupt-controller and a global interrupt-parent property.
[...]
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
Why does this get to have a non-default parent?
The per-cpu timers are using PPIs. As such,. they are not routed
through the LIC, but are wired to the GIC instead.
[...]
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
Why doesn't the Tegra timer get to keep the GIC as parent like for
Tegra114 and Tegra124? Instead I see that the Cortex-A9 TWD timer
gets
to keep the parent instead.
The Tegra timer is using SPI (and can probably be used as a wake-up
source). As such, it is connected to the LIC, not to the GIC.
Per-CPU timers (arch timer for A15 and TWD for A9) are all using PPIs,
and are directly wired to the GIC.
[...]
timer@60005000 {
compatible = nvidia,tegra30-timer, nvidia,tegra20-timer;
reg = 0x60005000 0x400;
Like for Tegra20, the Tegra timer is now switched to the LIC as
parent.
Which, in my understanding, is the right thing to do. Unless I missed
something obvious about this?
Thanks,
M.
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Re: [PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
On 2015-01-08 14:39, Nishanth Menon wrote:
On 17:42-20150107, Marc Zyngier wrote:
[..]
diff --git a/arch/arm/boot/dts/dra7-evm.dts
b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
^^ interrrupt-extended for uart1 here
[..]
diff --git a/arch/arm/boot/dts/dra7.dtsi
b/arch/arm/boot/dts/dra7.dtsi
[...]
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
^^ implies we will have both interrupts and interrupts-extended
properties for uart1 in dra7-evm.dtb
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
does not make it clear as to what the priority will be when both
properties are present.
Yup, good call. I don't think it matters (interrupts inherits the
implicit irq-parent, but consistency is good.
[...]
Also, for 3.19-rc3, Missing the following causing x15 to fail boot.
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c2241c2e5d9d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
- interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW; /* IRQ_SYS_1N */
pinctrl-names = default;
@@ -358,7 +357,7 @@
uart3 {
status = okay;
- interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 69
IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x248;
pinctrl-names = default;
Ah, thanks for the patch, I've folded this in.
Thanks,
M.
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Re: [PATCH v2 07/21] genirq: Add irqchip_set_wake_parent
On 2015-01-08 15:15, Nishanth Menon wrote: On 17:42-20150107, Marc Zyngier wrote: This proves to be usefull with stacked domains, when the current ^^ useful ? minor: +WARNING: 'usefull' may be misspelled - perhaps 'useful'? +#6: +This proves to be usefull with stacked domains, when the current +CHECK: extern prototypes should be avoided in .h files +#23: FILE: include/linux/irq.h:463: ++extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); Consistency trumps whatever checkpatch says, I'm afraid. Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
On 2015-01-08 15:06, Nishanth Menon wrote: On 17:42-20150107, Marc Zyngier wrote: Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked irq domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- Saw a few checkpatch warnings as below: all of them seem minors. @@ -0,0 +1,35 @@ +WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? I'll leave to the Tegra maintainers to update this file it they want to. +#36: +new file mode 100644 +WARNING: line over 80 characters +#169: FILE: drivers/irqchip/irq-tegra.c:129: ++ tegra_ictlr_info-cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER); As a matter of principle, I ignore what checkpatch says about the length of lines of code. I trust my eyes more than the tool. [...] +WARNING: Missing a blank line after declarations +#196: FILE: drivers/irqchip/irq-tegra.c:156: ++ void __iomem *ictlr = tegra_ictlr_info-ictlr_reg_base[i]; ++ writel_relaxed(tegra_ictlr_info-cpu_iep[i], Done. +WARNING: line over 80 characters +#284: FILE: drivers/irqchip/irq-tegra.c:244: ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, parent_args); +CHECK: Please don't use multiple blank lines +#287: FILE: drivers/irqchip/irq-tegra.c:247: ++ ++ +WARNING: Missing a blank line after declarations +#296: FILE: drivers/irqchip/irq-tegra.c:256: ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ` Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
On 2015-01-08 10:13, Thierry Reding wrote: On Wed, Jan 07, 2015 at 05:42:37PM +, Marc Zyngier wrote: Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked irq domain framework fits this pretty well, and allows Nit: s/irq/IRQ/ the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- drivers/irqchip/Makefile| 1 + drivers/irqchip/irq-tegra.c | 335 2 files changed, 336 insertions(+) create mode 100644 drivers/irqchip/irq-tegra.c This matches largely what I have in a local patch (modulo the stacked domains vs. gic_arch_extn). A few comments below. [snip] Thanks for the extensive review. I've implemented all of this, except for the hunk below: diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 9516a32..59f34be 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o obj-$(CONFIG_ARCH_MXS) += irq-mxs.o +obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o Should these be sorted alphabetically? Well, the left side is (up to S3C24xx, and then it all goes down the drain). Do you have a suggestion? Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
On 2015-01-07 17:42, Marc Zyngier wrote: The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have landed in -next, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we already broke it for the OMAP WUGEN block, we might as well do it again for the TI crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die I've updated this branch with the changes requested in this review cycle. I'll give it a test run on Monday with the platforms I have around (mainly Tegra20 and OMAP4/5). Unless anything major comes up, I'll post v3 with a view of getting this into 3.20. Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 06/21] ARM: tegra: remove old LIC support
On 2015-01-08 11:29, Thierry Reding wrote:
On Wed, Jan 07, 2015 at 05:42:41PM +, Marc Zyngier wrote:
[...]
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
[...]
void __init tegra_init_irq(void)
{
- int i;
- void __iomem *distbase;
-
- if (of_find_matching_node(NULL, tegra_ictlr_match))
- goto skip_extn_setup;
-
- tegra_legacy_irq_syscore_init();
-
- distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
- num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f;
-
- if (num_ictlrs ARRAY_SIZE(ictlr_reg_base)) {
- WARN(1, Too many (%d) interrupt controllers found. Maximum is
%d.,
- num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
- num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
- }
-
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- writel(~0, ictlr + ICTLR_CPU_IER_CLR);
- writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
- }
-
- gic_arch_extn.irq_ack = tegra_ack;
- gic_arch_extn.irq_eoi = tegra_eoi;
- gic_arch_extn.irq_mask = tegra_mask;
- gic_arch_extn.irq_unmask = tegra_unmask;
- gic_arch_extn.irq_retrigger = tegra_retrigger;
- gic_arch_extn.irq_set_wake = tegra_set_wake;
- gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+ if (!of_find_matching_node(NULL, tegra_ictlr_match))
+ pr_warn(Outdated DT detected, suspend/resume will NOT work\n);
I'm not very happy about the ABI breakage here, but I also realize
that
we need this change to properly describe the hardware. To make it
more
obvious that people really should update their DTBs, maybe turn this
into a WARN()?
Sure, done.
-skip_extn_setup:
tegra114_gic_cpu_pm_registration();
I'm not intimately familiar with the GIC, but is this really SoC
specific? Doesn't anybody else need this? Comparing to the GIC spec
the
write of 0x1e0 to the GIC_CPU_CTRL register (which I assume
corresponds
to GICC_CTLR in the spec), this simply disables the IRQ and FIQ
bypass
signals for both group 0 and group 1.
This seems to be a Tegra special, at least in mainline. But yes, I'd
very much like to be able to remove this from platform code and make it
part of the GIC driver if we can.
Something for a subsequent patch series, I guess.
Thanks,
M.
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Re: [PATCH v2 13/21] DT: omap4/5: add binding for the wake-up generator
On 2015-01-08 16:52, Nishanth Menon wrote: On 17:42-20150107, Marc Zyngier wrote: Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- .../interrupt-controller/ti,omap4-wugen-mpu| 32 ++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu new file mode 100644 index 000..16149d9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu @@ -0,0 +1,32 @@ +TI OMAP4 Wake-up Generator + +All TI OMAP4/5 (and their derivatives) an interrupt controllerthat controller that +routes interrupts to the GIC, and also serves as a wakeup source. It +is also refered to as WUGEN-MPU, hence the name of the binding. + +Reguired properties: + +- compatible : should contain at least ti,omap4-wugen-mpu Could we also document ti,omap5-wugen-mpu. In addition, if you could make this patch prior to patch #12, it helps the checkpatch at the very least ;) Sure. also saw a few checkpatch warnings: +WARNING: 'refered' may be misspelled - perhaps 'referred'? +#22: FILE: Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu:5: ++is also refered to as WUGEN-MPU, hence the name of the binding. +WARNING: 'explicitely' may be misspelled - perhaps 'explicitly'? +#39: FILE: Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu:22: ++ are explicitely forbiden. +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 3. +- interrupt-parent : a phandle to the GIC these interrupts are routed + to. + +Notes: + +- Because this HW ultimately routes interrupts to the GIC, the + interrupt specifier must be that of the GIC. +- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs I think you mean interrupt controller and not nvidia ictlr here.. :) -ECOPYPASTE... ;-) Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 12/21] ARM: omap: convert wakeupgen to stacked domains
On 2015-01-08 16:44, Nishanth Menon wrote:
On 17:42-20150107, Marc Zyngier wrote:
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like
this:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer
19: 233799 155916 GIC 27 arch_timer
23: 0 0 WUGEN 9 l3-dbg-irq
24: 1 0 WUGEN 10 l3-app-irq
27:282 0 WUGEN 13 omap-dma-engine
44: 0 0 4ae1.gpio 13 DMA
294: 0 0 WUGEN 20 gpmc
297:506 0 WUGEN 56 4807.i2c
298: 0 0 WUGEN 57 48072000.i2c
299: 0 0 WUGEN 61 4806.i2c
300: 0 0 WUGEN 62 4807a000.i2c
301: 8 0 WUGEN 60 4807c000.i2c
308: 2439 0 WUGEN 74 OMAP UART2
312:362 0 WUGEN 83 mmc2
313:502 0 WUGEN 86 mmc0
314: 13 0 WUGEN 94 mmc1
350: 0 0 PRCM pinctrl, pinctrl
406: 35155709 0 GIC 109 ehci_hcd:usb1
407: 0 0 WUGEN 7 palmas
409: 0 0 WUGEN 119 twl6040
410: 0 0 twl6040 5 twl6040_irq_ready
411: 0 0 twl6040 0 twl6040_irq_th
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 95334 902334 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4:479648 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am4372.dtsi | 11 ++-
arch/arm/boot/dts/dra7.dtsi | 12 ++-
arch/arm/boot/dts/dra72x.dtsi | 2 +-
arch/arm/boot/dts/dra74x.dtsi | 2 +-
arch/arm/boot/dts/omap4-duovero.dtsi | 2 -
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +-
arch/arm/boot/dts/omap4-sdp.dts | 8 +-
arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 -
arch/arm/boot/dts/omap4.dtsi | 18 -
arch/arm/boot/dts/omap5-cm-t54.dts| 1 -
arch/arm/boot/dts/omap5-uevm.dts | 2 -
arch/arm/boot/dts/omap5.dtsi | 24 --
arch/arm/mach-omap2/omap-wakeupgen.c | 125
+++---
arch/arm/mach-omap2/omap-wakeupgen.h | 1 -
arch/arm/mach-omap2/omap4-common.c| 1 -
15 files changed, 154 insertions(+), 65 deletions(-)
we may need the following changes as well:
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4cf9f89..69f2313a49d1 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
- interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc90b26a..029badefad3d 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
- interrupt-parent = gic;
interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 662261d6b2ca..2d26bc11bad6 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -333,7 +333,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
- interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c2241c2e5d9d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
