Re: [PATCH v2 04/15] tests/exynos: disable the G2D userptr/blend test
On 16/02/15 13:46, Tobias Jakobi wrote: v2: Move the commit description into the patch itself. Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de --- tests/exynos/exynos_fimg2d_test.c | 8 1 file changed, 8 insertions(+) diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index aa140e5..55d2970 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -788,11 +788,19 @@ int main(int argc, char **argv) getchar(); + /* The blend test uses the userptr functionality of exynos-drm, which * + * is currently not safe to use. If the kernel hasn't been build with * + * exynos-iommu support, then the blend test is going to produce (kernel) * + * memory corruption, eventually leading to a system crash. * + ** + * Disable the test for now, until the kernel code has been sanitized. */ +#if 0 I cannot see a part of libdrm that uses this commenting format. Perhaps use the more common: /* * Some comment */ Cheers, Emil -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 00/18] thermal: exynos: Thermal code rework to use device tree
Hi Kukjin, Eduardo On 01/25/15 06:49, Eduardo Valentin wrote: On Fri, Jan 23, 2015 at 01:09:53PM +0100, Lukasz Majewski wrote: 1. Introduction Following patches aim to clean up the current implementation of the thermal framework on Exynos devices. The main goal was to use a generic code for reading thermal configuration (of-thermal.c). Due to that redundant exynos_thermal_common.[h|c] files were removed. Around 400 lines of code (LOC) were removed directly by this patch, which is around 20% of the Exynos thermal code base. This work should NOT bring any functional changes to Exynos thermal subsystem. 2. Patch-set structure Then the cpu_cooling functionality has been preserved to allow cooling devices by reducing operating frequency. Definition of trip points and cpufreq's cooling properties were moved to device tree. Then the rework of the way in which configuration data is provided to the Exynos thermal subsystem was performed. Now device tree is used for configuration. 3. Dead code removal Thermal support for some SoCs, previously available in the exynos_tmu_data.c file, was removed since, as of (almost) 3.19-rc3, they didn't have TMU bindings. Moreover, support for cpu_cooling devices was preserved only on those SoCs which had available and working cpufreq driver. 4. Testing Test devices: - Exynos4210 - Trats (TMU zone + cpu_cooling) - Exynos4412 - Trats2/Odroid U3 (TMU zone + cpu_cooling) - Exynos5250 - Arndale (TMU zone + cpu_cooling) - Exynos5420 - Arndale-octa (only TMU zones) Unfortunately, I don't posses Exynos5440 for testing. Its functionality has been preserved in the code, but not tested on the hardware. I would be grateful for help in testing. 5. This work apply on the following tree: kernel.org: 'linux-soc-thermal/next' - Eduardo Velentin's tree SHA1: 1813d80874699145f04af6b05ebab0a6419001fb Lukasz Majewski (18): I have applied the following patches to my -fixes branch (for next rc cycle) thermal: exynos: cosmetic: Correct comment format thermal: exynos: Provide thermal_exynos.h file to be included in device tree files thermal: exynos: Modify exynos thermal code to use device tree for cpu cooling configuration cpufreq: exynos: Use device tree to determine if cpufreq cooling should be registered dts: Documentation: Extending documentation entry for exynos-thermal dts: Documentation: Update exynos-thermal.txt example for Exynos5440 thermal: samsung: core: Exynos TMU rework to use device tree for configuration thermal: exynos: Remove exynos_thermal_common.[c|h] files thermal: exynos: Remove exynos_tmu_data.c file The patches below should go via platform tree: arm: dts: trats: Enable TMU on the Exynos4210 trats device arm: dts: odroid: Add LDO10 regulator node necessary for TMU on Odroid arm: dts: odroid: Enable TMU at Exynos4412 based Odroid U3 device arm: dts: Adding CPU cooling binding for Exynos SoCs thermal: exynos: dts: Add default definition of the TMU sensor parameter thermal: dts: Default trip points definition for Exynos5420 SoCs thermal: exynos: dts: Define default thermal-zones for Exynos4 thermal: dts: exynos: Trip points and sensor configuration data for Exynos5440 thermal: exynos: dts: Provide device tree bindings identical to the one in exynos_tmu_data.c I've applied above patches with small subject changes. BTW unfortunately, since missing the include/dt-bindings/thermal/thermal_exynos.h in my tree, I couldn't merge it into for-next yet. As of this writing: (Kernel 4.0-rc1) the include/dt-bindings/thermal/thermal_exynos.h file is in the kernel tree. Kukjin, could you add missing DTS files and send this to upstream. Thanks in advance. Can you please provide a topic branch for it? If not, this cannot be handled in arm-soc tree in this time, I think. - Kukjin Thanks a lot. .../devicetree/bindings/thermal/exynos-thermal.txt | 17 + arch/arm/boot/dts/exynos3250.dtsi | 2 + arch/arm/boot/dts/exynos4-cpu-thermal.dtsi | 52 +++ arch/arm/boot/dts/exynos4.dtsi | 4 + arch/arm/boot/dts/exynos4210-trats.dts | 19 + arch/arm/boot/dts/exynos4210.dtsi | 30 +- arch/arm/boot/dts/exynos4212.dtsi | 5 +- arch/arm/boot/dts/exynos4412-odroid-common.dtsi| 27 ++ arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi | 24 ++ arch/arm/boot/dts/exynos4412-trats2.dts| 15 + arch/arm/boot/dts/exynos4412.dtsi | 5 +- arch/arm/boot/dts/exynos4x12.dtsi | 1 + arch/arm/boot/dts/exynos5250.dtsi | 29 +- arch/arm/boot/dts/exynos5420-trip-points.dtsi | 35 ++ arch/arm/boot/dts/exynos5420.dtsi | 28 ++
RE: [PATCH v6 00/18] thermal: exynos: Thermal code rework to use device tree
Lukasz Majewski wrote: Hi Kukjin, Eduardo Hi, On 01/25/15 06:49, Eduardo Valentin wrote: On Fri, Jan 23, 2015 at 01:09:53PM +0100, Lukasz Majewski wrote: 1. Introduction Following patches aim to clean up the current implementation of the thermal framework on Exynos devices. The main goal was to use a generic code for reading thermal configuration (of-thermal.c). Due to that redundant exynos_thermal_common.[h|c] files were removed. Around 400 lines of code (LOC) were removed directly by this patch, which is around 20% of the Exynos thermal code base. This work should NOT bring any functional changes to Exynos thermal subsystem. 2. Patch-set structure Then the cpu_cooling functionality has been preserved to allow cooling devices by reducing operating frequency. Definition of trip points and cpufreq's cooling properties were moved to device tree. Then the rework of the way in which configuration data is provided to the Exynos thermal subsystem was performed. Now device tree is used for configuration. 3. Dead code removal Thermal support for some SoCs, previously available in the exynos_tmu_data.c file, was removed since, as of (almost) 3.19-rc3, they didn't have TMU bindings. Moreover, support for cpu_cooling devices was preserved only on those SoCs which had available and working cpufreq driver. 4. Testing Test devices: - Exynos4210 - Trats (TMU zone + cpu_cooling) - Exynos4412 - Trats2/Odroid U3 (TMU zone + cpu_cooling) - Exynos5250 - Arndale (TMU zone + cpu_cooling) - Exynos5420 - Arndale-octa (only TMU zones) Unfortunately, I don't posses Exynos5440 for testing. Its functionality has been preserved in the code, but not tested on the hardware. I would be grateful for help in testing. 5. This work apply on the following tree: kernel.org: 'linux-soc-thermal/next' - Eduardo Velentin's tree SHA1: 1813d80874699145f04af6b05ebab0a6419001fb Lukasz Majewski (18): I have applied the following patches to my -fixes branch (for next rc cycle) thermal: exynos: cosmetic: Correct comment format thermal: exynos: Provide thermal_exynos.h file to be included in device tree files thermal: exynos: Modify exynos thermal code to use device tree for cpu cooling configuration cpufreq: exynos: Use device tree to determine if cpufreq cooling should be registered dts: Documentation: Extending documentation entry for exynos-thermal dts: Documentation: Update exynos-thermal.txt example for Exynos5440 thermal: samsung: core: Exynos TMU rework to use device tree for configuration thermal: exynos: Remove exynos_thermal_common.[c|h] files thermal: exynos: Remove exynos_tmu_data.c file The patches below should go via platform tree: arm: dts: trats: Enable TMU on the Exynos4210 trats device arm: dts: odroid: Add LDO10 regulator node necessary for TMU on Odroid arm: dts: odroid: Enable TMU at Exynos4412 based Odroid U3 device arm: dts: Adding CPU cooling binding for Exynos SoCs thermal: exynos: dts: Add default definition of the TMU sensor parameter thermal: dts: Default trip points definition for Exynos5420 SoCs thermal: exynos: dts: Define default thermal-zones for Exynos4 thermal: dts: exynos: Trip points and sensor configuration data for Exynos5440 thermal: exynos: dts: Provide device tree bindings identical to the one in exynos_tmu_data.c I've applied above patches with small subject changes. BTW unfortunately, since missing the include/dt-bindings/thermal/thermal_exynos.h in my tree, I couldn't merge it into for-next yet. As of this writing: (Kernel 4.0-rc1) the include/dt-bindings/thermal/thermal_exynos.h file is in the kernel tree. I know. Kukjin, could you add missing DTS files and send this to upstream. Unfortunately, I couldn't take the DT changes in Samsung tree at that time because of missing header file and it causes build error. Now I can pick them into Samsung tree but I'm not sure it can be sent to upstream during this -rc... Eduardo, Lukasz, Do you guys think the DT changes are really fixes for 4.0? Thanks in advance. Can you please provide a topic branch for it? If not, this cannot be handled in arm-soc tree in this time, I think. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 12/15] exynos: add fimg2d header to common includes
On 16/02/15 13:46, Tobias Jakobi wrote: The reason for this change is to let userspace use the header. Currently 'make install' does not install it. Hi Tobias, Afaict that this was done intentionally. I believe the Samsung guys got this out only to fulfil the no drm(render) driver without open userspace policy. Although it's nice to see actual user(s) (outside of libdrm) perhaps the header could be cleaned up (#define TRUE 0, #define FALSE -1) a bit before that ? Either way it's up-to the Samsung/Exynos people to make the call. Cheers Emil -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [v2] libdrm: improvements to userspace exynos component
On 16/02/15 13:46, Tobias Jakobi wrote: Hello, here are some miscellaneous improvements (small features, bugfixes, spelling fixes, etc.) for the exynos component of libdrm. The general idea is to let userspace use the G2D engine functionality more efficiently. If someone is interested in an application that actually makes use of this, the RetroArch frontend has a custom video backend: https://github.com/libretro/RetroArch/blob/master/gfx/drivers/exynos_gfx.c Please review and let me know what I can improve. v2: - Mention value of G2D scaling normalization factor (02/15). - Moved patch (04/15) description from commit message to source itself, like suggested by Joonyoung Shim. Hi Tobias, Imho these are some nice cleanups. I believe that the Samsung/Exynos people need to comment on the device specific ones, but I've checked 2-4, 6, 8, 10, 13-15 and they are quite ok (baring a trivial comment) Reviewed-by: Emil Velikov emil.l.veli...@gmail.com Thanks Emil P.S. Please don't recent the entire series, unless needed. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 08/15] exynos: introduce g2d_add_base_addr helper function
On 16/02/15 13:46, Tobias Jakobi wrote:
In almost all functions the base address register is written, so it
makes sense to have a helper function for this.
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
exynos/exynos_fimg2d.c | 87
+++---
1 file changed, 33 insertions(+), 54 deletions(-)
diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c
index b79081e..c08974a 100644
--- a/exynos/exynos_fimg2d.c
+++ b/exynos/exynos_fimg2d.c
@@ -41,6 +41,11 @@
#define MIN(a, b)((a) (b) ? (a) : (b))
+enum g2d_base_addr_reg {
+ g2d_dst = 0,
+ g2d_src
+};
+
static unsigned int g2d_get_scaling(unsigned int src, unsigned int dst)
{
/* The G2D hw scaling factor is a normalized inverse of the scaling
factor. *
@@ -132,6 +137,25 @@ static int g2d_add_cmd(struct g2d_context *ctx, unsigned
long cmd,
}
/*
+ * g2d_add_base_addr - helper function to set dst/src base address register.
+ *
+ * @ctx: a pointer to g2d_context structure.
+ * @img: a pointer to the dst/src g2d_image structure.
+ * @reg: the register that should be set.
+ */
+static void g2d_add_base_addr(struct g2d_context *ctx, struct g2d_image *img,
+ enum g2d_base_addr_reg reg)
+{
+ const unsigned long cmd = (reg == g2d_dst) ? DST_BASE_ADDR_REG :
SRC_BASE_ADDR_REG;
+
Can we wrap this to 80 columns please ?
-Emil
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Re: [PATCH v2 06/15] tests/exynos: introduce wait_for_user_input
On 16/02/15 13:46, Tobias Jakobi wrote:
Currently getchar() is used to pause execution after each test.
The user isn't informed if one is supposed to do anything for
the tests to continue, so print a simple message to make this
more clear.
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
tests/exynos/exynos_fimg2d_test.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/tests/exynos/exynos_fimg2d_test.c
b/tests/exynos/exynos_fimg2d_test.c
index 55d2970..446a6c6 100644
--- a/tests/exynos/exynos_fimg2d_test.c
+++ b/tests/exynos/exynos_fimg2d_test.c
@@ -237,6 +237,18 @@ void *create_checkerboard_pattern(unsigned int
num_tiles_x,
return buf;
}
+static void wait_for_user_input(int last)
+{
+ printf(press ENTER to );
+
+ if (last)
+ printf(exit test application\n);
+ else
+ printf(skip to next test\n);
+
If interested you can compact this as
printf(press ENTER to %s\n, last ? exit test application :
skip to next test);
Cheers
Emil
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Re: [PATCH v2 06/15] tests/exynos: introduce wait_for_user_input
On Mon, Feb 23, 2015 at 11:22:09AM +, Emil Velikov wrote:
On 16/02/15 13:46, Tobias Jakobi wrote:
Currently getchar() is used to pause execution after each test.
The user isn't informed if one is supposed to do anything for
the tests to continue, so print a simple message to make this
more clear.
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
tests/exynos/exynos_fimg2d_test.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/tests/exynos/exynos_fimg2d_test.c
b/tests/exynos/exynos_fimg2d_test.c
index 55d2970..446a6c6 100644
--- a/tests/exynos/exynos_fimg2d_test.c
+++ b/tests/exynos/exynos_fimg2d_test.c
@@ -237,6 +237,18 @@ void *create_checkerboard_pattern(unsigned int
num_tiles_x,
return buf;
}
+static void wait_for_user_input(int last)
+{
+ printf(press ENTER to );
+
+ if (last)
+ printf(exit test application\n);
+ else
+ printf(skip to next test\n);
+
If interested you can compact this as
printf(press ENTER to %s\n, last ? exit test application :
skip to next test);
We have this and a ton of other neat helpers in igt. As I've probably said
countless times on irc and at conferences if someone bothers to make the
core of igt i915-agnostic (just needs changes in the function to open the
drm dev mostly) I'd love to see igt converted into a generic drm
testsuite.
And similar to piglit I think it makes more sense to have that outside of
any userspace components we ship to users, i.e. not in libdrm.
But I really can't justify doing this work to my dear employer ;-)
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [alsa-devel] [PATCH] ASoC: max98088: Add master clock handling
Hi, Am 23.02.2015 um 09:29 schrieb Javier Martinez Canillas: On 02/20/2015 04:27 AM, Tushar Behera wrote: On 02/20/2015 12:48 AM, Andreas Färber wrote: If master clock is provided through device tree, then update the master clock frequency during set_sysclk. Cc: Tushar Behera tushar.beh...@linaro.org Signed-off-by: Andreas Färber afaer...@suse.de --- sound/soc/codecs/max98088.c | 24 1 file changed, 24 insertions(+) Looks good. Acked-by: Tushar Behera trbli...@gmail.com Looks good to me as well. Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Thanks guys. One self-doubt: Is there any downside to returning -EPROBE_DEFER after regcache_mark_dirty(max98088-regmap)? I.e., should I move the last hunk some lines up to be the very first thing executed? Cheers, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Jennifer Guild, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] drivers: spi: fix compiler warning in spi-s3c64xx
On Mon, Feb 23, 2015 at 12:30:46PM +, Andre Przywara wrote: The Exynos 7 arm64 support now allows the S3C64xx SPI driver to be compiled into an ARM64 kernel, so the cast from the [rt]x_dmach int variable to a void* in this driver now triggers a warning. Add a long cast to silence the compiler. Applied, thanks. signature.asc Description: Digital signature
[PATCH] drivers: spi: fix compiler warning in spi-s3c64xx
The Exynos 7 arm64 support now allows the S3C64xx SPI driver to be
compiled into an ARM64 kernel, so the cast from the [rt]x_dmach int
variable to a void* in this driver now triggers a warning.
Add a long cast to silence the compiler.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
Hi,
this is only compile-tested for arm and arm64. Could someone with
the hardware please confirm that it still works?
Cheers,
Andre.
drivers/spi/spi-s3c64xx.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 9231c34..b1c6731 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -324,7 +324,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master
*spi)
/* Acquire DMA channels */
sdd-rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
- (void *)sdd-rx_dma.dmach, dev, rx);
+ (void *)(long)sdd-rx_dma.dmach, dev, rx);
if (!sdd-rx_dma.ch) {
dev_err(dev, Failed to get RX DMA channel\n);
ret = -EBUSY;
@@ -333,7 +333,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master
*spi)
spi-dma_rx = sdd-rx_dma.ch;
sdd-tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
- (void *)sdd-tx_dma.dmach, dev, tx);
+ (void *)(long)sdd-tx_dma.dmach, dev, tx);
if (!sdd-tx_dma.ch) {
dev_err(dev, Failed to get TX DMA channel\n);
ret = -EBUSY;
--
1.7.9.5
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Re: [PATCH v6 00/18] thermal: exynos: Thermal code rework to use device tree
Hi Kukjin, Lukasz Majewski wrote: Hi Kukjin, Eduardo Hi, On 01/25/15 06:49, Eduardo Valentin wrote: On Fri, Jan 23, 2015 at 01:09:53PM +0100, Lukasz Majewski wrote: 1. Introduction Following patches aim to clean up the current implementation of the thermal framework on Exynos devices. The main goal was to use a generic code for reading thermal configuration (of-thermal.c). Due to that redundant exynos_thermal_common.[h|c] files were removed. Around 400 lines of code (LOC) were removed directly by this patch, which is around 20% of the Exynos thermal code base. This work should NOT bring any functional changes to Exynos thermal subsystem. 2. Patch-set structure Then the cpu_cooling functionality has been preserved to allow cooling devices by reducing operating frequency. Definition of trip points and cpufreq's cooling properties were moved to device tree. Then the rework of the way in which configuration data is provided to the Exynos thermal subsystem was performed. Now device tree is used for configuration. 3. Dead code removal Thermal support for some SoCs, previously available in the exynos_tmu_data.c file, was removed since, as of (almost) 3.19-rc3, they didn't have TMU bindings. Moreover, support for cpu_cooling devices was preserved only on those SoCs which had available and working cpufreq driver. 4. Testing Test devices: - Exynos4210 - Trats (TMU zone + cpu_cooling) - Exynos4412 - Trats2/Odroid U3 (TMU zone + cpu_cooling) - Exynos5250 - Arndale (TMU zone + cpu_cooling) - Exynos5420 - Arndale-octa (only TMU zones) Unfortunately, I don't posses Exynos5440 for testing. Its functionality has been preserved in the code, but not tested on the hardware. I would be grateful for help in testing. 5. This work apply on the following tree: kernel.org: 'linux-soc-thermal/next' - Eduardo Velentin's tree SHA1: 1813d80874699145f04af6b05ebab0a6419001fb Lukasz Majewski (18): I have applied the following patches to my -fixes branch (for next rc cycle) thermal: exynos: cosmetic: Correct comment format thermal: exynos: Provide thermal_exynos.h file to be included in device tree files thermal: exynos: Modify exynos thermal code to use device tree for cpu cooling configuration cpufreq: exynos: Use device tree to determine if cpufreq cooling should be registered dts: Documentation: Extending documentation entry for exynos-thermal dts: Documentation: Update exynos-thermal.txt example for Exynos5440 thermal: samsung: core: Exynos TMU rework to use device tree for configuration thermal: exynos: Remove exynos_thermal_common.[c|h] files thermal: exynos: Remove exynos_tmu_data.c file The patches below should go via platform tree: arm: dts: trats: Enable TMU on the Exynos4210 trats device arm: dts: odroid: Add LDO10 regulator node necessary for TMU on Odroid arm: dts: odroid: Enable TMU at Exynos4412 based Odroid U3 device arm: dts: Adding CPU cooling binding for Exynos SoCs thermal: exynos: dts: Add default definition of the TMU sensor parameter thermal: dts: Default trip points definition for Exynos5420 SoCs thermal: exynos: dts: Define default thermal-zones for Exynos4 thermal: dts: exynos: Trip points and sensor configuration data for Exynos5440 thermal: exynos: dts: Provide device tree bindings identical to the one in exynos_tmu_data.c I've applied above patches with small subject changes. BTW unfortunately, since missing the include/dt-bindings/thermal/thermal_exynos.h in my tree, I couldn't merge it into for-next yet. As of this writing: (Kernel 4.0-rc1) the include/dt-bindings/thermal/thermal_exynos.h file is in the kernel tree. I know. Kukjin, could you add missing DTS files and send this to upstream. Unfortunately, I couldn't take the DT changes in Samsung tree at that time because of missing header file and it causes build error. The header problem was due to splitting this patch set to -samsung and -thermal trees. The intention was to merge it all at once, but unfortunately it was split. Now I can pick them into Samsung tree but I'm not sure it can be sent to upstream during this -rc... Eduardo, Lukasz, Do you guys think the DT changes are really fixes for 4.0? The thermal Samsung rework has been merged, so without this DTS files we have regression, since boards like Trats2, Odroid will not have thermal support in 4.0 final release. Additionally we are now at -rc1 state, so some extra time is left to handle unexpected situation (although there shouldn't be any). Thanks in advance. Can you please provide a topic branch for it? If not, this cannot be handled in
Re: [PATCH] [media] s5p-jpeg: Clear JPEG_CODEC_ON bits in sw reset function
Hi, On 17/12/14 07:22, Tony K Nadackal wrote: Bits EXYNOS4_DEC_MODE and EXYNOS4_ENC_MODE do not get cleared on software reset. These bits need to be cleared explicitly. Signed-off-by: Tony K Nadackal tony...@samsung.com --- This patch is created and tested on top of linux-next-20141210. It can be cleanly applied on media-next and kgene/for-next. drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c b/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c index ab6d6f43..e53f13a 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c +++ b/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c @@ -21,6 +21,10 @@ void exynos4_jpeg_sw_reset(void __iomem *base) unsigned int reg; reg = readl(base + EXYNOS4_JPEG_CNTL_REG); + writel(reg ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), + base + EXYNOS4_JPEG_CNTL_REG); + + reg = readl(base + EXYNOS4_JPEG_CNTL_REG); Do we really need the second read? Wouldn't it also work as below ? reg = readl(base + EXYNOS4_JPEG_CNTL_REG); + reg = ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE); + writel(reg, base + EXYNOS4_JPEG_CNTL_REG); ? writel(reg ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); udelay(100); -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] [media] s5p-jpeg: Fix crash in jpeg isr due to multiple interrupts.
On 17/12/14 07:25, Tony K Nadackal wrote: In case of corrupt images, multiple interrupts may occur due to different error scenarios. Since we are removing the src and dest buffers in the first interrupt itself, crash occurs in the second error interrupts. Disable the global interrupt before we start processing the interrupt avoid the crash. Disable System interrupt in isr to avoid the crash below. Rather than disabling all interrupts, is there no way to check the interrupt reason from some status register and decide whether we return the buffers or just ignore the interrupt ? -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH] ARM: EXYNOS: Fix failed second suspend on Exynos4
2015-02-23 17:25 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: Hi, On Wednesday, February 18, 2015 11:45:25 AM Krzysztof Kozlowski wrote: On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in 56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller) the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off) Cc: sta...@vger.kernel.org It turned out that this patch is also needed to fix cpuidle AFTR mode hang on Trats2. Tested-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Thanks for testing. Dear Kukjin, Could you pick it up for this RC cycle? This patch fixes fatal suspend and cpuidle failures on Exynos4 based boards on current mainline. Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/2] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 129 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 76173ca..1d21f02 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -152,6 +152,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -264,6 +267,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 9bb1b0b..72fa2d1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -196,6 +196,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -232,6 +235,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9dc2e97..d11a6ab 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -327,6 +327,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -769,6 +770,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 9e9dfdf..c623d39 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -166,16 +166,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -186,9 +185,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 52e2b1a..69ede2c 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
[PATCH v5 2/2] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b2113..2d6356d 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -29,10 +29,27 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- #interrupt-cells: must be identical to the that of the parent interrupt
+ controller.
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v5 0/2] irqchip: Move Exynos PM to use stacked domains
This series is extracted from [4], which is trying to remove all traces of gic_arch_extn from the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially. This series addresses Exynos by converting its PM support to a stacked domain on top of the standard GIC. Based on 4.0-rc1. * From v4: [4] - Extracted from the full series - Rebased on 4.0-rc1 * From v3 [3]: - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4] - Fixed more iMX6 DTs (Stephan) - Fixed Exynos4/5 DTs * From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan * From v1 [1]: - Rebased on 3.19-rc3 - Fixed a number of additional platforms - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth [4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html [3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html [2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html Marc Zyngier (2): ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding .../devicetree/bindings/arm/samsung/pmu.txt| 17 +++ arch/arm/boot/dts/exynos4.dtsi | 4 + arch/arm/boot/dts/exynos5250.dtsi | 4 + arch/arm/boot/dts/exynos5420.dtsi | 4 + arch/arm/mach-exynos/exynos.c | 14 +-- arch/arm/mach-exynos/suspend.c | 122 +++-- 6 files changed, 146 insertions(+), 19 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/8] hwmon: pwm-fan: Read PWM FAN configuration from device tree
On Mon, Feb 23, 2015 at 05:51:22PM +0100, Lukasz Majewski wrote:
Hi Guenter,
On Mon, Feb 23, 2015 at 05:13:36PM +0100, Lukasz Majewski wrote:
Hi Guenter,
[ ... ]
If devicetree is not configured, of_property_count_elems_of_size
returns -ENOSYS, which is returned, causing the driver to fail
loading.
Has of_property_count_elems_of_size() returns -ENOSYS?
Maybe something has changed, but in my linux-vanila (3.19-rc4)
at ./drivers/of/base.c it returns -EINVAL, -ENODATA or number of
elements.
Have I missed something?
Hi Lukasz,
Yes, you have. Check include/linux/of.h, line 484, in latest mainline.
Ok. Now I got it.
The above situation shouldn't happen if I put of_find_property() check
on the very beginning of this function (it returns NULL when DT support
is not compiled).
Correct.
The function would look as follows:
int
pwm_fan_of_get_cooling_data(struct device *dev, struct pwm_fan_ctx
*ctx)
{
struct device_node *np = dev-of_node;
int num, i, ret;
if (!of_find_property(np, cooling-levels, NULL))
return 0;
ret = of_property_count_u32_elems(np, cooling-levels);
if (ret = 0) {
dev_err(dev, Wrong data!\n);
return ret;
This should probably be something like
return ret ? : -EINVAL;
or ret == 0 is not an error, and you should not display an error message
in that case.
Thanks,
Guenter
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Re: [PATCH v4 7/8] hwmon: pwm-fan: Read PWM FAN configuration from device tree
On Mon, Feb 23, 2015 at 05:13:36PM +0100, Lukasz Majewski wrote: Hi Guenter, [ ... ] If devicetree is not configured, of_property_count_elems_of_size returns -ENOSYS, which is returned, causing the driver to fail loading. Has of_property_count_elems_of_size() returns -ENOSYS? Maybe something has changed, but in my linux-vanila (3.19-rc4) at ./drivers/of/base.c it returns -EINVAL, -ENODATA or number of elements. Have I missed something? Hi Lukasz, Yes, you have. Check include/linux/of.h, line 484, in latest mainline. Guenter -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/8] hwmon: pwm-fan: Read PWM FAN configuration from device tree
Hi Guenter,
On 02/18/2015 02:07 AM, Lukasz Majewski wrote:
This patch provides code for reading PWM FAN configuration data via
device tree. The pwm-fan can work with full speed when configuration
is not provided. However, errors are propagated when wrong DT
bindings are found.
Additionally the struct pwm_fan_ctx has been extended.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
Changes for v2:
- Rename pwm_fan_max_states to pwm_fan_cooling_levels
- Moving pwm_fan_of_get_cooling_data() call after setting end
enabling PWM FAN
- pwm_fan_of_get_cooling_data() now can fail - preserving old
behaviour
- Remove unnecessary dev_err() call
Changes for v3:
- Patch's headline has been reedited
- pwm_fan_of_get_cooling_data() return code is now being checked.
- of_property_count_elems_of_size() is now used instead
of_find_property()
- More verbose patch description added
Changes for v4:
- dev_err() has been removed from pwm_fan_of_get_cooling_data()
- Returning -EINVAL when cooling-levels are defined in DT, but
doesn't have the value
---
drivers/hwmon/pwm-fan.c | 52
- 1 file changed,
51 insertions(+), 1 deletion(-)
diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c
index bd42d39..82cd06a 100644
--- a/drivers/hwmon/pwm-fan.c
+++ b/drivers/hwmon/pwm-fan.c
@@ -30,7 +30,10 @@
struct pwm_fan_ctx {
struct mutex lock;
struct pwm_device *pwm;
- unsigned char pwm_value;
+ unsigned int pwm_value;
+ unsigned int pwm_fan_state;
+ unsigned int pwm_fan_max_state;
+ unsigned int *pwm_fan_cooling_levels;
};
static int __set_pwm(struct pwm_fan_ctx *ctx, unsigned long pwm)
@@ -100,6 +103,48 @@ static struct attribute *pwm_fan_attrs[] = {
ATTRIBUTE_GROUPS(pwm_fan);
+int pwm_fan_of_get_cooling_data(struct device *dev, struct
pwm_fan_ctx *ctx) +{
+ struct device_node *np = dev-of_node;
+ int num, i, ret;
+
+ ret = of_property_count_elems_of_size(np, cooling-levels,
+ sizeof(u32));
+
+ if (ret == -EINVAL)
+ return 0;
The function returns -EINVAL if there is no such property,
but also if prop-length % elem_size != 0. The latter _would_
be an error.
Overall I don't entirely understand why you do not call
of_find_property first. If that returns NULL, you would know for sure
that the property does not exist, and you would not have to second
guess the returned error from of_property_count_elems_of_size.
For sake of readability I will at v5 first check of_find_property() and
if it is correct, then I will call of_property_count_u32_elems().
On a side note, there is of_property_count_u32_elems() to count
properties of size u32.
+
+ if (ret = 0) {
+ dev_err(dev, Wrong data!\n);
+ return ret ? ret : -EINVAL;
+ }
If devicetree is not configured, of_property_count_elems_of_size
returns -ENOSYS, which is returned, causing the driver to fail
loading.
Has of_property_count_elems_of_size() returns -ENOSYS?
Maybe something has changed, but in my linux-vanila (3.19-rc4)
at ./drivers/of/base.c it returns -EINVAL, -ENODATA or number of
elements.
Have I missed something?
+
+ num = ret;
+ ctx-pwm_fan_cooling_levels = devm_kzalloc(dev, num *
sizeof(u32),
+ GFP_KERNEL);
+ if (!ctx-pwm_fan_cooling_levels)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(np, cooling-levels,
+
ctx-pwm_fan_cooling_levels, num);
+ if (ret) {
+ dev_err(dev, Property 'cooling-levels' cannot be
read!\n);
+ return ret;
+ }
+
+ for (i = 0; i num; i++) {
+ if (ctx-pwm_fan_cooling_levels[i] MAX_PWM) {
+ dev_err(dev, PWM fan state[%d]:%d
%d\n, i,
+ ctx-pwm_fan_cooling_levels[i],
MAX_PWM);
+ return -EINVAL;
+ }
+ }
+
+ ctx-pwm_fan_max_state = num - 1;
+
+ return 0;
+}
+
static int pwm_fan_probe(struct platform_device *pdev)
{
struct device *hwmon;
@@ -145,6 +190,11 @@ static int pwm_fan_probe(struct
platform_device *pdev) pwm_disable(ctx-pwm);
return PTR_ERR(hwmon);
}
+
+ ret = pwm_fan_of_get_cooling_data(pdev-dev, ctx);
+ if (ret)
+ return ret;
I think that here is the confusing part. Please compare this patch with
the following one.
Here we configure ctx struct via DT. If of_property_count_u32_elems()
returns -EINVAL, then we consider that cooling-levels wasn't defined
in DT and return with 0. Other error codes are considered as errors
and probe return error code.
+
return 0;
}
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [PATCH 1/6] ASoC: max98088: Document DT bindings
Hello Sylwester, On 02/20/2015 01:12 PM, Sylwester Nawrocki wrote: On 20/02/15 01:36, Andreas Färber wrote: So it seems the mclk is not always set up properly by the kernel, relying on firmware. Who's in charge of setting that clock up? Right, it seems audio is only working due the firmware doing some previous setup. Probably it works on every boot if you have sound init as a part of the u-boot boot commands? Indeed it does, 24 MHz without the reparenting patch, and sound working. You can have parent of the CLKOUT clock set by the clk core if it is specified in device tree in the PMU (the clkout clock supplier) device node. Similarly as we did for the Odroix U3: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/exynos4412-odroid-common.dtsi#n39 Relying on the clk_set_rate() to set the parent clock is not optimal IMO. Presumably you need to set select stable parent clock for clkout like XXTI. But I'm not very familiar with exyno5250 and that might be something different. Thanks a lot for your suggestion. I'll drop Tushar's patch to allow clkout to be reparent during set_rate then and change his DTS patch to set a default parent for CLKOUT using assigned-clock-parents. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH] ARM: EXYNOS: Fix failed second suspend on Exynos4
Hi, On Wednesday, February 18, 2015 11:45:25 AM Krzysztof Kozlowski wrote: On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in 56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller) the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off) Cc: sta...@vger.kernel.org It turned out that this patch is also needed to fix cpuidle AFTR mode hang on Trats2. Tested-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/8] hwmon: pwm-fan: Read PWM FAN configuration from device tree
Hi Guenter,
On Mon, Feb 23, 2015 at 05:13:36PM +0100, Lukasz Majewski wrote:
Hi Guenter,
[ ... ]
If devicetree is not configured, of_property_count_elems_of_size
returns -ENOSYS, which is returned, causing the driver to fail
loading.
Has of_property_count_elems_of_size() returns -ENOSYS?
Maybe something has changed, but in my linux-vanila (3.19-rc4)
at ./drivers/of/base.c it returns -EINVAL, -ENODATA or number of
elements.
Have I missed something?
Hi Lukasz,
Yes, you have. Check include/linux/of.h, line 484, in latest mainline.
Ok. Now I got it.
The above situation shouldn't happen if I put of_find_property() check
on the very beginning of this function (it returns NULL when DT support
is not compiled).
The function would look as follows:
int
pwm_fan_of_get_cooling_data(struct device *dev, struct pwm_fan_ctx
*ctx)
{
struct device_node *np = dev-of_node;
int num, i, ret;
if (!of_find_property(np, cooling-levels, NULL))
return 0;
ret = of_property_count_u32_elems(np, cooling-levels);
if (ret = 0) {
dev_err(dev, Wrong data!\n);
return ret;
}
num = ret;
ctx-pwm_fan_cooling_levels = devm_kzalloc(dev, num *
sizeof(u32), GFP_KERNEL);
if (!ctx-pwm_fan_cooling_levels)
return -ENOMEM;
ret = of_property_read_u32_array(np, cooling-levels,
ctx-pwm_fan_cooling_levels,
num);
if (ret) {
dev_err(dev, Property 'cooling-levels' cannot be
read!\n);
return ret;
}
for (i = 0; i num; i++) {
if (ctx-pwm_fan_cooling_levels[i] MAX_PWM) {
dev_err(dev, PWM fan state[%d]:%d %d\n, i,
ctx-pwm_fan_cooling_levels[i],
MAX_PWM);
return -EINVAL;
}
}
ctx-pwm_fan_max_state = num - 1;
return 0;
}
Guenter
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
Hello Chanwoo! Chanwoo Choi wrote: As you thought, when maintaining lower clock of memory bus frequency, some issue related to multimedia feature will happen. Separately, We have to check the miminum lower clock for working of multimedia feature. and then multimedia or other IP have to request it to DVFS driver (memory busfreq driver). But, latest mainline kernel currently has not some way to inform minimum clock to DVFS driver. So, If you check the miminum clock for hdmi, I'll use this clock as minumu frequency of dvfs table. Thanks, Chanwoo Choi First I have to apologize. I didn't check carefully. Actually it's not the HDMI subsystem which seems to hang during my test, but the G2D subsystem. Here's a snippet of the kernel log with drm.debug=0xff: [ 1157.911264] [drm:drm_framebuffer_reference] ee144e00: FB ID: 27 (2) [ 1157.911271] [drm:drm_framebuffer_unreference] ee37fb80: FB ID: 25 (2) [ 1157.911277] [drm:drm_framebuffer_unreference] ee144e00: FB ID: 27 (3) [ 1157.911315] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_GET_VER [ 1158.434439] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_SET_CMDLIST [ 1158.434536] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_EXEC [ 1158.437484] [drm:drm_vm_close_locked] 0xaf84,0x0014 [ 1158.437507] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE [ 1158.437524] [drm:exynos_drm_gem_destroy] handle count = 0 [ 1158.437532] [drm:lowlevel_buffer_deallocate] dma_addr(0x2050), size(0x14) [ 1158.437810] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_GEM_CREATE [ 1158.437819] [drm:exynos_drm_init_buf] desired size = 0x256000 [ 1158.437851] [drm:exynos_drm_gem_init] created file object = 0xe97c8d00 [ 1158.445506] [drm:lowlevel_buffer_allocate] dma_addr(0x2140), size(0x256000) [ 1158.445535] [drm:exynos_drm_gem_handle_create] gem handle = 0x1 [ 1158.445556] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, DRM_IOCTL_MODE_MAP_DUMB [ 1158.445570] [drm:exynos_drm_gem_dumb_map_offset] offset = 0x101c2000 [ 1158.445600] [drm:drm_vm_open_locked] 0xaec15000,0x00256000 [ 1158.445608] [drm:update_vm_cache_attr] flags = 0x0 [ 1158.457696] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_SET_CMDLIST [ 1158.457745] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_EXEC So G2D_EXEC seems to work once, but the second time it hangs forever. I even fail at attaching gdb to the application then (gdb then also hangs in D state). If I just use the 'vsynced page flipping' test, then everything works: ./modetest -M exynos -s 16@13:1280x720 -v setting mode 1280x720-60Hz@XR24 on connectors 16, crtc 13 freq: 61.08Hz freq: 60.00Hz freq: 60.00Hz etc. I'm going to do some tests with the G2D in the next time, checking how much I can lower MIF/INT clocks before the engine becomes unstable. With best wishes, Tobias -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH] ASoC: max98088: Add master clock handling
Hello, On 02/20/2015 04:27 AM, Tushar Behera wrote: On 02/20/2015 12:48 AM, Andreas Färber wrote: If master clock is provided through device tree, then update the master clock frequency during set_sysclk. Cc: Tushar Behera tushar.beh...@linaro.org Signed-off-by: Andreas Färber afaer...@suse.de --- sound/soc/codecs/max98088.c | 24 1 file changed, 24 insertions(+) Looks good. Acked-by: Tushar Behera trbli...@gmail.com Looks good to me as well. Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH] ARM: EXYNOS: Fix failed second suspend on Exynos4
Hi Krzysztof,
I tested this patch for suspend-to-ram on Exynos4412-based trats2 board.
When I tested suspend-to-ram repetitively, I faced on hang issue of
suspend-to-ram for Exynos4 as before.
Could you send .config file for test?
Thanks,
Chanwoo Choi
On 02/18/2015 07:45 PM, Krzysztof Kozlowski wrote:
On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in
56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache
controller) the second suspend to RAM failed. First suspend worked fine
but the next one hang just after powering down of secondary CPUs (system
consumed energy as it would be running but was not responsive).
The issue was caused by enabling delayed reset assertion for CPU0 just
after issuing power down of cores. This was introduced for Exynos4 in
13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off).
The whole behavior is not well documented but after checking with vendor
code this should be done like this (on Exynos4):
1. Enable delayed reset assertion when system is running (for all CPUs).
2. Disable delayed reset assertion before suspending the system.
This can be done after powering off secondary CPUs.
3. Re-enable the delayed reset assertion when system is resumed.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off)
Cc: sta...@vger.kernel.org
---
arch/arm/mach-exynos/common.h | 2 ++
arch/arm/mach-exynos/exynos.c | 27 +++
arch/arm/mach-exynos/platsmp.c | 39 ++-
arch/arm/mach-exynos/suspend.c | 3 +++
4 files changed, 34 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f70eca7ee705..0ef8d4b47102 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -153,6 +153,8 @@ extern void exynos_enter_aftr(void);
extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
+extern void exynos_set_delayed_reset_assertion(bool enable);
+
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
extern void __iomem *cpu_boot_reg_base(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 2013f73797ed..e2f46295eed7 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -166,6 +166,33 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code
+ * and suspend.
+ *
+ * This is necessary only on Exynos4 SoCs. When system is running
+ * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down
+ * feature could properly detect global idle state when secondary CPU is
+ * powered down.
+ *
+ * However this should not be set when such system is going into suspend.
+ */
+void exynos_set_delayed_reset_assertion(bool enable)
+{
+ if (soc_is_exynos4()) {
+ unsigned int tmp, core_id;
+
+ for (core_id = 0; core_id num_possible_cpus(); core_id++) {
+ tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
+ if (enable)
+ tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
+ else
+ tmp = ~(S5P_USE_DELAYED_RESET_ASSERTION);
+ pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
+ }
+ }
+}
+
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
{ .compatible = samsung,exynos4210-pmu },
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 3f32c47a6d74..19d5c87c842c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,30 +34,6 @@
extern void exynos4_secondary_startup(void);
-/*
- * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
- * during hot-(un)plugging CPUx.
- *
- * The feature can be cleared safely during first boot of secondary CPU.
- *
- * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
- * down a CPU so the CPU idle clock down feature could properly detect global
- * idle state when CPUx is off.
- */
-static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
-{
- if (soc_is_exynos4()) {
- unsigned int tmp;
-
- tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
- if (enable)
- tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
- else
- tmp = ~(S5P_USE_DELAYED_RESET_ASSERTION);
- pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
- }
-}
-
#ifdef CONFIG_HOTPLUG_CPU
static inline void cpu_leave_lowpower(u32 core_id)
{
@@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32
Re: Re: [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
Hello Chanwoo! Chanwoo Choi wrote: As you thought, when maintaining lower clock of memory bus frequency, some issue related to multimedia feature will happen. Separately, We have to check the miminum lower clock for working of multimedia feature. and then multimedia or other IP have to request it to DVFS driver (memory busfreq driver). But, latest mainline kernel currently has not some way to inform minimum clock to DVFS driver. So, If you check the miminum clock for hdmi, I'll use this clock as minumu frequency of dvfs table. Thanks, Chanwoo Choi First I have to apologize. I didn't check carefully. Actually it's not the HDMI subsystem which seems to hang during my test, but the G2D subsystem. Here's a snippet of the kernel log with drm.debug=0xff: [ 1157.911264] [drm:drm_framebuffer_reference] ee144e00: FB ID: 27 (2) [ 1157.911271] [drm:drm_framebuffer_unreference] ee37fb80: FB ID: 25 (2) [ 1157.911277] [drm:drm_framebuffer_unreference] ee144e00: FB ID: 27 (3) [ 1157.911315] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_GET_VER [ 1158.434439] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_SET_CMDLIST [ 1158.434536] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_EXEC [ 1158.437484] [drm:drm_vm_close_locked] 0xaf84,0x0014 [ 1158.437507] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE [ 1158.437524] [drm:exynos_drm_gem_destroy] handle count = 0 [ 1158.437532] [drm:lowlevel_buffer_deallocate] dma_addr(0x2050), size(0x14) [ 1158.437810] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_GEM_CREATE [ 1158.437819] [drm:exynos_drm_init_buf] desired size = 0x256000 [ 1158.437851] [drm:exynos_drm_gem_init] created file object = 0xe97c8d00 [ 1158.445506] [drm:lowlevel_buffer_allocate] dma_addr(0x2140), size(0x256000) [ 1158.445535] [drm:exynos_drm_gem_handle_create] gem handle = 0x1 [ 1158.445556] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, DRM_IOCTL_MODE_MAP_DUMB [ 1158.445570] [drm:exynos_drm_gem_dumb_map_offset] offset = 0x101c2000 [ 1158.445600] [drm:drm_vm_open_locked] 0xaec15000,0x00256000 [ 1158.445608] [drm:update_vm_cache_attr] flags = 0x0 [ 1158.457696] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_SET_CMDLIST [ 1158.457745] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_EXEC So G2D_EXEC seems to work once, but the second time it hangs forever. I even fail at attaching gdb to the application then (gdb then also hangs in D state). If I just use the 'vsynced page flipping' test, then everything works: ./modetest -M exynos -s 16@13:1280x720 -v setting mode 1280x720-60Hz@XR24 on connectors 16, crtc 13 freq: 61.08Hz freq: 60.00Hz freq: 60.00Hz etc. I'm going to do some tests with the G2D in the next time, checking how much I can lower MIF/INT clocks before the engine becomes unstable. With best wishes, Tobias Unless you are willing to wait for 2 minutes after the kernal hangs, you may want to adjust DEFAULT_HUNG_TASK_TIMEOUT to shorter value (120 -- 5 for 5 seconds). It seems that you've cut it off in the middle of that 120 sec wait. If it's in D state (in kernel), gdb won't work as you are experiencing. Sorry for not testing with HDMI; my Exynos devices do not have HDMI. :) To Chanwoo, wouldn't it be ok to have the corresponding devfreq driver to set minimum higher IFF HDMI is enabled? (either by build time or run time) I guess Exynos HDMI driver should express PM-QoS requests later. (Or let Exynos HDMI driver not hung even if its memory transactions are not fast enough) Cheers, MyungJoo
[RESEND PATCH] ARM: exynos: Fix wrong hwirq of RTC interrupt for Exynos3250 SoC
This patch fixes wrong hwirq of RTC irq for Exynos3250 SoC. When entering
suspend state, 'enable_irq_wake fail' happen because of the mismatch of RTC
hwirq.
[ 429.200937] Freezing user space processes ... (elapsed 0.002
seconds) done.
[ 429.203383] Freezing remaining freezable tasks ... (elapsed 0.000
seconds) done.
[ 429.209914] Suspending console(s) (use no_console_suspend to debug)
[ 429.370685] wake enabled for irq 65
[ 429.370837] wake enabled for irq 64
[ 429.370868] wake enabled for irq 79
[snip]
[ 429.372120] s3c-rtc 1007.rtc: enable_irq_wake failed
Fixes: a4f582f5c5fe3 (ARM: EXYNOS: Add exynos3250 suspend-to-ram support)
Cc: Kukjin Kim kg...@kernel.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/suspend.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 52e2b1a..318d127 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -87,8 +87,8 @@ static unsigned int exynos_pmu_spare3;
static u32 exynos_irqwake_intmask = 0x;
static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
- { 73, BIT(1) }, /* RTC alarm */
- { 74, BIT(2) }, /* RTC tick */
+ { 105, BIT(1) }, /* RTC alarm */
+ { 106, BIT(2) }, /* RTC tick */
{ /* sentinel */ },
};
--
1.8.5.5
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[PATCH v3] rtc: s5m: Add the support for S2MPS13 RTC
This patch adds only the compatible string for S2MPS13 clock which is identical
with S2MPS14 clock driver.
Cc: Alessandro Zummo a.zu...@towertech.it
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
Changes from v1:
- Send this patch separately from S2MPS13 PMIC patchset[1]
[1] https://lkml.org/lkml/2014/11/18/130
drivers/rtc/rtc-s5m.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 89ac1d5..fffd5d3 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -191,6 +191,7 @@ static inline int s5m_check_peding_alarm_interrupt(struct
s5m_rtc_info *info,
ret = regmap_read(info-regmap, S5M_RTC_STATUS, val);
val = S5M_ALARM0_STATUS;
break;
+ case S2MPS13X:
case S2MPS14X:
ret = regmap_read(info-s5m87xx-regmap_pmic, S2MPS14_REG_ST2,
val);
@@ -254,6 +255,7 @@ static inline int s5m8767_rtc_set_alarm_reg(struct
s5m_rtc_info *info)
case S5M8767X:
data = ~S5M_RTC_TIME_EN_MASK;
break;
+ case S2MPS13X:
case S2MPS14X:
data |= S2MPS_RTC_RUDR_MASK;
break;
@@ -311,7 +313,9 @@ static int s5m_rtc_read_time(struct device *dev, struct
rtc_time *tm)
u8 data[info-regs-regs_count];
int ret;
- if (info-device_type == S2MPS14X) {
+ switch (info-device_type) {
+ case S2MPS13X:
+ case S2MPS14X:
ret = regmap_update_bits(info-regmap,
info-regs-rtc_udr_update,
S2MPS_RTC_RUDR_MASK, S2MPS_RTC_RUDR_MASK);
@@ -333,6 +337,7 @@ static int s5m_rtc_read_time(struct device *dev, struct
rtc_time *tm)
break;
case S5M8767X:
+ case S2MPS13X:
case S2MPS14X:
s5m8767_data_to_tm(data, tm, info-rtc_24hr_mode);
break;
@@ -359,6 +364,7 @@ static int s5m_rtc_set_time(struct device *dev, struct
rtc_time *tm)
s5m8763_tm_to_data(tm, data);
break;
case S5M8767X:
+ case S2MPS13X:
case S2MPS14X:
ret = s5m8767_tm_to_data(tm, data);
break;
@@ -406,6 +412,7 @@ static int s5m_rtc_read_alarm(struct device *dev, struct
rtc_wkalrm *alrm)
break;
case S5M8767X:
+ case S2MPS13X:
case S2MPS14X:
s5m8767_data_to_tm(data, alrm-time, info-rtc_24hr_mode);
alrm-enabled = 0;
@@ -454,6 +461,7 @@ static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
break;
case S5M8767X:
+ case S2MPS13X:
case S2MPS14X:
for (i = 0; i info-regs-regs_count; i++)
data[i] = ~ALARM_ENABLE_MASK;
@@ -498,6 +506,7 @@ static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
break;
case S5M8767X:
+ case S2MPS13X:
case S2MPS14X:
data[RTC_SEC] |= ALARM_ENABLE_MASK;
data[RTC_MIN] |= ALARM_ENABLE_MASK;
@@ -537,6 +546,7 @@ static int s5m_rtc_set_alarm(struct device *dev, struct
rtc_wkalrm *alrm)
break;
case S5M8767X:
+ case S2MPS13X:
case S2MPS14X:
s5m8767_tm_to_data(alrm-time, data);
break;
@@ -641,6 +651,7 @@ static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
ret = regmap_raw_write(info-regmap, S5M_ALARM0_CONF, data, 2);
break;
+ case S2MPS13X:
case S2MPS14X:
data[0] = (0 BCD_EN_SHIFT) | (1 MODEL24_SHIFT);
ret = regmap_write(info-regmap, info-regs-ctrl, data[0]);
@@ -678,6 +689,7 @@ static int s5m_rtc_probe(struct platform_device *pdev)
return -ENOMEM;
switch (pdata-device_type) {
+ case S2MPS13X:
case S2MPS14X:
regmap_cfg = s2mps14_rtc_regmap_config;
info-regs = s2mps_rtc_regs;
@@ -831,6 +843,7 @@ static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend,
s5m_rtc_resume);
static const struct platform_device_id s5m_rtc_id[] = {
{ s5m-rtc,S5M8767X },
+ { s2mps13-rtc,S2MPS13X },
{ s2mps14-rtc,S2MPS14X },
{ },
};
--
1.8.5.5
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[PATCH v4 7/8] arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC
From: Inha Song ideal.s...@samsung.com
This patch adds ADMA (Advanced DMA) device tree node for Exynos5433 SoC.
In Exynos5433 SoC, ADMA is used for I2S audio interface.
Cc: Kukjin Kim kg...@kernel.org
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 1c68d9e..6becaca 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -462,6 +462,17 @@
#dma-channels = 8;
#dma-requests = 32;
};
+
+ adma: adma@1142 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1142 0x1000;
+ interrupts = 0 73 0;
+ clocks = cmu_aud CLK_ACLK_DMAC;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
};
serial_0: serial@14c1 {
--
1.8.5.5
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[PATCH v4 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support
This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas catalin.mari...@arm.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com --- arch/arm64/Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1b8e973..d83cea0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -154,6 +154,17 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool ARMv8 based Samsung Exynos5433 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] rtc: s3c: Delete duplicate clock control
The current functions in s3c-rtc driver execute the clk_enable/disable() to
control clocks and some functions execute the s3c_rtc_alarm_clk_enable()
unnecessarily. So, This patch deletes the duplicate clock control ane spilt
s3c_rtc_alarm_clk_enable() out as s3c_rtc_enable_clk()/s3c_rtc_disable_clk()
to improve readability.
Cc: Alessandro Zummo a.zu...@towertech.it
Cc: Andrew Morton a...@linux-foundation.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
Changes from v1:
- Modify the patch description
drivers/rtc/rtc-s3c.c | 163 --
1 file changed, 39 insertions(+), 124 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 4241eea..16aca50 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -39,7 +39,6 @@ struct s3c_rtc {
void __iomem *base;
struct clk *rtc_clk;
struct clk *rtc_src_clk;
- bool enabled;
struct s3c_rtc_data *data;
@@ -67,26 +66,25 @@ struct s3c_rtc_data {
void (*disable) (struct s3c_rtc *info);
};
-static void s3c_rtc_alarm_clk_enable(struct s3c_rtc *info, bool enable)
+static void s3c_rtc_enable_clk(struct s3c_rtc *info)
{
unsigned long irq_flags;
spin_lock_irqsave(info-alarm_clk_lock, irq_flags);
- if (enable) {
- if (!info-enabled) {
- clk_enable(info-rtc_clk);
- if (info-data-needs_src_clk)
- clk_enable(info-rtc_src_clk);
- info-enabled = true;
- }
- } else {
- if (info-enabled) {
- if (info-data-needs_src_clk)
- clk_disable(info-rtc_src_clk);
- clk_disable(info-rtc_clk);
- info-enabled = false;
- }
- }
+ clk_enable(info-rtc_clk);
+ if (info-data-needs_src_clk)
+ clk_enable(info-rtc_src_clk);
+ spin_unlock_irqrestore(info-alarm_clk_lock, irq_flags);
+}
+
+static void s3c_rtc_disable_clk(struct s3c_rtc *info)
+{
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(info-alarm_clk_lock, irq_flags);
+ if (info-data-needs_src_clk)
+ clk_disable(info-rtc_src_clk);
+ clk_disable(info-rtc_clk);
spin_unlock_irqrestore(info-alarm_clk_lock, irq_flags);
}
@@ -119,20 +117,16 @@ static int s3c_rtc_setaie(struct device *dev, unsigned
int enabled)
dev_dbg(info-dev, %s: aie=%d\n, __func__, enabled);
- clk_enable(info-rtc_clk);
- if (info-data-needs_src_clk)
- clk_enable(info-rtc_src_clk);
+ s3c_rtc_enable_clk(info);
+
tmp = readb(info-base + S3C2410_RTCALM) ~S3C2410_RTCALM_ALMEN;
if (enabled)
tmp |= S3C2410_RTCALM_ALMEN;
writeb(tmp, info-base + S3C2410_RTCALM);
- if (info-data-needs_src_clk)
- clk_disable(info-rtc_src_clk);
- clk_disable(info-rtc_clk);
- s3c_rtc_alarm_clk_enable(info, enabled);
+ s3c_rtc_disable_clk(info);
return 0;
}
@@ -143,18 +137,12 @@ static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq)
if (!is_power_of_2(freq))
return -EINVAL;
- clk_enable(info-rtc_clk);
- if (info-data-needs_src_clk)
- clk_enable(info-rtc_src_clk);
spin_lock_irq(info-pie_lock);
if (info-data-set_freq)
info-data-set_freq(info, freq);
spin_unlock_irq(info-pie_lock);
- if (info-data-needs_src_clk)
- clk_disable(info-rtc_src_clk);
- clk_disable(info-rtc_clk);
return 0;
}
@@ -165,9 +153,7 @@ static int s3c_rtc_gettime(struct device *dev, struct
rtc_time *rtc_tm)
struct s3c_rtc *info = dev_get_drvdata(dev);
unsigned int have_retried = 0;
- clk_enable(info-rtc_clk);
- if (info-data-needs_src_clk)
- clk_enable(info-rtc_src_clk);
+ s3c_rtc_enable_clk(info);
retry_get_time:
rtc_tm-tm_min = readb(info-base + S3C2410_RTCMIN);
@@ -194,6 +180,8 @@ static int s3c_rtc_gettime(struct device *dev, struct
rtc_time *rtc_tm)
rtc_tm-tm_mon = bcd2bin(rtc_tm-tm_mon);
rtc_tm-tm_year = bcd2bin(rtc_tm-tm_year);
+ s3c_rtc_disable_clk(info);
+
rtc_tm-tm_year += 100;
dev_dbg(dev, read time %04d.%02d.%02d %02d:%02d:%02d\n,
@@ -202,10 +190,6 @@ static int s3c_rtc_gettime(struct device *dev, struct
rtc_time *rtc_tm)
rtc_tm-tm_mon -= 1;
- if (info-data-needs_src_clk)
- clk_disable(info-rtc_src_clk);
- clk_disable(info-rtc_clk);
-
return rtc_valid_tm(rtc_tm);
}
@@ -225,9 +209,7 @@ static int s3c_rtc_settime(struct device *dev, struct
rtc_time *tm)
return -EINVAL;
}
- clk_enable(info-rtc_clk);
- if (info-data-needs_src_clk)
- clk_enable(info-rtc_src_clk);
+
Re: [GIT PULL] clk/samsung: clk support for Exynos 5433 SoC
Dear Mike and Sylwester,
This pull-request was not merged on Linux 4.0-rc1.
Did you have any plan about it?
Best Regards,
Chanwoo Choi
On 02/06/2015 04:44 AM, Sylwester Nawrocki wrote:
Hi Mike,
This pull request includes driver for clock controller of the Exynos
5433 SoC. As the hardware is quite complex, with many peripherals and
corresponding clock management units the driver is rather huge. I guess
it will require a bit more cleanups than last time to balance lines
introduced in this patch set... Please review and pull if it looks OK.
The following changes since commit e64fb42da4c6c713cfc7cad607e97e0773fa41ff:
clk: samsung: exynos4: Add divider clock id for memory bus frequency
(2015-01-28 15:51:17 +0100)
are available in the git repository at:
git://linuxtv.org/snawrocki/samsung.git tags/v3.20-exynos5433-clk
for you to fetch changes up to b2f0e5f28e0686c0d5db238357a2e32555e97633:
clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to CMU_TOP
domain (2015-02-05 19:31:09 +0100)
Clock controller driver for Exynos 5433 SoC.
Chanwoo Choi (22):
clk: samsung: exynos5433: Add binding document for Exynos5433 clock
domains
clk: samsung: exynos5433: Add clocks using common clock framework
clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
clk: samsung: exynos5433: Add clocks for CMU_G2D domain
clk: samsung: exynos5433: Add clocks for CMU_MIF domain
clk: samsung: exynos5433: Add clocks for CMU_DISP domain
clk: samsung: exynos5433: Add clocks for CMU_AUD domain
clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
clk: samsung: exynos5433: Add clocks for CMU_G3D domain
clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain
clk: samsung: exynos5433: Add clocks for CMU_ATLAS domain
clk: samsung: exynos5433: Add clocks for CMU_MSCL domain
clk: samsung: exynos5433: Add clocks for CMU_MFC domain
clk: samsung: exynos5433: Add clocks for CMU_HEVC domain
clk: samsung: exynos5433: Add clocks for CMU_ISP domain
clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain
clk: samsung: exynos5433: Add clocks for CMU_CAM1 domain
clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to
CMU_TOP domain
Inha Song (1):
clk: samsung: Add CLKOUT driver support for Exynos5433 SoC
.../devicetree/bindings/clock/exynos5433-clock.txt | 462 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos-clkout.c|2 +
drivers/clk/samsung/clk-exynos5433.c | 5423
include/dt-bindings/clock/exynos5433.h | 1403 +
5 files changed, 7291 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5433.c
create mode 100644 include/dt-bindings/clock/exynos5433.h
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[PATCH v4] pinctrl: exynos: Add support for Exynos5433
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Tomasz Figa tomasz.f...@gmail.com
---
Changes from v3:
- Rebase it on Linux 4.0-rc1
- Add acked messgae of Tomasz Figa
Changes from v2:
- Rebase it on v3.19-rc5
drivers/pinctrl/samsung/pinctrl-exynos.c | 153 ++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 156 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index c8f83f9..d273fda 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1240,6 +1240,159 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[]
__initconst = {
},
};
+/* pin banks of exynos5433 pin-controller - ALIVE */
+static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos5433 pin-controller - AUD */
+static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos5433 pin-controller - CPIF */
+static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(2, 0x000, gpv6, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - eSE */
+static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj2, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FINGER */
+static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpd5, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FSYS */
+static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gph1, 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, gpr4, 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, gpr0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpr1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpr2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpr3, 0x14),
+};
+
+/* pin banks of exynos5433 pin-controller - IMEM */
+static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpf0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - NFC */
+static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - PERIC */
+static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gpv7, 0x00),
+ EXYNOS_PIN_BANK_EINTG(5, 0x020, gpb0, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpc0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x060, gpc1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x080, gpc2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpc3, 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0c0, gpg0, 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0e0, gpd0, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x100, gpd1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, gpd2, 0x24),
+ EXYNOS_PIN_BANK_EINTG(5, 0x140, gpd4, 0x28),
+ EXYNOS_PIN_BANK_EINTG(2, 0x160, gpd8, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(7, 0x180, gpd6, 0x30),
+ EXYNOS_PIN_BANK_EINTG(3, 0x1a0, gpd7, 0x34),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1c0, gpg1, 0x38),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1e0, gpg2, 0x3c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x200, gpg3, 0x40),
+};
+
+/* pin banks of exynos5433 pin-controller - TOUCH */
+static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * ten gpio/pin-mux/pinconfig controllers.
+ */
+const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5433_pin_banks1,
+ .nr_banks =
Re: [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
Hi Tobias, On 02/24/2015 04:57 AM, Tobias Jakobi wrote: Hello Chanwoo! Chanwoo Choi wrote: As you thought, when maintaining lower clock of memory bus frequency, some issue related to multimedia feature will happen. Separately, We have to check the miminum lower clock for working of multimedia feature. and then multimedia or other IP have to request it to DVFS driver (memory busfreq driver). But, latest mainline kernel currently has not some way to inform minimum clock to DVFS driver. So, If you check the miminum clock for hdmi, I'll use this clock as minumu frequency of dvfs table. Thanks, Chanwoo Choi First I have to apologize. I didn't check carefully. Actually it's not the HDMI subsystem which seems to hang during my test, but the G2D subsystem. Here's a snippet of the kernel log with drm.debug=0xff: [ 1157.911264] [drm:drm_framebuffer_reference] ee144e00: FB ID: 27 (2) [ 1157.911271] [drm:drm_framebuffer_unreference] ee37fb80: FB ID: 25 (2) [ 1157.911277] [drm:drm_framebuffer_unreference] ee144e00: FB ID: 27 (3) [ 1157.911315] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_GET_VER [ 1158.434439] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_SET_CMDLIST [ 1158.434536] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_EXEC [ 1158.437484] [drm:drm_vm_close_locked] 0xaf84,0x0014 [ 1158.437507] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE [ 1158.437524] [drm:exynos_drm_gem_destroy] handle count = 0 [ 1158.437532] [drm:lowlevel_buffer_deallocate] dma_addr(0x2050), size(0x14) [ 1158.437810] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_GEM_CREATE [ 1158.437819] [drm:exynos_drm_init_buf] desired size = 0x256000 [ 1158.437851] [drm:exynos_drm_gem_init] created file object = 0xe97c8d00 [ 1158.445506] [drm:lowlevel_buffer_allocate] dma_addr(0x2140), size(0x256000) [ 1158.445535] [drm:exynos_drm_gem_handle_create] gem handle = 0x1 [ 1158.445556] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, DRM_IOCTL_MODE_MAP_DUMB [ 1158.445570] [drm:exynos_drm_gem_dumb_map_offset] offset = 0x101c2000 [ 1158.445600] [drm:drm_vm_open_locked] 0xaec15000,0x00256000 [ 1158.445608] [drm:update_vm_cache_attr] flags = 0x0 [ 1158.457696] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_SET_CMDLIST [ 1158.457745] [drm:drm_ioctl] pid=2569, dev=0xe200, auth=1, EXYNOS_G2D_EXEC So G2D_EXEC seems to work once, but the second time it hangs forever. I even fail at attaching gdb to the application then (gdb then also hangs in D state). If I just use the 'vsynced page flipping' test, then everything works: ./modetest -M exynos -s 16@13:1280x720 -v setting mode 1280x720-60Hz@XR24 on connectors 16, crtc 13 freq: 61.08Hz freq: 60.00Hz freq: 60.00Hz etc. I'm going to do some tests with the G2D in the next time, checking how much I can lower MIF/INT clocks before the engine becomes unstable. Thanks for your test. If you have any question or help, please feel free to ask me. I'm working to implemnet new generic exynos memoby-bus frequency driver (exynos-busfreq.c). because this version of patch-set used the 'virtual operating-points'. So, I'm working to implment this drvier without 'virtual operation-points'. After finishing the implmentaion, I'll add you to mailing list ac Cc. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] thermal: exynos: Fix wrong control of power down detection mode for Exynos7
This patch fixes the wrong control of PD_DET_EN (power down detection mode)
for Exynos7 because exynos7_tmu_control() always enables the power down
detection
mode regardless 'on' parameter.
Cc: Zhang Rui rui.zh...@intel.com
Cc: Eduardo Valentin edubez...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index 933cd80..a60f527 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -682,6 +682,7 @@ static void exynos7_tmu_control(struct platform_device
*pdev, bool on)
if (on) {
con |= (1 EXYNOS_TMU_CORE_EN_SHIFT);
+ con |= (1 EXYNOS7_PD_DET_EN_SHIFT);
interrupt_en =
(of_thermal_is_trip_valid(tz, 7)
EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
@@ -704,9 +705,9 @@ static void exynos7_tmu_control(struct platform_device
*pdev, bool on)
interrupt_en EXYNOS_TMU_INTEN_FALL0_SHIFT;
} else {
con = ~(1 EXYNOS_TMU_CORE_EN_SHIFT);
+ con = ~(1 EXYNOS7_PD_DET_EN_SHIFT);
interrupt_en = 0; /* Disable all interrupts */
}
- con |= 1 EXYNOS7_PD_DET_EN_SHIFT;
writel(interrupt_en, data-base + EXYNOS7_TMU_REG_INTEN);
writel(con, data-base + EXYNOS_TMU_REG_CONTROL);
--
1.8.5.5
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[PATCH 2/2] thermal: exynos: Clean-up code to use oneline entry for exynos compatible table
This patch cleanup the code to use oneline for entry of exynos compatible
table.
Cc: Zhang Rui rui.zh...@intel.com
Cc: Eduardo Valentin edubez...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 38 ++--
1 file changed, 10 insertions(+), 28 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index a60f527..1d30b09 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -919,34 +919,16 @@ static irqreturn_t exynos_tmu_irq(int irq, void *id)
}
static const struct of_device_id exynos_tmu_match[] = {
- {
- .compatible = samsung,exynos3250-tmu,
- },
- {
- .compatible = samsung,exynos4210-tmu,
- },
- {
- .compatible = samsung,exynos4412-tmu,
- },
- {
- .compatible = samsung,exynos5250-tmu,
- },
- {
- .compatible = samsung,exynos5260-tmu,
- },
- {
- .compatible = samsung,exynos5420-tmu,
- },
- {
- .compatible = samsung,exynos5420-tmu-ext-triminfo,
- },
- {
- .compatible = samsung,exynos5440-tmu,
- },
- {
- .compatible = samsung,exynos7-tmu,
- },
- {},
+ { .compatible = samsung,exynos3250-tmu, },
+ { .compatible = samsung,exynos4210-tmu, },
+ { .compatible = samsung,exynos4412-tmu, },
+ { .compatible = samsung,exynos5250-tmu, },
+ { .compatible = samsung,exynos5260-tmu, },
+ { .compatible = samsung,exynos5420-tmu, },
+ { .compatible = samsung,exynos5420-tmu-ext-triminfo, },
+ { .compatible = samsung,exynos5440-tmu, },
+ { .compatible = samsung,exynos7-tmu, },
+ { /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, exynos_tmu_match);
--
1.8.5.5
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[PATCH v2 0/2] thermal: exynos: Fix NULL pointer error and bug of PD_DET_EN of Exynos7
This patch-set fix the bug of PD_DET_EN bit field of Exynos7 TMU. And the clean-up the exynos compatible table by making oneline entry. Changes from v1: - Rebased it on Linux 4.0-rc1 - Add acked message by Lukasz Majewski - Drop first patch [1] because NULL poiner error don't happen. [1] http://www.spinics.net/lists/linux-samsung-soc/msg42424.html Chanwoo Choi (2): thermal: exynos: Fix wrong control of power down detection mode for Exynos7 thermal: exynos: Clean-up code to use oneline entry for exynos compatible table drivers/thermal/samsung/exynos_tmu.c | 41 +++- 1 file changed, 12 insertions(+), 29 deletions(-) -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/8] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
This patch includes following dt node to support Exynos5433 SoC:
1. Octa core for big.LITTLE architecture
- Cortex-A53 LITTLE Quad-core
- Cortex-A57 big Quad-core
- Support PSCI v0.1
2. clock controller node:
- CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
- CMU_CPIF : clocks for LLI (Low Latency Interface)
- CMU_MIF : clocks for DRAM Memory Controller
- CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS
- CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC
- CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA
- CMU_G2D : clocks for G2D/MDMA
- CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER
- CMU_AUD : clocks for Cortex-A5/BUS/AUDIO
- CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses
- CMU_G3D : clocks for 3D Graphics Engine
- CMU_GSCL : clocks for GSCALER
- CMU_APOLLO: clocks for Cortex-A53 Quad-core processor.
- CMU_ATLAS : clocks for Cortex-A57 Quad-core processor,
CoreSight and L2 cache controller.
- CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- CMU_MFC : clocks for MFC (Multi-Format Codec) IP.
- CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP.
- CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
- CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
- CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.
3. pinctrl node for GPIO:
- alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad
4. HS (High-Speed) I2C device
5. Serial device
6. ARCH timer (arm,armv8-timer)
7. Interrupt controller (arm,gic-400)
Cc: Kukjin Kim kg...@kernel.org
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 696
2 files changed, 1394 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000..c56bbf8
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = gpz0-0, gpz0-1, gpz0-2, gpz0-3,
+ gpz0-4, gpz0-5, gpz0-6;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = gpz1-0,
[PATCH v4 5/8] arm64: dts: exynos: Add PMU dt node for Exynos5433
This patch adds PMU (Power Management Unit) dt node for Exynos5433 SoC and
set the source clock for CLKOUT register as xxti .
Cc: Kukjin Kim kg...@kernel.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
[ideal.song: Add the setting of CLKOUT register]
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi| 8
2 files changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b2113..a87fc43 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- samsung,exynos5260-pmu - for Exynos5260 SoC.
- samsung,exynos5410-pmu - for Exynos5410 SoC,
- samsung,exynos5420-pmu - for Exynos5420 SoC.
+ - samsung,exynos5433-pmu - for Exynos5433 SoC.
- samsung,exynos7-pmu - for Exynos7 SoC.
second value must be always syscon.
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 1b18fd3..84be8e2 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -844,6 +844,14 @@
status = disabled;
};
+ pmu_system_controller: system-controller@105c {
+ compatible = samsung,exynos5433-pmu, syscon;
+ reg = 0x105c 0x5008;
+ #clock-cells = 1;
+ clock-names = clkout16;
+ clocks = xxti;
+ };
+
timer {
compatible = arm,armv8-timer;
interrupts = 1 13 0xff04,
--
1.8.5.5
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[PATCH v4 0/8] arm64: Add the support for new Exynos5433 SoC
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset is based on Linux 4.0-rc1.
Depends on:
- This patch-set has the dependency on Exynos5433 clock driver[1][2] and
pinctrl driver[3].
The Exynos5433 clock controller patch-set[1][2] was merged by Sylwester Nawrocki
and Exynos5433's pinctrl patch[3] receviced the acked message by Tomasz Figa.
(http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/,
branch:for-v3.20/clk/next)
[1] [PATCH v5 00/13] clk: samsung: Add the support for exynos5433 clocks
- https://lkml.org/lkml/2015/2/2/368
[2] [PATCH v3 0/9] clk: samsung: Add clocks for remaining domains of Exynos5433
- https://lkml.org/lkml/2015/2/2/784
[3] [PATCH v4] pinctrl: exynos: Add support for Exynos5433
- https://lkml.org/lkml/2015/2/23/728
Changelog:
Changes from v3:
(https://lkml.org/lkml/2015/2/12/65)
- Rebased it on Linux 4.0-rc1.
- Remove ARM_GIC and ARM_AMBA dependency because CONFIG_ARM64 already included
them.
Changes from v2:
(https://lkml.org/lkml/2014/12/2/134)
: Fix the range of GICC memory map (0x1000 - 0x2000)
: Fix address space of 'range' property under 'soc' node
: Add ADMA / I2S dt node for sound playback/capture
- Select ARM_AMBA/ARM_GIC/HAVE_S3C_RTC for Exynos5433 in arch/arm64/Kconfig
- Send separate patch-set for Exynos5433 clock controller[1][2] and pinctrl[3]
Changes from v1:
(https://lkml.org/lkml/2014/11/27/92)
- Merge two patches (patch2, patch3) to solve incomplete description
- Exynos5433 Clock driver
: Fix wrong register and code clean by using space instead of tab
: Add CLK_IGNORE_UNUSED flag to pclk_sysreg_* clock for accessing system
control register
: Remove duplicate definition on the patch for CMU_BUS{0|1|2} domain
- Exynos5433 SoC DTS
: Remove un-supported properties of arch_timer
: Remove 'clock-frequency' property from 'cpus' dt node
: Fix interrupt type from edge rising triggering to level high triggering
because Cortex-A53/A57 use level triggering.
: Fix defult address-size/size-celss from 1 to 2 because Exynos5433 is 64-bit
SoC
: Modify 'fin_pll' dt node to remove un-needed and ugly code
: Move 'chipid' dt node under 'soc'
: Use lowercase on all case in exynos5433.dtsi
: Add PSCI dt node for secondary cpu boot
: Add 'samsung,exynos5433' compatible to MCT dt node
- Divide pinctrl patch from this patchset
- Add new following patches:
: clocksource: exynos_mct: Add the support for Exynos 64bit SoC
: arm64: Enable Exynos5433 SoC in the defconfig
Chanwoo Choi (5):
arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
arm64: dts: exynos: Add PMU dt node for Exynos5433
arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC
Inha Song (2):
arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC
arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/arm/samsung/pmu.txt| 1 +
arch/arm64/Kconfig | 11 +
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 911 +
4 files changed, 1621 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
--
1.8.5.5
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[PATCH v4 3/8] arm64: dts: exynos: Add MSHC dt node for Exynos5433
From: Jaehoon Chung jh80.ch...@samsung.com
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim kg...@kernel.org
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 6b30123..81f428e 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -52,6 +52,9 @@
i2c9 = hsi2c_9;
i2c10 = hsi2c_10;
i2c11 = hsi2c_11;
+ mshc0 = mshc_0;
+ mshc1 = mshc_1;
+ mshc2 = mshc_2;
};
cpus {
@@ -683,6 +686,45 @@
status = disabled;
};
+ mshc_0: mshc@1554 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 225 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1554 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC0,
+cmu_fsys CLK_SCLK_MMC0;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
+ mshc_1: mshc@1555 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 226 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1555 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC1,
+cmu_fsys CLK_SCLK_MMC1;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
+ mshc_2: mshc@1556 {
+ compatible = samsung,exynos7-dw-mshc-smu;
+ interrupts = 0 227 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1556 0x2000;
+ clocks = cmu_fsys CLK_ACLK_MMC2,
+cmu_fsys CLK_SCLK_MMC2;
+ clock-names = biu, ciu;
+ fifo-depth = 0x40;
+ status = disabled;
+ };
+
timer {
compatible = arm,armv8-timer;
interrupts = 1 13 0xff04,
--
1.8.5.5
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[PATCH v4 4/8] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim kg...@kernel.org
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 119 +
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 81f428e..1b18fd3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -55,6 +55,11 @@
mshc0 = mshc_0;
mshc1 = mshc_1;
mshc2 = mshc_2;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
+ spi3 = spi_3;
+ spi4 = spi_4;
};
cpus {
@@ -430,6 +435,35 @@
interrupts = 1 9 0xf04;
};
+ amba {
+ compatible = arm,amba-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ pdma0: pdma@1561 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1561 0x1000;
+ interrupts = 0 228 0;
+ clocks = cmu_fsys CLK_PDMA0;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@1560 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1560 0x1000;
+ interrupts = 0 246 0;
+ clocks = cmu_fsys CLK_PDMA1;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+ };
+
serial_0: serial@14c1 {
compatible = samsung,exynos5433-uart;
reg = 0x14c1 0x100;
@@ -530,6 +564,91 @@
interrupts = 0 442 0;
};
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 432 0;
+ dmas = pdma0 9, pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI0,
+cmu_top CLK_SCLK_SPI0_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ status = disabled;
+ };
+
+ spi_1: spi@14d3 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d3 0x100;
+ interrupts = 0 433 0;
+ dmas = pdma0 11, pdma0 10;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI1,
+cmu_top CLK_SCLK_SPI1_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+ pinctrl-0 = spi1_bus;
+ status = disabled;
+ };
+
+ spi_2: spi@14d4 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d4 0x100;
+ interrupts = 0 434 0;
+ dmas = pdma0 13, pdma0 12;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_peric CLK_PCLK_SPI2,
+cmu_top CLK_SCLK_SPI2_PERIC;
+ clock-names = spi, spi_busclk0;
+ samsung,spi-src-clk = 0;
+ pinctrl-names = default;
+
[PATCH v4 8/8] arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC
From: Inha Song ideal.s...@samsung.com
This patch adds I2S device tree node for Exynos5433 SoC.
In Exynos5433 SoC, I2S0 is used for audio interface.
Signed-off-by: Inha Song ideal.s...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 6becaca..0776b6d 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -511,6 +511,23 @@
status = disabled;
};
+ i2s0: i2s0@1144 {
+ compatible = samsung,exynos7-i2s;
+ reg = 0x1144 0x100;
+ dmas = adma 0 adma 2;
+ dma-names = tx, rx;
+ interrupts = 0 70 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = cmu_aud CLK_PCLK_AUD_I2S,
+cmu_aud CLK_SCLK_AUD_I2S,
+cmu_aud CLK_SCLK_I2S_BCLK;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
+ status = disabled;
+ };
+
pinctrl_alive: pinctrl@1058 {
compatible = samsung,exynos5433-pinctrl;
reg = 0x1058 0x1000;
--
1.8.5.5
--
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[PATCH v4 6/8] arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC
This patch adds RTC (Real Time Clock) dt node for Exynos5433 SoC and adds
ADC dt node for Exynos5433 SoC. The c1b501564c98a94b4(iio: adc: exynos_adc:
Add support for exynos7) commit supports the ADC for Exynos7. Exynos5433's ADC
IP is the same with Exynos7's ADC IP. Exynos5433 has a little different from
ADCv2 on ADC_CON2 register. Exynos5433 don't contain OSEL/ESEL /HIGHF of
ADC_CON2.
Cc: Kukjin Kim kg...@kernel.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 84be8e2..1c68d9e 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -852,6 +852,24 @@
clocks = xxti;
};
+ rtc: rtc@1059 {
+ compatible = samsung,exynos3250-rtc;
+ reg = 0x1059 0x100;
+ interrupts = 0 385 0, 0 386 0;
+ status = disabled;
+ };
+
+ adc: adc@14d1 {
+ compatible = samsung,exynos7-adc;
+ reg = 0x14d1 0x100;
+ interrupts = 0 438 0;
+ clock-names = adc;
+ clocks = cmu_peric CLK_PCLK_ADCIF;
+ #io-channel-cells = 1;
+ io-channel-ranges;
+ status = disabled;
+ };
+
timer {
compatible = arm,armv8-timer;
interrupts = 1 13 0xff04,
--
1.8.5.5
--
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