Re: [PATCH v2] ARM: EXYNOS: Fix failed second suspend on Exynos4
On śro, 2015-03-18 at 03:05 +0900, Kukjin Kim wrote: On 03/11/15 19:29, Krzysztof Kozlowski wrote: On śro, 2015-03-11 at 11:20 +0100, Krzysztof Kozlowski wrote: On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in 56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller) the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off) Cc: sta...@vger.kernel.org Tested-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Tested-by: Chanwoo Choi cw00.c...@samsung.com Dear Kukjin, This patch was first sent on 3rd of February. It could enter before opening 4.0 merge window. I did not receive any response from you in that time. So let me point next steps: 1. The Exynos4412 suspend on 4.0 is broken and now this patch applies as a fix. 2. I resent it on 18th of February. 3. I received tested-by from Bartlomiej and Chanwoo. 4. Bartlomiej pinged you on 3rd March. Still no response. If the patch does not look good then please share your comments. I'll fix it. If this patch looks good, why does it take so much time? Please use another way something like check ARM core rather than use 'soc_is_xxx()', as you know it is not acceptable now even it is just moving/modifying exist function though. Probably of_machine_is_compatible() could be used here but such change should be done in separate patch. This is fix for wrong usage of use_delayed_assertion so it should not mix with other changes in the code. This fixes one thing at a time. Fixing many things in one patch often leads to new errors or difficulties in debugging. I can prepare a separate patch for changing this to of_machine_is_compatible(). And please make sure your updates don't hurt other exynos5 stuff. Any tests on exynos5 platforms would be helpful. And I don't think the fix should be sent to 'stable' because I can't see the 'add node for L2$ controller' in v3.19...looks applied from v4.0-rc... You're right. git-describe gave me 3.19-rc1 but this was tag for the specific commit, not for merge-commit. The stable can be removed if this comes during this RC-cycle. One more if you have any doubts, I'd like to ask you to contact S.LSI guys who have created the vendor codes not assume with the code because maybe the vendor code you mentioned cannot cover all exynos stuff I think. Then we could make more clear pm codes in mainline. To be honest I'm not a Power Management hardware guy so I don't know every regarding PM stuff in exynos SoCs, I can contact them easier though...I mean please don't assume any hardware behavior with just vendor code. Please ask, you have an access in Samsung intranet before posting something like this...Hope let's make a better fix together during -rc. As you probably know I work in completely different company within Samsung Electronics than System LSI. I don't have access to the LSI intranet. I don't have access to guys from LSI. I'll try contacting them through my HQ partners. Thanks for feedback! Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: EXYNOS: Fix failed second suspend on Exynos4
Hi, On Wednesday, March 18, 2015 09:57:27 AM Krzysztof Kozlowski wrote: On śro, 2015-03-18 at 03:05 +0900, Kukjin Kim wrote: On 03/11/15 19:29, Krzysztof Kozlowski wrote: On śro, 2015-03-11 at 11:20 +0100, Krzysztof Kozlowski wrote: On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in 56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller) the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off) Cc: sta...@vger.kernel.org Tested-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Tested-by: Chanwoo Choi cw00.c...@samsung.com Dear Kukjin, This patch was first sent on 3rd of February. It could enter before opening 4.0 merge window. I did not receive any response from you in that time. So let me point next steps: 1. The Exynos4412 suspend on 4.0 is broken and now this patch applies as a fix. 2. I resent it on 18th of February. 3. I received tested-by from Bartlomiej and Chanwoo. 4. Bartlomiej pinged you on 3rd March. Still no response. If the patch does not look good then please share your comments. I'll fix it. If this patch looks good, why does it take so much time? Please use another way something like check ARM core rather than use 'soc_is_xxx()', as you know it is not acceptable now even it is just moving/modifying exist function though. Kukjin, could you please explain why 'soc_is_xxx()' usage inside arch/arm/mach-exynos/ code is not acceptable? I know that it should not be used outisde of this directory because of multiplatform support but what is wrong with using it for arch/arm/mach-exynos/ code? I'm also not sure if -rc4 is a desirable time to be doing such changes (especially given that the patch in question is moving an existing code, not adding new 'soc_is_xxx()' users). [ Moreover of_machine_is_compatible() can be sometimes harmful as could have been seen in commit ca489c58ef0b81 (ARM: EXYNOS: Don't use LDREX and STREX after disabling cache coherency fix. ] Probably of_machine_is_compatible() could be used here but such change should be done in separate patch. This is fix for wrong usage of use_delayed_assertion so it should not mix with other changes in the code. This fixes one thing at a time. Fixing many things in one patch often leads to new errors or difficulties in debugging. I can prepare a separate patch for changing this to of_machine_is_compatible(). IMHO this would be the best solution if there is an agreement on 'soc_is_xxx()' removal. And please make sure your updates don't hurt other exynos5 stuff. Any tests on exynos5 platforms would be helpful. The patch is quite obvious and only affects Exynos4 SoCs. Extra testing on Exynos5 SoCs won't hurt but they should not be required for merge. And I don't think the fix should be sent to 'stable' because I can't see the 'add node for L2$ controller' in v3.19...looks applied from v4.0-rc... You're right. git-describe gave me 3.19-rc1 but this was tag for the specific commit, not for merge-commit. The stable can be removed if this comes during this RC-cycle. Yes, the stable tag was a mistake and should be removed. One more if you have any doubts, I'd like to ask you to contact S.LSI guys who have created the vendor codes not assume with the code because maybe the vendor code you mentioned cannot cover all exynos stuff I think. Then we could make more clear pm codes in mainline. To be honest I'm not a Power Management hardware guy so I don't know every regarding PM stuff in exynos SoCs, I can contact them easier though...I mean please don't assume any hardware behavior with just vendor code. Please ask, you have an access in Samsung intranet before posting something like this...Hope let's make a better fix together during -rc. FWIW I think that -rc4 is too late to be doing 'perfect patch' (we've waited for 6 weeks on any feedback on this patch from you). The current solution is quite simple and has been tested to fix the regression without introducing other
Re: exynos5800-peach-pi: suspend/resume (still) broken
+people involved in Exynos5420 S2R support (Abhilash, Vikas and Pankaj) Hello Kevin, On 03/17/2015 06:35 PM, Kevin Hilman wrote: I've tried suspend/resume on peach-pi using v4.0-rc4, next/master and samsung/for-next, and it doesn't seem to work on any of them. The first problem was the exynos DRM driver is faulting so I had to set CONFIG_\ DRM_EXYNOS=n for testing in mainline, this is fixed in -next. Note that RTC wake from suspend to idle seems to work, which suggests that the RTC wake alarms are working fine. I tried with both the s3c and the max77802 RTC drivers (e.g. rtcwake -d rtc0 -m freeze -s4) Indeed, both max77802 and S3C RTCs wake alarm IRQ are being triggered: # echo +1 /sys/class/rtc/rtc0/wakealarm # echo +1 /sys/class/rtc/rtc1/wakealarm # grep alarm /proc/interrupts 62: 1 0 0 0 PMU 43 s3c2410-rtc alarm 124: 0 0 1 0 max77802-rtc 1 rtc-alarm1 and also as you said suspend-to-idle and resume works: # echo +5 /sys/class/rtc/rtc1/wakealarm echo freeze /sys/power/state However, trying suspend to RAM (rtcwake -d rtc0 -m mem -s4), it never resumes, and adding no_console_suspend doesn't give anything useful. Anyone else having better luck with suspend/resume on peach-pi? # echo +2 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state Suspend and CPUs shutdown seems to succeed according to [0] but the system never wakes up... I also tried to wakeup the system with the keyboard and the trackpad that is a wake up source but it does not work either. I remember that when the 5420 s2r support series were posted, aclk200_disp1 and aclk300_disp1 clocks needed to be marked as CLK_IGNORE_UNUSED but afaiu that was only because display support was not yet merged but it is now. I tried anyways both marking those clocks as CLK_IGNORE_UNUSED and passing the clk_ignore_unused to the kernel command line but did not work either. Abhilash, Vikas, Pankaj, Any ideas of what could be causing this regression? It seems that by the time the Exynos5420 S2R support landed in mainline, it was already not working which makes it hard to bisect what caused the issue. I also tried on exynos5422-odroid-xu3, but that doesn't seem to have any working RTC drivers. :( Kevin Best regards, Javier [0]: [ 517.448354] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 517.453827] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 517.547922] wake enabled for irq 123 [ 517.551373] wake enabled for irq 120 [ 518.285645] wake enabled for irq 129 [ 518.287762] wake enabled for irq 130 [ 518.291901] PM: suspend of devices complete after 827.494 msecs [ 518.297218] ldo_35: No configuration [ 518.300769] ldo_34: No configuration [ 518.304327] ldo_33: No configuration [ 518.307899] ldo_32: No configuration [ 518.311513] ldo_29: No configuration [ 518.315000] ldo_28: No configuration [ 518.318554] ldo_27: No configuration [ 518.322090] ldo_26: No configuration [ 518.325667] ldo_25: No configuration [ 518.329224] ldo_24: No configuration [ 518.332780] ldo_23: No configuration [ 518.336317] ldo_21: No configuration [ 518.339894] ldo_20: No configuration [ 518.343451] ldo_19: No configuration [ 518.346988] ldo_18: No configuration [ 518.351369] vdd_1v8_7: No configuration [ 518.354739] vdd_1v2_2: No configuration [ 518.362718] PM: late suspend of devices complete after 3.781 msecs [ 518.371062] PM: noirq suspend of devices complete after 3.631 msecs [ 518.375863] Disabling non-boot CPUs ... [ 518.380035] IRQ50 no longer affine to CPU1 [ 518.380266] CPU1: shutdown [ 518.399253] IRQ51 no longer affine to CPU2 [ 518.399472] CPU2: shutdown [ 518.418914] IRQ52 no longer affine to CPU3 [ 518.419121] CPU3: shutdown -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v12 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hello Thomas, On Tue, Feb 17, 2015 at 9:25 PM, Tobias Jakobi liquid.a...@gmx.net wrote: Hello! Lukasz Majewski wrote: Hi Krzysztof, Thomas, 2015-01-08 22:17 GMT+01:00 Kevin Hilman khil...@kernel.org: Hi Thomas, Do you plan to continue with this work? It would be very helpful. +1 from me. I also wonder if Exynos 4412 could be re-added (without the boost if these bindings are not ready)? I would prefer to have all platforms converted at once, since it might happen that some parts of the work would get lost. Joining in as well! Reviving this patch series would be very much appreciated, especially if it moves again into the direction of storing most information into the DT (so that one can easily modify it in the board dts). With best wishes, Tobias As others stated, it would be very useful to get this patch-set in but the current version has some issues as Kevin mentioned. Are you planning to continue working on this series? Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 Resend] pwm: samsung: Fix output race on disabling
On Wed, 2015-03-18 at 09:08 +0100, Lukasz Majewski wrote:
Hi Sjoerd,
Hey Jingoo, Kukjijn, Lukasz,
Pinging on this one again, could you please review this patch so it
can be merged through the PWM tree?
As fair as I remember, I've already acked the patch :-)
I don't think you did, but i might have missed it ofcourse. Seems
patchwork also missed it though:
https://patchwork.ozlabs.org/patch/446643/
Mind redoing you're acked-by so it gets picked up by patchwork ? :)
On Thu, 2015-03-05 at 09:14 +0100, Sjoerd Simons wrote:
When disabling the samsung PWM the output state remains at the
level it was in the end of a pwm cycle. In other words, calling
pwm_disable when at 100% duty will keep the output active, while at
all other setting the output will go/stay inactive. On top of that
the samsung PWM settings are double-buffered, which means the new
settings only get applied at the start of a new PWM cycle.
This results in a race if the PWM is at 100% duty and a driver
calls: pwm_config (pwm, 0, period);
pwm_disable (pwm);
In this case the PWMs output will unexpectedly stay active, unless
a new PWM cycle happened to start between the register writes in
_config and _disable. As far as i can tell this is a regression
introduced by 3bdf878, before that a call to pwm_config would call
pwm_samsung_enable which, while heavy-handed, made sure the
expected settings were live.
To resolve this, while not re-introducing the issues 3bdf878
(flickering as the PWM got reset while in a PWM cycle). Only force
an update of the settings when at 100% duty, which shouldn't have a
noticeable effect on the output but is enough to ensure the
behaviour is as expected on disable.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes since v1:
Fix small issues pointed out by Tomasz Figa
- Correct various coding style issues
- Read the current value of the tcmp register for comparison
rather then using a non-trivial comparison to decide whether the
current state was 100% duty
- Move the code to force manual update out into its own function
- Clarify the comment indicating why a manual update is sometimes
required
drivers/pwm/pwm-samsung.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c
index 3e9b583..649f6c4 100644
--- a/drivers/pwm/pwm-samsung.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -269,12 +269,31 @@ static void pwm_samsung_disable(struct
pwm_chip *chip, struct pwm_device *pwm)
spin_unlock_irqrestore(samsung_pwm_lock, flags); }
+static void pwm_samsung_manual_update(struct samsung_pwm_chip
*chip,
+ struct pwm_device *pwm)
+{
+ unsigned int tcon_chan = to_tcon_channel(pwm-hwpwm);
+ u32 tcon;
+ unsigned long flags;
+
+ spin_lock_irqsave(samsung_pwm_lock, flags);
+
+ tcon = readl(chip-base + REG_TCON);
+ tcon |= TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ tcon = ~TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ spin_unlock_irqrestore(samsung_pwm_lock, flags);
+}
+
static int pwm_samsung_config(struct pwm_chip *chip, struct
pwm_device *pwm, int duty_ns, int period_ns)
{
struct samsung_pwm_chip *our_chip =
to_samsung_pwm_chip(chip); struct samsung_pwm_channel *chan =
pwm_get_chip_data(pwm);
- u32 tin_ns = chan-tin_ns, tcnt, tcmp;
+ u32 tin_ns = chan-tin_ns, tcnt, tcmp, oldtcmp;
/*
* We currently avoid using 64bit arithmetic by using the
@@ -288,6 +307,7 @@ static int pwm_samsung_config(struct pwm_chip
*chip, struct pwm_device *pwm, return 0;
tcnt = readl(our_chip-base + REG_TCNTB(pwm-hwpwm));
+ oldtcmp = readl(our_chip-base + REG_TCMPB(pwm-hwpwm));
/* We need tick count for calculation, not last tick. */
++tcnt;
@@ -335,6 +355,15 @@ static int pwm_samsung_config(struct pwm_chip
*chip, struct pwm_device *pwm, writel(tcnt, our_chip-base +
REG_TCNTB(pwm-hwpwm)); writel(tcmp, our_chip-base +
REG_TCMPB(pwm-hwpwm));
+ /* In case the PWM is currently at 100% duty, force a
manual update
+ * to prevent the signal staying high in the pwm is
disabled shortly
+ * afer this update (before it autoreloaded the new
values) .
+ */
+ if (oldtcmp == (u32) -1) {
+ dev_dbg(our_chip-chip.dev, Forcing manual
update);
+ pwm_samsung_manual_update(our_chip, pwm);
+ }
+
chan-period_ns = period_ns;
chan-tin_ns = tin_ns;
chan-duty_ns = duty_ns;
--
Sjoerd Simons sjoerd.sim...@collabora.co.uk
Collabora Ltd.
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Re: [PATCH v2] ARM: EXYNOS: Fix failed second suspend on Exynos4
Hi, On Wednesday, March 18, 2015 10:47:44 AM Krzysztof Kozlowski wrote: On śro, 2015-03-18 at 09:57 +0100, Krzysztof Kozlowski wrote: On śro, 2015-03-18 at 03:05 +0900, Kukjin Kim wrote: On 03/11/15 19:29, Krzysztof Kozlowski wrote: On śro, 2015-03-11 at 11:20 +0100, Krzysztof Kozlowski wrote: On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in 56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller) the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off) Cc: sta...@vger.kernel.org Tested-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Tested-by: Chanwoo Choi cw00.c...@samsung.com (...) And please make sure your updates don't hurt other exynos5 stuff. Any tests on exynos5 platforms would be helpful. And I don't think the fix should be sent to 'stable' because I can't see the 'add node for L2$ controller' in v3.19...looks applied from v4.0-rc... You're right. git-describe gave me 3.19-rc1 but this was tag for the specific commit, not for merge-commit. The stable can be removed if this comes during this RC-cycle. Actually the fixes tag is for commit introducing wrong usage of use_delayed_reset_assertion which was merged for 3.19. Although mentioned bug (failed second to RAM) is observable only after enabling L2 cache, the fix is for original commit. IMHO fixes tag should be for L2 cache commit not for use delayed reset assertion one. Without L2 cache being enabled the delayed reset assertion code worked fine (even though in theory it was wrong). I have also other proposal: what about reverting the commit 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off)? It will introduce minor issue (CPU idle clock down will stop to work after CPU hot unplug) but the main problem with suspend to RAM will be fixed. Please don't do that. We should not replace one regression with the other one. If you want to revert something it would be better to revert the patch adding L2 cache nodes for Exynos4 SoCs for now. However we should not be reverting anything IMO. The regression fix patch is simple and is working. I would really prefer to have it applied now (to fix suspend and cpuidle v4.0-rc1 regressions finally and not keep code broken for months as we do now). We can always revisit it to something more 'perfect' later when we have more data. Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7] ARM: dts: Add HS400 support for exynos5420 and exynos5800
From: Seungwon Jeon tgih@samsung.com
HS400 timing values are added for SMDK5420, exynos5420-peach-pit
and exynos5800-peach-pi boards.
This also adds RCLK GPIO line, this gpio should be in pull-down
state.
This also enables HS400 on peach-pi and this updates the clock frequency
to 800MHz to be set as input clock to controller.
Signed-off-by: Seungwon Jeon tgih@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
[Alim: addressed review comments]
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
---
Changes in V7:
Add back bus1 pin, which was removed during rebase in v6
as rightly pointed out by Javier[1].
Changes in V6:
Rebased on kukjin's for-next branch[0]
(commit: 77105c8 Merge branch 'v4.0-samsung-fixes-2' into for-next)
[0]: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
[1]: http://www.spinics.net/lists/arm-kernel/msg406618.html
arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +++-
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 5 -
arch/arm/boot/dts/exynos5800-peach-pi.dts | 7 +--
4 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 3f4e2fe..0788d08 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -699,8 +699,10 @@
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 0 4;
samsung,dw-mshc-ddr-timing = 0 2;
+ samsung,dw-mshc-hs400-timing = 0 2;
+ samsung,read-strobe-delay = 90;
pinctrl-names = default;
- pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8 sd0_rclk;
bus-width = 8;
};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index ba686e4..8b15316 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -201,6 +201,13 @@
samsung,pin-drv = 3;
};
+ sd0_rclk: sd0-rclk {
+ samsung,pins = gpc0-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 3;
+ };
+
sd1_cmd: sd1-cmd {
samsung,pins = gpc1-1;
samsung,pin-function = 2;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 7a56852..9103f23 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -80,8 +80,11 @@
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 0 4;
samsung,dw-mshc-ddr-timing = 0 2;
+ samsung,dw-mshc-hs400-timing = 0 2;
+ samsung,read-strobe-delay = 90;
pinctrl-names = default;
- pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8
+sd0_rclk;
bus-width = 8;
cap-mmc-highspeed;
};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index c833bac..412f41d 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -654,15 +654,18 @@
num-slots = 1;
broken-cd;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
cap-mmc-highspeed;
non-removable;
card-detect-delay = 200;
- clock-frequency = 4;
+ clock-frequency = 8;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 0 4;
samsung,dw-mshc-ddr-timing = 0 2;
+ samsung,dw-mshc-hs400-timing = 0 2;
+ samsung,read-strobe-delay = 90;
pinctrl-names = default;
- pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8 sd0_rclk;
bus-width = 8;
};
--
1.9.1
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Re: [PATCH v2 Resend] pwm: samsung: Fix output race on disabling
Hi Sjoerd,
Hey Jingoo, Kukjijn, Lukasz,
Pinging on this one again, could you please review this patch so it
can be merged through the PWM tree?
As fair as I remember, I've already acked the patch :-)
On Thu, 2015-03-05 at 09:14 +0100, Sjoerd Simons wrote:
When disabling the samsung PWM the output state remains at the
level it was in the end of a pwm cycle. In other words, calling
pwm_disable when at 100% duty will keep the output active, while at
all other setting the output will go/stay inactive. On top of that
the samsung PWM settings are double-buffered, which means the new
settings only get applied at the start of a new PWM cycle.
This results in a race if the PWM is at 100% duty and a driver
calls: pwm_config (pwm, 0, period);
pwm_disable (pwm);
In this case the PWMs output will unexpectedly stay active, unless
a new PWM cycle happened to start between the register writes in
_config and _disable. As far as i can tell this is a regression
introduced by 3bdf878, before that a call to pwm_config would call
pwm_samsung_enable which, while heavy-handed, made sure the
expected settings were live.
To resolve this, while not re-introducing the issues 3bdf878
(flickering as the PWM got reset while in a PWM cycle). Only force
an update of the settings when at 100% duty, which shouldn't have a
noticeable effect on the output but is enough to ensure the
behaviour is as expected on disable.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes since v1:
Fix small issues pointed out by Tomasz Figa
- Correct various coding style issues
- Read the current value of the tcmp register for comparison
rather then using a non-trivial comparison to decide whether the
current state was 100% duty
- Move the code to force manual update out into its own function
- Clarify the comment indicating why a manual update is sometimes
required
drivers/pwm/pwm-samsung.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c
index 3e9b583..649f6c4 100644
--- a/drivers/pwm/pwm-samsung.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -269,12 +269,31 @@ static void pwm_samsung_disable(struct
pwm_chip *chip, struct pwm_device *pwm)
spin_unlock_irqrestore(samsung_pwm_lock, flags); }
+static void pwm_samsung_manual_update(struct samsung_pwm_chip
*chip,
+ struct pwm_device *pwm)
+{
+ unsigned int tcon_chan = to_tcon_channel(pwm-hwpwm);
+ u32 tcon;
+ unsigned long flags;
+
+ spin_lock_irqsave(samsung_pwm_lock, flags);
+
+ tcon = readl(chip-base + REG_TCON);
+ tcon |= TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ tcon = ~TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ spin_unlock_irqrestore(samsung_pwm_lock, flags);
+}
+
static int pwm_samsung_config(struct pwm_chip *chip, struct
pwm_device *pwm, int duty_ns, int period_ns)
{
struct samsung_pwm_chip *our_chip =
to_samsung_pwm_chip(chip); struct samsung_pwm_channel *chan =
pwm_get_chip_data(pwm);
- u32 tin_ns = chan-tin_ns, tcnt, tcmp;
+ u32 tin_ns = chan-tin_ns, tcnt, tcmp, oldtcmp;
/*
* We currently avoid using 64bit arithmetic by using the
@@ -288,6 +307,7 @@ static int pwm_samsung_config(struct pwm_chip
*chip, struct pwm_device *pwm, return 0;
tcnt = readl(our_chip-base + REG_TCNTB(pwm-hwpwm));
+ oldtcmp = readl(our_chip-base + REG_TCMPB(pwm-hwpwm));
/* We need tick count for calculation, not last tick. */
++tcnt;
@@ -335,6 +355,15 @@ static int pwm_samsung_config(struct pwm_chip
*chip, struct pwm_device *pwm, writel(tcnt, our_chip-base +
REG_TCNTB(pwm-hwpwm)); writel(tcmp, our_chip-base +
REG_TCMPB(pwm-hwpwm));
+ /* In case the PWM is currently at 100% duty, force a
manual update
+* to prevent the signal staying high in the pwm is
disabled shortly
+* afer this update (before it autoreloaded the new
values) .
+*/
+ if (oldtcmp == (u32) -1) {
+ dev_dbg(our_chip-chip.dev, Forcing manual
update);
+ pwm_samsung_manual_update(our_chip, pwm);
+ }
+
chan-period_ns = period_ns;
chan-tin_ns = tin_ns;
chan-duty_ns = duty_ns;
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [PATCH v2] ARM: EXYNOS: Fix failed second suspend on Exynos4
On śro, 2015-03-18 at 09:57 +0100, Krzysztof Kozlowski wrote: On śro, 2015-03-18 at 03:05 +0900, Kukjin Kim wrote: On 03/11/15 19:29, Krzysztof Kozlowski wrote: On śro, 2015-03-11 at 11:20 +0100, Krzysztof Kozlowski wrote: On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in 56b60b8bce4a (ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller) the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Fixes: 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off) Cc: sta...@vger.kernel.org Tested-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Tested-by: Chanwoo Choi cw00.c...@samsung.com (...) And please make sure your updates don't hurt other exynos5 stuff. Any tests on exynos5 platforms would be helpful. And I don't think the fix should be sent to 'stable' because I can't see the 'add node for L2$ controller' in v3.19...looks applied from v4.0-rc... You're right. git-describe gave me 3.19-rc1 but this was tag for the specific commit, not for merge-commit. The stable can be removed if this comes during this RC-cycle. Actually the fixes tag is for commit introducing wrong usage of use_delayed_reset_assertion which was merged for 3.19. Although mentioned bug (failed second to RAM) is observable only after enabling L2 cache, the fix is for original commit. I have also other proposal: what about reverting the commit 13cfa6c4f7fa (ARM: EXYNOS: Fix CPU idle clock down after CPU off)? It will introduce minor issue (CPU idle clock down will stop to work after CPU hot unplug) but the main problem with suspend to RAM will be fixed. Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6] ARM: dts: Add HS400 support for exynos5420 and exynos5800
Hello Alim, On Wed, Mar 18, 2015 at 4:08 AM, Alim Akhtar alim.akh...@samsung.com wrote: From: Seungwon Jeon tgih@samsung.com HS400 timing values are added for SMDK5420, exynos5420-peach-pit and exynos5800-peach-pi boards. This also adds RCLK GPIO line, this gpio should be in pull-down state. This also enables HS400 on peach-pi and this updates the clock frequency to 800MHz to be set as input clock to controller. Signed-off-by: Seungwon Jeon tgih@samsung.com Signed-off-by: Alim Akhtar alim.akh...@samsung.com [Alim: addressed review comments] Acked-by: Jaehoon Chung jh80.ch...@samsung.com --- Changes in V6: Rebased on kukjin's for-next branch[0] (commit: 77105c8 Merge branch 'v4.0-samsung-fixes-2' into for-next) [0]: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +++- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 4 +++- arch/arm/boot/dts/exynos5800-peach-pi.dts | 7 +-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index d0ee55f..e158861 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -695,8 +695,10 @@ samsung,dw-mshc-ciu-div = 3; samsung,dw-mshc-sdr-timing = 0 4; samsung,dw-mshc-ddr-timing = 0 2; + samsung,dw-mshc-hs400-timing = 0 2; + samsung,read-strobe-delay = 90; pinctrl-names = default; - pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8; + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk; Why are you removing the sd0_bus1 pinctrl here? Same comment for the other boards. This will cause a regression if the XMMCnDATA[0] pad was not mux'ed as SD_n_DATA[0] by the bootloader. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: samsung: Enable SND_SIMPLE_CARD for Odroid X2/U3
Odroid X2/U3 sound support can now be specified in device tree using the simple card binding, make SND_SOC_ODROIDX2 select SND_SIMPLE_CARD to ensure there are always required drivers in place. Reported-by: Tobias Jakobi liquid.a...@gmx.net Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com --- sound/soc/samsung/Kconfig |1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig index 0632a36..25caadf 100644 --- a/sound/soc/samsung/Kconfig +++ b/sound/soc/samsung/Kconfig @@ -226,6 +226,7 @@ config SND_SOC_ODROIDX2 depends on SND_SOC_SAMSUNG I2C select SND_SOC_MAX98090 select SND_SAMSUNG_I2S + select SND_SIMPLE_CARD help Say Y here to enable audio support for the Odroid-X2/U3. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/5] cpuidle: exynos: add coupled cpuidle support for Exynos3250
Hi, The following patchset adds coupled cpuidle support for Exynos3250 to an existing cpuidle-exynos driver. As a result it enables AFTR mode to be used by default on Exynos3250 without the need to hot unplug CPU1 first. The patchset depends on: - for-next branch (commit: 77105c882ba6) of linux-samsung.git kernel tree - [PATCH] ARM: EXYNOS: Fix failed second suspend on Exynos4 (https://lkml.org/lkml/2015/2/3/481) - [PATCH v3 0/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250 (https://lkml.org/lkml/2015/3/18/282) Changes since v1: - rebased on top of for-next branch (commit: 77105c882ba6) of linux-samsung.git kernel tree Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (5): ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: add exynos_get_boot_addr() helper cpuidle: exynos: add coupled cpuidle support for Exynos3250 arch/arm/include/asm/firmware.h | 4 ++ arch/arm/mach-exynos/common.h | 4 +- arch/arm/mach-exynos/exynos.c | 3 +- arch/arm/mach-exynos/firmware.c | 18 + arch/arm/mach-exynos/platsmp.c | 86 - arch/arm/mach-exynos/pm.c | 51 6 files changed, 129 insertions(+), 37 deletions(-) -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/4] ARM: EXYNOS: fix CPU1 hotplug for AFTR mode on Exynos3250
Hi,
On Wednesday, March 18, 2015 02:10:31 PM Krzysztof Kozlowski wrote:
2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com:
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/regs-pmu.h | 2 ++
2 files changed, 22 insertions(+), 3 deletions(-)
Looks good (except one nit below) and this also fixes hotplug issues
during resume from S2R:
$ echo mem /sys/power/state
[ 156.517266] Disabling non-boot CPUs ...
[ 156.517781] IRQ18 no longer affine to CPU1
[ 156.518043] CPU1: shutdown
[ 156.544718] Enabling non-boot CPUs ...
[ 156.554925] CPU1: Software reset
[ 158.552631] CPU1: failed to come online
[ 158.552753] Error taking CPU1 up: -5
Reviewed and tested on Rinato (Gear 2/Exynos 3250) board:
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Tested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Thank you!
One comment below...
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d2e9f12..ebd135b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,6 +126,8 @@ static inline void platform_do_lowpower(unsigned int
cpu, int *spurious)
*/
void exynos_cpu_power_down(int cpu)
{
+ u32 core_conf;
+
if (cpu == 0 (soc_is_exynos5420() || soc_is_exynos5800())) {
/*
* Bypass power down for CPU0 during suspend. Check for
@@ -137,7 +139,10 @@ void exynos_cpu_power_down(int cpu)
if (!(val S5P_CORE_LOCAL_PWR_EN))
return;
}
- pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+
+ core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ core_conf = ~S5P_CORE_LOCAL_PWR_EN;
+ pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -148,7 +153,12 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
+
+ if (soc_is_exynos3250())
+ core_conf |= S5P_CORE_AUTOWAKEUP_EN;
+
+ pmu_raw_writel(core_conf,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
@@ -226,6 +236,10 @@ static void exynos_core_restart(u32 core_id)
if (!of_machine_is_compatible(samsung,exynos3250))
return;
+ while (!pmu_raw_readl(S5P_PMU_SPARE2))
+ udelay(10);
+ udelay(10);
We really need to start documenting this. Please add short description
why this SPARE2 check is here and who uses it. Without documenting
this behavior future generations won't be able to debug this stuff.
Imagine replacing sboot with uboot by someone...
I've already planned to do this for this code and for coupled cpuidle
use of SPARE2 as well. However I would really prefer to do it in
an incremental patch if there are no other issues with this patchset.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [PATCH] ASoC: samsung: Enable SND_SIMPLE_CARD for Odroid X2/U3
On Wed, Mar 18, 2015 at 11:52:19AM +0100, Sylwester Nawrocki wrote: Odroid X2/U3 sound support can now be specified in device tree using the simple card binding, make SND_SOC_ODROIDX2 select SND_SIMPLE_CARD to ensure there are always required drivers in place. No, this isn't an actual dependency so it shouldn't be in Kconfig. signature.asc Description: Digital signature
[PATCH v3 3/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 8 +++-
arch/arm/mach-exynos/pm.c | 12 +++-
arch/arm/mach-exynos/regs-pmu.h | 1 +
arch/arm/mach-exynos/smc.h | 9 +
4 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 4791a3c..f236877 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,7 +48,13 @@ static int exynos_do_idle(unsigned long mode)
__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
sysram_ns_base_addr + 0x24);
__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
- exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
+ if (soc_is_exynos3250()) {
+ exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
+ SMC_POWERSTATE_IDLE, 0);
+ exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
+ SMC_POWERSTATE_IDLE, 0);
+ } else
+ exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
break;
case FW_DO_IDLE_SLEEP:
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 5685250..cc75ab4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -127,6 +127,8 @@ int exynos_pm_central_resume(void)
static void exynos_set_wakeupmask(long mask)
{
pmu_raw_writel(mask, S5P_WAKEUP_MASK);
+ if (soc_is_exynos3250())
+ pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
}
static void exynos_cpu_set_boot_vector(long flags)
@@ -140,7 +142,7 @@ static int exynos_aftr_finisher(unsigned long flags)
{
int ret;
- exynos_set_wakeupmask(0xff3e);
+ exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0xff3e);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
@@ -157,8 +159,13 @@ static int exynos_aftr_finisher(unsigned long flags)
void exynos_enter_aftr(void)
{
+ unsigned int cpuid = smp_processor_id();
+
cpu_pm_enter();
+ if (soc_is_exynos3250())
+ exynos_set_boot_flag(cpuid, C2_STATE);
+
exynos_pm_central_suspend();
if (of_machine_is_compatible(samsung,exynos4212) ||
@@ -178,6 +185,9 @@ void exynos_enter_aftr(void)
exynos_pm_central_resume();
+ if (soc_is_exynos3250())
+ exynos_clear_boot_flag(cpuid, C2_STATE);
+
cpu_pm_exit();
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 84ddce1..b761433 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -43,6 +43,7 @@
#define S5P_WAKEUP_STAT0x0600
#define S5P_EINT_WAKEUP_MASK 0x0604
#define S5P_WAKEUP_MASK0x0608
+#define S5P_WAKEUP_MASK2 0x0614
#define S5P_INFORM00x0800
#define S5P_INFORM10x0804
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index f7b82f9..27a976d 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -17,6 +17,8 @@
#define SMC_CMD_SLEEP (-3)
#define SMC_CMD_CPU1BOOT (-4)
#define SMC_CMD_CPU0AFTR (-5)
+#define SMC_CMD_SAVE (-6)
+#define SMC_CMD_SHUTDOWN (-7)
/* For CP15 Access */
#define SMC_CMD_C15RESUME (-11)
/* For L2 Cache Access */
@@ -32,4 +34,11 @@ extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32
arg3);
#endif /* __ASSEMBLY__ */
+/* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define OP_TYPE_CORE0x0
+#define OP_TYPE_CLUSTER 0x1
+
+/* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define SMC_POWERSTATE_IDLE 0x1
+
#endif
--
1.8.2.3
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[PATCH v3 1/4] ARM: EXYNOS: fix CPU1 hotplug for AFTR mode on Exynos3250
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/regs-pmu.h | 2 ++
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d2e9f12..ebd135b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,6 +126,8 @@ static inline void platform_do_lowpower(unsigned int cpu,
int *spurious)
*/
void exynos_cpu_power_down(int cpu)
{
+ u32 core_conf;
+
if (cpu == 0 (soc_is_exynos5420() || soc_is_exynos5800())) {
/*
* Bypass power down for CPU0 during suspend. Check for
@@ -137,7 +139,10 @@ void exynos_cpu_power_down(int cpu)
if (!(val S5P_CORE_LOCAL_PWR_EN))
return;
}
- pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+
+ core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ core_conf = ~S5P_CORE_LOCAL_PWR_EN;
+ pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -148,7 +153,12 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
+
+ if (soc_is_exynos3250())
+ core_conf |= S5P_CORE_AUTOWAKEUP_EN;
+
+ pmu_raw_writel(core_conf,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
@@ -226,6 +236,10 @@ static void exynos_core_restart(u32 core_id)
if (!of_machine_is_compatible(samsung,exynos3250))
return;
+ while (!pmu_raw_readl(S5P_PMU_SPARE2))
+ udelay(10);
+ udelay(10);
+
val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
@@ -346,7 +360,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
call_firmware_op(cpu_boot, core_id);
- arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+ if (soc_is_exynos3250())
+ dsb_sev();
+ else
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
if (pen_release == -1)
break;
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index eb461e1..84ddce1 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -49,6 +49,7 @@
#define S5P_INFORM50x0814
#define S5P_INFORM60x0818
#define S5P_INFORM70x081C
+#define S5P_PMU_SPARE2 0x0908
#define S5P_PMU_SPARE3 0x090C
#define EXYNOS_IROM_DATA2 0x0988
@@ -182,6 +183,7 @@
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 8)
+#define S5P_CORE_AUTOWAKEUP_EN (1 31)
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR0x1154
--
1.8.2.3
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[PATCH v3 4/4] ARM: EXYNOS: cpuidle: allow driver usage on Exynos3250 SoC
Register cpuidle platform device on Exynos3250 SoC allowing EXYNOS cpuidle driver usage on this SoC. Cc: Daniel Lezcano daniel.lezc...@linaro.org Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/exynos.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 90ed2e5..204f0e6 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -244,6 +244,7 @@ static void __init exynos_dt_machine_init(void) of_machine_is_compatible(samsung,exynos4212) || (of_machine_is_compatible(samsung,exynos4412) of_machine_is_compatible(samsung,trats2)) || + of_machine_is_compatible(samsung,exynos3250) || of_machine_is_compatible(samsung,exynos5250)) platform_device_register(exynos_cpuidle); -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/4] ARM: EXYNOS: add code for setting/clearing boot flag
This code is needed for cpuidle (W-)AFTR mode support on Exynos3250.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.h | 6 ++
arch/arm/mach-exynos/exynos.c | 25 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f70eca7..87bf1f3 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -119,6 +119,12 @@ extern void __iomem *sysram_base_addr;
extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
+/* CPU BOOT mode flag */
+#define C2_STATE (1 3)
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
+
enum {
FW_DO_IDLE_SLEEP,
FW_DO_IDLE_AFTR,
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 4031a96..90ed2e5 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -117,6 +117,31 @@ static void __init exynos_init_late(void)
exynos_pm_init();
}
+#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
+#define BOOT_MODE_MASK 0x1f
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+
+ if (mode BOOT_MODE_MASK)
+ tmp = ~BOOT_MODE_MASK;
+
+ tmp |= mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+ tmp = ~mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
int depth, void *data)
{
--
1.8.2.3
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[PATCH v2 3/5] ARM: EXYNOS: add exynos_set_boot_addr() helper
Add exynos_set_boot_addr() helper and covert existing code
(exynos_boot_secondary() and exynos_smp_prepare_cpus()) to
use it.
There should be no functional changes caused by this patch.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 53 +++---
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 6f7a1c7..b7cfcdc 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -247,6 +247,31 @@ static void exynos_secondary_init(unsigned int cpu)
spin_unlock(boot_lock);
}
+static int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
+{
+ int ret;
+
+ /*
+* Try to set boot address using firmware first
+* and fall back to boot register if it fails.
+*/
+ ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
+ if (ret ret != -ENOSYS)
+ goto fail;
+ if (ret == -ENOSYS) {
+ void __iomem *boot_reg = cpu_boot_reg(core_id);
+
+ if (IS_ERR(boot_reg)) {
+ ret = PTR_ERR(boot_reg);
+ goto fail;
+ }
+ __raw_writel(boot_addr, boot_reg);
+ ret = 0;
+ }
+fail:
+ return ret;
+}
+
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
@@ -306,22 +331,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
boot_addr = virt_to_phys(exynos4_secondary_startup);
- /*
-* Try to set boot address using firmware first
-* and fall back to boot register if it fails.
-*/
- ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
- if (ret ret != -ENOSYS)
+ ret = exynos_set_boot_addr(core_id, boot_addr);
+ if (ret)
goto fail;
- if (ret == -ENOSYS) {
- void __iomem *boot_reg = cpu_boot_reg(core_id);
-
- if (IS_ERR(boot_reg)) {
- ret = PTR_ERR(boot_reg);
- goto fail;
- }
- __raw_writel(boot_addr, boot_reg);
- }
call_firmware_op(cpu_boot, core_id);
@@ -409,16 +421,9 @@ static void __init exynos_smp_prepare_cpus(unsigned int
max_cpus)
core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
boot_addr = virt_to_phys(exynos4_secondary_startup);
- ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
- if (ret ret != -ENOSYS)
+ ret = exynos_set_boot_addr(core_id, boot_addr);
+ if (ret)
break;
- if (ret == -ENOSYS) {
- void __iomem *boot_reg = cpu_boot_reg(core_id);
-
- if (IS_ERR(boot_reg))
- break;
- __raw_writel(boot_addr, boot_reg);
- }
}
}
--
1.8.2.3
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[PATCH v2 5/5] cpuidle: exynos: add coupled cpuidle support for Exynos3250
The following patch adds coupled cpuidle support for Exynos3250 to
an existing cpuidle-exynos driver. As a result it enables AFTR mode
to be used by default on Exynos3250 without the need to hot unplug
CPU1 first.
The detailed changelog:
- use exynos_[get,set]_boot_addr() in cpuidle-exynos.c and then make
cpu_boot_reg_base() static
- use exynos_core_restart() in exynos_cpu0_enter_aftr()
- add missing smp_rmb() to exynos_cpu0_enter_aftr() (to make the code
in-sync with the platform SMP code)
- add call_firmware_op(cpu_boot, 1) to exynos_cpu0_enter_aftr()
- use dsb_sev() instead of IPI wakeup for Exynos3250 in
exynos_cpu0_enter_aftr()
- add CPU0 vs CPU1 synchronization based on S5P_PMU_SPARE2 register
for Exynos3250 to cpuidle-exynos.c
- add flush_cache_all() for CPU1/0 before powerdown/AFTR for
Exynos3250 to exynos_wfi_finisher()/exynos_do_idle()
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/mach-exynos/common.h | 4 +++-
arch/arm/mach-exynos/exynos.c | 3 ++-
arch/arm/mach-exynos/firmware.c | 1 +
arch/arm/mach-exynos/platsmp.c | 8 +++
arch/arm/mach-exynos/pm.c | 51 ++---
5 files changed, 53 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 826367f..bc515f0 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -163,7 +163,9 @@ extern void exynos_set_delayed_reset_assertion(bool enable);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
-extern void __iomem *cpu_boot_reg_base(void);
+extern void exynos_core_restart(u32 core_id);
+extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
+extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
static inline void pmu_raw_writel(u32 val, u32 offset)
{
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index ec0312b..c4a2852 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -264,7 +264,8 @@ static void __init exynos_dt_machine_init(void)
exynos_sysram_init();
#if defined(CONFIG_SMP) defined(CONFIG_ARM_EXYNOS_CPUIDLE)
- if (of_machine_is_compatible(samsung,exynos4210))
+ if (of_machine_is_compatible(samsung,exynos4210) ||
+ of_machine_is_compatible(samsung,exynos3250))
exynos_cpuidle.dev.platform_data = cpuidle_coupled_exynos_data;
#endif
if (of_machine_is_compatible(samsung,exynos4210) ||
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index c9e4481..90db46f 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -49,6 +49,7 @@ static int exynos_do_idle(unsigned long mode)
sysram_ns_base_addr + 0x24);
__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
if (soc_is_exynos3250()) {
+ flush_cache_all();
exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
SMC_POWERSTATE_IDLE, 0);
exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 449edd1..58e05a2 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -169,7 +169,7 @@ int exynos_cluster_power_state(int cluster)
S5P_CORE_LOCAL_PWR_EN);
}
-void __iomem *cpu_boot_reg_base(void)
+static void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM5;
@@ -195,7 +195,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
*
* Currently this is needed only when booting secondary CPU on Exynos3250.
*/
-static void exynos_core_restart(u32 core_id)
+void exynos_core_restart(u32 core_id)
{
u32 val;
@@ -247,7 +247,7 @@ static void exynos_secondary_init(unsigned int cpu)
spin_unlock(boot_lock);
}
-static int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
+int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
{
int ret;
@@ -272,7 +272,7 @@ fail:
return ret;
}
-static int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
+int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
{
int ret;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index cc75ab4..9c1506b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -22,6 +22,7 @@
#include asm/firmware.h
#include asm/smp_scu.h
#include asm/suspend.h
+#include asm/cacheflush.h
#include mach/map.h
@@ -209,6 +210,8 @@ static int exynos_cpu0_enter_aftr(void)
* sequence, let's wait for one of these to happen
*/
while
[PATCH v2 1/5] ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
exynos_boot_secondary() can erroneously return 0 or -ENOSYS even when waiting on pen_release being set to -1 timeouts. Fix it by adjusting ret variable value to -ETIMEDOUT when necessary. Cc: Daniel Lezcano daniel.lezc...@linaro.org Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com --- arch/arm/mach-exynos/platsmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index a825bca..48f950d 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -337,6 +337,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) udelay(10); } + if (pen_release != -1) + ret = -ETIMEDOUT; + /* * now the secondary core is starting up let it run its * calibrations, then wait for it to finish -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: The patchset itself looks good... but it's missing commit message. What benefits does the AFTR bring? Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
Hi, This patch series adds support for AFTR idle mode on boards with Exynos3250 SoC and allows EXYNOS cpuidle driver usage on these boards. It has been tested on Samsung Rinato board (Gear 2). Depends on: - for-next branch (commit: 77105c882ba6) of linux-samsung.git kernel tree Changes since v2: - rebased on top of for-next branch (commit: 77105c882ba6) of linux-samsung.git kernel tree Changes since v1: - rebased on top of for-next branch (commit: ce275c369a0b) of linux-samsung.git kernel tree - fixed lockup on hotplug by using dsb_sev() instead of IPI in exynos_boot_secondary() on Exynos3250 Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (4): ARM: EXYNOS: fix CPU1 hotplug for AFTR mode on Exynos3250 ARM: EXYNOS: add code for setting/clearing boot flag ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250 ARM: EXYNOS: cpuidle: allow driver usage on Exynos3250 SoC arch/arm/mach-exynos/common.h | 6 ++ arch/arm/mach-exynos/exynos.c | 26 ++ arch/arm/mach-exynos/firmware.c | 8 +++- arch/arm/mach-exynos/platsmp.c | 23 --- arch/arm/mach-exynos/pm.c | 12 +++- arch/arm/mach-exynos/regs-pmu.h | 3 +++ arch/arm/mach-exynos/smc.h | 9 + 7 files changed, 82 insertions(+), 5 deletions(-) -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] ARM: EXYNOS: add code for setting/clearing boot flag
2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com:
This code is needed for cpuidle (W-)AFTR mode support on Exynos3250.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.h | 6 ++
arch/arm/mach-exynos/exynos.c | 25 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f70eca7..87bf1f3 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -119,6 +119,12 @@ extern void __iomem *sysram_base_addr;
extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
+/* CPU BOOT mode flag */
+#define C2_STATE (1 3)
Is this C2_STATE like ACPI C2 state? It looks specific to Exynos3250
boot loader so maybe describe its real purpose?
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
+
enum {
FW_DO_IDLE_SLEEP,
FW_DO_IDLE_AFTR,
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 4031a96..90ed2e5 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -117,6 +117,31 @@ static void __init exynos_init_late(void)
exynos_pm_init();
}
+#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
+#define BOOT_MODE_MASK 0x1f
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+
+ if (mode BOOT_MODE_MASK)
+ tmp = ~BOOT_MODE_MASK;
+
+ tmp |= mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+ tmp = ~mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
Shouldn't these to functions be put in firmware.c? The
exynos_set_cpu_boot_addr() is there already. It would be consistent to
have them in one place.
Best regards,
Krzysztof
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Re: [rtc-s3c.c] add .needs_src_clk to s3c6410 RTC data / break exynos4
Hello Tobias, On 03/18/2015 02:00 PM, Tobias Jakobi wrote: Hello Javier, I noticed that this recent commit breaks rtc-s3c on my Odroid-X2 (Exynos4412). The exynos4 dtsi includes a rtc of type s3c6410. Hence all board files based on exynos4, and using the rtc-s3c, are now required to specific the rtc_src clock. I don't think that this is correct, since the rtc was properly working on this board before the commit. Yes, when I posted the patch [0] I mentioned that it could break rtc-s3c in Odroid boards. I'll save you one click and include it here again: I see that Exynos4 uses the same s3c6410 RTC IP version but at least the Exynos4412 Odroid boards don't define a source clock for the RTC. According to the Exynos4 documentation I've, the RTC uses XRTCXTI as its source clock so I think those boards are relying on the HW not being completely defined in DT and the clock setup by the bootloader. Maybe the check should be relaxed to make the clock optional again? The question I think is if the source clock is really optional for that IP. The rtc-s3c driver did not have support for the RTC source clock so all the boards were relying on the bootloader enabling it and the kernel not gating it. Then Chanwoo made rtc_src required in commit df9e26d093d3 (rtc: s3c: add support for RTC of Exynos3250 SoC) for all platforms since he forgot to check for .needs_src_clk and only added that field to exynos3250_rtc_data. Since the s3c6410 RTC IP in the Exynos5 needs a source clock, I added those for the Exynos5 Chromebooks in commits: 90fbb382dac5 (ARM: dts: Add rtc_src clk for s3c-rtc on exynos5250-snow) fa781ddab929 (ARM: dts: Add rtc_src clk for s3c-rtc on exynos Peach boards) Later Marek found that the RTC was not working on Odroid boards and added the check for .needs_src_clk in commit eaf3a659086e (drivers/rtc/rtc-s3c.c: fix initialization failure without rtc source clock) But didn't set the .needs_src_clk field on all the IP data structs so the RTC on Exynos5 boards broke. Since now the RTC source clock was known to the CCF and the rtc-s3c driver wouldn't grab that clock anymore, the kernel disabled that clock since it was unused. Marek's patch is correct since .needs_src_clk has to be checked but I believe it was not the right fix for the Odroid issue. The right fix IMHO is to add the RTC source clock in the DTS and not rely on the bootloader to enable it. Anyway, here's a short dmesg snip: [1.611352] s3c-rtc 1007.rtc: s3c2410_rtc: tick irq 65, alarm irq 64 [1.611430] s3c-rtc 1007.rtc: failed to find rtc source clock [1.616740] s3c-rtc: probe of 1007.rtc failed with error -2 With best wishes, Tobias Jakobi Best regards, Javier [0]: https://lkml.org/lkml/2015/2/24/388 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/4] ARM: EXYNOS: fix CPU1 hotplug for AFTR mode on Exynos3250
2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com:
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/regs-pmu.h | 2 ++
2 files changed, 22 insertions(+), 3 deletions(-)
Looks good (except one nit below) and this also fixes hotplug issues
during resume from S2R:
$ echo mem /sys/power/state
[ 156.517266] Disabling non-boot CPUs ...
[ 156.517781] IRQ18 no longer affine to CPU1
[ 156.518043] CPU1: shutdown
[ 156.544718] Enabling non-boot CPUs ...
[ 156.554925] CPU1: Software reset
[ 158.552631] CPU1: failed to come online
[ 158.552753] Error taking CPU1 up: -5
Reviewed and tested on Rinato (Gear 2/Exynos 3250) board:
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Tested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
One comment below...
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d2e9f12..ebd135b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,6 +126,8 @@ static inline void platform_do_lowpower(unsigned int cpu,
int *spurious)
*/
void exynos_cpu_power_down(int cpu)
{
+ u32 core_conf;
+
if (cpu == 0 (soc_is_exynos5420() || soc_is_exynos5800())) {
/*
* Bypass power down for CPU0 during suspend. Check for
@@ -137,7 +139,10 @@ void exynos_cpu_power_down(int cpu)
if (!(val S5P_CORE_LOCAL_PWR_EN))
return;
}
- pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+
+ core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ core_conf = ~S5P_CORE_LOCAL_PWR_EN;
+ pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -148,7 +153,12 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
+
+ if (soc_is_exynos3250())
+ core_conf |= S5P_CORE_AUTOWAKEUP_EN;
+
+ pmu_raw_writel(core_conf,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
@@ -226,6 +236,10 @@ static void exynos_core_restart(u32 core_id)
if (!of_machine_is_compatible(samsung,exynos3250))
return;
+ while (!pmu_raw_readl(S5P_PMU_SPARE2))
+ udelay(10);
+ udelay(10);
We really need to start documenting this. Please add short description
why this SPARE2 check is here and who uses it. Without documenting
this behavior future generations won't be able to debug this stuff.
Imagine replacing sboot with uboot by someone...
Best regards,
Krzysztof
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[rtc-s3c.c] add .needs_src_clk to s3c6410 RTC data / break exynos4
Hello Javier, I noticed that this recent commit breaks rtc-s3c on my Odroid-X2 (Exynos4412). The exynos4 dtsi includes a rtc of type s3c6410. Hence all board files based on exynos4, and using the rtc-s3c, are now required to specific the rtc_src clock. I don't think that this is correct, since the rtc was properly working on this board before the commit. Maybe the check should be relaxed to make the clock optional again? Anyway, here's a short dmesg snip: [1.611352] s3c-rtc 1007.rtc: s3c2410_rtc: tick irq 65, alarm irq 64 [1.611430] s3c-rtc 1007.rtc: failed to find rtc source clock [1.616740] s3c-rtc: probe of 1007.rtc failed with error -2 With best wishes, Tobias Jakobi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/4] ARM: EXYNOS: fix CPU1 hotplug for AFTR mode on Exynos3250
On śro, 2015-03-18 at 14:23 +0100, Bartlomiej Zolnierkiewicz wrote: Hi, On Wednesday, March 18, 2015 02:10:31 PM Krzysztof Kozlowski wrote: 2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: + while (!pmu_raw_readl(S5P_PMU_SPARE2)) + udelay(10); + udelay(10); We really need to start documenting this. Please add short description why this SPARE2 check is here and who uses it. Without documenting this behavior future generations won't be able to debug this stuff. Imagine replacing sboot with uboot by someone... I've already planned to do this for this code and for coupled cpuidle use of SPARE2 as well. However I would really prefer to do it in an incremental patch if there are no other issues with this patchset. OK, please do so in incremental patch. Usage of various memory regions of sysram also should be documented. In patch 2 you add usage of 0x28 + 4*cpu. The various sysrams regions are spread over different files... Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/5] ARM: EXYNOS: make exynos_core_restart() less verbose
There is a kernel message about secondary CPU bootup when exynos_core_restart() is called through CPU hotplug code-path (the only exynos_core_restart() user currently) so there is no need for an extra info on Exynos3250 SoC about software reset. This also prepares exynos_core_restart() to be re-used in coupled cpuidle code-path in the future. Cc: Daniel Lezcano daniel.lezc...@linaro.org Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com --- arch/arm/mach-exynos/platsmp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 48f950d..6f7a1c7 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -210,7 +210,6 @@ static void exynos_core_restart(u32 core_id) val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG; pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id)); - pr_info(CPU%u: Software reset\n, core_id); pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET); } -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/5] ARM: EXYNOS: add exynos_set_boot_addr() helper
2015-03-18 14:09 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: Add exynos_set_boot_addr() helper and covert existing code (exynos_boot_secondary() and exynos_smp_prepare_cpus()) to use it. There should be no functional changes caused by this patch. Cc: Daniel Lezcano daniel.lezc...@linaro.org Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com --- arch/arm/mach-exynos/platsmp.c | 53 +++--- 1 file changed, 29 insertions(+), 24 deletions(-) Looks good. Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] ARM: EXYNOS: add code for setting/clearing boot flag
On Wednesday, March 18, 2015 02:33:54 PM Krzysztof Kozlowski wrote:
2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com:
This code is needed for cpuidle (W-)AFTR mode support on Exynos3250.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.h | 6 ++
arch/arm/mach-exynos/exynos.c | 25 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f70eca7..87bf1f3 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -119,6 +119,12 @@ extern void __iomem *sysram_base_addr;
extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
+/* CPU BOOT mode flag */
+#define C2_STATE (1 3)
Is this C2_STATE like ACPI C2 state? It looks specific to Exynos3250
boot loader so maybe describe its real purpose?
According to my knowledge it is not like ACPI C2 but my knowledge is
limited since this state is not documented anywhere. I can add a comment
about it being currently limited to Exynos3250 though.
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
+
enum {
FW_DO_IDLE_SLEEP,
FW_DO_IDLE_AFTR,
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 4031a96..90ed2e5 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -117,6 +117,31 @@ static void __init exynos_init_late(void)
exynos_pm_init();
}
+#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
+#define BOOT_MODE_MASK 0x1f
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+
+ if (mode BOOT_MODE_MASK)
+ tmp = ~BOOT_MODE_MASK;
+
+ tmp |= mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+ tmp = ~mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
Shouldn't these to functions be put in firmware.c? The
exynos_set_cpu_boot_addr() is there already. It would be consistent to
have them in one place.
I can move it to firmware.c if this is desired.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [PATCH v2 4/5] ARM: EXYNOS: add exynos_get_boot_addr() helper
On śro, 2015-03-18 at 16:18 +0100, Bartlomiej Zolnierkiewicz wrote:
On Wednesday, March 18, 2015 02:43:49 PM Krzysztof Kozlowski wrote:
2015-03-18 14:09 GMT+01:00 Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com:
Add get_cpu_boot_addr() firmware operation and then
exynos_get_boot_addr() helper.
This is a preparation for adding coupled cpuidle support
for Exynos3250 SoC.
There should be no functional changes caused by this patch.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/include/asm/firmware.h | 4
arch/arm/mach-exynos/firmware.c | 17 +
arch/arm/mach-exynos/platsmp.c | 25 +
3 files changed, 46 insertions(+)
diff --git a/arch/arm/include/asm/firmware.h
b/arch/arm/include/asm/firmware.h
index 89aefe1..34c1d96 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -34,6 +34,10 @@ struct firmware_ops {
*/
int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);
/*
+* Gets boot address of specified physical CPU
+*/
+ int (*get_cpu_boot_addr)(int cpu, unsigned long *boot_addr);
+ /*
* Boots specified physical CPU
*/
int (*cpu_boot)(int cpu);
diff --git a/arch/arm/mach-exynos/firmware.c
b/arch/arm/mach-exynos/firmware.c
index f236877..c9e4481 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -104,6 +104,22 @@ static int exynos_set_cpu_boot_addr(int cpu,
unsigned long boot_addr)
return 0;
}
+static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
+{
+ void __iomem *boot_reg;
+
+ if (!sysram_ns_base_addr)
+ return -ENODEV;
+
+ boot_reg = sysram_ns_base_addr + 0x1c;
+
+ if (soc_is_exynos4412())
+ boot_reg += 4 * cpu;
+
+ *boot_addr = __raw_readl(boot_reg);
+ return 0;
+}
+
static int exynos_cpu_suspend(unsigned long arg)
{
flush_cache_all();
@@ -138,6 +154,7 @@ static int exynos_resume(void)
static const struct firmware_ops exynos_firmware_ops = {
.do_idle= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_do_idle : NULL,
.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
+ .get_cpu_boot_addr = exynos_get_cpu_boot_addr,
.cpu_boot = exynos_cpu_boot,
.suspend= IS_ENABLED(CONFIG_PM_SLEEP) ?
exynos_suspend : NULL,
.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_resume : NULL,
diff --git a/arch/arm/mach-exynos/platsmp.c
b/arch/arm/mach-exynos/platsmp.c
index b7cfcdc..449edd1 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -272,6 +272,31 @@ fail:
return ret;
}
+static int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
+{
+ int ret;
+
+ /*
+* Try to get boot address using firmware first
+* and fall back to boot register if it fails.
+*/
+ ret = call_firmware_op(get_cpu_boot_addr, core_id, boot_addr);
+ if (ret ret != -ENOSYS)
+ goto fail;
The exynos_get_cpu_boot_addr() returns ENODEV. Do you really want to
check for ENOSYS here?
Yes. When secure firmware is not present on the board the call_firmware_op()
itself returns -ENOSYS (exynos_get_cpu_boot_addr() is not called in this
case) and it needs to be handled in a special way.
Right, my mistake. Rest looks good:
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Best regards,
Krzysztof
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Re: [PATCH v2 4/5] ARM: EXYNOS: add exynos_get_boot_addr() helper
On Wednesday, March 18, 2015 02:43:49 PM Krzysztof Kozlowski wrote:
2015-03-18 14:09 GMT+01:00 Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com:
Add get_cpu_boot_addr() firmware operation and then
exynos_get_boot_addr() helper.
This is a preparation for adding coupled cpuidle support
for Exynos3250 SoC.
There should be no functional changes caused by this patch.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/include/asm/firmware.h | 4
arch/arm/mach-exynos/firmware.c | 17 +
arch/arm/mach-exynos/platsmp.c | 25 +
3 files changed, 46 insertions(+)
diff --git a/arch/arm/include/asm/firmware.h
b/arch/arm/include/asm/firmware.h
index 89aefe1..34c1d96 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -34,6 +34,10 @@ struct firmware_ops {
*/
int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);
/*
+* Gets boot address of specified physical CPU
+*/
+ int (*get_cpu_boot_addr)(int cpu, unsigned long *boot_addr);
+ /*
* Boots specified physical CPU
*/
int (*cpu_boot)(int cpu);
diff --git a/arch/arm/mach-exynos/firmware.c
b/arch/arm/mach-exynos/firmware.c
index f236877..c9e4481 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -104,6 +104,22 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned
long boot_addr)
return 0;
}
+static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
+{
+ void __iomem *boot_reg;
+
+ if (!sysram_ns_base_addr)
+ return -ENODEV;
+
+ boot_reg = sysram_ns_base_addr + 0x1c;
+
+ if (soc_is_exynos4412())
+ boot_reg += 4 * cpu;
+
+ *boot_addr = __raw_readl(boot_reg);
+ return 0;
+}
+
static int exynos_cpu_suspend(unsigned long arg)
{
flush_cache_all();
@@ -138,6 +154,7 @@ static int exynos_resume(void)
static const struct firmware_ops exynos_firmware_ops = {
.do_idle= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_do_idle : NULL,
.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
+ .get_cpu_boot_addr = exynos_get_cpu_boot_addr,
.cpu_boot = exynos_cpu_boot,
.suspend= IS_ENABLED(CONFIG_PM_SLEEP) ?
exynos_suspend : NULL,
.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_resume : NULL,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index b7cfcdc..449edd1 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -272,6 +272,31 @@ fail:
return ret;
}
+static int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
+{
+ int ret;
+
+ /*
+* Try to get boot address using firmware first
+* and fall back to boot register if it fails.
+*/
+ ret = call_firmware_op(get_cpu_boot_addr, core_id, boot_addr);
+ if (ret ret != -ENOSYS)
+ goto fail;
The exynos_get_cpu_boot_addr() returns ENODEV. Do you really want to
check for ENOSYS here?
Yes. When secure firmware is not present on the board the call_firmware_op()
itself returns -ENOSYS (exynos_get_cpu_boot_addr() is not called in this
case) and it needs to be handled in a special way.
+ if (ret == -ENOSYS) {
+ void __iomem *boot_reg = cpu_boot_reg(core_id);
+
+ if (IS_ERR(boot_reg)) {
+ ret = PTR_ERR(boot_reg);
+ goto fail;
+ }
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [PATCH v3 1/4] ARM: EXYNOS: fix CPU1 hotplug for AFTR mode on Exynos3250
On Wednesday, March 18, 2015 02:32:25 PM Krzysztof Kozlowski wrote: On śro, 2015-03-18 at 14:23 +0100, Bartlomiej Zolnierkiewicz wrote: Hi, On Wednesday, March 18, 2015 02:10:31 PM Krzysztof Kozlowski wrote: 2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: + while (!pmu_raw_readl(S5P_PMU_SPARE2)) + udelay(10); + udelay(10); We really need to start documenting this. Please add short description why this SPARE2 check is here and who uses it. Without documenting this behavior future generations won't be able to debug this stuff. Imagine replacing sboot with uboot by someone... I've already planned to do this for this code and for coupled cpuidle use of SPARE2 as well. However I would really prefer to do it in an incremental patch if there are no other issues with this patchset. OK, please do so in incremental patch. Usage of various memory regions OK. of sysram also should be documented. In patch 2 you add usage of 0x28 + 4*cpu. The various sysrams regions are spread over different files... I completely agree that there should be some Documentation file with the SYSRAM layout. I'll do it later unless someone beats me to it (please also add this to our internal TODO list of open issues, thanks!). Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
On Wednesday, March 18, 2015 02:38:26 PM Krzysztof Kozlowski wrote: 2015-03-18 13:51 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: The patchset itself looks good... but it's missing commit message. What benefits does the AFTR bring? AFTR support brings reduced energy consumption and is a prerequisite for more advanced W-AFTR/LPA power saving modes. AFTR has been already supported on other Exynos SoCs for few years so there is really no need to explain its purpose with every new SoC support addition. [ Moreover you know this all really well since we've worked together on many Exynos Power Management issues :). ] I understand that you are complaining about skimpy commit message and I can certainly improve it (however personally I think that it will not bring much benefit because the patch is rather straightforward one). Please also note that while I appreciate review comments please try to make them more substantial and bring them earlier (this patchset hasn't really changed since v1 which was posted in October 2014). Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 4/4] ARM: EXYNOS: cpuidle: allow driver usage on Exynos3250 SoC
Register cpuidle platform device on Exynos3250 SoC allowing EXYNOS cpuidle driver usage on this SoC. Cc: Daniel Lezcano daniel.lezc...@linaro.org Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/exynos.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 4031a96..a140872 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -219,6 +219,7 @@ static void __init exynos_dt_machine_init(void) of_machine_is_compatible(samsung,exynos4212) || (of_machine_is_compatible(samsung,exynos4412) of_machine_is_compatible(samsung,trats2)) || + of_machine_is_compatible(samsung,exynos3250) || of_machine_is_compatible(samsung,exynos5250)) platform_device_register(exynos_cpuidle); -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/4] ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
This patch also fixes hotplug issues during resume from S2R:
$ echo mem /sys/power/state
[ 156.517266] Disabling non-boot CPUs ...
[ 156.517781] IRQ18 no longer affine to CPU1
[ 156.518043] CPU1: shutdown
[ 156.544718] Enabling non-boot CPUs ...
[ 156.554925] CPU1: Software reset
[ 158.552631] CPU1: failed to come online
[ 158.552753] Error taking CPU1 up: -5
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Tested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/regs-pmu.h | 2 ++
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d2e9f12..ebd135b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,6 +126,8 @@ static inline void platform_do_lowpower(unsigned int cpu,
int *spurious)
*/
void exynos_cpu_power_down(int cpu)
{
+ u32 core_conf;
+
if (cpu == 0 (soc_is_exynos5420() || soc_is_exynos5800())) {
/*
* Bypass power down for CPU0 during suspend. Check for
@@ -137,7 +139,10 @@ void exynos_cpu_power_down(int cpu)
if (!(val S5P_CORE_LOCAL_PWR_EN))
return;
}
- pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+
+ core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ core_conf = ~S5P_CORE_LOCAL_PWR_EN;
+ pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -148,7 +153,12 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
+
+ if (soc_is_exynos3250())
+ core_conf |= S5P_CORE_AUTOWAKEUP_EN;
+
+ pmu_raw_writel(core_conf,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
@@ -226,6 +236,10 @@ static void exynos_core_restart(u32 core_id)
if (!of_machine_is_compatible(samsung,exynos3250))
return;
+ while (!pmu_raw_readl(S5P_PMU_SPARE2))
+ udelay(10);
+ udelay(10);
+
val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
@@ -346,7 +360,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
call_firmware_op(cpu_boot, core_id);
- arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+ if (soc_is_exynos3250())
+ dsb_sev();
+ else
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
if (pen_release == -1)
break;
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index eb461e1..84ddce1 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -49,6 +49,7 @@
#define S5P_INFORM50x0814
#define S5P_INFORM60x0818
#define S5P_INFORM70x081C
+#define S5P_PMU_SPARE2 0x0908
#define S5P_PMU_SPARE3 0x090C
#define EXYNOS_IROM_DATA2 0x0988
@@ -182,6 +183,7 @@
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 8)
+#define S5P_CORE_AUTOWAKEUP_EN (1 31)
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR0x1154
--
1.8.2.3
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[PATCH v4 2/4] ARM: EXYNOS: add code for setting/clearing boot flag
This code is needed for cpuidle (W-)AFTR mode support on Exynos3250.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.h | 6 ++
arch/arm/mach-exynos/firmware.c | 25 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f70eca7..acd5b56 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -126,6 +126,12 @@ enum {
void exynos_firmware_init(void);
+/* CPU BOOT mode flag for Exynos3250 SoC bootloader */
+#define C2_STATE (1 3)
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
+
extern u32 exynos_get_eint_wake_mask(void);
#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 4791a3c..27b8ae3 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -206,3 +206,28 @@ void __init exynos_firmware_init(void)
outer_cache.configure = exynos_l2_configure;
}
}
+
+#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
+#define BOOT_MODE_MASK 0x1f
+
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+
+ if (mode BOOT_MODE_MASK)
+ tmp = ~BOOT_MODE_MASK;
+
+ tmp |= mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ unsigned int tmp;
+
+ tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+ tmp = ~mode;
+ __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
--
1.8.2.3
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[PATCH v4 3/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
AFTR mode support brings reduced energy consumption and is
a prerequisite for more advanced W-AFTR/LPA power saving modes.
AFTR mode has been already supported on other Exynos SoCs for
few years and this patch adds its support for Exynos3250 SoC.
The differences in Exynos3250 SoC AFTR mode support when compared
to Exynos4x12 SoCs are:
- different secure firmware calls are used
- different S5P_WAKEUP_MASK wakeup mask is used
- S5P_WAKEUP_MASK2 wakeup mask needs to be set in addition to
the standard S5P_WAKEUP_MASK one
- C2_STATE BOOT mode flag needs to be set/cleared pre/post AFTR
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 8 +++-
arch/arm/mach-exynos/pm.c | 12 +++-
arch/arm/mach-exynos/regs-pmu.h | 1 +
arch/arm/mach-exynos/smc.h | 9 +
4 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 27b8ae3..1bd3576 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,7 +48,13 @@ static int exynos_do_idle(unsigned long mode)
__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
sysram_ns_base_addr + 0x24);
__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
- exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
+ if (soc_is_exynos3250()) {
+ exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
+ SMC_POWERSTATE_IDLE, 0);
+ exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
+ SMC_POWERSTATE_IDLE, 0);
+ } else
+ exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
break;
case FW_DO_IDLE_SLEEP:
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 5685250..cc75ab4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -127,6 +127,8 @@ int exynos_pm_central_resume(void)
static void exynos_set_wakeupmask(long mask)
{
pmu_raw_writel(mask, S5P_WAKEUP_MASK);
+ if (soc_is_exynos3250())
+ pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
}
static void exynos_cpu_set_boot_vector(long flags)
@@ -140,7 +142,7 @@ static int exynos_aftr_finisher(unsigned long flags)
{
int ret;
- exynos_set_wakeupmask(0xff3e);
+ exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0xff3e);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
@@ -157,8 +159,13 @@ static int exynos_aftr_finisher(unsigned long flags)
void exynos_enter_aftr(void)
{
+ unsigned int cpuid = smp_processor_id();
+
cpu_pm_enter();
+ if (soc_is_exynos3250())
+ exynos_set_boot_flag(cpuid, C2_STATE);
+
exynos_pm_central_suspend();
if (of_machine_is_compatible(samsung,exynos4212) ||
@@ -178,6 +185,9 @@ void exynos_enter_aftr(void)
exynos_pm_central_resume();
+ if (soc_is_exynos3250())
+ exynos_clear_boot_flag(cpuid, C2_STATE);
+
cpu_pm_exit();
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 84ddce1..b761433 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -43,6 +43,7 @@
#define S5P_WAKEUP_STAT0x0600
#define S5P_EINT_WAKEUP_MASK 0x0604
#define S5P_WAKEUP_MASK0x0608
+#define S5P_WAKEUP_MASK2 0x0614
#define S5P_INFORM00x0800
#define S5P_INFORM10x0804
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index f7b82f9..94180ba 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -17,6 +17,8 @@
#define SMC_CMD_SLEEP (-3)
#define SMC_CMD_CPU1BOOT (-4)
#define SMC_CMD_CPU0AFTR (-5)
+#define SMC_CMD_SAVE (-6)
+#define SMC_CMD_SHUTDOWN (-7)
/* For CP15 Access */
#define SMC_CMD_C15RESUME (-11)
/* For L2 Cache Access */
@@ -32,4 +34,11 @@ extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32
arg3);
#endif /* __ASSEMBLY__ */
+/* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define OP_TYPE_CORE0x0
+#define OP_TYPE_CLUSTER 0x1
+
+/* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define SMC_POWERSTATE_IDLE 0x1
+
#endif
--
1.8.2.3
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[PATCH v3] ARM: l2c: Maintain CPU endianness for early resume function
In big-endian CPU mode l2x0_saved_regs structure stores registers values in BE format. In order to maintain BE CPU mode, these values and immediate constants must be converted back to LE format before writing them to cache controller. Signed-off-by: Dmitry Osipenko dig...@gmail.com Acked-by: Russell King rmk+ker...@arm.linux.org.uk --- Changelog: V2: no code change, fixed patch numbering, extended mail recipients list V3: added missed register reverse for 'ldr' instructions arch/arm/mm/l2c-l2x0-resume.S | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S index fda415e4..ecb5b74 100644 --- a/arch/arm/mm/l2c-l2x0-resume.S +++ b/arch/arm/mm/l2c-l2x0-resume.S @@ -30,9 +30,19 @@ ENTRY(l2c310_early_resume) teq r1, #0 reteq lr + @ Reverse for big-endian kernel +ARM_BE8(revr2, r2) +ARM_BE8(revr3, r3) +ARM_BE8(revr4, r4) +ARM_BE8(revr5, r5) +ARM_BE8(revr6, r6) +ARM_BE8(revr7, r7) +ARM_BE8(revr8, r8) + @ The prefetch and power control registers are revision dependent @ and can be written whether or not the L2 cache is enabled ldr r0, [r1, #L2X0_CACHE_ID] +ARM_BE8(revr0, r0) and r0, r0, #L2X0_CACHE_ID_RTL_MASK cmp r0, #L310_CACHE_ID_RTL_R2P0 strcs r7, [r1, #L310_PREFETCH_CTRL] @@ -41,6 +51,7 @@ ENTRY(l2c310_early_resume) @ Don't setup the L2 cache if it is already enabled ldr r0, [r1, #L2X0_CTRL] +ARM_BE8(revr0, r0) tst r0, #L2X0_CTRL_EN retne lr @@ -51,6 +62,7 @@ ENTRY(l2c310_early_resume) str r2, [r1, #L2X0_AUX_CTRL] mov r9, #L2X0_CTRL_EN +ARM_BE8(revr9, r9) str r9, [r1, #L2X0_CTRL] ret lr ENDPROC(l2c310_early_resume) -- 2.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
Hi,
This patch series adds support for AFTR idle mode on boards with
Exynos3250 SoC and allows EXYNOS cpuidle driver usage on these
boards.
It has been tested on Samsung Rinato board (Gear 2).
Depends on:
- for-next branch (commit: 77105c882ba6) of linux-samsung.git
kernel tree
Changes since v3:
- enhanced patch description for patch #1
- added Reviewed-by/Tested-by tags from Krzysztof
- enhanced C2_STATE BOOT mode flag comment
- moved exynos_{set,clear}_boot_flag() to firmware.c
- added patch description to patch #3
Changes since v2:
- rebased on top of for-next branch (commit: 77105c882ba6) of
linux-samsung.git kernel tree
Changes since v1:
- rebased on top of for-next branch (commit: ce275c369a0b) of
linux-samsung.git kernel tree
- fixed lockup on hotplug by using dsb_sev() instead of IPI in
exynos_boot_secondary() on Exynos3250
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
Bartlomiej Zolnierkiewicz (4):
ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
ARM: EXYNOS: add code for setting/clearing boot flag
ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
ARM: EXYNOS: cpuidle: allow driver usage on Exynos3250 SoC
arch/arm/mach-exynos/common.h | 6 ++
arch/arm/mach-exynos/exynos.c | 1 +
arch/arm/mach-exynos/firmware.c | 33 -
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/pm.c | 12 +++-
arch/arm/mach-exynos/regs-pmu.h | 3 +++
arch/arm/mach-exynos/smc.h | 9 +
7 files changed, 82 insertions(+), 5 deletions(-)
--
1.8.2.3
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Re: [PATCH v2 0/5] cpuidle: exynos: add coupled cpuidle support for Exynos3250
On Wednesday, March 18, 2015 02:09:52 PM Bartlomiej Zolnierkiewicz wrote: Hi, The following patchset adds coupled cpuidle support for Exynos3250 to an existing cpuidle-exynos driver. As a result it enables AFTR mode to be used by default on Exynos3250 without the need to hot unplug CPU1 first. The patchset depends on: - for-next branch (commit: 77105c882ba6) of linux-samsung.git kernel tree - [PATCH] ARM: EXYNOS: Fix failed second suspend on Exynos4 (https://lkml.org/lkml/2015/2/3/481) - [PATCH v3 0/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250 (https://lkml.org/lkml/2015/3/18/282) This patchset also applies fine on top of v4 of the above patchset: [PATCH v4 0/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250 (https://lkml.org/lkml/2015/3/18/505). Changes since v1: - rebased on top of for-next branch (commit: 77105c882ba6) of linux-samsung.git kernel tree Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (5): ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: add exynos_get_boot_addr() helper cpuidle: exynos: add coupled cpuidle support for Exynos3250 arch/arm/include/asm/firmware.h | 4 ++ arch/arm/mach-exynos/common.h | 4 +- arch/arm/mach-exynos/exynos.c | 3 +- arch/arm/mach-exynos/firmware.c | 18 + arch/arm/mach-exynos/platsmp.c | 86 - arch/arm/mach-exynos/pm.c | 51 6 files changed, 129 insertions(+), 37 deletions(-) Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Handle of_find_device_by_node and kstrdup failures
2015-02-24 16:42 GMT+01:00 Krzysztof Kozlowski k.kozlow...@samsung.com: On wto, 2015-02-03 at 18:28 +0100, Krzysztof Kozlowski wrote: Prevent possible NULL pointer dereference of pointer returned by of_find_device_by_node(). Handle this by skipping such power domain. Additionally fail the init on kstrdup() failure. Such case is actually not fatal because the name for power domain allocated by kstrdup() is used only in printk. Still as a precaution handle this as an error condition. Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Hi Kukjin, What is the status of this patch and the ARM: EXYNOS: Handle of of_iomap() failure. The latter should be in your tree but I cannot find it. Best regards, Krzysztof Hi Kukjin, You haven't applied this and the ARM: EXYNOS: Handle of of_iomap() failure yet. Any comments? Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] thermal: exynos: Add the support for Exynos5433 TMU
Hi Chanwoo,
Hi Lukasz,
Genlty Ping.
I've got your patches at the back of my head :-)
I will try to review them today or tomorrow.
Best Regards,
Chanwoo Choi
On 03/10/2015 11:23 AM, Chanwoo Choi wrote:
This patch adds the support for Exynos5433's TMU (Thermal
Management Unit). Exynos5433 has a little different register bit
fields as following description:
- Support the eight trip points for rising/falling interrupt by
using two registers
- Read the calibration type (1-point or 2-point) and sensor id from
TRIMINFO register
- Use a little different register address
Cc: Zhang Rui rui.zh...@intel.com
Cc: Eduardo Valentin edubez...@gmail.com
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
Changes from v1:
(https://lkml.org/lkml/2015/2/26/234)
- Add exynos5433_tmu_control() instead of using
exynos7_tmu_control() on both Exynos5433 and Exynos7.
- Separate the patches related to devicetree and then send send
Exnos5433's tmu patches[1] with other Exynos5433 devicetree patches.
[1] https://lkml.org/lkml/2015/3/9/1036
drivers/thermal/samsung/exynos_tmu.c | 187
++-
drivers/thermal/samsung/exynos_tmu.h | 1 + 2 files changed, 186
insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 1d30b09..531f4b17
100644 --- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -97,6 +97,32 @@
#define EXYNOS4412_MUX_ADDR_VALUE 6
#define EXYNOS4412_MUX_ADDR_SHIFT 20
+/* Exynos5433 specific registers */
+#define EXYNOS5433_TMU_REG_CONTROL10x024
+#define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c
+#define EXYNOS5433_TMU_COUNTER_VALUE0 0x030
+#define EXYNOS5433_TMU_COUNTER_VALUE1 0x034
+#define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044
+#define EXYNOS5433_THD_TEMP_RISE3_00x050
+#define EXYNOS5433_THD_TEMP_RISE7_40x054
+#define EXYNOS5433_THD_TEMP_FALL3_00x060
+#define EXYNOS5433_THD_TEMP_FALL7_40x064
+#define EXYNOS5433_TMU_REG_INTEN 0x0c0
+#define EXYNOS5433_TMU_REG_INTPEND 0x0c8
+#define EXYNOS5433_TMU_EMUL_CON0x110
+#define EXYNOS5433_TMU_PD_DET_EN 0x130
+
+#define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT16
+#define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT23
+#define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \
+ (0xf
EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) +#define
EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) +
+#define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0
+#define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1
+
+#define EXYNOS5433_PD_DET_EN 1
+
/*exynos5440 specific registers*/
#define EXYNOS5440_TMU_S0_7_TRIM 0x000
#define EXYNOS5440_TMU_S0_7_CTRL 0x020
@@ -484,6 +510,101 @@ out:
return ret;
}
+static int exynos5433_tmu_initialize(struct platform_device *pdev)
+{
+ struct exynos_tmu_data *data = platform_get_drvdata(pdev);
+ struct exynos_tmu_platform_data *pdata = data-pdata;
+ struct thermal_zone_device *tz = data-tzd;
+ unsigned int status, trim_info;
+ unsigned int rising_threshold = 0, falling_threshold = 0;
+ unsigned long temp, temp_hist;
+ int ret = 0, threshold_code, i, sensor_id, cal_type;
+
+ status = readb(data-base + EXYNOS_TMU_REG_STATUS);
+ if (!status) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ trim_info = readl(data-base + EXYNOS_TMU_REG_TRIMINFO);
+ sanitize_temp_error(data, trim_info);
+
+ /* Read the temperature sensor id */
+ sensor_id = (trim_info
EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
+
EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
+ dev_info(pdev-dev, Temperature sensor ID: 0x%x\n,
sensor_id); +
+ /* Read the calibration mode */
+ writel(trim_info, data-base + EXYNOS_TMU_REG_TRIMINFO);
+ cal_type = (trim_info EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
+
EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; +
+ switch (cal_type) {
+ case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
+ pdata-cal_type = TYPE_ONE_POINT_TRIMMING;
+ break;
+ case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
+ pdata-cal_type = TYPE_TWO_POINT_TRIMMING;
+ break;
+ default:
+ pdata-cal_type = TYPE_ONE_POINT_TRIMMING;
+ break;
+ };
+
+ dev_info(pdev-dev, Calibration type is %d-point
calibration\n,
+ cal_type ? 2 : 1);
+
+ /* Write temperature code for rising and falling threshold
*/
+ for (i = 0; i of_thermal_get_ntrips(tz); i++) {
+ int rising_reg_offset, falling_reg_offset;
+ int j =
Re: [PATCH v2 Resend] pwm: samsung: Fix output race on disabling
Hey Jingoo, Kukjijn, Lukasz,
Pinging on this one again, could you please review this patch so it can
be merged through the PWM tree?
On Thu, 2015-03-05 at 09:14 +0100, Sjoerd Simons wrote:
When disabling the samsung PWM the output state remains at the level it
was in the end of a pwm cycle. In other words, calling pwm_disable when
at 100% duty will keep the output active, while at all other setting the
output will go/stay inactive. On top of that the samsung PWM settings are
double-buffered, which means the new settings only get applied at the
start of a new PWM cycle.
This results in a race if the PWM is at 100% duty and a driver calls:
pwm_config (pwm, 0, period);
pwm_disable (pwm);
In this case the PWMs output will unexpectedly stay active, unless a new
PWM cycle happened to start between the register writes in _config and
_disable. As far as i can tell this is a regression introduced by 3bdf878,
before that a call to pwm_config would call pwm_samsung_enable which,
while heavy-handed, made sure the expected settings were live.
To resolve this, while not re-introducing the issues 3bdf878 (flickering
as the PWM got reset while in a PWM cycle). Only force an update of the
settings when at 100% duty, which shouldn't have a noticeable effect on
the output but is enough to ensure the behaviour is as expected on
disable.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes since v1:
Fix small issues pointed out by Tomasz Figa
- Correct various coding style issues
- Read the current value of the tcmp register for comparison rather then
using a non-trivial comparison to decide whether the current state was
100% duty
- Move the code to force manual update out into its own function
- Clarify the comment indicating why a manual update is sometimes required
drivers/pwm/pwm-samsung.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c
index 3e9b583..649f6c4 100644
--- a/drivers/pwm/pwm-samsung.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -269,12 +269,31 @@ static void pwm_samsung_disable(struct pwm_chip *chip,
struct pwm_device *pwm)
spin_unlock_irqrestore(samsung_pwm_lock, flags);
}
+static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
+ struct pwm_device *pwm)
+{
+ unsigned int tcon_chan = to_tcon_channel(pwm-hwpwm);
+ u32 tcon;
+ unsigned long flags;
+
+ spin_lock_irqsave(samsung_pwm_lock, flags);
+
+ tcon = readl(chip-base + REG_TCON);
+ tcon |= TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ tcon = ~TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ spin_unlock_irqrestore(samsung_pwm_lock, flags);
+}
+
static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
- u32 tin_ns = chan-tin_ns, tcnt, tcmp;
+ u32 tin_ns = chan-tin_ns, tcnt, tcmp, oldtcmp;
/*
* We currently avoid using 64bit arithmetic by using the
@@ -288,6 +307,7 @@ static int pwm_samsung_config(struct pwm_chip *chip,
struct pwm_device *pwm,
return 0;
tcnt = readl(our_chip-base + REG_TCNTB(pwm-hwpwm));
+ oldtcmp = readl(our_chip-base + REG_TCMPB(pwm-hwpwm));
/* We need tick count for calculation, not last tick. */
++tcnt;
@@ -335,6 +355,15 @@ static int pwm_samsung_config(struct pwm_chip *chip,
struct pwm_device *pwm,
writel(tcnt, our_chip-base + REG_TCNTB(pwm-hwpwm));
writel(tcmp, our_chip-base + REG_TCMPB(pwm-hwpwm));
+ /* In case the PWM is currently at 100% duty, force a manual update
+ * to prevent the signal staying high in the pwm is disabled shortly
+ * afer this update (before it autoreloaded the new values) .
+ */
+ if (oldtcmp == (u32) -1) {
+ dev_dbg(our_chip-chip.dev, Forcing manual update);
+ pwm_samsung_manual_update(our_chip, pwm);
+ }
+
chan-period_ns = period_ns;
chan-tin_ns = tin_ns;
chan-duty_ns = duty_ns;
--
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Re: [PATCH v4 1/4] ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
Hi Bartlomiej,
I tested this patch on Exynos3250-based Gear2 board.
Thanks for your effor to solve this issue.
Tested-by: Chanwoo Choi cw00.c...@samsung.com
Best Regards,
Chanwoo Choi
On 03/19/2015 01:00 AM, Bartlomiej Zolnierkiewicz wrote:
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
This patch also fixes hotplug issues during resume from S2R:
$ echo mem /sys/power/state
[ 156.517266] Disabling non-boot CPUs ...
[ 156.517781] IRQ18 no longer affine to CPU1
[ 156.518043] CPU1: shutdown
[ 156.544718] Enabling non-boot CPUs ...
[ 156.554925] CPU1: Software reset
[ 158.552631] CPU1: failed to come online
[ 158.552753] Error taking CPU1 up: -5
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Tested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/regs-pmu.h | 2 ++
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d2e9f12..ebd135b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,6 +126,8 @@ static inline void platform_do_lowpower(unsigned int cpu,
int *spurious)
*/
void exynos_cpu_power_down(int cpu)
{
+ u32 core_conf;
+
if (cpu == 0 (soc_is_exynos5420() || soc_is_exynos5800())) {
/*
* Bypass power down for CPU0 during suspend. Check for
@@ -137,7 +139,10 @@ void exynos_cpu_power_down(int cpu)
if (!(val S5P_CORE_LOCAL_PWR_EN))
return;
}
- pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+
+ core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ core_conf = ~S5P_CORE_LOCAL_PWR_EN;
+ pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -148,7 +153,12 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
+
+ if (soc_is_exynos3250())
+ core_conf |= S5P_CORE_AUTOWAKEUP_EN;
+
+ pmu_raw_writel(core_conf,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
@@ -226,6 +236,10 @@ static void exynos_core_restart(u32 core_id)
if (!of_machine_is_compatible(samsung,exynos3250))
return;
+ while (!pmu_raw_readl(S5P_PMU_SPARE2))
+ udelay(10);
+ udelay(10);
+
val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
@@ -346,7 +360,10 @@ static int exynos_boot_secondary(unsigned int cpu,
struct task_struct *idle)
call_firmware_op(cpu_boot, core_id);
- arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+ if (soc_is_exynos3250())
+ dsb_sev();
+ else
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
if (pen_release == -1)
break;
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index eb461e1..84ddce1 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -49,6 +49,7 @@
#define S5P_INFORM5 0x0814
#define S5P_INFORM6 0x0818
#define S5P_INFORM7 0x081C
+#define S5P_PMU_SPARE2 0x0908
#define S5P_PMU_SPARE3 0x090C
#define EXYNOS_IROM_DATA20x0988
@@ -182,6 +183,7 @@
#define S5P_CORE_LOCAL_PWR_EN0x3
#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 8)
+#define S5P_CORE_AUTOWAKEUP_EN (1 31)
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
--
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Re: [PATCH v4 0/4] ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
Hi Bartlomiej,
I tested this patch-set for AFTR mode.
When CPU1 is offline state, I checked that CPU0 enter the AFTR mode.
Tested-by: Chanwoo Choi cw00.c...@samsung.com
Best Regards,
Chanwoo Choi
On 03/19/2015 01:00 AM, Bartlomiej Zolnierkiewicz wrote:
Hi,
This patch series adds support for AFTR idle mode on boards with
Exynos3250 SoC and allows EXYNOS cpuidle driver usage on these
boards.
It has been tested on Samsung Rinato board (Gear 2).
Depends on:
- for-next branch (commit: 77105c882ba6) of linux-samsung.git
kernel tree
Changes since v3:
- enhanced patch description for patch #1
- added Reviewed-by/Tested-by tags from Krzysztof
- enhanced C2_STATE BOOT mode flag comment
- moved exynos_{set,clear}_boot_flag() to firmware.c
- added patch description to patch #3
Changes since v2:
- rebased on top of for-next branch (commit: 77105c882ba6) of
linux-samsung.git kernel tree
Changes since v1:
- rebased on top of for-next branch (commit: ce275c369a0b) of
linux-samsung.git kernel tree
- fixed lockup on hotplug by using dsb_sev() instead of IPI in
exynos_boot_secondary() on Exynos3250
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
Bartlomiej Zolnierkiewicz (4):
ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
ARM: EXYNOS: add code for setting/clearing boot flag
ARM: EXYNOS: cpuidle: add AFTR mode support for Exynos3250
ARM: EXYNOS: cpuidle: allow driver usage on Exynos3250 SoC
arch/arm/mach-exynos/common.h | 6 ++
arch/arm/mach-exynos/exynos.c | 1 +
arch/arm/mach-exynos/firmware.c | 33 -
arch/arm/mach-exynos/platsmp.c | 23 ---
arch/arm/mach-exynos/pm.c | 12 +++-
arch/arm/mach-exynos/regs-pmu.h | 3 +++
arch/arm/mach-exynos/smc.h | 9 +
7 files changed, 82 insertions(+), 5 deletions(-)
--
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[PATCH v2] USB3503: Always respect refclk-frequency
My apologies for the double-post; the previous patch lacked an Acked-by and several important recipients. Keep me on the CC list as I'm not subscribed to the linux-usb list. The USB3503 driver exposes the refclk-frequency DT property to allow users to specify the rate of the clock provided on the device's REFCLK. This is necessary for the driver to correctly configure the REF_SEL and INT_N pins. Currently the driver only pays attention to refclk-frequency if the refclk property is also provided. The binding documentation stipulates that the user should omit refclk if the clock can be assumed to be always available. This patch reworks the initialization codepath such that the driver always respects the refclk-frequency property, even if refclk is omitted. Cheers, - Ben [1] https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/commit/drivers/usb/misc/usb3503.c?id=657d898a9320a7cdb9b94565d75ecf75c25cbf0a -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] usb/misc/usb3503: Always read refclk frequency from DT
This is necessary to set REF_SEL appropriately in uses where refclk is
always available.
Signed-off-by: Ben Gamari b...@smart-cactus.org
Acked-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/usb/misc/usb3503.c | 47 +++---
1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index 258d2f5..64ff5b9 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -186,8 +186,31 @@ static int usb3503_probe(struct usb3503 *hub)
hub-mode = pdata-initial_mode;
} else if (np) {
struct clk *clk;
+ u32 rate = 0;
hub-port_off_mask = 0;
+ if (!of_property_read_u32(np, refclk-frequency, rate)) {
+ switch (rate) {
+ case 3840:
+ case 2600:
+ case 1920:
+ case 1200:
+ hub-secondary_ref_clk = 0;
+ break;
+ case 2400:
+ case 2700:
+ case 2500:
+ case 5000:
+ hub-secondary_ref_clk = 1;
+ break;
+ default:
+ dev_err(dev,
+ unsupported reference clock rate
(%d)\n,
+ (int) rate);
+ return -EINVAL;
+ }
+ }
+
clk = devm_clk_get(dev, refclk);
if (IS_ERR(clk) PTR_ERR(clk) != -ENOENT) {
dev_err(dev, unable to request refclk (%ld)\n,
@@ -196,31 +219,9 @@ static int usb3503_probe(struct usb3503 *hub)
}
if (!IS_ERR(clk)) {
- u32 rate = 0;
hub-clk = clk;
- if (!of_property_read_u32(np, refclk-frequency,
-rate)) {
-
- switch (rate) {
- case 3840:
- case 2600:
- case 1920:
- case 1200:
- hub-secondary_ref_clk = 0;
- break;
- case 2400:
- case 2700:
- case 2500:
- case 5000:
- hub-secondary_ref_clk = 1;
- break;
- default:
- dev_err(dev,
- unsupported reference clock
rate (%d)\n,
- (int) rate);
- return -EINVAL;
- }
+ if (rate != 0) {
err = clk_set_rate(hub-clk, rate);
if (err) {
dev_err(dev,
--
2.1.0
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