Re: [PATCH] ARM: exynos_defconfig: Enable cpufreq-dt driver
Hello Krzysztof, On 08/11/2015 04:15 AM, Krzysztof Kozlowski wrote: > With the latest patches the cpufreq-dt can be used on multiple > Exynos SoCs: 3250, 4210, 4212, 4412 and 5250. > > Enable it along with default ondemand governor to conserve the energy, > reduce temperature while maintaining acceptable performance. > > Signed-off-by: Krzysztof Kozlowski > --- > arch/arm/configs/exynos_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/configs/exynos_defconfig > b/arch/arm/configs/exynos_defconfig > index 67965cedeb69..2263cd94cb93 100644 > --- a/arch/arm/configs/exynos_defconfig > +++ b/arch/arm/configs/exynos_defconfig > @@ -27,6 +27,8 @@ CONFIG_ARM_APPENDED_DTB=y > CONFIG_ARM_ATAG_DTB_COMPAT=y > CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M > console=ttySAC1,115200 init=/linuxrc mem=256M" > CONFIG_CPU_FREQ=y > +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y > +CONFIG_CPUFREQ_DT=y > CONFIG_CPU_IDLE=y > CONFIG_ARM_EXYNOS_CPUIDLE=y > CONFIG_VFP=y > Reviewed-by: Javier Martinez Canillas Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
---
drivers/clk/samsung/clk-exynos3250.c | 6 ++
include/dt-bindings/clock/exynos3250.h | 6 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c
b/drivers/clk/samsung/clk-exynos3250.c
index 538de66a759e..2105863a3ace 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -307,6 +307,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
/* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -389,6 +390,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_PERIL0 */
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -551,6 +553,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -648,6 +653,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
diff --git a/include/dt-bindings/clock/exynos3250.h
b/include/dt-bindings/clock/exynos3250.h
index aab088d30199..89a7d97b002c 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -78,6 +78,7 @@
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
+#define CLK_MOUT_UART2 61
/* Dividers */
#define CLK_DIV_GPL64
@@ -126,6 +127,7 @@
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM108
#define CLK_DIV_COPY 109
+#define CLK_DIV_UART2 110
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -222,6 +224,7 @@
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
+#define CLK_UART2 222
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -248,12 +251,13 @@
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
+#define CLK_SCLK_UART2 248
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS248
+#define CLK_NR_CLKS249
/*
* CMU DMC
--
1.8.5.5
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[PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC
This patch add the uart2 devicetree node for Exynos3250 SoC.
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++
arch/arm/boot/dts/exynos3250.dtsi | 12
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 5ab81c39e2c9..eac1d21c10d4 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -120,6 +120,13 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2db99433e17f..02f3250766c9 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
};
cpus {
@@ -435,6 +436,17 @@
status = "disabled";
};
+ serial_2: serial@1382 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x1382 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c@1386 {
#address-cells = <1>;
#size-cells = <0>;
--
1.8.5.5
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[PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
---
drivers/clk/samsung/clk-exynos3250.c | 9 +
include/dt-bindings/clock/exynos3250.h | 7 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c
b/drivers/clk/samsung/clk-exynos3250.c
index 2105863a3ace..2683cf03e656 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -303,6 +303,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
/* SRC_FSYS */
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+ MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
@@ -389,6 +390,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ /* DIV_FSYS2 */
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
/* DIV_PERIL0 */
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
@@ -539,6 +545,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+ GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -634,6 +642,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
diff --git a/include/dt-bindings/clock/exynos3250.h
b/include/dt-bindings/clock/exynos3250.h
index 89a7d97b002c..fbc9ef61b191 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,7 @@
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
#define CLK_MOUT_UART2 61
+#define CLK_MOUT_MMC2 62
/* Dividers */
#define CLK_DIV_GPL64
@@ -128,6 +129,8 @@
#define CLK_DIV_HPM108
#define CLK_DIV_COPY 109
#define CLK_DIV_UART2 110
+#define CLK_DIV_MMC2_PRE 111
+#define CLK_DIV_MMC2 112
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -225,6 +228,7 @@
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
#define CLK_UART2 222
+#define CLK_SDMMC2 223
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -252,12 +256,13 @@
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
#define CLK_SCLK_UART2 248
+#define CLK_SCLK_MMC2 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS249
+#define CLK_NR_CLKS250
/*
* CMU DMC
--
1.8.5.5
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[PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks
This patch add the UART2 / MMC2 devicetree node for Exynos3250 SoC and add the related clocks (mux, divider, gate) of UART2 / MMC2 device. Chanwoo Choi (4): clk: samsung: exynos3250: Add UART2 clock clk: samsung: exynos3250: Add MMC2 clock ARM: dts: Add UART2 dt node for Exynos3250 SoC ARM: dts: Add MSHC2 dt node for Exynos3250 SoC arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 42 +++ arch/arm/boot/dts/exynos3250.dtsi | 25 ++ drivers/clk/samsung/clk-exynos3250.c | 15 +++ include/dt-bindings/clock/exynos3250.h| 11 +++- 4 files changed, 92 insertions(+), 1 deletion(-) -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
This patch add the MSHC2 (Mobile Storage Host Controller) devicetree node for
Exynos3250 SoC.
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++
arch/arm/boot/dts/exynos3250.dtsi | 13
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index eac1d21c10d4..78b995fed6c7 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -452,6 +452,41 @@
samsung,pin-drv = <3>;
};
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 02f3250766c9..5a91eaa26565 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -30,6 +30,7 @@
pinctrl1 = &pinctrl_1;
mshc0 = &mshc_0;
mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
spi0 = &spi_0;
spi1 = &spi_1;
i2c0 = &i2c_0;
@@ -341,6 +342,18 @@
status = "disabled";
};
+ mshc_2: mshc@1253 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x1253 0x1000>;
+ interrupts = <0 144 0>;
+ clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
exynos_usbphy: exynos-usbphy@125B {
compatible = "samsung,exynos3250-usb2-phy";
reg = <0x125B 0x100>;
--
1.8.5.5
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Re: [PATCH v4 0/6] cpufreq: use generic cpufreq drivers for Exynos4x12 platform
On 10.08.2015 10:27, Kukjin Kim wrote: > Krzysztof Kozlowski wrote: >> >> W dniu 08.08.2015 o 11:07, Viresh Kumar pisze: >>> On 08-08-15, 00:24, Rafael J. Wysocki wrote: OK, so please let me know which patches you want me to pick up. Ideally, I'd prefer them to be resent in a separate series with ACKs and all with a cover letter clearly stating whose tree they are being targeted at. >>> >>> He already sent it separately, let me send a confirmatory mail in >>> reply to that. >> >> Dear Kukjin, >> >> Can you apply the 2-5 of this series to v4.3? It's getting late but >> maybe they still could go? >> > Once my previous pull-request landed into arm-soc, I'll try to send out this > series 2-5 for v4.3. Additionally (better late than never): Patches 2-5 tested on Trats2 board (Exynos4412) Tested-by: Krzysztof Kozlowski Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: exynos_defconfig: Enable cpufreq-dt driver
With the latest patches the cpufreq-dt can be used on multiple Exynos SoCs: 3250, 4210, 4212, 4412 and 5250. Enable it along with default ondemand governor to conserve the energy, reduce temperature while maintaining acceptable performance. Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 67965cedeb69..2263cd94cb93 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -27,6 +27,8 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M console=ttySAC1,115200 init=/linuxrc mem=256M" CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_VFP=y -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mmc: sdhci-of-arasan: Add the support for sdhci-5.1
On 2015/8/11 9:14, Shawn Lin wrote:
This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan5.1 version of controller.
Sorry for wrong send-email ops, pls ignore this patch :(
Signed-off-by: Shawn Lin
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
drivers/mmc/host/sdhci-of-arasan.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
Required Properties:
- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..c9012f5 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -175,6 +175,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) {
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ } else if (of_device_is_compatible(pdev->dev.of_node,
+ "arasan,sdhci-5.1")) {
+ host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
}
sdhci_get_of_property(pdev);
@@ -217,6 +220,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+ { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
{ }
};
--
Shawn Lin
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[PATCH] mmc: sdhci-of-arasan: Add the support for sdhci-5.1
This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan5.1 version of controller.
Signed-off-by: Shawn Lin
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
drivers/mmc/host/sdhci-of-arasan.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
Required Properties:
- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..c9012f5 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -175,6 +175,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) {
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ } else if (of_device_is_compatible(pdev->dev.of_node,
+ "arasan,sdhci-5.1")) {
+ host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
}
sdhci_get_of_property(pdev);
@@ -217,6 +220,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+ { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
{ }
};
--
2.3.7
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Re: [PATCH v2 11/11] drm/exynos: remove struct exynos_drm_encoder layer
Hi Inki, 2015-08-07 Inki Dae : > Hi Gustavo, > > On 2015년 08월 06일 22:31, Gustavo Padovan wrote: > > From: Gustavo Padovan > > > > struct exynos_drm_encoder was justing wrapping struct drm_encoder, it had > > only a drm_encoder member and the internal exynos_drm_encoders ops that > > was directly mapped to the drm_encoder helper funcs. > > > > So now exynos DRM uses struct drm_encoder directly, this removes > > completely the struct exynos_drm_encoder. > > > > Trats2 board, which uses Exynos4412 Soc, doesn't work after this patch > is applied. Below is the booting logs, > [1.171318] console [ttySAC2] enabled > [1.175522] 1383.serial: ttySAC3 at MMIO 0x1383 (irq = 60, > base_baud = 0) is a S3C6400/10 > [1.185545] [drm] Initialized drm 1.1.0 20060810 > [1.194104] exynos-drm exynos-drm: bound 11c0.fimd (ops > fimd_component_ops) > [1.200352] exynos-drm exynos-drm: bound 11c8.dsi (ops > exynos_dsi_component_ops) > [1.207688] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [1.214313] [drm] No driver support for vblank timestamp query. > [1.220218] [drm] Initialized exynos 1.0.0 20110530 on minor 0 > > Booting is locked up here. This patch looks good to me so I tried to > find why locked up and I found the booting is locked up as soon as > console_lock function is called. Can you and other guys look into this > issue? I've realized that I left a fix for patch 01 behind, it could be the cause of this issue. I've just resent this patch with the added v2 fix up. Gustavo -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/11] drm/exynos: split display's .dpms() into .enable() and .disable()
From: Gustavo Padovan
The DRM Core doesn't have a dpms() operation anymore, everything
now is enable() or disable().
Signed-off-by: Gustavo Padovan
---
v2: set dp->dpms_mode after enable/disable
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 36 ++--
drivers/gpu/drm/exynos/exynos_drm_dpi.c | 36
drivers/gpu/drm/exynos/exynos_drm_drv.h | 6 ++-
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 44 ++-
drivers/gpu/drm/exynos/exynos_drm_encoder.c | 8 ++--
drivers/gpu/drm/exynos/exynos_hdmi.c| 65 ++---
6 files changed, 65 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 172b800..ef24952 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1066,8 +1066,9 @@ static void exynos_dp_phy_exit(struct exynos_dp_device
*dp)
phy_power_off(dp->phy);
}
-static void exynos_dp_poweron(struct exynos_dp_device *dp)
+static void exynos_dp_enable(struct exynos_drm_display *display)
{
+ struct exynos_dp_device *dp = display_to_dp(display);
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1088,10 +1089,13 @@ static void exynos_dp_poweron(struct exynos_dp_device
*dp)
exynos_dp_init_dp(dp);
enable_irq(dp->irq);
exynos_dp_commit(&dp->display);
+
+ dp->dpms_mode = DRM_MODE_DPMS_ON;
}
-static void exynos_dp_poweroff(struct exynos_dp_device *dp)
+static void exynos_dp_disable(struct exynos_drm_display *display)
{
+ struct exynos_dp_device *dp = display_to_dp(display);
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1116,30 +1120,14 @@ static void exynos_dp_poweroff(struct exynos_dp_device
*dp)
if (drm_panel_unprepare(dp->panel))
DRM_ERROR("failed to turnoff the panel\n");
}
-}
-
-static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
-{
- struct exynos_dp_device *dp = display_to_dp(display);
- switch (mode) {
- case DRM_MODE_DPMS_ON:
- exynos_dp_poweron(dp);
- break;
- case DRM_MODE_DPMS_STANDBY:
- case DRM_MODE_DPMS_SUSPEND:
- case DRM_MODE_DPMS_OFF:
- exynos_dp_poweroff(dp);
- break;
- default:
- break;
- }
- dp->dpms_mode = mode;
+ dp->dpms_mode = DRM_MODE_DPMS_OFF;
}
static struct exynos_drm_display_ops exynos_dp_display_ops = {
.create_connector = exynos_dp_create_connector,
- .dpms = exynos_dp_dpms,
+ .enable = exynos_dp_enable,
+ .disable = exynos_dp_disable,
.commit = exynos_dp_commit,
};
@@ -1319,7 +1307,7 @@ static void exynos_dp_unbind(struct device *dev, struct
device *master,
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
- exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
+ exynos_dp_disable(&dp->display);
}
static const struct component_ops exynos_dp_ops = {
@@ -1377,7 +1365,7 @@ static int exynos_dp_suspend(struct device *dev)
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
- exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
+ exynos_dp_disable(&dp->display);
return 0;
}
@@ -1385,7 +1373,7 @@ static int exynos_dp_resume(struct device *dev)
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
- exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_ON);
+ exynos_dp_enable(&dp->display);
return 0;
}
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
index 7cb6595..e042670 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
@@ -32,7 +32,6 @@ struct exynos_dpi {
struct drm_encoder *encoder;
struct videomode *vm;
- int dpms_mode;
};
#define connector_to_dpi(c) container_of(c, struct exynos_dpi, connector)
@@ -133,46 +132,30 @@ static int exynos_dpi_create_connector(struct
exynos_drm_display *display,
return 0;
}
-static void exynos_dpi_poweron(struct exynos_dpi *ctx)
+static void exynos_dpi_enable(struct exynos_drm_display *display)
{
+ struct exynos_dpi *ctx = display_to_dpi(display);
+
if (ctx->panel) {
drm_panel_prepare(ctx->panel);
drm_panel_enable(ctx->panel);
}
}
-static void exynos_dpi_poweroff(struct exynos_dpi *ctx)
+static void exynos_dpi_disable(struct exynos_drm_display *display)
{
+ struct exynos_dpi *ctx = display_to_dpi(display);
+
if (ctx->panel) {
drm_panel_disable(ctx->panel);
drm_panel_unprepare(ctx->panel);
}
}
-static void exynos_dpi_dpms(struct exynos_drm_display *display, int mode)
-{
- struct exynos_dpi *ctx
Re: [PATCH 1/2] mfd: s2mps11: Add manual shutdown method for Odroid XU3
On 11.08.2015 00:49, Lee Jones wrote:
> On Mon, 03 Aug 2015, Krzysztof Kozlowski wrote:
>
>> On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1
>> register must be manually set to 0 before initiating power off sequence.
>>
>> One of usual power down methods for Exynos based devices looks like:
>> 1. PWRHOLD pin of PMIC is connected to PSHOLD of Exynos.
>> 2. Exynos holds up this pin during system operation.
>> 3. ACOKB pin of PMIC is pulled up to VBATT and optionally to pin in
>>other device.
>> 4. When PWRHOLD/PSHOLD goes low, the PMIC will turn off the power if
>>ACOKB goes high.
>>
>> On Odroid XU3 family the difference is in (3) - the ACOKB is grounded.
>> This means that PMIC must manually set PWRHOLD field to low and then
>> wait for signal from Application Processor (the usual change in
>> PWRHOLD/PSHOLD pin will actually cut off the power).
>>
>> The patch adds respective binding allowing Odroid XU3 device to be
>> powered off.
>>
>> Signed-off-by: Krzysztof Kozlowski
>> Reported-by: Anand Moon
>>
>> ---
>>
>> Patch is losely based on patch in Hardkernel repository [0] and previous
>> work of Anand Moon [1].
>>
>> [0]
>> https://github.com/hardkernel/linux/commit/6897e62ba328bd1c8c095d918101863250cd73e7
>> [1] http://www.spinics.net/lists/linux-samsung-soc/msg45959.html
>> ---
>> Documentation/devicetree/bindings/mfd/s2mps11.txt | 4 +++
>> drivers/mfd/sec-core.c| 31
>> +++
>> include/linux/mfd/samsung/core.h | 2 ++
>> include/linux/mfd/samsung/s2mps11.h | 1 +
>> 4 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> b/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> index 57a045016fca..90eaef393325 100644
>> --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> @@ -15,6 +15,10 @@ Optional properties:
>> - interrupt-parent: Specifies the phandle of the interrupt controller to
>> which
>>the interrupts from s2mps11 are delivered to.
>> - interrupts: Interrupt specifiers for interrupt sources.
>
>> +- samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is
>> + connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1
>> + register to turn off the power. Usually the ACOKB is pulled up to VBATT so
>> + when PWRHOLD pin goes low, the rising ACOKB will trigger power off.
>
> Binding looks fine. Please seperate it into a different patch and
> apply my Ack:
>
> Acked-by: Lee Jones
OK
>
>> Optional nodes:
>> - clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered
>> 32.768
>> diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
>> index d206a3e8fe87..a56ab2102a32 100644
>> --- a/drivers/mfd/sec-core.c
>> +++ b/drivers/mfd/sec-core.c
>> @@ -278,6 +278,8 @@ static struct sec_platform_data
>> *sec_pmic_i2c_parse_dt_pdata(
>> * not parsed here.
>> */
>>
>> +pd->manual_poweroff = of_property_read_bool(dev->of_node,
>> +"samsung,s2mps11-acokb-ground");
>> return pd;
>> }
>> #else
>> @@ -440,6 +442,34 @@ static int sec_pmic_remove(struct i2c_client *i2c)
>> return 0;
>> }
>>
>> +static void sec_pmic_shutdown(struct i2c_client *i2c)
>> +{
>> +struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
>> +unsigned int reg, mask;
>> +
>> +if (!sec_pmic->pdata->manual_poweroff)
>> +return;
>> +
>> +switch (sec_pmic->device_type) {
>> +case S2MPS11X:
>> +reg = S2MPS11_REG_CTRL1;
>> +mask = S2MPS11_CTRL1_PWRHOLD_MASK;
>> +break;
>> +default:
>> +/*
>> + * Currently only one board with S2MPS11 needs this, so just
>> + * ignore the rest.
>> + */
>> +dev_warn(sec_pmic->dev,
>> +"Unsupported device %lu for manual power off\n",
>> +sec_pmic->device_type);
>> +return;
>> +}
>> +
>> +regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0);
>> +}
>> +
>> +
>
> Remove the extra '\n'.
>
> When you resubmit, apply my Ack:
>
> Acked-by: Lee Jones
Sure, I'll resend. The patch may go through your tree because there are
no external dependencies.
Best regards,
Krzysztof
>
>> #ifdef CONFIG_PM_SLEEP
>> static int sec_pmic_suspend(struct device *dev)
>> {
>> @@ -491,6 +521,7 @@ static struct i2c_driver sec_pmic_driver = {
>> },
>> .probe = sec_pmic_probe,
>> .remove = sec_pmic_remove,
>> +.shutdown = sec_pmic_shutdown,
>> .id_table = sec_pmic_id,
>> };
>>
>> diff --git a/include/linux/mfd/samsung/core.h
>> b/include/linux/mfd/samsung/core.h
>> index 75115384f3fc..aa78957e092f 100644
>> --- a/include/linux/mfd/samsung/core.h
>> +++ b/include/linux/mfd/samsung/core.h
>> @@ -132,6 +132,8 @@ struct sec_platform_data {
>> int
Re: [RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support
在 2015/8/11 2:03, Alim Akhtar 写道:
Hi Shawn
On Thu, Aug 6, 2015 at 12:14 PM, Shawn Lin wrote:
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.
Just curious to know if their are any performance (read/write)
difference with Idmac and edmac?
yes, actually the performance with edmac is worse than that does with
idmac since other peripheral blocks(e.g:I2C/uart/i2s etc.) share generic
DMA with it that means dw_mmc has to compete with them to request the
free channel and be shceduled if generic DMA is busy.
Signed-off-by: Shawn Lin
---
Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size
Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms
Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave
drivers/mmc/host/Kconfig| 11 +-
drivers/mmc/host/dw_mmc-pltfm.c | 2 +
drivers/mmc/host/dw_mmc.c | 258
include/linux/mmc/dw_mmc.h | 27 -
4 files changed, 232 insertions(+), 66 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
This selects support for the Synopsys DesignWare Mobile Storage IP
block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
- bool "Internal DMAC interface"
- depends on MMC_DW
- help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.
config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
- select MMC_DW_IDMAC
help
This selects support for Hisilicon K3 SoC specific extensions to the
Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ /* Get registers' physical base address */
+ host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 40e9d8e..5d6cdff 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,7 @@
#define DW_MCI_FREQ_MAX2 /* unit: HZ */
#define DW_MCI_FREQ_MIN40 /* unit: HZ */
-#ifdef CONFIG_MMC_DW_IDMAC
+
#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -99,7 +99,6 @@ struct idmac_desc {
__le32 des3; /* buffer 2 physical address */
};
-#endif /* CONFIG_MMC_DW_IDMAC */
static bool dw_mci_reset(struct dw_mci *host);
static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
return DMA_FROM_DEVICE;
}
-#ifdef CONFIG_MMC_DW_IDMAC
static void dw_mci_dma_cleanup(struct dw_mci *host)
{
struct mmc_data *data = host->data;
@@ -441,12 +439,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
mci_writel(host, BMOD, temp);
}
-static void dw_mci_idmac_complete_dma(struct dw_mci *host)
+static void dw_mci_dmac_complete_dma(void *arg)
{
+ struct dw_mci *host = arg;
struct mmc_data *data = host->data;
dev_vdbg(host->dev, "DMA complete\n");
+ if (host->use_dma == TRANS_MODE_EDMAC)
+
Re: [RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support
Hi Shawn
On Thu, Aug 6, 2015 at 12:14 PM, Shawn Lin wrote:
> DesignWare MMC Controller can supports two types of DMA
> mode: external dma and internal dma. We get a RK312x platform
> integrated dw_mmc and ARM pl330 dma controller. This patch add
> edmac ops to support these platforms. I've tested it on RK312x
> platform with edmac mode and RK3288 platform with idmac mode.
>
Just curious to know if their are any performance (read/write)
difference with Idmac and edmac?
> Signed-off-by: Shawn Lin
>
> ---
>
> Changes in v4:
> - remove "host->trans_mode" and use "host->use_dma" to indicate
> transfer mode.
> - remove all bt-bindings' changes since we don't need new properities.
> - check transfer mode at runtime by reading HCON reg
> - spilt defconfig changes for each sub-architecture
> - fix the title of cover letter
> - reuse some code for reducing code size
>
> Changes in v3:
> - choose transfer mode at runtime
> - remove all CONFIG_MMC_DW_IDMAC config option
> - add supports-idmac property for some platforms
>
> Changes in v2:
> - Fix typo of dev_info msg
> - remove unused dmach from declaration of dw_mci_dma_slave
>
> drivers/mmc/host/Kconfig| 11 +-
> drivers/mmc/host/dw_mmc-pltfm.c | 2 +
> drivers/mmc/host/dw_mmc.c | 258
>
> include/linux/mmc/dw_mmc.h | 27 -
> 4 files changed, 232 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 6a0f9c7..a86c0eb 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -607,15 +607,7 @@ config MMC_DW
> help
> This selects support for the Synopsys DesignWare Mobile Storage IP
> block, this provides host support for SD and MMC interfaces, in both
> - PIO and external DMA modes.
> -
> -config MMC_DW_IDMAC
> - bool "Internal DMAC interface"
> - depends on MMC_DW
> - help
> - This selects support for the internal DMAC block within the Synopsys
> - Designware Mobile Storage IP block. This disables the external DMA
> - interface.
> + PIO, internal DMA mode and external DMA modes.
>
> config MMC_DW_PLTFM
> tristate "Synopsys Designware MCI Support as platform device"
> @@ -644,7 +636,6 @@ config MMC_DW_K3
> tristate "K3 specific extensions for Synopsys DW Memory Card
> Interface"
> depends on MMC_DW
> select MMC_DW_PLTFM
> - select MMC_DW_IDMAC
> help
> This selects support for Hisilicon K3 SoC specific extensions to the
> Synopsys DesignWare Memory Card Interface driver. Select this option
> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
> index ec6dbcd..7e1d13b 100644
> --- a/drivers/mmc/host/dw_mmc-pltfm.c
> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
> @@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
> host->pdata = pdev->dev.platform_data;
>
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + /* Get registers' physical base address */
> + host->phy_regs = (void *)(regs->start);
> host->regs = devm_ioremap_resource(&pdev->dev, regs);
> if (IS_ERR(host->regs))
> return PTR_ERR(host->regs);
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 40e9d8e..5d6cdff 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -56,7 +56,7 @@
> #define DW_MCI_FREQ_MAX2 /* unit: HZ */
> #define DW_MCI_FREQ_MIN40 /* unit: HZ */
>
> -#ifdef CONFIG_MMC_DW_IDMAC
> +
> #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
> SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
> SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
> @@ -99,7 +99,6 @@ struct idmac_desc {
>
> __le32 des3; /* buffer 2 physical address */
> };
> -#endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
> @@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
> return DMA_FROM_DEVICE;
> }
>
> -#ifdef CONFIG_MMC_DW_IDMAC
> static void dw_mci_dma_cleanup(struct dw_mci *host)
> {
> struct mmc_data *data = host->data;
> @@ -441,12 +439,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
> mci_writel(host, BMOD, temp);
> }
>
> -static void dw_mci_idmac_complete_dma(struct dw_mci *host)
> +static void dw_mci_dmac_complete_dma(void *arg)
> {
> + struct dw_mci *host = arg;
> struct mmc_data *data = host->data;
>
> dev_vdbg(host->dev, "DMA complete\n");
>
> + if (host->use_dma == TRANS_MODE_EDMAC)
> + if (data && (data->flags & MMC_DATA_READ))
> + /* Invalidate cache after read */
> +
Re: [PATCH 0/3] mfd: ChromeOS EC Kconfig dependency cleanup
Hello Lee, On Mon, Aug 10, 2015 at 6:13 PM, Lee Jones wrote: > On Mon, 10 Aug 2015, Lee Jones wrote: >> On Fri, 07 Aug 2015, Javier Martinez Canillas wrote: [snip] >> > >> > Do you know what happened with this patches? I see 3/3 in linux-next >> > but no 1/3 and 2/3. >> >> No idea why you're not seeing them. They are in my -fixes branch, >> which is pulled into -next. I have _just_ sent them to Linus for >> inclusion into v4.2. > > Okay, scrap that. It likes like MFD -fixes isn't pulled into -next. > I'll see what I can do about that. > Ok, that explains it. Thanks a lot for the heads up. Best regards, Javier -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver
Hi Thierry,
在 2015/8/10 21:17, Thierry Reding 写道:
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = <0>;
vsync-active-high = <0>;
interlaced = <0>;
These look like they should come from the display mode definition (EDID)
rather than device tree.
I do think so, those numbers can parse from struct drm_mode. But I haven't
send those changes yet, cause I want to merge the split analogix_dp first,
and
then send some patches to improve it. If you think it's better to imptoved
those
now, I would like to do it , please let me know ;)
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
I think these should also come from EDID, though I'm not sure if we
store this in internal data structures yet.
Same to previous reply
samsung,color-depth = <1>;
This is probably drm_display_info.bpc.
Same to previous reply
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
And these should really be derived from values in the DPCD and adjusted
(if necessary) during link training.
Why would you ever want to hard-code the above?
Yes, I do meet the problem that my eDP screen need lane-count to 4, but my
DP TV need lane-count to 1. Just like previous reply, if you think I should
improved
them in this series, I would rather to do it.
The problem with these is that if you keep them in for your initial
submission, you can never (or only under extreme pain) remove them.
Anything in DTB needs to be effectively supported forever.
Also since these don't make sense to hard-code, just improve the code
and get rid of the need for these DT properties. Mind you that you still
need to keep the code to parse them, because presumably Exynos relies on
them. But depending on how you split up the driver you might be able to
restrict these compatibility hacks to Exynos and not carry them forward
into your new driver.
Okay, thanks for your remind ;)
+ dp->clk_24m = devm_clk_get(dev, "clk_dp_24m");
Same here, maybe "dp_24m".
Like my previous reply. And actually as those two clocks all have
a common prefix "SCLK" in rk3288 clock tree, I thinkt we can name
them to "sclk_dp" & "sclk_dp_24m", is it okay ?
I don't think there's a need for these common prefixes. The names here
are identifiers in the context of the IP block, so any SoC-specific
prefixes are irrelevant. Also they do appear, in DT and in code, in the
context of clocks already, so "sclk_" or "clk_" is completely redundant
in these names.
The sclk_dp & sclk_dp_24m is not IP common ask, it's only exist in RK3288
SoC (Like exynos
only got one "dp" clock), and actually I add this to rockchip platform dp
driver not analogix
dp driver. So I think it's okay to add some platform some common prefixes.
And I got a better idea for those clock. "sclk_dp" & "sclk_dp_24m" is
provided for the eDP phy,
and I just take Heiko suggest that add an new phy-rockchip-dp.c driver, so
it's better to move
those clock to phy driver, and rename them to "dp-phy" && "dp-phy-24m".
I agree that dealing with these in a PHY driver sounds like the better
option. However, I still think that the dp-phy prefix is redundant. The
names are in a per-driver scope, so "dp-phy" is implied by the device
tree binding and driver already. You could simply use shorter names such
as "phy" and "24m" for example.
Also note that the clock provider will already have the proper names for
these, so the clock tree will end up showing the provider names. The
names in the binding are merely the "consumer" names.
Agree, thanks
- Yakir
Thierry
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Re: [PATCH 0/3] mfd: ChromeOS EC Kconfig dependency cleanup
On Mon, 10 Aug 2015, Lee Jones wrote: > On Fri, 07 Aug 2015, Javier Martinez Canillas wrote: > > On Thu, Jun 25, 2015 at 2:20 AM, Javier Martinez Canillas > > wrote: > > > > > > This is a trivial series that do some changes to the dependency for the > > > ChromeOS EC drivers Kconfig symbols. The patches are on top of Paul's > > > patch "mfd: fix dependency warning for CHROME_PLATFORMS on !X86, !ARM": > > > https://lkml.org/lkml/2015/6/20/219. > > > > > > Paul fixed a warning about unmet dependencies but I think the correct fix > > > is to remove unneded dependencies. So that is what this series do and are > > > composed of the following patches: > > > > > > > > > Javier Martinez Canillas (3): > > > platform/chrome: Don't make CHROME_PLATFORMS depends on X86 || ARM > > > mfd: Remove MFD_CROS_EC depends on X86 || ARM > > > mfd: Remove MFD_CROS_EC_SPI depends on OF > > > > > > drivers/mfd/Kconfig | 3 +-- > > > drivers/platform/chrome/Kconfig | 1 - > > > 2 files changed, 1 insertion(+), 3 deletions(-) > > > > > > > The warning that this series fixes has appeared again in linux-next. > > You said some time ago that applied the patches for 4.3 [0] and indeed > > I remember the warning going away at some point. > > > > Do you know what happened with this patches? I see 3/3 in linux-next > > but no 1/3 and 2/3. > > No idea why you're not seeing them. They are in my -fixes branch, > which is pulled into -next. I have _just_ sent them to Linus for > inclusion into v4.2. Okay, scrap that. It likes like MFD -fixes isn't pulled into -next. I'll see what I can do about that. > Let me know if you still see the issue. > > > [0]: https://lkml.org/lkml/2015/6/25/115 > > > > Thanks a lot and best regards, > > Javier > -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] mfd: ChromeOS EC Kconfig dependency cleanup
On Fri, 07 Aug 2015, Javier Martinez Canillas wrote: > On Thu, Jun 25, 2015 at 2:20 AM, Javier Martinez Canillas > wrote: > > > > This is a trivial series that do some changes to the dependency for the > > ChromeOS EC drivers Kconfig symbols. The patches are on top of Paul's > > patch "mfd: fix dependency warning for CHROME_PLATFORMS on !X86, !ARM": > > https://lkml.org/lkml/2015/6/20/219. > > > > Paul fixed a warning about unmet dependencies but I think the correct fix > > is to remove unneded dependencies. So that is what this series do and are > > composed of the following patches: > > > > > > Javier Martinez Canillas (3): > > platform/chrome: Don't make CHROME_PLATFORMS depends on X86 || ARM > > mfd: Remove MFD_CROS_EC depends on X86 || ARM > > mfd: Remove MFD_CROS_EC_SPI depends on OF > > > > drivers/mfd/Kconfig | 3 +-- > > drivers/platform/chrome/Kconfig | 1 - > > 2 files changed, 1 insertion(+), 3 deletions(-) > > > > The warning that this series fixes has appeared again in linux-next. > You said some time ago that applied the patches for 4.3 [0] and indeed > I remember the warning going away at some point. > > Do you know what happened with this patches? I see 3/3 in linux-next > but no 1/3 and 2/3. No idea why you're not seeing them. They are in my -fixes branch, which is pulled into -next. I have _just_ sent them to Linus for inclusion into v4.2. Let me know if you still see the issue. > [0]: https://lkml.org/lkml/2015/6/25/115 > > Thanks a lot and best regards, > Javier -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] mfd: s2mps11: Add manual shutdown method for Odroid XU3
On Mon, 03 Aug 2015, Krzysztof Kozlowski wrote:
> On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1
> register must be manually set to 0 before initiating power off sequence.
>
> One of usual power down methods for Exynos based devices looks like:
> 1. PWRHOLD pin of PMIC is connected to PSHOLD of Exynos.
> 2. Exynos holds up this pin during system operation.
> 3. ACOKB pin of PMIC is pulled up to VBATT and optionally to pin in
>other device.
> 4. When PWRHOLD/PSHOLD goes low, the PMIC will turn off the power if
>ACOKB goes high.
>
> On Odroid XU3 family the difference is in (3) - the ACOKB is grounded.
> This means that PMIC must manually set PWRHOLD field to low and then
> wait for signal from Application Processor (the usual change in
> PWRHOLD/PSHOLD pin will actually cut off the power).
>
> The patch adds respective binding allowing Odroid XU3 device to be
> powered off.
>
> Signed-off-by: Krzysztof Kozlowski
> Reported-by: Anand Moon
>
> ---
>
> Patch is losely based on patch in Hardkernel repository [0] and previous
> work of Anand Moon [1].
>
> [0]
> https://github.com/hardkernel/linux/commit/6897e62ba328bd1c8c095d918101863250cd73e7
> [1] http://www.spinics.net/lists/linux-samsung-soc/msg45959.html
> ---
> Documentation/devicetree/bindings/mfd/s2mps11.txt | 4 +++
> drivers/mfd/sec-core.c| 31
> +++
> include/linux/mfd/samsung/core.h | 2 ++
> include/linux/mfd/samsung/s2mps11.h | 1 +
> 4 files changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt
> b/Documentation/devicetree/bindings/mfd/s2mps11.txt
> index 57a045016fca..90eaef393325 100644
> --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
> +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
> @@ -15,6 +15,10 @@ Optional properties:
> - interrupt-parent: Specifies the phandle of the interrupt controller to
> which
>the interrupts from s2mps11 are delivered to.
> - interrupts: Interrupt specifiers for interrupt sources.
> +- samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is
> + connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1
> + register to turn off the power. Usually the ACOKB is pulled up to VBATT so
> + when PWRHOLD pin goes low, the rising ACOKB will trigger power off.
Binding looks fine. Please seperate it into a different patch and
apply my Ack:
Acked-by: Lee Jones
> Optional nodes:
> - clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered
> 32.768
> diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
> index d206a3e8fe87..a56ab2102a32 100644
> --- a/drivers/mfd/sec-core.c
> +++ b/drivers/mfd/sec-core.c
> @@ -278,6 +278,8 @@ static struct sec_platform_data
> *sec_pmic_i2c_parse_dt_pdata(
>* not parsed here.
>*/
>
> + pd->manual_poweroff = of_property_read_bool(dev->of_node,
> + "samsung,s2mps11-acokb-ground");
> return pd;
> }
> #else
> @@ -440,6 +442,34 @@ static int sec_pmic_remove(struct i2c_client *i2c)
> return 0;
> }
>
> +static void sec_pmic_shutdown(struct i2c_client *i2c)
> +{
> + struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
> + unsigned int reg, mask;
> +
> + if (!sec_pmic->pdata->manual_poweroff)
> + return;
> +
> + switch (sec_pmic->device_type) {
> + case S2MPS11X:
> + reg = S2MPS11_REG_CTRL1;
> + mask = S2MPS11_CTRL1_PWRHOLD_MASK;
> + break;
> + default:
> + /*
> + * Currently only one board with S2MPS11 needs this, so just
> + * ignore the rest.
> + */
> + dev_warn(sec_pmic->dev,
> + "Unsupported device %lu for manual power off\n",
> + sec_pmic->device_type);
> + return;
> + }
> +
> + regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0);
> +}
> +
> +
Remove the extra '\n'.
When you resubmit, apply my Ack:
Acked-by: Lee Jones
> #ifdef CONFIG_PM_SLEEP
> static int sec_pmic_suspend(struct device *dev)
> {
> @@ -491,6 +521,7 @@ static struct i2c_driver sec_pmic_driver = {
> },
> .probe = sec_pmic_probe,
> .remove = sec_pmic_remove,
> + .shutdown = sec_pmic_shutdown,
> .id_table = sec_pmic_id,
> };
>
> diff --git a/include/linux/mfd/samsung/core.h
> b/include/linux/mfd/samsung/core.h
> index 75115384f3fc..aa78957e092f 100644
> --- a/include/linux/mfd/samsung/core.h
> +++ b/include/linux/mfd/samsung/core.h
> @@ -132,6 +132,8 @@ struct sec_platform_data {
> int buck2_init;
> int buck3_init;
> int buck4_init;
> + /* Whether or not manually set PWRHOLD to low during shutdown. */
> + boolmanual_poweroff;
> };
>
Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
> Hi Thierry,
>
> 在 2015/8/10 18:00, Thierry Reding 写道:
> >On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
> >[...]
> >> edp: edp@ff97 {
> >[...]
> >> hsync-active-high = <0>;
> >> vsync-active-high = <0>;
> >> interlaced = <0>;
> >These look like they should come from the display mode definition (EDID)
> >rather than device tree.
>
> I do think so, those numbers can parse from struct drm_mode. But I haven't
> send those changes yet, cause I want to merge the split analogix_dp first,
> and
> then send some patches to improve it. If you think it's better to imptoved
> those
> now, I would like to do it , please let me know ;)
>
> >> samsung,color-space = <0>;
> >> samsung,dynamic-range = <0>;
> >> samsung,ycbcr-coeff = <0>;
> >I think these should also come from EDID, though I'm not sure if we
> >store this in internal data structures yet.
>
> Same to previous reply
>
> >> samsung,color-depth = <1>;
> >This is probably drm_display_info.bpc.
>
> Same to previous reply
>
> >> samsung,link-rate = <0x0a>;
> >> samsung,lane-count = <1>;
> >And these should really be derived from values in the DPCD and adjusted
> >(if necessary) during link training.
> >
> >Why would you ever want to hard-code the above?
>
> Yes, I do meet the problem that my eDP screen need lane-count to 4, but my
> DP TV need lane-count to 1. Just like previous reply, if you think I should
> improved
> them in this series, I would rather to do it.
The problem with these is that if you keep them in for your initial
submission, you can never (or only under extreme pain) remove them.
Anything in DTB needs to be effectively supported forever.
Also since these don't make sense to hard-code, just improve the code
and get rid of the need for these DT properties. Mind you that you still
need to keep the code to parse them, because presumably Exynos relies on
them. But depending on how you split up the driver you might be able to
restrict these compatibility hacks to Exynos and not carry them forward
into your new driver.
> + dp->clk_24m = devm_clk_get(dev, "clk_dp_24m");
> >>>Same here, maybe "dp_24m".
> >>Like my previous reply. And actually as those two clocks all have
> >>a common prefix "SCLK" in rk3288 clock tree, I thinkt we can name
> >>them to "sclk_dp" & "sclk_dp_24m", is it okay ?
> >I don't think there's a need for these common prefixes. The names here
> >are identifiers in the context of the IP block, so any SoC-specific
> >prefixes are irrelevant. Also they do appear, in DT and in code, in the
> >context of clocks already, so "sclk_" or "clk_" is completely redundant
> >in these names.
>
> The sclk_dp & sclk_dp_24m is not IP common ask, it's only exist in RK3288
> SoC (Like exynos
> only got one "dp" clock), and actually I add this to rockchip platform dp
> driver not analogix
> dp driver. So I think it's okay to add some platform some common prefixes.
>
> And I got a better idea for those clock. "sclk_dp" & "sclk_dp_24m" is
> provided for the eDP phy,
> and I just take Heiko suggest that add an new phy-rockchip-dp.c driver, so
> it's better to move
> those clock to phy driver, and rename them to "dp-phy" && "dp-phy-24m".
I agree that dealing with these in a PHY driver sounds like the better
option. However, I still think that the dp-phy prefix is redundant. The
names are in a per-driver scope, so "dp-phy" is implied by the device
tree binding and driver already. You could simply use shorter names such
as "phy" and "24m" for example.
Also note that the clock provider will already have the proper names for
these, so the clock tree will end up showing the provider names. The
names in the binding are merely the "consumer" names.
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver
Hi Heiko,
在 2015/8/10 20:08, Heiko Stübner 写道:
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev,
+ "rk3288-dp needs rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ dp->clk_dp = devm_clk_get(dev, "clk_dp");
I've looked at the manual, but couldn't find an actual clock-name
used there. Is it really "clk_dp" or should it just be "dp"?
This should be "clk_dp", not "dp".
Cause analogix_dp_core would need a clock name with "dp", so I would
rather to pasted my rockchip-dp node here before I add dt-bindings in
next version ;)
The clock we name PCLK_EDP_CTRL in the clock controller is probably the clock
supplying the APB interface and named pclk already in the "Figure 3-2
DP_TXclock domain" diagram on page 19 of the manual. So your "clk_dp" should
actually be "pclk".
So you would have "dp", "dp_24m" and "pclk" for the 3 supplying clocks.
Oh, yes, "pclk" is for APB interface, and "sclk_edp" for IP controller,
and "sclk_edp_24m" for DP PHY,
thanks for your explain.
So for now, I would pass "sclk_edp" to "edp" in analogix_dp, and
"sclk_edp_24m" to "dp-phy_24m"
in phy-rockchip-dp.c, and "pclk_edp" to "pclk" in analogix_dp-rockchip.c.
edp: edp@ff97 {
compatible = "rockchip,rk3288-dp";
reg = <0xff97 0x4000>;
interrupts = ;
clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru
PCLK_EDP_CTRL>;
clock-names = "clk_dp", "clk_dp_24m", "dp";
rockchip,grf = <&grf>;
resets = <&cru 111>;
reset-names = "dp";
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
hsync-active-high = <0>;
vsync-active-high = <0>;
interlaced = <0>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
Thierry already said, that these should probably be somehow auto-detected.
Properties needing to stay around should probably also be "analogix,..." with
a fallback to not break Samsung devicetrees, so
look for "analogix,foo!, if not found try "samsung,foo"
Okay, it's better to rename to "analogxi...", done.
ports {
edp_in: port {
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
};
};
+
+ dp->clk_24m = devm_clk_get(dev, "clk_dp_24m");
Same here, maybe "dp_24m".
Like my previous reply. And actually as those two clocks all have
a common prefix "SCLK" in rk3288 clock tree, I thinkt we can name
them to "sclk_dp" & "sclk_dp_24m", is it okay ?
As Thierry said, please don't add prefixes.
Okay, so is it okay to rename them to "dp", "dp-phy-24m", "pclk" ?
+ if (IS_ERR(dp->clk_24m)) {
+ dev_err(dev, "cannot get clk_dp_24m\n");
+ return PTR_ERR(dp->clk_24m);
+ }
I think you're missing the pclk here (PCLK_EDP_CTRL) or is this part of
something else?
Whops, as I refered in commit message I leave pclk_dp to
analogix_dp_core driver ;-)
The reason why I want to leave pclk is I thought this clock is more like
analogix dp
core driver want, like a IP controller clock (whatever analogix_dp do
need a clock
named with "dp").
Hmm, I'd think what the core (and Samsung) driver use as "dp" clock is
probably the generic clock for the IP and not the pclk for the APB interface.
So I think it still should be "dp" for the core and "dp_24m" + "pclk" for the
rockchip part?
Yes, I think you are right, thanks ;)
+
+ dp->rst = devm_reset_control_get(dev, "dp");
+ if (IS_ERR(dp->rst)) {
+ dev_err(dev, "failed to get reset\n");
+ return PTR_ERR(dp->rst);
+ }
+
+ ret = rockchip_dp_clk_enable(dp);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot enable dp clk %d\n", ret);
+ return ret;
+ }
+
+ ret = rockchip_dp_pre_init(dp);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to pre init %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
[...]
+static int rockchip
Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = <0>;
vsync-active-high = <0>;
interlaced = <0>;
These look like they should come from the display mode definition (EDID)
rather than device tree.
I do think so, those numbers can parse from struct drm_mode. But I haven't
send those changes yet, cause I want to merge the split analogix_dp
first, and
then send some patches to improve it. If you think it's better to
imptoved those
now, I would like to do it , please let me know ;)
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
I think these should also come from EDID, though I'm not sure if we
store this in internal data structures yet.
Same to previous reply
samsung,color-depth = <1>;
This is probably drm_display_info.bpc.
Same to previous reply
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
And these should really be derived from values in the DPCD and adjusted
(if necessary) during link training.
Why would you ever want to hard-code the above?
Yes, I do meet the problem that my eDP screen need lane-count to 4, but my
DP TV need lane-count to 1. Just like previous reply, if you think I
should improved
them in this series, I would rather to do it.
+ dp->clk_24m = devm_clk_get(dev, "clk_dp_24m");
Same here, maybe "dp_24m".
Like my previous reply. And actually as those two clocks all have
a common prefix "SCLK" in rk3288 clock tree, I thinkt we can name
them to "sclk_dp" & "sclk_dp_24m", is it okay ?
I don't think there's a need for these common prefixes. The names here
are identifiers in the context of the IP block, so any SoC-specific
prefixes are irrelevant. Also they do appear, in DT and in code, in the
context of clocks already, so "sclk_" or "clk_" is completely redundant
in these names.
The sclk_dp & sclk_dp_24m is not IP common ask, it's only exist in
RK3288 SoC (Like exynos
only got one "dp" clock), and actually I add this to rockchip platform
dp driver not analogix
dp driver. So I think it's okay to add some platform some common prefixes.
And I got a better idea for those clock. "sclk_dp" & "sclk_dp_24m" is
provided for the eDP phy,
and I just take Heiko suggest that add an new phy-rockchip-dp.c driver,
so it's better to move
those clock to phy driver, and rename them to "dp-phy" && "dp-phy-24m".
Thanks,
- Yakir
Thierry
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Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
> >> +static int rockchip_dp_init(struct rockchip_dp_device *dp)
> >> +{
> >> + struct device *dev = dp->dev;
> >> + struct device_node *np = dev->of_node;
> >> + int ret;
> >> +
> >> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> >> + if (IS_ERR(dp->grf)) {
> >> + dev_err(dev,
> >> + "rk3288-dp needs rockchip,grf property\n");
> >> + return PTR_ERR(dp->grf);
> >> + }
> >> +
> >> + dp->clk_dp = devm_clk_get(dev, "clk_dp");
> >
> > I've looked at the manual, but couldn't find an actual clock-name
> > used there. Is it really "clk_dp" or should it just be "dp"?
>
> This should be "clk_dp", not "dp".
> Cause analogix_dp_core would need a clock name with "dp", so I would
> rather to pasted my rockchip-dp node here before I add dt-bindings in
> next version ;)
The clock we name PCLK_EDP_CTRL in the clock controller is probably the clock
supplying the APB interface and named pclk already in the "Figure 3-2
DP_TXclock domain" diagram on page 19 of the manual. So your "clk_dp" should
actually be "pclk".
So you would have "dp", "dp_24m" and "pclk" for the 3 supplying clocks.
>
> edp: edp@ff97 {
> compatible = "rockchip,rk3288-dp";
> reg = <0xff97 0x4000>;
> interrupts = ;
>
> clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru
> PCLK_EDP_CTRL>;
> clock-names = "clk_dp", "clk_dp_24m", "dp";
>
> rockchip,grf = <&grf>;
> resets = <&cru 111>;
> reset-names = "dp";
> power-domains = <&power RK3288_PD_VIO>;
> status = "disabled";
>
> hsync-active-high = <0>;
> vsync-active-high = <0>;
> interlaced = <0>;
> samsung,color-space = <0>;
> samsung,dynamic-range = <0>;
> samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <1>;
Thierry already said, that these should probably be somehow auto-detected.
Properties needing to stay around should probably also be "analogix,..." with
a fallback to not break Samsung devicetrees, so
look for "analogix,foo!, if not found try "samsung,foo"
> ports {
> edp_in: port {
> #address-cells = <1>;
> #size-cells = <0>;
> edp_in_vopb: endpoint@0 {
> reg = <0>;
> remote-endpoint = <&vopb_out_edp>;
> };
> };
> };
> >> +
> >> + dp->clk_24m = devm_clk_get(dev, "clk_dp_24m");
> >
> > Same here, maybe "dp_24m".
>
> Like my previous reply. And actually as those two clocks all have
> a common prefix "SCLK" in rk3288 clock tree, I thinkt we can name
> them to "sclk_dp" & "sclk_dp_24m", is it okay ?
As Thierry said, please don't add prefixes.
>
> >> + if (IS_ERR(dp->clk_24m)) {
> >> + dev_err(dev, "cannot get clk_dp_24m\n");
> >> + return PTR_ERR(dp->clk_24m);
> >> + }
> >
> > I think you're missing the pclk here (PCLK_EDP_CTRL) or is this part of
> > something else?
>
> Whops, as I refered in commit message I leave pclk_dp to
> analogix_dp_core driver ;-)
>
> The reason why I want to leave pclk is I thought this clock is more like
> analogix dp
> core driver want, like a IP controller clock (whatever analogix_dp do
> need a clock
> named with "dp").
Hmm, I'd think what the core (and Samsung) driver use as "dp" clock is
probably the generic clock for the IP and not the pclk for the APB interface.
So I think it still should be "dp" for the core and "dp_24m" + "pclk" for the
rockchip part?
>
> >> +
> >> + dp->rst = devm_reset_control_get(dev, "dp");
> >> + if (IS_ERR(dp->rst)) {
> >> + dev_err(dev, "failed to get reset\n");
> >> + return PTR_ERR(dp->rst);
> >> + }
> >> +
> >> + ret = rockchip_dp_clk_enable(dp);
> >> + if (ret < 0) {
> >> + dev_err(dp->dev, "cannot enable dp clk %d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + ret = rockchip_dp_pre_init(dp);
> >> + if (ret < 0) {
> >> + dev_err(dp->dev, "failed to pre init %d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + return 0;
> >> +}
> >
> > [...]
> >
> >> +static int rockchip_dp_probe(struct platform_device *pdev)
> >> +{
> >> + struct device *dev = &pdev->dev;
> >> + struct device_node *panel_node;
> >> + struct rockchip_dp_device *dp;
> >> + struct drm_panel *panel;
> >> +
> >> + panel_node = of_parse_phandle(dev->of_node, "rockchip,panel", 0);
> >> + if (!panel_node) {
> >> + DRM_ERROR("faile
[PATCH 08/74] clockevents/drivers/exynos_mct: Remove unneeded container_of()
From: Alexey Klimov
Patch removes unneeded container_of() macro in exynos4_local_timer_setup().
Instead let's pass mevt pointer to setup and stop functions from
exynos4_mct_cpu_notify() and let them get evt pointer.
Tested on odroid-xu3.
Signed-off-by: Alexey Klimov
Acked-by: Stephen Boyd
Signed-off-by: Daniel Lezcano
Reviewed-by: Krzysztof Kozlowski
---
drivers/clocksource/exynos_mct.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9064ff7..4d2330a 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -442,13 +442,11 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int exynos4_local_timer_setup(struct clock_event_device *evt)
+static int exynos4_local_timer_setup(struct mct_clock_event_device *mevt)
{
- struct mct_clock_event_device *mevt;
+ struct clock_event_device *evt = &mevt->evt;
unsigned int cpu = smp_processor_id();
- mevt = container_of(evt, struct mct_clock_event_device, evt);
-
mevt->base = EXYNOS4_MCT_L_BASE(cpu);
snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
@@ -477,8 +475,10 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
return 0;
}
-static void exynos4_local_timer_stop(struct clock_event_device *evt)
+static void exynos4_local_timer_stop(struct mct_clock_event_device *mevt)
{
+ struct clock_event_device *evt = &mevt->evt;
+
evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
if (mct_int_type == MCT_INT_SPI) {
if (evt->irq != -1)
@@ -500,11 +500,11 @@ static int exynos4_mct_cpu_notify(struct notifier_block
*self,
switch (action & ~CPU_TASKS_FROZEN) {
case CPU_STARTING:
mevt = this_cpu_ptr(&percpu_mct_tick);
- exynos4_local_timer_setup(&mevt->evt);
+ exynos4_local_timer_setup(mevt);
break;
case CPU_DYING:
mevt = this_cpu_ptr(&percpu_mct_tick);
- exynos4_local_timer_stop(&mevt->evt);
+ exynos4_local_timer_stop(mevt);
break;
}
@@ -570,7 +570,7 @@ static void __init exynos4_timer_resources(struct
device_node *np, void __iomem
goto out_irq;
/* Immediately configure the timer on the boot CPU */
- exynos4_local_timer_setup(&mevt->evt);
+ exynos4_local_timer_setup(mevt);
return;
out_irq:
--
1.9.1
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Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
> edp: edp@ff97 {
[...]
> hsync-active-high = <0>;
> vsync-active-high = <0>;
> interlaced = <0>;
These look like they should come from the display mode definition (EDID)
rather than device tree.
> samsung,color-space = <0>;
> samsung,dynamic-range = <0>;
> samsung,ycbcr-coeff = <0>;
I think these should also come from EDID, though I'm not sure if we
store this in internal data structures yet.
> samsung,color-depth = <1>;
This is probably drm_display_info.bpc.
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <1>;
And these should really be derived from values in the DPCD and adjusted
(if necessary) during link training.
Why would you ever want to hard-code the above?
> >>+ dp->clk_24m = devm_clk_get(dev, "clk_dp_24m");
> >Same here, maybe "dp_24m".
> Like my previous reply. And actually as those two clocks all have
> a common prefix "SCLK" in rk3288 clock tree, I thinkt we can name
> them to "sclk_dp" & "sclk_dp_24m", is it okay ?
I don't think there's a need for these common prefixes. The names here
are identifiers in the context of the IP block, so any SoC-specific
prefixes are irrelevant. Also they do appear, in DT and in code, in the
context of clocks already, so "sclk_" or "clk_" is completely redundant
in these names.
Thierry
signature.asc
Description: PGP signature
[PATCH 51/74] clockevents/drivers/exynos_mct: Migrate to new 'set-state' interface
From: Viresh Kumar
Migrate exynos_mct driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.
This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.
Cc: Kukjin Kim
Signed-off-by: Viresh Kumar
Signed-off-by: Daniel Lezcano
---
drivers/clocksource/exynos_mct.c | 85 +++-
1 file changed, 40 insertions(+), 45 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 4d2330a..029f96a 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -257,15 +257,14 @@ static void exynos4_mct_comp0_stop(void)
exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}
-static void exynos4_mct_comp0_start(enum clock_event_mode mode,
- unsigned long cycles)
+static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
{
unsigned int tcon;
cycle_t comp_cycle;
tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
- if (mode == CLOCK_EVT_MODE_PERIODIC) {
+ if (periodic) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
}
@@ -283,38 +282,38 @@ static void exynos4_mct_comp0_start(enum clock_event_mode
mode,
static int exynos4_comp_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
- exynos4_mct_comp0_start(evt->mode, cycles);
+ exynos4_mct_comp0_start(false, cycles);
return 0;
}
-static void exynos4_comp_set_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
+static int mct_set_state_shutdown(struct clock_event_device *evt)
{
- unsigned long cycles_per_jiffy;
exynos4_mct_comp0_stop();
+ return 0;
+}
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- cycles_per_jiffy =
- (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult)
>> evt->shift);
- exynos4_mct_comp0_start(mode, cycles_per_jiffy);
- break;
+static int mct_set_state_periodic(struct clock_event_device *evt)
+{
+ unsigned long cycles_per_jiffy;
- case CLOCK_EVT_MODE_ONESHOT:
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_RESUME:
- break;
- }
+ cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
+ >> evt->shift);
+ exynos4_mct_comp0_stop();
+ exynos4_mct_comp0_start(true, cycles_per_jiffy);
+ return 0;
}
static struct clock_event_device mct_comp_device = {
- .name = "mct-comp",
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .rating = 250,
- .set_next_event = exynos4_comp_set_next_event,
- .set_mode = exynos4_comp_set_mode,
+ .name = "mct-comp",
+ .features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .rating = 250,
+ .set_next_event = exynos4_comp_set_next_event,
+ .set_state_periodic = mct_set_state_periodic,
+ .set_state_shutdown = mct_set_state_shutdown,
+ .set_state_oneshot = mct_set_state_shutdown,
+ .tick_resume= mct_set_state_shutdown,
};
static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
@@ -390,39 +389,32 @@ static int exynos4_tick_set_next_event(unsigned long
cycles,
return 0;
}
-static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
-struct clock_event_device *evt)
+static int set_state_shutdown(struct clock_event_device *evt)
+{
+ exynos4_mct_tick_stop(this_cpu_ptr(&percpu_mct_tick));
+ return 0;
+}
+
+static int set_state_periodic(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
unsigned long cycles_per_jiffy;
+ cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
+ >> evt->shift);
exynos4_mct_tick_stop(mevt);
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- cycles_per_jiffy =
- (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult)
>> evt->shift);
- exynos4_mct_tick_start(cycles_per_jiffy, mevt);
- break;
-
- case CLOCK_EVT_MODE_ONESHOT:
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_RESUME:
- break;
- }
+ exynos4_mct_tick_start(cycles_per_jiffy, mevt);
+ return 0;
}
static void exynos4_mct_tick_clear(struct mct_clock_ev
