Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Tested-by: Javier Martinez Canillas
Hi Rob,
On 12/09/2015 12:25 PM, Rob Herring wrote:
On Wed, Dec 09, 2015 at 10:10:39AM +0800, Yakir Yang wrote:
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,nee
On 08.12.2015 22:46, Marek Szyprowski wrote:
> Add support for restoring GScaler parent clocks configuration when GSCL
> power domain is turned on.
>
> Signed-off-by: Marek Szyprowski
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> dif
On 08.12.2015 22:46, Marek Szyprowski wrote:
> This patch adds clocks, which are required for preserving parent clock
> configuration on GSCL power domain on/off.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/clk/samsung/clk-exynos5420.c | 8
> include/dt-bindings/clock/exynos54
On 08.12.2015 22:29, Marek Szyprowski wrote:
> Proper source for MFC block is mout_user_aclk333 (in datasheet named
> USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 +-
> 1 file changed, 1 insertion(
On Wed, Dec 09, 2015 at 10:10:39AM +0800, Yakir Yang wrote:
> Some edp screen do not have hpd signal, so we can't just return
> failed when hpd plug in detect failed.
>
> This is an hardware property, so we need add a devicetree property
> "analogix,need-force-hpd" to indicate this sutiation.
>
>
Hi Chanwoo,
On 9 December 2015 at 09:41, Chanwoo Choi wrote:
> Hi Anand,
>
> On 2015년 11월 27일 09:34, Chanwoo Choi wrote:
>> Hi Anand,
>>
>> On 2015년 11월 27일 02:17, Anand Moon wrote:
>>> Hi Chanwoo,
>>>
>>> On 26 November 2015 at 21:42, Chanwoo Choi wrote:
On Thu, Nov 26, 2015 at 11:00 PM, M
This patch adds the new devfreq_get_devfreq_by_phandle() OF helper function
which can find the instance of devfreq device by using phandle ("devfreq").
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/devfreq.c | 44
include/linux/devfreq.h | 9
This patch adds the DMC (Dynamic Memory Controller) bus frequency node
which includes the devfreq-events and regulator properties. The bus
frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
with ondemand governor.
The devfreq-events (ppmu_dmc0*) can monitor the utilization of D
This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the sour
This patch adds the detailed corrleation between sub-blocks and power line
for Exynos3250, Exynos4210 and Exynos4x12.
Signed-off-by: Chanwoo Choi
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 51 ++
1 file changed, 51 insertions(+)
diff --git a/Documentation/devic
This patch removes the unused exynos4/5 busfreq driver. Instead,
generic exynos-bus frequency driver support the all Exynos SoCs.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/Kconfig | 22 -
drivers/devfreq/exynos/Makefile |2 -
drivers/devfreq/exynos/exynos4_bus.c | 1
This patch updates the documentation for passive bus devices and adds the
detailed example of Exynos3250.
Signed-off-by: Chanwoo Choi
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 244 -
1 file changed, 241 insertions(+), 3 deletions(-)
diff --git a/Documentation/
This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
one power line for all buses to translate data between DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- DMC/ACP clock for DMC (Dynamic Memory Controller)
- ACLK200 clock for LCD0
This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD
This patch modifies the following sysfs entry of DEVFREQ framework
because the devfreq device using passive governor don't need the same
information of the devfreq device using rest governor.
- polling_interval: passive gov don't use the sampling rate.
- available_governors : passive gov don't
This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
exynos4412-odroidu3 board. Each PPMU dt node includes one event of
'PPMU Count3'.
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40 +
1 file changed, 40 insertions(+)
dif
This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos4x12.dtsi | 72 +++
1 file changed, 72 insertions(+)
This patch expands the voltage range of buck1/3 regulator due to as following:
- MIF (Memory Interface) bus frequency needs the 9uV ~ 105uV V.
- INT (Internal) bus frequency needs 9uV ~ 100uV.
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++
THis patch adds the bus device tree nodes for both MIF (Memory) and INT
(Internal) block to enable the bus frequency.
The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
bus is parent device in INT block using VDD_INT.
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos
This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
SDRAM devices. The bus includes the OPP tables and the source clock for DMC
block.
Following list specifies the detailed relation between the
Hi Anand,
On 2015년 11월 27일 09:34, Chanwoo Choi wrote:
> Hi Anand,
>
> On 2015년 11월 27일 02:17, Anand Moon wrote:
>> Hi Chanwoo,
>>
>> On 26 November 2015 at 21:42, Chanwoo Choi wrote:
>>> On Thu, Nov 26, 2015 at 11:00 PM, MyungJoo Ham
>>> wrote:
On Thu, Nov 26, 2015 at 10:47 PM, Chanwoo Ch
This patch adds the new passive governor for DEVFREQ framework. The following
governors are already present and used for DVFS (Dynamic Voltage and Frequency
Scaling) drivers. The following governors are independently used for one device
driver which don't give the influence to other device drviers
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
This patch adds the bus device-tree node of INT (internal) block
to enable the bus frequency. The following sub-blocks share
the VDD_INT power source:
- LEFTBUS (parent device)
- RIGHTBUS
- PERIL
- LCD0
- FSYS
- MCUISP / ISP
- MFC
The LEFTBUS is parent device with devfreq ondemand governor
and the
This patch-set includes the two features as following. The generic exynos bus
frequency driver is able to support almost Exynos SoCs for bus frequency
scaling. And the new passive governor is able to make the dependency on
between devices for frequency/voltage scaling. I had posted the patch-set[1]
This patch adds the documentation for generic exynos bus frequency
driver.
Signed-off-by: Chanwoo Choi
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 94 ++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
This patch adds the generic exynos bus frequency driver for AMBA AXI bus
of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
have the common architecture for bus between DRAM and sub-blocks in SoC.
This driver can support the generic bus frequency driver for Exynos SoCs.
In
Hello Krzysztof,
On 12/08/2015 09:34 PM, Krzysztof Kozlowski wrote:
> On 08.12.2015 22:41, Javier Martinez Canillas wrote:
>> On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
>>>
>>> This looks like a very-non-atomic way of handling a change. You added
>>> opp tables to exynos5420 before so at t
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Chang
Add dt binding documentation for rockchip display port PHY.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v10.1:
- Add the ack from Rob Herring
- Correct the title of this rockchip dp phy document(Rob)
Changes in v9: None
Changes in v8:
- Remove the
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v10.1:
- Add the ack from Rob Herring
Changes in v10: None
Chang
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Tested-by: Javie
Hi Rob,
Thanks for your respond.
On 12/08/2015 11:09 PM, Rob Herring wrote:
On Mon, Dec 07, 2015 at 02:40:42PM +0800, Yakir Yang wrote:
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicet
Hi Rob
On 12/08/2015 11:06 PM, Rob Herring wrote:
On Mon, Dec 07, 2015 at 02:39:50PM +0800, Yakir Yang wrote:
Add dt binding documentation for rockchip display port PHY.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
One possible typo below, otherwise:
Acked-by: Rob Herring
Thank
Hi Rob,
On 12/08/2015 11:03 PM, Rob Herring wrote:
On Mon, Dec 07, 2015 at 02:39:34PM +0800, Yakir Yang wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Reviewed-by: Heik
Hi Rob,
Thanks
- Yakir
On 12/08/2015 11:01 PM, Rob Herring wrote:
On Mon, Dec 07, 2015 at 02:39:07PM +0800, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with
Hi,
On Tue, Dec 01, 2015 at 12:02:57PM +0100, Boris Brezillon wrote:
> Hello,
>
> This huge series aims at clarifying the relationship between the mtd and
> nand_chip structures and hiding NAND framework internals to NAND
> controller drivers.
>
> The first part of the series provide an mtd_to_n
On 08.12.2015 22:41, Javier Martinez Canillas wrote:
> Hello Krzysztof,
>
> On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
>> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>>> From: Ben Gamari
>>>
>>> The Exynos 5422 is identical to the 5800 except for the fact that it
>>> boots from
Hi Boris,
On Wed, Dec 02, 2015 at 09:50:01AM +0100, Boris Brezillon wrote:
> struct nand_chip now embeds an mtd device. Patch all drivers to make use
> of this mtd instance instead of using the instance embedded in their
> private struct or dynamically allocated.
>
> Signed-off-by: Boris Brezillo
Em Sun, 06 Dec 2015 04:16:15 +0200
Laurent Pinchart escreveu:
> Hi Mauro,
>
> Thank you for the patch.
>
> On Sunday 30 August 2015 00:06:43 Mauro Carvalho Chehab wrote:
> > Instead of relying on media subtype, use the new macros to detect
> > if an entity is a subdev or an A/V DMA entity.
> >
Hi Yakir,
Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang:
>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some plat
On Mon, Dec 07, 2015 at 09:52:37PM +0900, Inki Dae wrote:
> This patch updates a ports node binding for panel.
>
> With this, dp node can have a ports node which describes
> a remote endpoint node that can be connected to panel or bridge
> node.
>
> Changelog v2:
> - remove unnecessary properties
On Mon, Dec 07, 2015 at 02:40:42PM +0800, Yakir Yang wrote:
> Some edp screen do not have hpd signal, so we can't just return
> failed when hpd plug in detect failed.
>
> This is an hardware property, so we need add a devicetree property
> "analogix,need-force-hpd" to indicate this sutiation.
I c
On Mon, Dec 07, 2015 at 02:39:34PM +0800, Yakir Yang wrote:
> Rockchip DP driver is a helper driver of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Signed-off-by: Yakir Yang
> Reviewed-by: Heiko Stuebner
I already acked the previous v10
On Mon, Dec 07, 2015 at 02:39:50PM +0800, Yakir Yang wrote:
> Add dt binding documentation for rockchip display port PHY.
>
> Signed-off-by: Yakir Yang
> Reviewed-by: Heiko Stuebner
One possible typo below, otherwise:
Acked-by: Rob Herring
> ---
> Changes in v10: None
> Changes in v9: None
>
On Mon, Dec 07, 2015 at 02:39:07PM +0800, Yakir Yang wrote:
> Analogix dp driver is split from exynos dp driver, so we just
> make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
>
> Beside update some exynos dtsi file with the latest change
> according to the devicetree binding document
On Mon, Dec 7, 2015 at 6:08 AM, Marek Szyprowski
wrote:
> This patch allows device drivers to use more than one reserved memory
> region assigned to given device. When NULL name is passed to
> of_reserved_mem_device_init(), the default (first) region is used.
Every property that's an array does n
From: Andrzej Pietrasiewicz
Eliminate iommu fault during encoding by adjusting image size
used for buffer size computation and ensuring that the buffer is not
overrun.
Signed-off-by: Andrzej Pietrasiewicz
Signed-off-by: Marek Szyprowski
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 7
Ironically, 7d4020c3c400 ("[media] exynos4-is: fix some warnings when
compiling on arm64") fixed some format string bugs but introduced a
new one. buf_index is a simple int, so it should be printed with %d,
not %pad (which is correctly used for dma_addr_t).
Fixes: 7d4020c3c400 ("[media] exynos4-is
This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.
Signed-off-by: Marek Szyprowski
---
drivers/clk/samsung/clk-exynos5420.c | 8
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 6 insertions(+), 4 deletions(
Add support for restoring GScaler parent clocks configuration when GSCL
power domain is turned on.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos5420.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dt
Hello Krzysztof,
On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>> From: Ben Gamari
>>
>> The Exynos 5422 is identical to the 5800 except for the fact that it
>> boots from the A7 cores. Consequently, the core numbering is different:
>>
Hi,
On Mon, Dec 07, 2015 at 12:45:12PM +0900, Krzysztof Kozlowski wrote:
> Currently the reset/power off handlers (POWER_RESET) and Adaptive Voltage
> Scaling class (POWER_AVS) are not built when POWER_SUPPLY is disabled.
> The POWER_RESET is also not visible in drivers main section of config.
>
Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.
Signed-off-by: Marek Szyprowski
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exy
On Tue, 8 Dec 2015 10:30:40 +
Harvey Hunt wrote:
> Hi Boris,
>
> On 07/12/15 22:26, Boris Brezillon wrote:
> > ->ecc_layout is not used by any board file. Kill this field to avoid any
> > confusion. New boards are encouraged to use the default ECC layout defined
> > in NAND core.
> >
> > Sig
Hi Boris,
On 07/12/15 22:26, Boris Brezillon wrote:
->ecc_layout is not used by any board file. Kill this field to avoid any
confusion. New boards are encouraged to use the default ECC layout defined
in NAND core.
Signed-off-by: Boris Brezillon
---
arch/mips/include/asm/mach-jz4740/jz4740_na
Hi,
tested the patch successfully on Odroid-XU4.
Thanks
--
Markus
Am 07.12.2015 um 19:18 schrieb Bartlomiej Zolnierkiewicz:
> Add cluster regulator supply properties as a preparation to
> adding generic cpufreq-dt driver support for Exynos542x and
> Exynos5800 based boards.
>
> Cc: Kukjin Kim
On Mon, Dec 07, 2015 at 11:26:14PM +0100, Boris Brezillon wrote:
Looking good,
Acked-by: Ralf Baechle
Ralf
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Hi Julian,
On Tue, 8 Dec 2015 10:59:53 +1100
Julian Calaby wrote:
> Hi Boris,
>
> On Tue, Dec 8, 2015 at 9:26 AM, Boris Brezillon
> wrote:
> > Signed-off-by: Boris Brezillon
> > ---
> > drivers/staging/mt29f_spinand/mt29f_spinand.c | 44
> > ---
> > 1 file changed, 2
Hello,
On 2015-12-07 13:08, Marek Szyprowski wrote:
This patchset finally perform cleanup of custom code in s5p-mfc codec
driver. The first part is removal of custom, driver specific code for
intializing and handling of reserved memory. Instead, a generic code for
reserved memory regions is used
On Tue, Dec 01, 2015 at 12:03:12PM +0100, Boris Brezillon wrote:
> struct nand_chip now embeds an mtd device. Patch all drivers to make use
> of this mtd instance instead of using the instance embedded in their
> private struct or dynamically allocated.
>
> Signed-off-by: Boris Brezillon
Acked-b
On Tue, Dec 01, 2015 at 12:03:15PM +0100, Boris Brezillon wrote:
> mtd_to_nand() now uses the container_of() approach to transform an
> mtd_info pointer into a nand_chip one. Drop useless mtd->priv
> assignments from NAND controller drivers.
>
> Signed-off-by: Boris Brezillon
Acked-by: Jesper Ni
Hi Priit,
On Tue, 08 Dec 2015 08:43:05 +0200
Priit Laes wrote:
> On Mon, 2015-12-07 at 23:25 +0100, Boris Brezillon wrote:
> > ecclayout->oobavail is just redundant with the mtd->oobavail field.
> > Moreover, it prevents static const definition of ecc layouts since
> > the
> > NAND framework is
On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Ben Gamari
>
> The Exynos 5422 is identical to the 5800 except for the fact that it
> boots from the A7 cores. Consequently, the core numbering is different:
> cores 0-3 are A7s whereas 4-7 are A15s.
>
> We can reuse the device tree o
On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> Fix CPU operating points for Exynos5800 (it use different
> voltages than Exynos5420 and supports additional frequencies).
> However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
> 1400MHz OPP (for A7 cores) for now as they are not avai
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