Re: [PATCH 16/19] ARM: dts: s5pv210: replace legacy *,wakeup property with wakeup-source

On 21/10/15 11:10, Sudeep Holla wrote: Though the keyboard and other driver will continue to support the legacy "gpio-key,wakeup", "linux,input-wakeup" boolean property to enable the wakeup source, "wakeup-source" is the new standard binding. This patch replaces all the legacy wakeup

Re: [PATCH 12/19] ARM: dts: exynos: replace legacy *,wakeup property with wakeup-source

On 21/10/15 11:10, Sudeep Holla wrote: Though the keyboard and other driver will continue to support the legacy "gpio-key,wakeup", "linux-keypad,wakeup" boolean property to enable the wakeup source, "wakeup-source" is the new standard binding. This patch replaces all the legacy wakeup

[PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties

From: Thomas Abraham For Exynos542x/5800 platforms, add CPU operating points for migrating from Exynos specific cpufreq driver to using generic cpufreq driver. Changes by Bartlomiej: - split Exynos5420 support from the original patch - merged Exynos5422 fixes from Ben

[PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

Hi, This patch series adds generic cpufreq-dt driver support for Exynos542x/5800 (using the new CPU clock type which allows it). It has been tested on Exynos5422 based ODROID-XU3 Lite board. Depends on: - next-20151211 branch of linux-next kernel tree - "[PATCH] ARM: dts: Make CPU configuration

[PATCH v6 1/7] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

Add cluster regulator supply properties as a preparation to adding generic cpufreq-dt driver support for Exynos542x and Exynos5800 based boards. Cc: Kukjin Kim Cc: Doug Anderson Cc: Javier Martinez Canillas Cc: Andreas

[PATCH v6 2/7] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock

From: Thomas Abraham With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5420. Changes by Bartlomiej: - split Exynos5420

[PATCH v6 4/7] ARM: Exynos: use generic cpufreq driver for Exynos5420

The new CPU clock type allows the use of cpufreq-dt driver for Exynos5420. Cc: Tomasz Figa Cc: Kukjin Kim Cc: Javier Martinez Canillas Cc: Thomas Abraham Reviewed-by: Krzysztof Kozlowski

[PATCH v6 6/7] ARM: dts: Exynos5800: fix CPU OPP

Fix CPU operating points for Exynos5800 (it use different voltages than Exynos5420 and supports additional frequencies). However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and 1400MHz OPP (for A7 cores) for now as they are not available on all boards. Based on Hardkernel's kernel for

[PATCH v6 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data

Fix cpu clock configuration data for Exynos5422/5800 SoCs (they use higher PCLK_DBG divider values than Exynos5420 and support additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa Cc: Mike Turquette Cc:

Re: [PATCH v2 4/7] media: vb2-dma-contig: add helper for setting dma max seg size

Hi Laurent, On 2015-12-14 16:50, Laurent Pinchart wrote: Hi Marek, On Monday 14 December 2015 10:20:22 Marek Szyprowski wrote: On 2015-12-13 20:57, Laurent Pinchart wrote: On Wednesday 09 December 2015 14:58:19 Marek Szyprowski wrote: Add a helper function for device drivers to set DMA's

Re: [PATCH 1/3] Device tree binding documentation for gpio-switch

Hi, On Monday 14 December 2015 09:45:48 Rob Herring wrote: > On Mon, Dec 14, 2015 at 8:28 AM, Linus Walleij > wrote: > > On Fri, Dec 11, 2015 at 3:06 PM, Rob Herring wrote: > >> On Fri, Dec 11, 2015 at 6:39 AM, Linus Walleij

Re: [PATCH 2/2] [media] media-device: split media initialization and registration

Em Thu, 10 Sep 2015 20:14:04 +0300 Sakari Ailus escreveu: > Hi Javier, > > Thanks for the set! A few comments below. > > Javier Martinez Canillas wrote: > > The media device node is registered and so made visible to user-space > > before entities are registered

[PATCH] [media] media-device: handle errors at media_device_init()

Changeset 43ac4401dca9 ("[media] media-device: split media initialization and registration") broke media device register into two separate functions, but introduced a BUG_ON() and made media_device_init() void. It also introduced several warnings. Instead of adding BUG_ON(), let's revert to

[PATCH v2] [media] media-device: handle errors at media_device_init()

Changeset 43ac4401dca9 ("[media] media-device: split media initialization and registration") broke media device register into two separate functions, but introduced a BUG_ON() and made media_device_init() void. It also introduced several warnings. Instead of adding BUG_ON(), let's revert to

Re: [PATCH 12/19] ARM: dts: exynos: replace legacy *,wakeup property with wakeup-source

On 16.12.2015 01:35, Sudeep Holla wrote: > > > On 21/10/15 11:10, Sudeep Holla wrote: >> Though the keyboard and other driver will continue to support the legacy >> "gpio-key,wakeup", "linux-keypad,wakeup" boolean property to enable the >> wakeup source, "wakeup-source" is the new standard

Re: [PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties

On 16.12.2015 02:33, Bartlomiej Zolnierkiewicz wrote: > From: Thomas Abraham > > For Exynos542x/5800 platforms, add CPU operating points > for migrating from Exynos specific cpufreq driver to using > generic cpufreq driver. > > Changes by Bartlomiej: > - split Exynos5420

Re: [PATCH v10 0/17] Add Analogix Core Display Port Driver

Hi Heiko, On 12/15/2015 08:06 AM, Heiko Stübner wrote: Hi Yakir, Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang: The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller share the same IP, so a lot of parts can be re-used. I split the common code into bridge

[PATCH v11 02/19] drm: bridge: analogix/dp: fix some obvious code style

Fix some obvious alignment problems, like alignment and line over 80 characters problems, make this easy to be maintained later. Signed-off-by: Yakir Yang Reviewed-by: Krzysztof Kozlowski Tested-by: Javier Martinez Canillas

[PATCH v11 0/19] Add Analogix Core Display Port Driver

Hi all, The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller share the same IP, so a lot of parts can be re-used. I split the common code into bridge directory, then rk3288 and exynos only need to keep some platform code. Cause I can't find the exact IP name of exynos dp

[PATCH v11 05/19] dt-bindings: add document for analogix display port driver

Analogix dp driver is split from exynos dp driver, so we just make an copy of exynos_dp.txt, and then simplify exynos_dp.txt Beside update some exynos dtsi file with the latest change according to the devicetree binding documents. Signed-off-by: Yakir Yang Acked-by: Rob

[PATCH v11 11/19] drm: rockchip: vop: add bpc and color mode setting

From: Mark Yao Add bpc and color mode setting in rockchip_drm_vop driver, so connector could try to use the edid drm_display_info to config vop output mode. Signed-off-by: Mark Yao Signed-off-by: Yakir Yang --- Changes in v11:

[PATCH v11 15/19] drm: bridge: analogix/dp: move hpd detect to connector detect function

This change just make a little clean to make code more like drm core expect, move hdp detect code from bridge->enable(), and place them into connector->detect(). Note: Gustavo Padovan try to remove the controller and phy power on function in bind time at bellow commit: drm/exynos: do not

[PATCH v11 17/19] drm: bridge: analogix/dp: expand the look time for waiting AUX CH reply

After test on rockchiop platform, i found sometims driver would failed at reading EDID message. After debugging more, i found that it's okay to read_a byte from i2c, but it would failed at AUX transcation if we try to ready multi-bytes from i2c. Driver just can't received the AUX CH reply

[PATCH v11 18/19] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time

Turn off the panel power in suspend time would help to reduce power waste. Signed-off-by: Yakir Yang --- Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes

Re: [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote: > Hi, > > This patch series adds generic cpufreq-dt driver support for > Exynos542x/5800 (using the new CPU clock type which allows it). > > It has been tested on Exynos5422 based ODROID-XU3 Lite board. > > Depends on: > - next-20151211

[PATCH v11 07/19] drm: rockchip: dp: add rockchip platform dp driver

Rockchip have three clocks for dp controller, we leave pclk_edp to analogix_dp driver control, and keep the sclk_edp_24m and sclk_edp in platform driver. Signed-off-by: Yakir Yang Tested-by: Javier Martinez Canillas --- Changes in v11: None Changes

[PATCH v11 06/19] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver

After exynos_dp have been split the common IP code into analogix_dp driver, the analogix_dp driver have deprecated some Samsung platform properties which could be dynamically parsed from EDID/MODE/DPCD message, so this is an update for Exynos DTS file for dp-controller. Beside the backward

[PATCH v11 10/19] dt-bindings: add document for rockchip dp phy

Add dt binding documentation for rockchip display port PHY. Signed-off-by: Yakir Yang Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v11: - Correct the title of this rockchip dp phy document(Rob) - Add the ack from Rob

[PATCH v11 14/19] drm: bridge: analogix/dp: try force hpd after plug in lookup failed

Some edp screen do not have hpd signal, so we can't just return failed when hpd plug in detect failed. This is an hardware property, so we need add a devicetree property "analogix,need-force-hpd" to indicate this sutiation. Signed-off-by: Yakir Yang Acked-by: Rob Herring

[PATCH v11 16/19] drm: bridge: analogix/dp: add edid modes parse in get_modes method

Display Port monitor could support kinds of mode which indicate in monitor edid, not just one single display resolution which defined in panel or devivetree property display timing. Note: Gustavo Padovan try to remove the controller and phy power on function in bind time at bellow commit:

[PATCH v11 19/19] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time

It may caused a dead lock if we flush the hpd work in bridge disable time. The normal flow would like: IN --> DRM IOCTL 1. Acquire crtc_ww_class_mutex (DRM IOCTL) IN --> analogix_dp_bridge 2. Acquire hpd work lock (Flush hpd work) 3. HPD work already in idle, no need

[PATCH v11 03/19] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count

link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps,

[PATCH v11 04/19] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Both hsync/vsync polarity and interlace mode can be parsed from drm display mode, and dynamic_range and ycbcr_coeff can be judge by the video code. But presumably Exynos still relies on the DT properties, so take good use of mode_fixup() in to achieve the compatibility hacks. Signed-off-by:

[PATCH v11 09/19] phy: Add driver for rockchip Display Port PHY

Add phy driver for the Rockchip DisplayPort PHY module. This is required to get DisplayPort working in Rockchip SoCs. Signed-off-by: Yakir Yang Reviewed-by: Heiko Stuebner --- Changes in v11: None Changes in v10: - Fix the wrong macro value of

[PATCH v11 08/19] dt-bindings: add document for rockchip variant of analogix_dp

Rockchip DP driver is a helper driver of analogix_dp coder driver, so most of the DT property should be descriped in analogix_dp document. Signed-off-by: Yakir Yang Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v11: None

[PATCH v11 12/19] drm: bridge: analogix/dp: add some rk3288 special registers setting

RK3288 need some special registers setting, we can separate them out by the dev_type of plat_data. Signed-off-by: Yakir Yang Tested-by: Javier Martinez Canillas --- Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None

[PATCH v11 13/19] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288

There are some IP limit on rk3288 that only support 4 physical lanes of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag. Signed-off-by: Yakir Yang Tested-by: Javier Martinez Canillas --- Changes in v11: None Changes in v10: - Remove the