every 2 seconds for AC
detect, which is sufficient.
For proper functioning, requires (mfd: tps65090: Don't tell child
devices we have an IRQ if we don't). If we don't have that patch
we'll simply fail to probe on devices without an interrupt (just like
we did before this patch).
Signed-off-by: Doug
.
Doug Anderson (5):
mfd: tps65090: Don't tell child devices we have an IRQ if we don't
charger: tps65090: Allow charger module to be used when no irq
mfd: tps65090: Stop caching most registers
regulator: tps65090: Allow setting the overcurrent wait time
regulator: tps65090: Make FETs more
names).
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Leave cache on for the registers that can be cached.
- Move register offsets to mfd header file.
drivers/mfd/tps65090.c | 27 ++-
drivers/power/tps65090-charger.c | 11
Mark,
On Tue, Apr 15, 2014 at 3:52 PM, Mark Brown broo...@kernel.org wrote:
On Tue, Apr 15, 2014 at 01:14:36PM -0700, Doug Anderson wrote:
Mitigate the problem by:
* Allow setting the overcurrent wait time so devices with this problem
can set it to the max.
* Add retry logic on enables
Mark,
On Wed, Apr 16, 2014 at 3:13 AM, Mark Brown broo...@kernel.org wrote:
On Wed, Apr 16, 2014 at 10:59:22AM +0100, Lee Jones wrote:
NOTE: the IRQnMASK and CG_CTRLn registers are the exception and could
be cached. If we find that we spend a lot of time reading those we
can turn on
The tps65090 regulator allows you to specify how long you want it to
wait before detecting an overcurrent condition. Allow specifying that
through the device tree (or through platform data).
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed
was plugged in to AC power (when
the backlight voltage was higher).
Mitigate the problem by adding retries on the enables of the FETs,
which works around the problem fairly effectively.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Michael
-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v2:
- Split noirq (polling mode) changes into MFD and charger
drivers/mfd/tps65090.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd/tps65090.c b/drivers/mfd
Simon,
On Wed, Apr 16, 2014 at 1:50 PM, Simon Glass s...@chromium.org wrote:
+#define MAX_CTRL_READ_TRIES5
+#define MAX_FET_ENABLE_TRIES 1000
Gosh that is a lot of tries - should we maybe give up sooner?
That's actually a squash of a recent patch. See
Mark,
On Wed, Apr 16, 2014 at 1:51 PM, Mark Brown broo...@kernel.org wrote:
On Wed, Apr 16, 2014 at 11:25:24AM -0700, Doug Anderson wrote:
An issue was discovered with tps65090 where sometimes the FETs
wouldn't actually turn on when requested (they would report
overcurrent). The most
Mark,
On Wed, Apr 16, 2014 at 2:54 PM, Mark Brown broo...@kernel.org wrote:
On Wed, Apr 16, 2014 at 02:34:47PM -0700, Doug Anderson wrote:
On Wed, Apr 16, 2014 at 1:51 PM, Mark Brown broo...@kernel.org wrote:
Please don't send new patches as replies in the middle of threads, it
makes
-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v3: None
Changes in v2:
- Split noirq (polling mode) changes into MFD and charger
drivers/mfd/tps65090.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd
Randy,
On Wed, Apr 16, 2014 at 1:33 PM, Randy Dunlap rdun...@infradead.org wrote:
On 04/16/2014 11:25 AM, Doug Anderson wrote:
diff --git a/drivers/regulator/tps65090-regulator.c
b/drivers/regulator/tps65090-regulator.c
index 2e92ef6..ca13a1a 100644
--- a/drivers/regulator/tps65090
.
- For loop = while true.
- Removed a set of braces.
Doug Anderson (5):
mfd: tps65090: Don't tell child devices we have an IRQ if we don't
charger: tps65090: Allow charger module to be used when no irq
mfd: tps65090: Stop caching most registers
regulator: tps65090: Allow setting
The tps65090 regulator allows you to specify how long you want it to
wait before detecting an overcurrent condition. Allow specifying that
through the device tree (or through platform data).
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed
every 2 seconds for AC
detect, which is sufficient.
For proper functioning, requires (mfd: tps65090: Don't tell child
devices we have an IRQ if we don't). If we don't have that patch
we'll simply fail to probe on devices without an interrupt (just like
we did before this patch).
Signed-off-by: Doug
names).
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v3: None
Changes in v2:
- Leave cache on for the registers that can be cached.
- Move register offsets to mfd header file.
drivers/mfd/tps65090.c | 27 ++-
drivers/power/tps65090-charger.c
was plugged in to AC power (when
the backlight voltage was higher).
Mitigate the problem by adding retries on the enables of the FETs,
which works around the problem fairly effectively.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Michael
every 2 seconds for AC
detect, which is sufficient.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/tps65090.c | 14 ++--
drivers/power/tps65090-charger.c | 76 +++-
2 files changed, 70 insertions(+), 20 deletions(-)
diff --git
the backlight voltage higher.
Mitigate the problem by:
* Allow setting the overcurrent wait time so devices with this problem
can set it to the max.
* Add retry logic on enables of FETs.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off
on cache for just those registers.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/tps65090.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/mfd/tps65090.c b/drivers/mfd/tps65090.c
index c3cddb4..4cfdd07 100644
--- a/drivers/mfd/tps65090.c
+++ b/drivers
working on pure upstream, I augmented
the code to turn FET1 (vcd_led) on/off 500 times at bootup. When
testing I included https://patchwork.kernel.org/patch/3980731/ to
make sure tps65090 was in exynos5250-snow's device tree.
Doug Anderson (3):
mfd: tps65090: Allow charger module to be used when
Sachin,
On Mon, Apr 14, 2014 at 6:16 AM, Sachin Kamat sachin.ka...@linaro.org wrote:
From: Doug Anderson diand...@chromium.org
Added TPS65090 regulator related nodes to Snow board.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Sachin,
On Mon, Apr 14, 2014 at 6:16 AM, Sachin Kamat sachin.ka...@linaro.org wrote:
From: Doug Anderson diand...@chromium.org
Added TPS65090 regulator related nodes to Snow board.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Tomasz,
On Mon, Apr 14, 2014 at 3:38 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Doug,
On 15.04.2014 00:30, Doug Anderson wrote:
Sachin,
On Mon, Apr 14, 2014 at 6:16 AM, Sachin Kamat sachin.ka...@linaro.org
wrote:
From: Doug Anderson diand...@chromium.org
I probably wouldn't
Sachin,
On Mon, Apr 14, 2014 at 6:16 AM, Sachin Kamat sachin.ka...@linaro.org wrote:
From: Doug Anderson diand...@chromium.org
For this patch in particular giving me authorship is pretty tenuous.
I don't think I was even the author of the majority of the code in the
chromium tree.
Added
have seen the -EIO return
instead.
Signed-off-by: Olof Johansson o...@lixom.net
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/i2c/busses/i2c-s3c2410.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c
Tomasz,
On Fri, Feb 7, 2014 at 3:59 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 07.02.2014 23:15, Olof Johansson wrote:
On Thu, Feb 06, 2014 at 08:12:45PM +0100, Tomasz Figa wrote:
On Exynos4210-based Trats, Exynos4412-based Trats2 and Exynos5250-based
Arndale boards (except
WIll,
Thanks for your comments!
On Wed, Jan 8, 2014 at 6:35 AM, Will Deacon will.dea...@arm.com wrote:
On Wed, Jan 08, 2014 at 01:33:11PM +, Vivek Gautam wrote:
The erratum-773769 occurs on Arm Coretex-A15 (rev r2p0),
when L2 Data Ram latency is set to 4 cycles or more; or
when ACP is in
Hi,
On Wed, Jan 8, 2014 at 11:20 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, Jan 08, 2014 at 08:21:21AM -0800, Doug Anderson wrote:
WIll,
Thanks for your comments!
On Wed, Jan 8, 2014 at 6:35 AM, Will Deacon will.dea...@arm.com wrote:
NAK. Whilst I appreciate
Nicolas,
On Wed, Jan 8, 2014 at 12:58 PM, Nicolas Pitre n...@fluxnic.net wrote:
On Wed, 8 Jan 2014, Doug Anderson wrote:
On Wed, Jan 8, 2014 at 11:20 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
We've been through these arguments many times, you're not the first to
raise
Russell,
On Wed, Jan 8, 2014 at 1:02 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, Jan 08, 2014 at 11:43:29AM -0800, Doug Anderson wrote:
Olof came up with the idea that you could update the RW firmware
(affects initial boot) and then cache away the value and restore
Nicolas,
On Wed, Jan 8, 2014 at 1:08 PM, Nicolas Pitre n...@fluxnic.net wrote:
On Wed, 8 Jan 2014, Doug Anderson wrote:
Hi,
On Wed, Jan 8, 2014 at 11:20 AM, Russell King - ARM Linux
No, we're saying to put the work-around in the boot loader, not the kernel.
Unfortunately the resume path
it the exynos5250 prefix that the boards have.
Signed-off-by: Mark Brownbroo...@linaro.org
Acked-by: Tomasz Figat.f...@samsung.com
The rename makes a lot of sense to me.
Reviewed-by: Doug Anderson diand...@chromium.org
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Tomasz,
On Fri, Dec 20, 2013 at 1:19 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi,
On Friday 20 of December 2013 15:56:38 sunil joshi wrote:
Hi Abhilash,
I saw another patch in chrome tree ..by Andrew Bresticker
which may be relevant here ..
Just wondering if you missed adding this ?
problems with backslash).
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos5250-snow.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index fd711e2..28fe2e2 100644
--- a/arch/arm/boot/dts
it.
* There is no L_META key on the board, so it's nice to have.
* For those people who really want it to be caps lock, they can use
xmodmap or somesuch.
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos5250-snow.dts | 2 +-
1 file changed, 1 insertion(+), 1
Leela Krishna,
On Wed, Dec 11, 2013 at 4:22 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Hi,
As I was in travel not accessed my mails.
I'll try to post next version of this series tomorrow addressing
Sylwester's comments.
It's completely up to you (and Wim), of course. ...but if
). You'd have to extend that to add a clock, but that
wouldn't be too hard.
That being said, I'd personally be OK with this solution for now (to
match the other exynos products), so:
Reviewed-by: Doug Anderson diand...@chromium.org
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Abhliash,
On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan a.kesa...@samsung.com wrote:
Fix the following warning message:
[ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399
irq_create_mapping+0xe4/0xfc()
[ 2921.679907] irq_create_mapping(, b) called with NULL domain
[
Tomasz,
On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
2013/12/12 Doug Anderson diand...@chromium.org:
This does match what's done in exynos4 and exynos5420 and it's not
terrible. I'm always a fan of actually specifying clocks properly and
that's more possible now
Yuvaraj,
On Sun, Dec 8, 2013 at 10:38 PM, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
Commit 0c3de788 (ARM: dts: change status property of dwmmc nodes
for exynos5250) missed out handling the exynos5250 snow dts file.
Signed-off-by : Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by:
specific exynos5250.dtsi file.
Signed-off-by : Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
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the body of a message
Hi,
On Mon, Dec 9, 2013 at 1:07 PM, Kukjin Kim kgene@samsung.com wrote:
On 12/10/13 00:23, Tomasz Figa wrote:
Hi Kukjin,
Hi,
On Monday 25 of November 2013 12:15:08 Mark Brown wrote:
From: Mark Brownbroo...@linaro.org
Rather than requiring each board to explicitly disable the SPI
add my Reviewed-by:
Reviewed-by: Doug Anderson diand...@chromium.org
-Doug
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More majordomo info at http://vger.kernel.org/majordomo-info.html
...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 15 +++
arch/arm/boot/dts/exynos5250.dtsi |5
/disable of watchdog in probe and s2r scenarios.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
---
.../devicetree/bindings/watchdog/samsung-wdt.txt | 21 ++-
drivers/watchdog/Kconfig |1
Guenter,
On Fri, Dec 6, 2013 at 11:54 AM, Guenter Roeck li...@roeck-us.net wrote:
On Thu, Dec 05, 2013 at 10:15:29AM -0800, Doug Anderson wrote:
A good watchdog driver is supposed to report when it was responsible
for resetting the system. Implement this for the s3c2410, at least
, but providing
that is left as an exercise for future changes and is not plumbed up
in this patch series. Also note the exynos4 SoCs don't appear to need
any PMU config, which is why this patch separates the concepts of
having PMU Registers vs. needing PMU Config.
Signed-off-by: Doug Anderson
driver
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Acked-by: Guenter Roeck li...@roeck-us.net
I'm curious of your opinion of Sylwester's
Guenter and Olof,
On Mon, Dec 2, 2013 at 1:36 PM, Guenter Roeck li...@roeck-us.net wrote:
On Mon, Dec 02, 2013 at 12:47:53PM -0800, Olof Johansson wrote:
On Mon, Dec 2, 2013 at 12:21 PM, Guenter Roeck li...@roeck-us.net wrote:
On Mon, Dec 02, 2013 at 10:14:41AM -0800, Doug Anderson wrote
Tomasz,
On Thu, Dec 5, 2013 at 8:21 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi Doug,
Please see my comments inline.
On Monday 02 of December 2013 10:14:41 Doug Anderson wrote:
A good watchdog driver is supposed to report when it was responsible
for resetting the system. Implement
-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Added EXYNOS5 prefix to REG_OFFSET defines (Tomasz)
- NEEDS_PMU_CONFIG = HAS_PMU_CONFIG (Olof, Guenter)
- Move QUIRK_HAS_PMU_CONFIG to (Guenter)
drivers/watchdog/s3c2410_wdt.c | 59 +++---
1 file
Guenter,
On Thu, Dec 5, 2013 at 8:40 AM, Guenter Roeck li...@roeck-us.net wrote:
On Thu, Dec 05, 2013 at 05:21:47PM +0100, Tomasz Figa wrote:
Hi Doug,
Please see my comments inline.
On Monday 02 of December 2013 10:14:41 Doug Anderson wrote:
A good watchdog driver is supposed to report
, but providing
that is left as an exercise for future changes and is not plumbed up
in this patch series. Also note the exynos4 SoCs don't appear to need
any PMU config, which is why this patch separates the concepts of
having PMU Registers vs. needing PMU Config.
Signed-off-by: Doug Anderson
-us.net wrote:
On Mon, Dec 02, 2013 at 12:47:53PM -0800, Olof Johansson wrote:
On Mon, Dec 2, 2013 at 12:21 PM, Guenter Roeck li...@roeck-us.net
wrote:
On Mon, Dec 02, 2013 at 10:14:41AM -0800, Doug Anderson wrote:
A good watchdog driver is supposed to report when
and exynos5420 dtsi files to
handle PMU register accesses in a centralized way using syscon driver
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand
Leela Krishna,
On Mon, Dec 2, 2013 at 9:32 AM, Doug Anderson diand...@chromium.org wrote:
Leela Krishna,
On Wed, Nov 27, 2013 at 8:34 PM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Add device tree support for exynos5250 and 5420 SoCs and use syscon regmap
interface
to configure
Tomasz,
On Thu, Dec 5, 2013 at 10:30 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
I'd vote for using pmu-system-registers. We end up using the
syscon subsystem but really we're describing pmu registers.
I'd even say that you don't need to formally specify the name in the
bindings (though
Tomasz,
On Thu, Dec 5, 2013 at 10:59 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Thursday 05 of December 2013 10:35:20 Doug Anderson wrote:
Tomasz,
On Thu, Dec 5, 2013 at 10:30 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
I'd vote for using pmu-system-registers. We end up using
++--
3 files changed, 171 insertions(+), 10 deletions(-)
Tested on ARM Chromebook in a backport to 3.8. See
https://chromium-review.googlesource.com/#/c/177932/3 for this
patch.
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Guenter and Olof,
On Mon, Dec 2, 2013 at 12:21 PM, Guenter Roeck li...@roeck-us.net wrote:
On Mon, Dec 02, 2013 at 10:14:41AM -0800, Doug Anderson wrote:
A good watchdog driver is supposed to report when it was responsible
for resetting the system. Implement this for the s3c2410, at least
to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/watchdog/s3c2410_wdt.c | 10 +-
1 file changed, 5 insertions(+), 5
Guenter,
On Tue, Nov 26, 2013 at 10:48 AM, Guenter Roeck li...@roeck-us.net wrote:
On 11/26/2013 10:30 AM, Doug Anderson wrote:
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32
to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2
Guenter,
On Tue, Nov 26, 2013 at 4:10 PM, Guenter Roeck li...@roeck-us.net wrote:
On 11/26/2013 01:34 PM, Doug Anderson wrote:
Guenter,
On Tue, Nov 26, 2013 at 10:48 AM, Guenter Roeck li...@roeck-us.net
wrote:
On 11/26/2013 10:30 AM, Doug Anderson wrote:
The existing watchdog timeout
, 26 insertions(+)
Looks good to me. I've tested this applied to our local tree
https://chromium-review.googlesource.com/#/c/177931/ and it's
working well for me.
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
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Hi Leela Krishna,
On Mon, Nov 18, 2013 at 1:49 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Add device tree support for exynos5250 and 5420 SoCs and use syscon regmap
interface
to configure AUTOMATIC_WDT_RESET_DISABLE and MASK_WDT_RESET_REQUEST registers
of PMU
to mask/unmask
this locally running in our tree
https://chromium-review.googlesource.com/#/c/177933/ based on your
patch.
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
-Doug
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the body
(the watchdog is constantly patted
by the kernel). If we need CPU_FREQ_S3C24XX defined on a
multiplatform kernel we'll need to make sure that kernel supports
common clock and change this to user common clock framework.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/watchdog
Guenter,
On Mon, Nov 25, 2013 at 3:23 PM, Guenter Roeck li...@roeck-us.net wrote:
On 11/25/2013 02:55 PM, Doug Anderson wrote:
On modern SoCs the watchdog timer is parented on a clock that doesn't
change every time we have a cpufreq change. That means we don't need
to constantly adjust
ch.nav...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
Changes since v2:
None, Rebased on for-next of linux-i2c git repo.
Changes since v1:
Use CONFIG_CPU_FREQ_S3C24XX instead of (CONFIG_CPU_FREQ !CONFIG_EXYNOS)
As commented
useless (the watchdog is constantly patted
by the kernel). If we need ARM_S3C24XX_CPUFREQ defined on a
multiplatform kernel we'll need to make sure that kernel supports
common clock and change this to user common clock framework.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes
On Tue, Nov 19, 2013 at 10:46 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 11/19/2013 10:15 AM, Tomasz Figa wrote:
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins.
Shouldn't there be a
://patchwork.kernel.org/patch/2279591/
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Lars-Peter Clausen l...@metafoo.de
---
Changes since v1:
As per discussion at
http://marc.info/?l=linux-kernelm=136517637228869w=3
Changes since v2:
None.
Rebased
|4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Looks great to me. Thank you for the suggestions Tomasz, as always.
Reviewed-by: Doug Anderson diand...@chromium.org
We need to come up with a solution for the CPU_FREQ stuff in
s3c2410_wdt too. We could use a similar solution
Tomasz,
On Fri, Oct 11, 2013 at 7:06 PM, Tomasz Figa t.f...@samsung.com wrote:
Well, it's some kind of difference indeed. However, how often can
a frequency transition happen?
I believe that ondemand allows minimum sampling period of
100 * transition latency, so even without considering the
Arun,
On Mon, Oct 7, 2013 at 11:56 PM, Arun Kumar K arun...@samsung.com wrote:
PLL35XX lock factor is 250 as per the manual whereas its
wrongly set as 270 now.
Signed-off-by: Arun Kumar K arun...@samsung.com
---
drivers/clk/samsung/clk-pll.c |4 ++--
1 file changed, 2 insertions(+), 2
Tomasz,
On Sat, Sep 28, 2013 at 6:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Fri, Sep 27, 2013 at 11:14 AM, Tomasz Figa tomasz.f...@gmail.com
wrote:
So isn't the register in the PMU there to save power in the case that
the watchdog timer isn't being used? How is the PMU driver to
Tomasz,
On Fri, Sep 27, 2013 at 11:14 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
So isn't the register in the PMU there to save power in the case that
the watchdog timer isn't being used? How is the PMU driver to know
whether the watchdog is being used? Better IMHO that the watchdog
---
arch/arm/boot/dts/exynos5.dtsi|2 +-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Doug Anderson diand...@chromium.org
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Reviewed-by: Doug Anderson diand...@chromium.org
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Tomasz,
On Tue, Sep 17, 2013 at 6:30 AM, Tomasz Figa t.f...@samsung.com wrote:
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -7,8 +7,20 @@ occurred.
Required properties:
- compatible : should be
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events due
to a silicon errata. It is safe to do on all exynos variants.
Signed-off-by: Doug
in v4:
- Take Seungwon's suggestion and don't add any dw_mmc-pltfm code.
Changes in v3:
- Add freeze/thaw and poweroff/restore noirq entries.
Changes in v2:
- Use suspend_noirq as per James Hogan.
Doug Anderson (3):
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
mmc: dw_mmc
reference that patch anywhere. I also wouldn't have tagged this ARM:
dts, since this doesn't actually update a dts file. I'd probably
tag it mmc: dw_mmc:. You should probably re-spin for that.
Aside from that this looks fine to me.
Reviewed-by: Doug Anderson diand...@chromium.org
b.samsung,dw-mshc-ciu-div
c.samsung,dw-mshc-sdr-timing
d.samsung,dw-mshc-ddr-timing
from SOC dts to board dts file as suggested by Doug Anderson
changes since V2:
1.dropped num-slots property from node as its not required
Naveen
On Tue, Aug 27, 2013 at 10:33 PM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
I would like to know any comments on
https://patchwork.kernel.org/patch/2513361/
Its been pending for a while now.
Thanks,
Naveen
Ping
Any comments please
I assume you're asking for a ping for
Yuvaraj,
On Thu, Aug 22, 2013 at 11:25 PM, Yuvaraj Cd yuvaraj.l...@gmail.com wrote:
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
OK, so I don't know about
:
- Add freeze/thaw and poweroff/restore noirq entries.
Changes in v2:
- Use suspend_noirq as per James Hogan.
Doug Anderson (3):
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
mmc: dw_mmc: Honor requests to set the clock to 0 (turn off clock)
mmc: dw_mmc: Set timeout
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events due
to a silicon errata. It is safe to do on all exynos variants.
Signed-off-by: Doug
Hi,
Thanks for adding my Thomasz,
On Thu, Aug 22, 2013 at 4:51 AM, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from
Seungwon,
On Wed, Aug 21, 2013 at 4:48 AM, Seungwon Jeon tgih@samsung.com wrote:
Hi Doug,
Do you have any update for this series?
Please let me know.
Thank you for the ping. The changes requested looked big enough that
I knew I was going to have to devote some time to looking this all
Hi,
On Thu, Aug 8, 2013 at 8:18 PM, Seungwon Jeon tgih@samsung.com wrote:
On Fri, August 09, 2013, Chris Ball wrote:
On Fri, Aug 09 2013, Olof Johansson wrote:
On Thu, Aug 8, 2013 at 5:16 PM, Doug Anderson diand...@google.com wrote:
I guess my overall question
:
- Fix typo (some - come)
- Use ~0 instead of 0x; add comment about value
- Use suspend_noirq as per James Hogan.
Doug Anderson (4):
mmc: dw_mmc: Invalidate cache of current_speed after suspend/resume
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
mmc: dw_mmc
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events due
to a silicon errata. It is safe to do on all exynos variants.
Signed-off-by: Doug
Fabio,
Thanks for your review.
On Fri, Aug 9, 2013 at 9:41 AM, Fabio Estevam feste...@gmail.com wrote:
On Fri, Aug 9, 2013 at 1:33 PM, Doug Anderson diand...@chromium.org wrote:
+#else
+#define dw_mci_exynos_suspend NULL
+#define dw_mci_exynos_resume NULL
+#define
Hi,
A quick question: does anyone know of any hardware that actually
implements multiple slots per host on the dw_mmc controller?
When working on the driver I often find myself running into questions
about how things should work on the theoretical multiple slot dw_mmc
implementation. ...and I
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events due
to a silicon errata. It is safe to do on all exynos variants.
Signed-off-by: Doug
Tomasz,
On Tue, Aug 6, 2013 at 2:58 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
+static int dw_mci_exynos_resume_noirq(struct device *dev)
+{
+ struct dw_mci *host = dev_get_drvdata(dev);
+ u32 clksel;
+
+ clksel = mci_readl(host, CLKSEL);
+ if (clksel
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