Hello Marek,
On 01/22/2015 01:41 PM, Marek Szyprowski wrote:
+ mixer_res-hdmi = devm_clk_get(dev, hdmi);
You need to update the
Documentation/devicetree/bindings/video/exynos_mixer.txt
DT binding docs to also mention the hdmi clock in the list of clocks.
Right, I've send an updated
.
Suggested-by: Andrzej Hajda a.ha...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
The patch looks good to me and I tested that it does not regress HDMI on
other platforms (Exynos5420 Peach Pit). I've just a comment below.
Reviewed-by: Javier Martinez Canillas
patches:
Bill Richardson (4):
platform/chrome: Add cros_ec_lpc driver for x86 devices
platform/chrome: Add Chrome OS EC userspace device interface
platform/chrome: Create sysfs attributes for the ChromeOS EC
platform/chrome: Expose Chrome OS Lightbar to users
Javier Martinez Canillas (3
byte boundaries, use fixed size arrays instead of pointers
for transferring ingoing and outgoing data with the Embedded Controller.
Also, re-arrange struct members by decreasing alignment requirements to
reduce the needing padding size.
Signed-off-by: Javier Martinez Canillas javier.marti
The ChromeOS EC character device is an user-space interface to
allow applications to access the Embedded Controller.
Add a cell for this device so it's spawned from the mfd driver.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Acked-by: Lee Jones lee.jo...@linaro.org
echo ro reboot
cat version
echo rw reboot
cat version
echo cold reboot
That last command will reboot the AP too.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti
Reviewed-by: Olof Johansson ol...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Reviewed-by: Benson Leung ble...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v4: None.
Changes since v3: None.
Changes since v2: None.
Changes
.
Currently, there are drivers to communicate with the EC over
I2C and SPI and this driver adds support for LPC.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v4:
- Move from drivers/misc to drivers
From: Bill Richardson wfric...@chromium.org
This patch adds a device interface to access the
Chrome OS Embedded Controller from user-space.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Simon Glass s...@google.com
Signed-off-by: Javier Martinez Canillas javier.marti
The ChromeOS Embedded Controller has to be accessed by applications.
A virtual character device is used as an interface with user-space.
Extend the struct cros_ec_device with the fields needed by the driver
of this virtual character device.
Signed-off-by: Javier Martinez Canillas javier.marti
Hello,
On 01/30/2015 01:51 PM, Javier Martinez Canillas wrote:
On 01/29/2015 10:11 PM, Paul Bolle wrote:
+ help
+ If you say Y here, you get support for talking to the ChromeOS EC
+ over an LPC bus. This uses a simple byte-level protocol with a
+ checksum. This is used
Hello Sergei,
Thanks a lot for your feedback.
On 02/06/2015 08:09 PM, Sergei Shtylyov wrote:
Hello.
On 02/06/2015 08:37 PM, Javier Martinez Canillas wrote:
All the device nodes for the Exynos5420 power-domains have a quite
generic power-domain name.
And this is in conformance
Hello Kukjin,
On 01/30/2015 02:06 PM, Javier Martinez Canillas wrote:
On 01/30/2015 12:13 PM, Ulf Hansson wrote:
Patch #1 extends the simple MMC power sequence DT binding to support more
than one GPIO and patch #2 adds the actual implementation.
In the same way, patch #3 and #4 extend
Hello Kukjin,
On 02/04/2015 04:19 PM, Kukjin Kim wrote:
On 02/05/15 00:06, Javier Martinez Canillas wrote:
I noticed that you are applying patches to your Samsung tree, do you want me
to
re-send patches #5 and #6 or is OK for you to pick them from from this
series?
Oh, I've missed
://permalink.gmane.org/gmane.linux.kernel.samsung-soc/42743
Your patches looks good to me so please feel free to add:
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
I also tested on an Exynos5420 Peach Pit Chromebook and both the Power
domain power-domain disable failed message and the system
Hello Andrzej,
On 02/06/2015 11:55 AM, Andrzej Hajda wrote:
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Hi,
This is 2nd version of the
Hello Joonyoung,
On 02/06/2015 06:27 AM, Joonyoung Shim wrote:
On 02/05/2015 11:45 PM, Javier Martinez Canillas wrote:
I also tested on an Exynos5420 Peach Pit Chromebook and both the Power
domain power-domain disable failed message and the system crash are gone.
Really gone out Power
.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/boot/dts/exynos5420.dtsi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index b63b569ca4b4..4642cec50c0d 100644
Many Exynos boards have an HDMI port so enable Exynos DRM HDMI support.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Exynos DRM HDMI has some issues that were fixed by Andrzej's [0] series.
So now is safe to HDMI support for Exynos boards.
[0]: https://lkml.org
From: Tushar Behera tusha...@samsung.com
On Snow, Peach Pit and Peach Pi boards, the Exynos SoC XCLKOUT output pin
provides the master clock (mclk) to codecs. So make them a clock consumer.
Signed-off-by: Tushar Behera tusha...@samsung.com
Signed-off-by: Javier Martinez Canillas javier.marti
From: Tushar Behera tusha...@samsung.com
On Snow, Peach Pit and Peach Pi boards, the Exynos SoC XCLKOUT output pin
provides the master clock (mclk) to codecs. So make them a clock consumer.
Signed-off-by: Tushar Behera tusha...@samsung.com
Signed-off-by: Javier Martinez Canillas javier.marti
of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk-exynos5420.c | 23 ---
include/dt-bindings/clock/exynos5420.h | 6 ++
2 files
a reference to the input
and parent clocks of the devices are needed to manage that.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/boot/dts/exynos5420.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
Hello Marek,
On 01/20/2015 01:16 PM, Marek Szyprowski wrote:
Mixed need to have hdmi clock enabled to properly perform power on/off
sequences, so add handling of this clock directly to the mixer driver.
Dependency between hdmi clock and mixer module has been observed on
Exynos4 based boards.
the exynos_mixer driver needing clocks enabled
by the exynos_hdmi driver that are gated on hdmi_poweroff().
The same issue has been reported on other Exynos platforms so it's orthogonal
to this series and needs to be fixed for all platforms.
Javier Martinez Canillas (2):
clk: exynos5420: Add IDs for clocks
[Adding Inki and Joonyoung to cc list]
Hello Marek,
On Mon, Jan 19, 2015 at 5:30 PM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
The board instantly died then. No kernel log output from the serial
console, the heartbeat just stops and the board is dead. Need to
power-cycle to get it
Hello Joonyoung,
On 01/20/2015 12:12 PM, Joonyoung Shim wrote:
I dug further on this issue and found that the cause is that the
exynos_mixer
driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
to be kept enabled after hdmi_poweroff
Hello Lee,
On 01/20/2015 05:36 PM, Lee Jones wrote:
Is this safe? Are you sure it's okay to provide an interface from
userspace to read (kernel?) memory?
This interface is not to read any kernel memory but only the memory mapped
I/O region for the Low Pin Count (LPC) bus. So
Hello Lee,
On 01/20/2015 05:55 PM, Lee Jones wrote:
On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
Hello Lee,
On 01/20/2015 05:29 PM, Lee Jones wrote:
It's not a blocker, but it is a ridiculous name to use inside the
driver/ directory 'cos almost everything is a dev(ice) here
Hello Lee,
On 01/20/2015 05:34 PM, Lee Jones wrote:
So, the Embedded Controller driver (drivers/mfd/cros_ec.c) falls into that
category and in fact has been in the mfd driver for a long time. Now, if
an mfd device support different type of buses (e.g: i2c, spi, etc) I see
that both the core
Hello Lee,
Thanks a lot for your feedback.
On 01/20/2015 08:50 AM, Lee Jones wrote:
@@ -59,9 +60,17 @@ struct cros_ec_command {
*
* @ec_name: name of EC device (e.g. 'chromeos-ec')
* @phys_name: name of physical comms layer (e.g. 'i2c-4')
- * @dev: Device pointer
+ * @dev: Device
Hello Lee,
On 01/20/2015 08:48 AM, Lee Jones wrote:
Looks okay to me, but I'd be happy with some more reviews from the
Chrome guys. I would especially like some knowledgeable type to
answer your EC_PROTO2_MAX_PARAM_SIZE question. If no one does, I
guess it can always be changed later.
Hello Lee,
Thanks a lot for your feedback.
On 01/20/2015 09:20 AM, Lee Jones wrote:
On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
The ChromeOS EC character device is an user-space interface to
allow applications to access the Embedded Controller.
Add a cell for this device so it's
Hello Lee,
On 01/20/2015 05:29 PM, Lee Jones wrote:
It's not a blocker, but it is a ridiculous name to use inside the
driver/ directory 'cos almost everything is a dev(ice) here.
Right, do you think that cros-ec-chardev will be a more suitable
name? Sorry, I'm really bad at naming
Hello Lee,
On 01/20/2015 06:11 PM, Javier Martinez Canillas wrote:
But is it really a chardev? Don't chardevs usually live in
drivers/char? It probably uses a chardev node in /dev, but what does
it really do? What information can/will userspace obtain from this
memory block?
Right
Hello Lee,
On 01/20/2015 05:52 PM, Javier Martinez Canillas wrote:
Now, all those drivers may be wrong and the buses don't belong to the mfd
subsystem but then I think we need to document that since it seems that is
the correct way to do it just by looking at the other drivers.
I don't
Hello Lee,
On 01/22/2015 09:42 AM, Lee Jones wrote:
I don't think the drivers you mentioned above do anything practical.
For instance, they are not SPI/IC2/etc drivers. They should only
offer some abstraction layers which are used to communicate with the
device. The driver you are
Hello Marek,
I wanted to test your IOMMU series on an Exynos5420 Peach Pit but the
kernel hangs with your series + dependencies on top of 3.19-rc5.
Bisecting I found that $subject is the offending commit. I've pushed
my test branch [0] in case I missed something.
On Fri, Jan 16, 2015 at 10:13
Hello Thierry,
On 01/05/2015 02:50 PM, Thierry Reding wrote:
On Fri, Jan 02, 2015 at 01:10:14PM +, Daniel Stone wrote:
Ajay's series don't apply cleanly anymore because it has been a while since
he posted it but he can rebase on top of 3.19-rc1 once it is released and
re-resend.
: rebased onto generic power domains dt bindings]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 file changed, 10 insertions(+)
This patch makes HDMI to work on my Exynos5250 Snow Chromebook:
Tested-by: Javier Martinez Canillas
dropped so here goes again:
For the whole series on an Exynos5420 Peach Pit and an Exynos5250 Snow
Chromebooks:
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Also I think the last update was that Ajay was going to resend this
based on v3.19-rc1 or something. Is that still
Hello Kukjin,
On 01/14/2015 04:17 PM, Kukjin Kim wrote:
pinctrl_0 {
+power_key_irq: power-key-irq {
+samsung,pins = gpx1-3;
+samsung,pin-function = 0xf;
I think, this setting should be same with exynos5250-spring but different.
from:
Hello Kukjin,
On 01/14/2015 04:28 PM, Kukjin Kim wrote:
I saw that you collected some DTS patches for 3.20 but these are not
included. Any comments about this series?
Yeah, but I don't think I checked all of submitted patches including
this at that time and I'll have a look at this series
Hello Lee,
On 01/22/2015 10:46 AM, Lee Jones wrote:
But there doesn't seem to be a LPC subsystem in the kernel so we don't have a
nice abstraction layer in this case.
This is the crux of the problem. However, I feel bad for MFD, as it
is, once more, being used as an well it doesn't fit
Hello,
On 01/20/2015 06:54 PM, Mike Turquette wrote:
Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented
byte boundaries, use fixed size arrays instead of pointers
for transferring ingoing and outgoing data with the Embedded Controller.
Also, re-arrange struct members by decreasing alignment requirements to
reduce the needing padding size.
Signed-off-by: Javier Martinez Canillas javier.marti
From: Bill Richardson wfric...@chromium.org
This patch adds a device interface to access the
Chrome OS Embedded Controller from user-space.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Simon Glass s...@google.com
Signed-off-by: Javier Martinez Canillas javier.marti
.
Currently, there are drivers to communicate with the EC over
I2C and SPI and this driver adds support for LPC.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- Move out from drivers/mfd
The ChromeOS Embedded Controller has to be accessed by applications.
A virtual character device is used as an interface with user-space.
Extend the struct cros_ec_device with the fields needed by the driver
of this virtual character device.
Signed-off-by: Javier Martinez Canillas javier.marti
The ChromeOS EC character device is an user-space interface to
allow applications to access the Embedded Controller.
Add a cell for this device so it's spawned from the mfd driver.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- Rename the name
echo ro reboot
cat version
echo rw reboot
cat version
echo cold reboot
That last command will reboot the AP too.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti
Reviewed-by: Olof Johansson ol...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Reviewed-by: Benson Leung ble...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2: None
Changes since v1:
- Moved from drivers/mfd to drivers
Chrome OS Lightbar to users
Javier Martinez Canillas (3):
mfd: cros_ec: Use fixed size arrays to transfer data with the EC
mfd: cros_ec: Add char dev and virtual dev pointers
mfd: cros_ec: Instantiate ChromeOS EC character device
Documentation/ioctl/ioctl-number.txt | 1 +
drivers/i2c
Hello Simon,
On 02/18/2015 03:26 AM, Simon Glass wrote:
On 16 February 2015 at 01:19, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Olof,
On 02/02/2015 12:26 PM, Javier Martinez Canillas wrote:
Hello,
The mainline ChromeOS Embedded Controller (EC) driver is still
= 8;
cap-mmc-highspeed;
};
--
Your patch looks good to me though from what I've seen in the Odroid
XU3 schematic and taking into account that the eMMC can be removed in
that board.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
Hello Stephen,
On 02/12/2015 08:55 PM, Stephen Boyd wrote:
On 02/12/15 05:58, Javier Martinez Canillas wrote:
After the clk API change to return a per-user clock instance, both the
struct clk_core and struct clk pointers from the hw clock needs to be
assigned to clock that share the same
Hello Stephen,
On 02/12/2015 08:55 PM, Stephen Boyd wrote:
On 02/12/15 05:58, Javier Martinez Canillas wrote:
The changes were made using the following cocinelle semantic patch:
@i@
@@
@depends on i@
identifier dst;
@@
- dst-clk = hw-clk;
+ __clk_hw_set_clk(dst, hw);
@depends on i
Exynos5420 Peach Pit and Exynos5800 Peach Pi boards have a MMC/SDIO
Marvell WiFi-Ex chip. This patch enables wireless support and the
mwifiex driver.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/configs/exynos_defconfig | 4
1 file changed, 4
(e7f001f2)
[1.754502] ---[ end trace f58ad362326928d7 ]---
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/configs/exynos_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/exynos_defconfig
b/arch/arm/configs/exynos_defconfig
index
Hello Charles,
On Tue, Feb 17, 2015 at 5:58 PM, Charles Keepax
ckee...@opensource.wolfsonmicro.com wrote:
This reverts commit 8dcc14f82f06fce997e35f4c77ced9d4ed192f31.
This patch causes this error on Arndale:
IMHO the commit you are referring is correct so it should not be
reverted but I also
Hello Andreas,
We already talked over irc but for completeness I'll comment here
as well.
On 02/19/2015 07:54 PM, Andreas Färber wrote:
Am 19.02.2015 um 19:40 schrieb Andreas Färber:
Am 19.02.2015 um 18:48 schrieb Doug Anderson:
On Thu, Feb 19, 2015 at 6:13 AM, Andreas Färber afaer...@suse.de
1 file changed, 4 insertions(+), 12 deletions(-)
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More
Hello Andreas,
On 02/18/2015 05:17 PM, Andreas Färber wrote:
Configure the pins in external interrupt mode, as done for Snow in
e5e5c6d14e39 (ARM: dts: Add power and lid GPIO keys pinctrl for
exynos5250-snow).
Reported-by: Kukjin Kim kg...@kernel.org
Suggested-by: Javier Martinez Canillas
Hello Kukjin,
On 02/06/2015 06:52 PM, Javier Martinez Canillas wrote:
From: Tushar Behera tusha...@samsung.com
On Snow, Peach Pit and Peach Pi boards, the Exynos SoC XCLKOUT output pin
provides the master clock (mclk) to codecs. So make them a clock consumer.
Signed-off-by: Tushar Behera
Hello Andreas,
On 02/18/2015 07:25 PM, Andreas Färber wrote:
Signed-off-by: Andreas Färber afaer...@suse.de
---
Documentation/devicetree/bindings/sound/max98088.txt | 16
1 file changed, 16 insertions(+)
create mode 100644
Hello Andreas,
On 02/18/2015 07:25 PM, Andreas Färber wrote:
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/exynos5250-spring.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts
Hello Krzysztof,
On 02/17/2015 01:20 PM, Krzysztof Kozlowski wrote:
On wto, 2015-02-17 at 12:38 +0100, Javier Martinez Canillas wrote:
Enabling Exynos DRM IOMMU support for Exynos is currently broken and
causes a BUG on exynos-iommu driver. This was not an issue since the
options was disabled
number, it uses the of_gpio_named_count()
since the MMC power sequence is only built when CONFIG_OF is enabled.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mmc/core/pwrseq_simple.c | 54 ++--
1 file changed, 41 insertions
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Documentation/devicetree
is not found.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mmc/core/pwrseq_simple.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
index
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- Make the explanation clearer by adding an explicit
is not found.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- Rebase on top of latest changes.
- Use IS_ERR() instead of checking for NULL to see if the clock exists.
---
drivers/mmc/core/pwrseq_simple.c | 34 --
1 file
MMC/SDIO slot.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/boot/dts/exynos5250-snow.dts | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250
Enabling SDIO IRQ signalling for the wifi MMC/SDIO slot
doubles the transmission transfer rate.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1: None, new patch.
---
arch/arm/boot/dts/exynos5250-snow.dts | 1 +
1 file changed, 1 insertion(+)
diff
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 6 +++---
1
clock.
This is the second version of the series that addressed issues pointed out
by Arend van Spriel and Srinivas Kandagatla.
The series depend on v4 mmc: core: Add support for MMC power sequences:
http://comments.gmane.org/gmane.linux.kernel.mmc/30665
Javier Martinez Canillas (6):
mmc: pwrseq
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1: None
number, it uses the of_gpio_named_count()
since the MMC power sequence is only built when CONFIG_OF is enabled.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
Changes since v1:
- Many code cleanups
Martinez Canillas javier.marti...@collabora.co.uk
---
This patch was tested on an Exynos5420 Peach Pit and with MCPM support
enabled, all the 8 CPUs are powered up:
Brought up 8 CPUs
SMP: Total of 8 processors activated (384.00 BogoMIPS).
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1
Srinivas,
On 01/28/2015 05:34 PM, Srinivas Kandagatla wrote:
-- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted at
-initialization and prior we start the power up procedure of the card. It
-will be de-asserted right after the power has been provided to the card.
+-
Hello Arend,
Thanks for your feedback.
On 01/28/2015 03:03 PM, Arend van Spriel wrote:
On 01/28/15 11:10, Javier Martinez Canillas wrote:
dp {
@@ -531,17 +538,33 @@
status = okay;
num-slots =1;
broken-cd;
+cap-sdio-irq;
This seems like an unrelated change, right
Enabling SDIO IRQ signalling for the wifi MMC/SDIO slot
doubles the transmission transfer rate.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2: None.
Changes since v1: None, new patch.
---
arch/arm/boot/dts/exynos5250-snow.dts | 1 +
1 file changed
MMC/SDIO slot.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2: None.
Changes since v1:
- Remove cap-sdio-irq from mmc3 dev node since is a separate change.
Suggested by Arend van Spriel.
---
arch/arm/boot/dts/exynos5250-snow.dts | 25
clock.
This is the third version of the series that addressed issues pointed out
in the previous versions.
The series depend on v4 mmc: core: Add support for MMC power sequences:
http://comments.gmane.org/gmane.linux.kernel.mmc/30665
Javier Martinez Canillas (6):
mmc: pwrseq: Document
is not found.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- Add a clk_enabled bool to struct mmc_pwrseq_simple to track clock
gate/ungate since .power_off can be called prior to .pre_power_on.
Suggested by Ulf Hansson.
- clk_get() does not return
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2: None
number, it uses the of_gpio_named_count()
since the MMC power sequence is only built when CONFIG_OF is enabled.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
Changes since v2: None.
Changes since v1
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2: None.
Changes since v1:
- Make the explanation
Reviewed-by: Olof Johansson ol...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Reviewed-by: Benson Leung ble...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v3: None.
Changes since v2: None.
Changes since v1:
- Moved from
echo ro reboot
cat version
echo rw reboot
cat version
echo cold reboot
That last command will reboot the AP too.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti
From: Bill Richardson wfric...@chromium.org
This patch adds a device interface to access the
Chrome OS Embedded Controller from user-space.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Simon Glass s...@google.com
Signed-off-by: Javier Martinez Canillas javier.marti
.
Currently, there are drivers to communicate with the EC over
I2C and SPI and this driver adds support for LPC.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v3:
- Rename MYNAME to DRV_NAME
- Use
The ChromeOS Embedded Controller has to be accessed by applications.
A virtual character device is used as an interface with user-space.
Extend the struct cros_ec_device with the fields needed by the driver
of this virtual character device.
Signed-off-by: Javier Martinez Canillas javier.marti
byte boundaries, use fixed size arrays instead of pointers
for transferring ingoing and outgoing data with the Embedded Controller.
Also, re-arrange struct members by decreasing alignment requirements to
reduce the needing padding size.
Signed-off-by: Javier Martinez Canillas javier.marti
The ChromeOS EC character device is an user-space interface to
allow applications to access the Embedded Controller.
Add a cell for this device so it's spawned from the mfd driver.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Acked-by: Lee Jones lee.jo...@linaro.org
patches:
Bill Richardson (4):
misc: Add cros_ec_lpc driver for x86 devices
platform/chrome: Add Chrome OS EC userspace device interface
platform/chrome: Create sysfs attributes for the ChromeOS EC
platform/chrome: Expose Chrome OS Lightbar to users
Javier Martinez Canillas (3):
mfd
Hello Marek,
On Fri, Jan 23, 2015 at 1:40 PM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
+
+ list_add_tail(data-owner_node, owner-clients);
This is the line that causes the kernel to hang, if I comment the
list_add_tail() call then the kernel boots.
I checked that neither data
Hello Kukjin,
On 01/23/2015 07:51 AM, Kukjin Kim wrote:
Acked-by: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Michael Turquette mturque...@linaro.org
Thanks a lot Sylwester and Mike for your acks.
Kukjin, could you please pick $subject and Patch 2/2 ARM: dts: Add DISP1
for distros with systemd)
so the same should be done in exynos_defconfig.
That can of course be a follow-up patch though, so for $subject:
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
--
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Hello Varka,
Thanks a lot for your feedback.
On 01/23/2015 04:57 AM, Varka Bhadram wrote:
(...)
+static int cros_ec_lpc_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev-dev;
+ struct cros_ec_device *ec_dev;
+ int err = -ENOTTY;
+
+ if
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