Re: [alsa-devel] [PATCH] ASoC: max98088: Add master clock handling
On 02/20/2015 12:48 AM, Andreas Färber wrote: If master clock is provided through device tree, then update the master clock frequency during set_sysclk. Cc: Tushar Behera tushar.beh...@linaro.org Signed-off-by: Andreas Färber afaer...@suse.de --- sound/soc/codecs/max98088.c | 24 1 file changed, 24 insertions(+) Looks good. Acked-by: Tushar Behera trbli...@gmail.com -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH 4/6] ASoC: samsung: Document binding for max98089 based Snow driver
On 02/18/2015 11:55 PM, Andreas Färber wrote: Signed-off-by: Andreas Färber afaer...@suse.de --- Documentation/devicetree/bindings/sound/snow.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/snow.txt b/Documentation/devicetree/bindings/sound/snow.txt index 6df74f15687f..1430a6bdb2ae 100644 --- a/Documentation/devicetree/bindings/sound/snow.txt +++ b/Documentation/devicetree/bindings/sound/snow.txt @@ -2,6 +2,7 @@ Audio Binding for Snow boards Required properties: - compatible : Can be one of the following, + google,snow-audio-max98089 or google,snow-audio-max98090 or google,snow-audio-max98091 or google,snow-audio-max98095 Looks good. Acked-by: Tushar Behera trbli...@gmail.com -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3 09/15] ASoC: samsung: i2s: Protect more registers with a spinlock
On Thu, Jan 15, 2015 at 3:42 AM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
Ensure the I2SMOD, I2SPSR registers, which are also exposed through
clk API are only accessed with the i2s-spinlock spinlock held.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
sound/soc/samsung/i2s.c | 81
+--
1 file changed, 51 insertions(+), 30 deletions(-)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 20cc51f..05fc2f0 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -472,17 +472,22 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
{
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = get_other_dai(i2s);
- u32 mod = readl(i2s-addr + I2SMOD);
const struct samsung_i2s_variant_regs *i2s_regs = i2s-variant_regs;
unsigned int cdcon_mask = 1 i2s_regs-cdclkcon_off;
unsigned int rsrc_mask = 1 i2s_regs-rclksrc_off;
+ u32 mod, mask, val = 0;
+
+ spin_lock(i2s-lock);
+ mod = readl(i2s-addr + I2SMOD);
+ spin_unlock(i2s-lock);
'mod' is now updated only at the bottom of this function. The above
readl can be omitted.
switch (clk_id) {
case SAMSUNG_I2S_OPCLK:
- mod = ~MOD_OPCLK_MASK;
- mod |= dir;
+ mask = MOD_OPCLK_MASK;
+ val = dir;
break;
case SAMSUNG_I2S_CDCLK:
+ mask = 1 i2s_regs-cdclkcon_off;
Use BIT() macro instead?
/* Shouldn't matter in GATING(CLOCK_IN) mode */
if (dir == SND_SOC_CLOCK_IN)
rfs = 0;
@@ -499,15 +504,15 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
}
if (dir == SND_SOC_CLOCK_IN)
- mod |= 1 i2s_regs-cdclkcon_off;
- else
- mod = ~(1 i2s_regs-cdclkcon_off);
+ val = 1 i2s_regs-cdclkcon_off;
Same as above.
i2s-rfs = rfs;
break;
case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0
*/
case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1
*/
+ mask = 1 i2s_regs-rclksrc_off;
+
Same as above.
if ((i2s-quirks QUIRK_NO_MUXPSR)
|| (clk_id == SAMSUNG_I2S_RCLKSRC_0))
clk_id = 0;
@@ -557,18 +562,19 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
return 0;
}
- if (clk_id == 0)
- mod = ~(1 i2s_regs-rclksrc_off);
- else
- mod |= 1 i2s_regs-rclksrc_off;
-
+ if (clk_id == 1)
+ val = 1 i2s_regs-rclksrc_off;
Same as above.
--
Tushar Behera
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Re: [PATCH] ARM: exynos_defconfig: Enable PL330 DMA
On Thu, Jul 31, 2014 at 7:59 PM, Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com wrote: Hi, On Thursday, July 31, 2014 08:09:49 AM Andreas Färber wrote: Hi Tushar, Am 31.07.2014 07:42, schrieb Tushar Behera: We are getting a system hang on Arndale-Octa board if PL330_DMA is not enabled. The issue is related to [1]. AUDSS block provides the clock for audio DMA controller. Any operation on this clock requires that the clock to AUDSS block be enabled. In current configuration, the clock is gated during late boot process when all unused clocks are disabled. When PL330_DMA is enabled, the 'apb_pclk' is enabled/disabled during amba_probe(). Otherwise, this clock is also disabled during late boot. If the AUDSS block clock is disabled by then, we get a system hang. Could you please explain this more? I don't get it how apb_pclk is related to AUDSS block clock and why apb_pclk for ADMA is provided by AUDSS block on Exynos5420. Access to the control register for this clock cause the system hang when the clock to the AUDSS block is gated. enabling PL330_DMA fixes the issue (I suspect that enabling PL330_DMA enables PL330 DMA AMBA device so the amba_probe() keeps apb_pclk clock enabled but what is its relation to AUDSS block clock?). [1] https://lkml.org/lkml/2014/6/11/32 Signed-off-by: Tushar Behera tusha...@samsung.com --- arch/arm/configs/exynos_defconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e07a227..c5888e8 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -109,6 +109,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y Reviewed-by: Andreas Färber afaer...@suse.de Turns out I had those enabled in my local config when testing the memory patches on Arndale Octa. multi_v7_defconfig has them already. I observe more and more discrepancies between exynos_defconfig and multi_v7_defconfig when it comes to Exynos specific options. I wanted to avoid this by proposing exynos_defconfig removal when multiplatform support was added to Exynos. Unfortunately there was no agreement on this at that time. It would really be great if all Exynos users run on a common configuration so the testing is done more efficiently. However, shouldn't Kconfig grow a dependency to enable those options automatically for whatever driver or SoC needs them? Yes, moreover it is not clear yet that enabling PL330 DMA to resolve the hang issue is the right approach (to be honest it looks like a workaround for the lack of proper clock dependencies in a code). This, for sure, is only a temporary fix. The real fix lies in patch [1] (mentioned in the original patch comment) which needs a bit of redesign. I am not able to work on that because of lack of time. Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: exynos_defconfig: Enable PL330 DMA
We are getting a system hang on Arndale-Octa board if PL330_DMA is not enabled. The issue is related to [1]. AUDSS block provides the clock for audio DMA controller. Any operation on this clock requires that the clock to AUDSS block be enabled. In current configuration, the clock is gated during late boot process when all unused clocks are disabled. When PL330_DMA is enabled, the 'apb_pclk' is enabled/disabled during amba_probe(). Otherwise, this clock is also disabled during late boot. If the AUDSS block clock is disabled by then, we get a system hang. [1] https://lkml.org/lkml/2014/6/11/32 Signed-off-by: Tushar Behera tusha...@samsung.com --- arch/arm/configs/exynos_defconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e07a227..c5888e8 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -109,6 +109,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 3/3] clk: exynos-audss: Use samsung clock APIs to register/unregister clocks
On Mon, Jul 14, 2014 at 9:04 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
On 11/07/14 14:00, Tushar Behera wrote:
@@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct
platform_device *pdev)
return PTR_ERR(reg_base);
}
- clk_table = devm_kzalloc(pdev-dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
+ ctx = samsung_clk_init(pdev-dev.of_node, reg_base, nr_clks);
There is an issue here that this registers the clk provider before all
its clocks are registered with the clk core. Therefore it introduces
a race condition.
Please have a look at patch [1], you may want to rebase this series
onto that patch.
Thanks for the pointer. I will re-post.
+ samsung_clk_register_div(ctx, exynos_audss_div_clks,
+ ARRAY_SIZE(exynos_audss_div_clks));
[...]
+ samsung_clk_register_gate(ctx, exynos_audss_gate_clks,
+ ARRAY_SIZE(exynos_audss_gate_clks));
[...]
- ret = of_clk_add_provider(pdev-dev.of_node, of_clk_src_onecell_get,
- clk_data);
- if (ret) {
- dev_err(pdev-dev, failed to add clock provider\n);
- goto unregister;
+ samsung_clk_register_gate(ctx, exynos5420_audss_gate_clks,
+
ARRAY_SIZE(exynos5420_audss_gate_clks));
}
[1]
https://git.kernel.org/cgit/linux/kernel/git/tfiga/samsung-clk.git/commit/?h=samsung-clk-nextid=d5e136a21b2028fb1f45143ea7112d5869bfc6c7
--
Regards,
Sylwester
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Re: [PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
On 06/13/2014 02:39 AM, Mike Turquette wrote: Quoting Tushar Behera (2014-06-12 00:29:23) On Wed, Jun 11, 2014 at 10:20 PM, Mike Turquette mturque...@linaro.org wrote: Quoting Tushar Behera (2014-06-10 22:32:17) When the output clock of AUDSS mux is disabled, we are getting kernel oops while doing a clk_get() on other clocks provided by AUDSS. Though user manual doesn't specify this dependency, we came across this issue while disabling the parent of AUDSS mux clocks. Hi Tushar, Can you help me understand better what the actual problem is? What is the root cause of the kernel oops? Currently AUDSS mux has two parents, XXTI crystal and MAU_EPLL clock. As per observation, when the output of AUDSS mux is gated, we are not able to do any operation on the clocks provided by MAU block (mostly the clocks used by ADMA and audio blocks). I tried to get a datasheet for Exynos 54xx but could not find it. I even looked at the public 5250 data sheet, but it is completely missing Chapter 34, Audio Subsystem, which apparently contains Figure 34-3, Clock names and clock tree diagram of MAUDIO_BLK. So without any clue about your hardware (not for lack of trying) I would guess that somewhere in the parent hierarchy you have an interface clock which must be enabled in order for you to touch the registers pertaining to the downstream audio clocks. Yes, right. As per observation, we need to keep the output of AUDSS mux enabled to access the registers present in MAU block. The right way to handle this requires two steps: 1) model your interface clock in the Linux clock framework if you haven't already (I assume it is a gate clock, or the child of a gate clock) The interface clock is already part of the clock framework. 2) the clk_ops callbacks for the affected audio clocks should wrap their operations (i.e. critical secion) with a clk_enable/clk_disable pair, where the clock being enables/disable is the interface clock mentioned above in #1 The CCF is reentrant, so you can do this by simply using the top-level clk.h API from within your clk_ops callbacks. Right now, the clocks are registered with clk_register_mux, clk_register_div and clk_register_gate calls which in turn set appropriate clk_ops callbacks. If I need to wrap the register access during these clk_ops callbacks with clk_enable/clk_disable of interface lock, I would have to reimplement the clk_ops callbacks in clk-exynos-audss driver. Is that the approach that you are suggesting? I might be totally wrong about the cause of the hang, but that's my best guess based on everyone's bug reports. There are 5 gate clocks within MAU block. While disabling the unused clocks, if CLK_MAU_EPLL is disabled first, then we are getting this system hang. Regards, Mike You mention calling clk_get on child clocks of the AUDSS mux fails, but I cannot imagine why. How can the enable/disable state of a clock affect the ability to clk_get other clocks? I might have a little vogue while updating the commit message (mentioning about clk_get which surely is only a s/w operation), but there is definitely some issue with handling those clocks under given scenario. I am on leave till end of this week, so I will update you more with the logs on Monday. Thanks, -- Tushar ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] clk: exynos-audss: Simplify code to get clock names
Instead of getting the clock names individually, it would be good to put
the logic within a loop.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
drivers/clk/samsung/clk-exynos-audss.c | 33
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 13eae14c..ebfc5da 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -80,10 +80,14 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
{
int i, ret = 0;
struct resource *res;
+ struct clk *tmp;
+ const char *clk_name_ref[] = {
+ pll_ref, pll_in, cdclk, sclk_audio, sclk_pcm_in };
+ const char *clk_name_actual[] = {
+ fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
const char *sclk_pcm_p = sclk_pcm0;
- struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
@@ -111,23 +115,23 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
else
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
- pll_ref = devm_clk_get(pdev-dev, pll_ref);
- pll_in = devm_clk_get(pdev-dev, pll_in);
- if (!IS_ERR(pll_ref))
- mout_audss_p[0] = __clk_get_name(pll_ref);
- if (!IS_ERR(pll_in))
- mout_audss_p[1] = __clk_get_name(pll_in);
+ for (i = 0; i ARRAY_SIZE(clk_name_ref); i++) {
+ tmp = devm_clk_get(pdev-dev, clk_name_ref[i]);
+ if (!IS_ERR(tmp))
+ clk_name_actual[i] = __clk_get_name(tmp);
+ }
+
+ mout_audss_p[0] = clk_name_actual[0];
+ mout_audss_p[1] = clk_name_actual[1];
+ mout_i2s_p[1] = clk_name_actual[2];
+ mout_i2s_p[2] = clk_name_actual[3];
+ sclk_pcm_p = clk_name_actual[4];
+
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, lock);
- cdclk = devm_clk_get(pdev-dev, cdclk);
- sclk_audio = devm_clk_get(pdev-dev, sclk_audio);
- if (!IS_ERR(cdclk))
- mout_i2s_p[1] = __clk_get_name(cdclk);
- if (!IS_ERR(sclk_audio))
- mout_i2s_p[2] = __clk_get_name(sclk_audio);
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, mout_i2s,
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
@@ -161,9 +165,6 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, lock);
- sclk_pcm_in = devm_clk_get(pdev-dev, sclk_pcm_in);
- if (!IS_ERR(sclk_pcm_in))
- sclk_pcm_p = __clk_get_name(sclk_pcm_in);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, sclk_pcm,
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
--
1.7.9.5
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[PATCH 0/2] clk: exynos-audss: Adapt to exising clock framework
The patchset is targetted as moving exising exynos-audss clock driver from being a module driver. The driver is now registered through CLK_OF_DECLARE and is inline with other Samsung clock drivers. The patches are tested on Exynos5800 based Peach-Pi board. More tests are welcome. Tushar Behera (2): clk: exynos-audss: Simplify code to get clock names clk: exynos-audss: Update as per existing framework drivers/clk/samsung/clk-exynos-audss.c | 268 1 file changed, 102 insertions(+), 166 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] clk: exynos-audss: Update as per existing framework
Change exynos-audss clock driver as per existing clock framework from
the existing module driver framework.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
drivers/clk/samsung/clk-exynos-audss.c | 239
1 file changed, 87 insertions(+), 152 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index ebfc5da..49f4163 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,26 +19,25 @@
#include dt-bindings/clock/exynos-audss-clk.h
+#include clk.h
+
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
TYPE_EXYNOS5250,
TYPE_EXYNOS5420,
};
-static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
-#define ASS_CLK_SRC 0x0
-#define ASS_CLK_DIV 0x4
-#define ASS_CLK_GATE 0x8
+#define ASS_CLK_SRC0x0
+#define ASS_CLK_DIV0x4
+#define ASS_CLK_GATE 0x8
#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = {
- {ASS_CLK_SRC, 0},
- {ASS_CLK_DIV, 0},
- {ASS_CLK_GATE, 0},
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
};
static int exynos_audss_clk_suspend(void)
@@ -65,21 +64,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
-static const struct of_device_id exynos_audss_clk_of_match[] = {
- { .compatible = samsung,exynos4210-audss-clock,
- .data = (void *)TYPE_EXYNOS4210, },
- { .compatible = samsung,exynos5250-audss-clock,
- .data = (void *)TYPE_EXYNOS5250, },
- { .compatible = samsung,exynos5420-audss-clock,
- .data = (void *)TYPE_EXYNOS5420, },
- {},
-};
-
-/* register exynos_audss clocks */
-static int exynos_audss_clk_probe(struct platform_device *pdev)
+static void __init exynos_audss_clk_init(struct device_node *np,
+ enum exynos_audss_clk_type variant)
{
- int i, ret = 0;
- struct resource *res;
+ int i;
struct clk *tmp;
const char *clk_name_ref[] = {
pll_ref, pll_in, cdclk, sclk_audio, sclk_pcm_in };
@@ -87,163 +75,110 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
- const char *sclk_pcm_p = sclk_pcm0;
- const struct of_device_id *match;
- enum exynos_audss_clk_type variant;
-
- match = of_match_node(exynos_audss_clk_of_match, pdev-dev.of_node);
- if (!match)
- return -EINVAL;
- variant = (enum exynos_audss_clk_type)match-data;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- reg_base = devm_ioremap_resource(pdev-dev, res);
- if (IS_ERR(reg_base)) {
- dev_err(pdev-dev, failed to map audss registers\n);
- return PTR_ERR(reg_base);
- }
- clk_table = devm_kzalloc(pdev-dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
- return -ENOMEM;
-
- clk_data.clks = clk_table;
- if (variant == TYPE_EXYNOS5420)
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- else
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
+ char sclk_pcm_p[32];
+
+ struct samsung_mux_clock exynos_audss_mux_clks[] = {
+ MUX(EXYNOS_MOUT_AUDSS, mout_audss, mout_audss_p,
+ ASS_CLK_SRC, 0, 1),
+ MUX(EXYNOS_MOUT_I2S, mout_i2s, mout_i2s_p,
+ ASS_CLK_SRC, 2, 2),
+ };
+
+ struct samsung_div_clock exynos_audss_div_clks[] = {
+ DIV(EXYNOS_DOUT_SRP, dout_srp, mout_audss,
+ ASS_CLK_DIV, 0, 4),
+ DIV(EXYNOS_DOUT_AUD_BUS, dout_aud_bus, dout_srp,
+ ASS_CLK_DIV, 4, 4),
+ DIV(EXYNOS_DOUT_I2S, dout_i2s, mout_i2s, ASS_CLK_DIV, 8, 4),
+ };
+
+ struct samsung_gate_clock exynos_audss_gate_clks[] = {
+ GATE(EXYNOS_SRP_CLK, srp_clk, dout_srp,
+ ASS_CLK_GATE, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_I2S_BUS, i2s_bus, dout_aud_bus,
+ ASS_CLK_GATE, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_I2S, sclk_i2s, dout_i2s,
+ ASS_CLK_GATE, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_PCM_BUS, pcm_bus, sclk_pcm,
+ ASS_CLK_GATE, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_PCM, sclk_pcm, sclk_pcm_p,
+ ASS_CLK_GATE, 5, CLK_SET_RATE_PARENT, 0
Re: [PATCH 0/2] clk: exynos-audss: Adapt to exising clock framework
On 07/11/2014 03:21 PM, Tomasz Figa wrote: Hi Tushar, On 11.07.2014 11:37, Tushar Behera wrote: The patchset is targetted as moving exising exynos-audss clock driver from being a module driver. The driver is now registered through CLK_OF_DECLARE and is inline with other Samsung clock drivers. I'm afraid I have to NAK this series or at least the part converting the driver back to use CLK_OF_DECLARE(). Considering the more prevalent usage of CLK_OF_DECLARE() in drivers/clk led me into thinking it was the normal way for the clock drivers. Keeping only one clock driver using a different approach looked odd to me. Anyways, I don't have any other reason to pursue this case. We have deliberately made this driver a platform driver, because this is how drivers should be modeled in Linux kernel whenever possible. CLK_OF_DECLARE() should be only considered a hack to work around late initialization of driver model. Reverting this change without a good reason (and you haven't provided such) is just going backwards. Rest of this series is actually quite nice, though, as reusing Samsung clock helpers reduces the line count significantly, so if you could rework this to keep this driver a platform driver then we could get something I could ack. Sure. There are still some valid cleanups even if we plan to retain the platform driver infrastructure. I will split and repost. Best regards, Tomasz -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/3] clk: exynos-audss: Simplify code to get clock names
Instead of getting the clock names individually, it would be good to put
the logic within a loop.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changes for V2:
* Calling clk_put as soon as the clock is not required anymore
drivers/clk/samsung/clk-exynos-audss.c | 35 +---
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 13eae14c..1a5294c 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -80,10 +80,14 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
{
int i, ret = 0;
struct resource *res;
+ struct clk *tmp;
+ const char *clk_name_ref[] = {
+ pll_ref, pll_in, cdclk, sclk_audio, sclk_pcm_in };
+ const char *clk_name_actual[] = {
+ fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
const char *sclk_pcm_p = sclk_pcm0;
- struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
@@ -111,23 +115,25 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
else
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
- pll_ref = devm_clk_get(pdev-dev, pll_ref);
- pll_in = devm_clk_get(pdev-dev, pll_in);
- if (!IS_ERR(pll_ref))
- mout_audss_p[0] = __clk_get_name(pll_ref);
- if (!IS_ERR(pll_in))
- mout_audss_p[1] = __clk_get_name(pll_in);
+ for (i = 0; i ARRAY_SIZE(clk_name_ref); i++) {
+ tmp = clk_get(pdev-dev, clk_name_ref[i]);
+ if (!IS_ERR(tmp)) {
+ clk_name_actual[i] = __clk_get_name(tmp);
+ clk_put(tmp);
+ }
+ }
+
+ mout_audss_p[0] = clk_name_actual[0];
+ mout_audss_p[1] = clk_name_actual[1];
+ mout_i2s_p[1] = clk_name_actual[2];
+ mout_i2s_p[2] = clk_name_actual[3];
+ sclk_pcm_p = clk_name_actual[4];
+
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, lock);
- cdclk = devm_clk_get(pdev-dev, cdclk);
- sclk_audio = devm_clk_get(pdev-dev, sclk_audio);
- if (!IS_ERR(cdclk))
- mout_i2s_p[1] = __clk_get_name(cdclk);
- if (!IS_ERR(sclk_audio))
- mout_i2s_p[2] = __clk_get_name(sclk_audio);
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, mout_i2s,
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
@@ -161,9 +167,6 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, lock);
- sclk_pcm_in = devm_clk_get(pdev-dev, sclk_pcm_in);
- if (!IS_ERR(sclk_pcm_in))
- sclk_pcm_p = __clk_get_name(sclk_pcm_in);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, sclk_pcm,
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
--
1.7.9.5
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[PATCH V2 2/3] clk: samsung: Add API to unregister clocks
Added an API to unregister all the clocks defined within a context. This
is helpful in case where the clock is registered through a platform
driver and we want to unregister the clocks during remove callback.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changelog:
This is new patch required because of changes to patch 3/3.
drivers/clk/samsung/clk.c | 19 +++
drivers/clk/samsung/clk.h |2 ++
2 files changed, 21 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 49629c7..b9310b9 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -83,6 +83,25 @@ struct samsung_clk_provider *__init samsung_clk_init(struct
device_node *np,
return ctx;
}
+/* API to remove a clock provider */
+void samsung_clk_exit(struct device_node *np, struct samsung_clk_provider *ctx)
+{
+ int i;
+
+ if (np)
+ of_clk_del_provider(np);
+
+ if (!ctx)
+ return;
+
+ for (i = 0; i ctx-clk_data.clk_num; i++)
+ if (!IS_ERR(ctx-clk_data.clks[i]))
+ clk_unregister(ctx-clk_data.clks[i]);
+
+ kfree(ctx-clk_data.clks);
+ kfree(ctx);
+}
+
/* add a clock instance to the clock lookup table used for dt based lookup */
void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
unsigned int id)
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 9693b80..8ecc85a 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -327,6 +327,8 @@ struct samsung_pll_clock {
extern struct samsung_clk_provider *__init samsung_clk_init(
struct device_node *np, void __iomem *base,
unsigned long nr_clks);
+extern void samsung_clk_exit(struct device_node *np,
+ struct samsung_clk_provider *ctx);
extern void __init samsung_clk_of_register_fixed_ext(
struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
--
1.7.9.5
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[PATCH V2 3/3] clk: exynos-audss: Use samsung clock APIs to register/unregister clocks
Using samsung clock APIs to register/unregister clocks will save some
lines of code.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changes of v2:
* Retain platform driver structure.
drivers/clk/samsung/clk-exynos-audss.c | 146
1 file changed, 56 insertions(+), 90 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 1a5294c..2b90967 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,16 +19,16 @@
#include dt-bindings/clock/exynos-audss-clk.h
+#include clk.h
+
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
TYPE_EXYNOS5250,
TYPE_EXYNOS5420,
};
-static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
+static struct samsung_clk_provider *ctx;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
@@ -78,7 +78,7 @@ static const struct of_device_id exynos_audss_clk_of_match[]
= {
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
- int i, ret = 0;
+ int i;
struct resource *res;
struct clk *tmp;
const char *clk_name_ref[] = {
@@ -87,14 +87,51 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
- const char *sclk_pcm_p = sclk_pcm0;
+ char sclk_pcm_p[32];
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
+ struct samsung_mux_clock exynos_audss_mux_clks[] = {
+ MUX(EXYNOS_MOUT_AUDSS, mout_audss, mout_audss_p,
+ ASS_CLK_SRC, 0, 1),
+ MUX(EXYNOS_MOUT_I2S, mout_i2s, mout_i2s_p,
+ ASS_CLK_SRC, 2, 2),
+ };
+
+ struct samsung_div_clock exynos_audss_div_clks[] = {
+ DIV(EXYNOS_DOUT_SRP, dout_srp, mout_audss,
+ ASS_CLK_DIV, 0, 4),
+ DIV(EXYNOS_DOUT_AUD_BUS, dout_aud_bus, dout_srp,
+ ASS_CLK_DIV, 4, 4),
+ DIV(EXYNOS_DOUT_I2S, dout_i2s, mout_i2s, ASS_CLK_DIV, 8, 4),
+ };
+
+ struct samsung_gate_clock exynos_audss_gate_clks[] = {
+ GATE(EXYNOS_SRP_CLK, srp_clk, dout_srp,
+ ASS_CLK_GATE, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_I2S_BUS, i2s_bus, dout_aud_bus,
+ ASS_CLK_GATE, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_I2S, sclk_i2s, dout_i2s,
+ ASS_CLK_GATE, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_PCM_BUS, pcm_bus, sclk_pcm,
+ ASS_CLK_GATE, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_PCM, sclk_pcm, sclk_pcm_p,
+ ASS_CLK_GATE, 5, CLK_SET_RATE_PARENT, 0),
+ };
+
+ struct samsung_gate_clock exynos5420_audss_gate_clks[] = {
+ GATE(EXYNOS_ADMA, adma, dout_srp,
+ ASS_CLK_GATE, 9, CLK_SET_RATE_PARENT, 0),
+ };
+
+ int nr_clks = EXYNOS_AUDSS_MAX_CLKS;
+
match = of_match_node(exynos_audss_clk_of_match, pdev-dev.of_node);
if (!match)
return -EINVAL;
variant = (enum exynos_audss_clk_type)match-data;
+ if (variant != TYPE_EXYNOS5420)
+ nr_clks--;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(pdev-dev, res);
@@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
return PTR_ERR(reg_base);
}
- clk_table = devm_kzalloc(pdev-dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
+ ctx = samsung_clk_init(pdev-dev.of_node, reg_base, nr_clks);
+ if (!ctx) {
+ dev_err(pdev-dev, failed to get clock provier context\n);
return -ENOMEM;
-
- clk_data.clks = clk_table;
- if (variant == TYPE_EXYNOS5420)
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- else
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
+ }
for (i = 0; i ARRAY_SIZE(clk_name_ref); i++) {
tmp = clk_get(pdev-dev, clk_name_ref[i]);
@@ -127,69 +158,20 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
mout_audss_p[1] = clk_name_actual[1];
mout_i2s_p[1] = clk_name_actual[2];
mout_i2s_p[2] = clk_name_actual[3];
- sclk_pcm_p = clk_name_actual[4];
-
- clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss
[PATCH V2 0/3] clk: exynos-audss: Adapt to exising clock framework
Generic cleanup and usage of samsung clock register/unregister APIs. The patches are tested on Exynos5800 based Peach-Pi board. More tests are welcome. Tushar Behera (3): clk: exynos-audss: Simplify code to get clock names clk: samsung: Add API to unregister clocks clk: exynos-audss: Use samsung clock APIs to register/unregister clocks drivers/clk/samsung/clk-exynos-audss.c | 179 +--- drivers/clk/samsung/clk.c | 19 drivers/clk/samsung/clk.h |2 + 3 files changed, 95 insertions(+), 105 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] clk: exynos-audss: Update as per existing framework
On 07/11/2014 04:10 PM, Sylwester Nawrocki wrote: Hi Tushar, On 11/07/14 11:37, Tushar Behera wrote: Change exynos-audss clock driver as per existing clock framework from the existing module driver framework. Can you explain what's the actual issue you're trying to solve with that patch ? What's the problem with this driver being a platform driver ? It feels we're moving in circles here, see commit b37a4224104568198b93fb9831224cfe7d83fff8 Author: Andrew Bresticker abres...@chromium.org Date: Wed Sep 25 14:12:47 2013 -0700 clk: exynos-audss: convert to platform device The Exynos AudioSS clock controller will later be modified to allow input clocks to be specified via device-tree in order to support multiple Exynos SoCs. This will introduce a dependency on the core SoC clock controller being initialized first so that the AudioSS driver can look up its input clocks, but the order in which clock providers are probed in of_clk_init() is not guaranteed. Since deferred probing is not supported in of_clk_init() and the AudioSS block is not the core controller, we can initialize it later as a platform device. Signed-off-by: Andrew Bresticker abres...@chromium.org Acked-by: Tomasz Figa t.f...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com Acked-by: Mike Turquette mturque...@linaro.org Acked-by: Kukjin Kim kgene@samsung.com Signed-off-by: Tomasz Figa t.f...@samsung.com I realize of_clk_init() now handles better clock provider dependencies, nevertheless do we really need all this churn ? I have sent v2 of the patchset while retaining the platform driver infrastructure. Awaiting your review comments on that. -- Thanks, Sylwester Thanks, -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 07/09/2014 03:44 PM, Javier Martinez Canillas wrote: Hello Tushar, On Tue, Jul 8, 2014 at 5:00 AM, Tushar Behera trbli...@gmail.com wrote: The u-boot version is a little different on my Peach-Pi as compared to the market release version. Not sure if that is making any difference. Peach # version U-Boot 2013.04 (Feb 13 2014 - 16:35:03) for Peach armv7a-cros-linux-gnueabi-gcc.real (4.8.1_cos_gg_feea904_4.8.1-r66) 4.8.x-google 20130905 (prerelease) GNU ld (binutils-2.22_cos_gg_2) 2.22 I'm using the same U-Boot version than Kevin (U-Boot 2013.04-gb98ed09) and on my setup using chained nv-uboot I also need patch 1/3 along with 2/3 to fix the issue. Note that I've applied this only from this series so I'm not sure how much the problem can be solved...any updates for 1/3 and 3/3? - Kukjin Thanks for applying 2/3. I am working on 1/3 to see if we are following the right approach to fix Kevin's issue (unfortunately, I am not hitting the bug on my board ATM). 3/3 has already been merged through a different patchset. I'm sending as an attachment my complete boot log when booting today's next (20140709) until it hangs and my u-boot env vars. I hope that helps. Would you please check the behaviour after enabling following config options? diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e07a227..d6056ab 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -93,6 +93,11 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_7x14=y CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SNOW=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_EXYNOS=y @@ -109,6 +114,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -- Tushar Behera -- Best regards, Javier -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 07/08/2014 05:04 AM, Kukjin Kim wrote: On 07/01/14 20:59, Tushar Behera wrote: On 06/27/2014 08:18 PM, Kevin Hilman wrote: On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilmankhil...@linaro.org wrote: On Thu, Jun 26, 2014 at 8:38 PM, Tushar Beheratrbli...@gmail.com wrote: Would you please provide me the environment setting of your u-boot? U-boot environment on my board has been over-written, I would like to set it same as yours and try to reproduce the issue at my end. With only 'sound init', I don't seem to hit this issue anymore. Attached is a full boot log using v3.16-rc2 with my patch adding CLK_IGNORE_UNUSED to mau_epll and Doug's aclk66_peric patch. In the boot log, you'll see the output of 'printenv' inside u-boot where the environment is dumped. Oops, I sent you a boot log for the octa board. Here's the one for peach-pi with the same kernel (built with upstream exynos_defconfig) Kevin The u-boot version is a little different on my Peach-Pi as compared to the market release version. Not sure if that is making any difference. Peach # version U-Boot 2013.04 (Feb 13 2014 - 16:35:03) for Peach armv7a-cros-linux-gnueabi-gcc.real (4.8.1_cos_gg_feea904_4.8.1-r66) 4.8.x-google 20130905 (prerelease) GNU ld (binutils-2.22_cos_gg_2) 2.22 Note that I've applied this only from this series so I'm not sure how much the problem can be solved...any updates for 1/3 and 3/3? - Kukjin Thanks for applying 2/3. I am working on 1/3 to see if we are following the right approach to fix Kevin's issue (unfortunately, I am not hitting the bug on my board ATM). 3/3 has already been merged through a different patchset. -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ASoC: samsung: Update sound-card name for Snow
Snow sound-card driver supports multiple boards with different
audio codecs. Updating the sound card name per board basis would provide
some more information to the end-user.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Documentation/devicetree/bindings/sound/snow.txt |4
sound/soc/samsung/snow.c |3 +++
2 files changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/snow.txt
b/Documentation/devicetree/bindings/sound/snow.txt
index e0b7a82..6df74f1 100644
--- a/Documentation/devicetree/bindings/sound/snow.txt
+++ b/Documentation/devicetree/bindings/sound/snow.txt
@@ -8,11 +8,15 @@ Required properties:
- samsung,i2s-controller: The phandle of the Samsung I2S controller
- samsung,audio-codec: The phandle of the audio codec
+Optional:
+- samsung,model: The name of the sound-card
+
Example:
sound {
compatible = google,snow-audio-max98095;
+ samsung,model = Snow-I2S-MAX98095;
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98095;
};
diff --git a/sound/soc/samsung/snow.c b/sound/soc/samsung/snow.c
index 8bbd348..0acf5d0 100644
--- a/sound/soc/samsung/snow.c
+++ b/sound/soc/samsung/snow.c
@@ -92,6 +92,9 @@ static int snow_probe(struct platform_device *pdev)
card-dev = pdev-dev;
+ /* Update card-name if provided through DT, else use default name */
+ snd_soc_of_parse_card_name(card, samsung,model);
+
ret = devm_snd_soc_register_card(pdev-dev, card);
if (ret) {
dev_err(pdev-dev, snd_soc_register_card failed (%d)\n, ret);
--
1.7.9.5
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[PATCH 2/2] ASoC: core: Fix possible NULL pointer dereference
snd_soc_of_parse_card_name() may be called before card-dev has been
set, which results in a kernel panic.
Unable to handle kernel NULL pointer dereference at virtual address 0210
PC is at snd_soc_of_parse_card_name+0x18/0x54
LR is at snow_probe+0x5c/0xd4
Add an error check in snd_soc_of_parse_card_name() to take care of this
case and print out a message in case of error.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
sound/soc/soc-core.c |9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index c4db07f..2e4bdc0 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -4391,9 +4391,16 @@ EXPORT_SYMBOL_GPL(snd_soc_unregister_codec);
int snd_soc_of_parse_card_name(struct snd_soc_card *card,
const char *propname)
{
- struct device_node *np = card-dev-of_node;
+ struct device_node *np;
int ret;
+ if (!card-dev) {
+ pr_err(card-dev is not set before calling %s\n, __func__);
+ return -EINVAL;
+ }
+
+ np = card-dev-of_node;
+
ret = of_property_read_string_index(np, propname, 0, card-name);
/*
* EINVAL means the property does not exist. This is fine providing
--
1.7.9.5
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[PATCH] ARM: dts: Add sound-card name for Snow/Peach-Pit/Peach-Pi
Add sound-card name property to Snow/Peach-Pit/Peach-Pi boards.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Patch to update driver is submitted here[1].
[1] ASoC: samsung: Update sound-card name for Snow
https://lkml.org/lkml/2014/7/4/125
arch/arm/boot/dts/exynos5250-snow.dts |1 +
arch/arm/boot/dts/exynos5420-peach-pit.dts |1 +
arch/arm/boot/dts/exynos5800-peach-pi.dts |1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index 7bd2df1..c682c88 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -262,6 +262,7 @@
sound {
compatible = google,snow-audio-max98095;
+ samsung,model = Snow-I2S-MAX98095;
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98095;
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 7649982..6c7cab0 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -62,6 +62,7 @@
sound {
compatible = google,snow-audio-max98090;
+ samsung,model = Peach-Pit-I2S-MAX98090;
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98090;
};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 2c2c137..28f2a25 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -60,6 +60,7 @@
sound {
compatible = google,snow-audio-max98091;
+ samsung,model = Peach-Pi-I2S-MAX98091;
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98091;
};
--
1.7.9.5
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[PATCH] drm/exynos: fimd: Keep power enabled during fimd_bind
Under some conditions (when IOMMU is enabled), fimd_bind() accesses hardware registers and power-domain should be enabled during that time. fimd_bind -- fimd_mgr_initialize -- fimd_clear_channel If the power-domain is disabled by that time, we get a boot-time crash. It would be better to keep power-domain enabled explicitly. Unhandled fault: external abort on non-linefetch (0x1008) at 0xf0180034 Internal error: : 1008 [#1] PREEMPT SMP ARM ... PC is at fimd_bind+0x84/0x134 LR is at component_bind_all+0xb4/0x1d8 Signed-off-by: Tushar Behera tusha...@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 33161ad..34275fb 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -888,11 +888,15 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) struct fimd_context *ctx = fimd_manager.ctx; struct drm_device *drm_dev = data; + pm_runtime_get_sync(dev); + fimd_mgr_initialize(fimd_manager, drm_dev); exynos_drm_crtc_create(fimd_manager); if (ctx-display) exynos_drm_create_enc_conn(drm_dev, ctx-display); + pm_runtime_put_sync(dev); + return 0; } -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 1/3] of: Split early_init_dt_scan into two parts
On 07/02/2014 07:33 AM, Laura Abbott wrote:
Currently, early_init_dt_scan validates the header, sets the
boot params, and scans for chosen/memory all in one function.
Split this up into two separate functions (validation/setting
boot params in one, scanning in another) to allow for
additional setup between boot params and scanning the memory.
Signed-off-by: Laura Abbott lau...@codeaurora.org
---
Tested the patchset on top of Linus' tree.
Verified after enabling following debug message.
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -865,7 +865,7 @@ int __init early_init_dt_scan_memory(unsigned long
node, const char *uname,
endp = reg + (l / sizeof(__be32));
- pr_debug(memory scan node %s, reg size %d, data: %x %x %x %x,\n,
+ pr_err(memory scan node %s, reg size %d, data: %x %x %x %x,\n,
Output before:
memory scan node memory, reg size 96, data: 20 10 30 10,
Output after:
memory scan node memory, reg size 64, data: 20 10 30 10,
Tested-by: Tushar Behera trbli...@gmail.com
One minor nit below ...
drivers/of/fdt.c | 18 +-
include/linux/of_fdt.h | 2 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index c4cddf0..55bfca9 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -922,7 +922,7 @@ int __init __weak
early_init_dt_reserve_memory_arch(phys_addr_t base,
}
#endif
-bool __init early_init_dt_scan(void *params)
+bool __init early_init_dt_verify(void *params)
{
if (!params)
return false;
@@ -936,6 +936,12 @@ bool __init early_init_dt_scan(void *params)
return false;
}
+ return true;
+}
+
+
Extra blank line here. Can be removed.
--
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[PATCH] ARM: dts: disable MDMA1 node for exynos5420
From: Seungwon Jeon tgih@samsung.com commit e6015c1f8a9032c2aecb78d23edf49582563bd47 upstream. This change places MDMA1 in disabled node for Exynos5420. If MDMA1 region is configured with secure mode, it makes the boot failure with the following on smdk5420 board. (Unhandled fault: imprecise external abort (0x1406) at 0x) Thus, arndale-octa board don't need to do the same thing anymore. Signed-off-by: Seungwon Jeon tgih@samsung.com Tested-by: Javi Merino javi.mer...@arm.com Signed-off-by: Kukjin Kim kgene@samsung.com Signed-off-by: Tushar Behera tusha...@samsung.com --- Tested on top of v3.14.10. Fixes issue reported at [1]. [1] http://armcloud.us/kernel-ci/stable/v3.14.10/arm-exynos_defconfig/boot-exynos5420-arndale-octa.html arch/arm/boot/dts/exynos5420.dtsi |7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8db792b..15eb8d4 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -323,6 +323,13 @@ #dma-cells = 1; #dma-channels = 8; #dma-requests = 1; + /* +* MDMA1 can support both secure and non-secure +* AXI transactions. When this is enabled in the kernel +* for boards that run in secure mode, we are getting +* imprecise external aborts causing the kernel to oops. +*/ + status = disabled; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 06/27/2014 08:18 PM, Kevin Hilman wrote: On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilman khil...@linaro.org wrote: On Thu, Jun 26, 2014 at 8:38 PM, Tushar Behera trbli...@gmail.com wrote: Would you please provide me the environment setting of your u-boot? U-boot environment on my board has been over-written, I would like to set it same as yours and try to reproduce the issue at my end. With only 'sound init', I don't seem to hit this issue anymore. Attached is a full boot log using v3.16-rc2 with my patch adding CLK_IGNORE_UNUSED to mau_epll and Doug's aclk66_peric patch. In the boot log, you'll see the output of 'printenv' inside u-boot where the environment is dumped. Oops, I sent you a boot log for the octa board. Here's the one for peach-pi with the same kernel (built with upstream exynos_defconfig) Kevin The u-boot version is a little different on my Peach-Pi as compared to the market release version. Not sure if that is making any difference. Peach # version U-Boot 2013.04 (Feb 13 2014 - 16:35:03) for Peach armv7a-cros-linux-gnueabi-gcc.real (4.8.1_cos_gg_feea904_4.8.1-r66) 4.8.x-google 20130905 (prerelease) GNU ld (binutils-2.22_cos_gg_2) 2.22 -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/17] ARM: S5P64X0, S5PC100: no more support in mainline
On 07/01/2014 03:02 AM, Kukjin Kim wrote: This series removes S5P64X0 and S5PC100 related codes in mainline, because no more user now. And if its supporting is required later, it will be done with using device tree. [PATCH 01/17] ARM: S5P64X0: no more support S5P6440 and S5P6450 SoCs [PATCH 02/17] gpio: samsung: remove s5p64x0 related gpio codes [PATCH 03/17] spi: s3c64xx: remove s5p64x0 related spi codes [PATCH 04/17] ASoC: samsung: no more support for S5P6440 and S5P6450 [PATCH 05/17] pwm: samsung: remove s5p64x0 related pwm codes [PATCH 06/17] video: fbdev: s3c-fb: remove s5p64x0 related fimd [PATCH 07/17] serial: samsung: no more support for S5P6440 and [PATCH 08/17] ARM: S5PC100: no more support S5PC100 SoC [PATCH 09/17] gpio: samsung: remov s5pc100 related gpio codes [PATCH 10/17] spi: s3c64xx: remove s5pc100 related spi codes [PATCH 11/17] pwm: samsung: remove s5pc100 related pwm codes [PATCH 12/17] serial: samsung: no more support for S5PC100 SoC [PATCH 13/17] ata: pata_samsung_cf: removes s5pc100 related ata [PATCH 14/17] mtd: onenand: remove s5pc100 related onenand codes [PATCH 15/17] video: fbdev: s3c-fb: remove s5pc100 related fimd and [PATCH 16/17] [media] exynos4-is: removes s5pc100 related fimc codes [PATCH 17/17] ASoC: Samsung: remove s5pc100 related codes One more reference to S5PC100 can be found at drivers/irqchip/Kconfig. diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 131f185..9f39cc6 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -23,7 +23,6 @@ config ARM_VIC config ARM_VIC_NR int default 4 if ARCH_S5PV210 - default 3 if ARCH_S5PC100 default 2 depends on ARM_VIC help ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: mainline boot: 64 boots: 62 pass, 2 fail (v3.16-rc1-2-gebe0618)
On 06/26/2014 03:27 AM, Laura Abbott wrote: On 6/25/2014 5:13 AM, Tushar Behera wrote: On 06/25/2014 03:59 AM, Laura Abbott wrote: On 6/24/2014 10:47 AM, Laura Abbott wrote: On 6/23/2014 11:32 AM, Kevin Hilman wrote: On Sun, Jun 22, 2014 at 8:56 PM, Tushar Behera trbli...@gmail.com wrote: Adding linux-samsung-soc and linux-arm-kernel ML for wider audience. On 06/19/2014 04:12 PM, Tushar Behera wrote: On 06/19/2014 03:02 PM, Tushar Behera wrote: On 06/18/2014 09:22 AM, Kevin Hilman wrote: On Tue, Jun 17, 2014 at 8:26 PM, Tushar Behera trbli...@gmail.com wrote: On 06/17/2014 10:23 PM, Kevin Hilman wrote: Sachin, On Mon, Jun 16, 2014 at 11:16 PM, Kevin's boot bot khil...@linaro.org wrote: Tree/Branch: mainline Git describe: v3.16-rc1-2-gebe0618 Failed boot tests (console logs at the end) === exynos5420-arndale-octa: FAIL:arm-exynos_defconfig ste-snowball: FAIL:arm-u8500_defconfig FYI... these failures are getting more consistent on my octa board, but still not failing every time. Kevin Hi Kevin, Same here. Observation: If you soft-reset the board (through the jumpers) after getting this problem, the problem keeps repeating. But if you hard-reset the board (by removing the power cord), the problem doesn't occur during next iteration. I don't ever use the soft-reset, I only toggle the wall power. I don't ever actually remove the power cord though, I'm using a USB-controlled relay to toggle the wall power. Kevin Laura, We are getting following kernel panic [1] (not always, but quite regularly) while booting Arndale-Octa (based on Samsung's Exynos5420) board with upstream kernel. I haven't observed this issue with other boards yet. This issue is observed when I am booting with uImage + dtb (within roughly ~10 iterations). Some more information: The boot logs are provided in pastebin, okay[2] and failed[3]. In case of boot failures, I am getting a higher value for vm_total_pages (684424 in [3]). In case of successful boot on my board, it is always 521232 [2] on my board. I can confirm that reverting the Get rid of meminfo patch gets the Octa board booting reliably again for me also. In case it helps, some boot logs for failures from the last copule linux-next build/boot cycles can be seen here: http://armcloud.us/kernel-ci/next/next-20140623/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log http://armcloud.us/kernel-ci/next/next-20140620/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log Sorry, I missed this yesterday. I'm going to take a look. Were all of http://pastebin.com/1iLaizuL http://pastebin.com/5tdDt4GL http://armcloud.us/kernel-ci/next/next-20140623/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log http://armcloud.us/kernel-ci/next/next-20140620/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log collected on the same type of board with the same amount of DRAM? I'm seeing a different amount of total pages across all those logs. All the logs have the same lowmem limit so it seems like the upper bound was being calculated incorrectly for passing to free_area_init_node. Nothing is immediately jumping out at me so can you boot up with a small debug patch? diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 659c75d..88eac1f 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -187,6 +187,8 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max_low, unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES]; struct memblock_region *reg; + pr_err(XXX min %lx max_low %lx max_high %lx\n, min, max_low, max_high); + __memblock_dump_all(); /* * initialise the zones. */ It would be helpful to do this across a few bootups to see if the values are actually consistent. I'll keep looking in the meantime. Thanks, Laura Thanks Laura for the pointer. In case of error, I am getting some random memblock_add() calls from drivers/of/fdt.c:early_init_dt_scan_memory. The issue seems to be from u-boot, where it is not updating the memory subnode properly. I have got a fix for the u-boot, which I am testing right now. I will update tomorrow after I do some more test. I'm concerned my change can stay as is if this is exposing an issue in u-boot. Asking people to change bootloaders rarely ends well. Can you elaborate on what u-boot is doing that would be exposing this issue? Thanks, Laura Laura, Here is my assessment of the current situation. *Bug in the u-boot* Current u-boot for Arndale-octa board has defined NR_BANKS as 12 and the core uses a global structure (gd-bd) to maintain the start and size of individual banks. Depending on the revision of SoC used on the board, the board file [1] updates the start/size for either 8 or 12 banks. In case of current revision of Arndale-Octa boards
Re: mainline boot: 64 boots: 62 pass, 2 fail (v3.16-rc1-2-gebe0618)
On 06/27/2014 01:12 AM, Laura Abbott wrote:
+static unsigned int bank_cnt;
+static unsigned int max_cnt;
+
int __init arm_add_memory(u64 start, u64 size)
{
u64 aligned_start;
/*
+ * Some buggy bootloaders rely on the old meminfo behavior of not adding
+ * more than n banks since anything past that may contain invalid data.
+ */
+ if (bank_cnt = max_cnt) {
+ pr_crit(Max banks too low, ignoring memory at 0x%08llx\n,
+ (long long)start);
+ return -EINVAL;
+ }
+
+ bank_cnt++;
+
+ /*
* Ensure that start/size are aligned to a page boundary.
* Size is appropriately rounded down, start is rounded up.
*/
@@ -879,6 +894,7 @@ void __init setup_arch(char **cmdline_p)
mdesc = setup_machine_tags(__atags_pointer,
__machine_arch_type);
machine_desc = mdesc;
machine_name = mdesc-name;
+ max_cnt = mdesc-bank_limit;
arm_add_memory is getting called before this is being set, resulting in
none of the memory banks getting added[1].
setup_machine_fdt - early_init_dt_scan - early_init_dt_scan_memory
Would it make sense to re-introduce the config option ARM_NR_BANKS and
replace max_cnt with NR_BANKS?
[1] http://pastebin.com/MawYD7kb
if (mdesc-reboot_mode != REBOOT_HARD)
reboot_mode = mdesc-reboot_mode;
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f38cf7c..91283fd 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -350,4 +350,5 @@ DT_MACHINE_START(EXYNOS_DT, SAMSUNG EXYNOS (Flattened
Device Tree))
.dt_compat = exynos_dt_compat,
.restart= exynos_restart,
.reserve= exynos_reserve,
+ .bank_limit = 8,
MACHINE_END
--
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Re: mainline boot: 64 boots: 62 pass, 2 fail (v3.16-rc1-2-gebe0618)
On 06/26/2014 10:34 PM, Andreas Färber wrote: Hi Kevin and Tushar, Am 26.06.2014 16:59, schrieb Kevin Hilman: IMO, the bug is in u-boot and we should fix that. I agree that the u-boot bug needs to be fixed, and FWIW, I updated my u-boot and haven't seen the boot failure yet after several boots with next-20140625. Could you clarify your test setup: Are you using the original InSignal SPL [1] with just your own u-boot.bin? Or do you have access to some newer Samsung-signed SPL? The u-boot changes for Arndale-Octa was done as part of an activity within Linaro. Insignal had signed the SPL binary for us. You can extract the signed SPL binary from following hwpack[6] (tar xfz and then within u_boot folder[7]). The source code for this u-boot can be found here.[8] Just in case, commands to flash u-boot binaries are listed here.[9] That being said, since it's not always feasible/practical to update u-boot, and when it comes down to it, this is still a kernel regression, we should also fix the kernel to sanity check the values coming from u-boot, like it was doing before. Sounds good. Apart from this memory issue here, I noticed that CPUs don't appear to be in HYP mode for virtualization, which had required a signed SPL update for the ODROID-XU [2]. And to me it looks as if there's no Arndale Octa support in upstream U-Boot [3], no real maintenance on the InSignal fork [4] and a policy of not cooperating with others [5]. Adding Arndale-Octa support to upstream U-Boot was on a TODO list, but that didn't materialize because of some other reasons. Thanks, Andreas [1] http://forum.insignal.co.kr/viewtopic.php?f=6t=3199 [2] http://forum.odroid.com/viewtopic.php?f=64t=2778start=40#p32581 [3] http://git.denx.de/?p=u-boot.git;a=blob;f=boards.cfg;h=947f2bc5ba2794c94b3b2cea04664f005e025f9f;hb=HEAD#l286 [4] http://git.insignal.co.kr/insignal/arndale_octa-jb_mr1.1/u-boot/ [5] http://forum.insignal.co.kr/viewtopic.php?f=40t=3613 [6] http://snapshots.linaro.org/kernel-hwpack/linux-linaro-tracking-ll-arndale-octa/442/hwpack_linaro-arndale-octa_20140626-442_armhf_supported.tar.gz [7] path_to_extracted_folder/u_boot/usr/lib/u-boot/arndale_octa [8] git.linaro.org/landing-teams/working/samsung/u-boot.git/shortlog/refs/heads/tracking-arndale_octa [9] http://pastebin.com/pfGF2giq Thanks, -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 06/26/2014 09:38 PM, Kevin Hilman wrote:
Tushar Behera trbli...@gmail.com writes:
On Thu, Jun 26, 2014 at 4:51 AM, Kevin Hilman khil...@linaro.org wrote:
Doug Anderson diand...@google.com writes:
Tushar,
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com
wrote:
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.
The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: Tushar Behera tusha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Reported-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/exynos5420.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
I've tested this myself now as well.
Tested-by: Doug Anderson diand...@chromium.org
For me, this patch alone (on top of -next) doesn't solve the boot hang.
I still need clk_ignore_unused for a successful boot.
So, this patch might be correct, but it doesn't prevent a boot hang
using a chain-loaded nv_uboot on peach-pi. There's still another clock
being disabled that causes a hang.
Kevin
Kevin,
Can you please check if adding patch 1/3 alongwith patch 2/3 fixes the
issue for you?
Yes, using patch 1/3 along with 2/3 fixes the issue.
Okay, that adds some more reason to re-investigate patch 1/3.
Kevin,
Would you please provide me the environment setting of your u-boot?
U-boot environment on my board has been over-written, I would like to
set it same as yours and try to reproduce the issue at my end. With only
'sound init', I don't seem to hit this issue anymore.
Also can you please confirm that setting CLK_IGNORE_UNUSED flag
CLK_MAU_EPLL alone fixes the issue, without any need for
clk_ignore_unused in u-boot bootargs?
Yes, I have this patch[1] in my local branch which fixes the issue
alone, without clk_ignore_unused on the command line.
Kevin
[1]
From ab1627127730ef4507ce96cbf95047d626bbb53f Mon Sep 17 00:00:00 2001
From: Kevin Hilman khil...@linaro.org
Date: Thu, 5 Jun 2014 17:12:28 -0700
Subject: [PATCH] KJH: leave mau_epll enabled
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 61eccf0dd72f..ed175088ee7e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -911,7 +911,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[]
__initdata = {
SRC_MASK_TOP2, 24, 0, 0),
GATE(CLK_MAU_EPLL, mau_epll, mout_mau_epll_clk,
- SRC_MASK_TOP7, 20, 0, 0),
+ SRC_MASK_TOP7, 20, CLK_IGNORE_UNUSED, 0),
/* sclk */
GATE(CLK_SCLK_UART0, sclk_uart0, dout_uart0,
--
Tushar Behera
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Re: [PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode
On 05/31/2014 12:17 AM, Tomasz Figa wrote: On 30.05.2014 20:42, Kukjin Kim wrote: On 05/31/14 03:19, Andreas Färber wrote: Am 28.05.2014 06:13, schrieb Sachin Kamat: Almost all Exynos-series of SoCs that run in secure mode don't need additional offset for every CPU, with Exynos4412 being the only exception. Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420). While at it, fix the coding style (space around *). Signed-off-by: Sachin Kamatsachin.ka...@linaro.org Signed-off-by: Tushar Beheratushar.beh...@linaro.org --- arch/arm/mach-exynos/firmware.c |9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) Fixes ODROID-XU (Exynos5410) as well - thought it had been a prereq to applying the 5410 patches... Tested-by: Andreas Färberafaer...@suse.de Andreas, thanks for your test :-) Sachin, How about exynos4210, 5250, 5260 and 5440?... I need to check again, honestly I don't remember all of Exynos SoCs' different things ;-) Then will apply into fixes for 3.16. Exynos4210 doesn't use secure firmware, at least on any board supported in mainline. Not sure about those Exynos5 models, but the only boards supported in mainline with firmware node in DT are based on Exynos4412 or Exynos5410. Best regards, Tomasz Kukjin, Would you please pick this patch as a fix for 3.16? -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: mainline boot: 64 boots: 62 pass, 2 fail (v3.16-rc1-2-gebe0618)
On 06/25/2014 03:59 AM, Laura Abbott wrote:
On 6/24/2014 10:47 AM, Laura Abbott wrote:
On 6/23/2014 11:32 AM, Kevin Hilman wrote:
On Sun, Jun 22, 2014 at 8:56 PM, Tushar Behera trbli...@gmail.com wrote:
Adding linux-samsung-soc and linux-arm-kernel ML for wider audience.
On 06/19/2014 04:12 PM, Tushar Behera wrote:
On 06/19/2014 03:02 PM, Tushar Behera wrote:
On 06/18/2014 09:22 AM, Kevin Hilman wrote:
On Tue, Jun 17, 2014 at 8:26 PM, Tushar Behera trbli...@gmail.com
wrote:
On 06/17/2014 10:23 PM, Kevin Hilman wrote:
Sachin,
On Mon, Jun 16, 2014 at 11:16 PM, Kevin's boot bot
khil...@linaro.org wrote:
Tree/Branch: mainline
Git describe: v3.16-rc1-2-gebe0618
Failed boot tests (console logs at the end)
===
exynos5420-arndale-octa: FAIL:arm-exynos_defconfig
ste-snowball: FAIL:arm-u8500_defconfig
FYI... these failures are getting more consistent on my octa board,
but still not failing every time.
Kevin
Hi Kevin,
Same here.
Observation: If you soft-reset the board (through the jumpers) after
getting this problem, the problem keeps repeating. But if you
hard-reset
the board (by removing the power cord), the problem doesn't occur
during
next iteration.
I don't ever use the soft-reset, I only toggle the wall power. I
don't ever actually remove the power cord though, I'm using a
USB-controlled relay to toggle the wall power.
Kevin
Laura,
We are getting following kernel panic [1] (not always, but quite
regularly) while booting Arndale-Octa (based on Samsung's Exynos5420)
board with upstream kernel. I haven't observed this issue with other
boards yet.
This issue is observed when I am booting with uImage + dtb (within
roughly ~10 iterations).
Some more information:
The boot logs are provided in pastebin, okay[2] and failed[3].
In case of boot failures, I am getting a higher value for vm_total_pages
(684424 in [3]). In case of successful boot on my board, it is always
521232 [2] on my board.
I can confirm that reverting the Get rid of meminfo patch gets the
Octa board booting reliably again for me also.
In case it helps, some boot logs for failures from the last copule
linux-next build/boot cycles can be seen here:
http://armcloud.us/kernel-ci/next/next-20140623/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log
http://armcloud.us/kernel-ci/next/next-20140620/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log
Sorry, I missed this yesterday. I'm going to take a look.
Were all of
http://pastebin.com/1iLaizuL
http://pastebin.com/5tdDt4GL
http://armcloud.us/kernel-ci/next/next-20140623/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log
http://armcloud.us/kernel-ci/next/next-20140620/arm-exynos_defconfig/boot-exynos5420-arndale-octa.log
collected on the same type of board with the same amount of DRAM? I'm seeing a
different amount of total pages across all those logs. All the logs have the
same lowmem limit so it seems like the upper bound was being calculated
incorrectly for passing to free_area_init_node. Nothing is immediately jumping
out at me so can you boot up with a small debug patch?
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 659c75d..88eac1f 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -187,6 +187,8 @@ static void __init zone_sizes_init(unsigned long min,
unsigned long max_low,
unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
struct memblock_region *reg;
+ pr_err(XXX min %lx max_low %lx max_high %lx\n, min, max_low,
max_high);
+ __memblock_dump_all();
/*
* initialise the zones.
*/
It would be helpful to do this across a few bootups to see if the values are
actually consistent. I'll keep looking in the meantime.
Thanks,
Laura
Thanks Laura for the pointer. In case of error, I am getting some random
memblock_add() calls from drivers/of/fdt.c:early_init_dt_scan_memory.
The issue seems to be from u-boot, where it is not updating the memory
subnode properly. I have got a fix for the u-boot, which I am testing
right now. I will update tomorrow after I do some more test.
Additional changes in kernel.
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index c4cddf0..bca82b3 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -817,7 +817,7 @@ int __init early_init_dt_scan_memory(unsigned long
node, const char *uname,
endp = reg + (l / sizeof(__be32));
- pr_debug(memory scan node %s, reg size %d, data: %x %x %x %x,\n,
+ pr_err(memory scan node %s, reg size %d, data: %x %x %x %x,\n,
uname, l, reg[0], reg[1], reg[2], reg[3]);
while ((endp - reg) = (dt_root_addr_cells + dt_root_size_cells)) {
@@ -891,6 +891,7 @@ void __init __weak early_init_dt_add_memory_arch(u64
base, u64 size)
size -= phys_offset - base;
base = phys_offset
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On Thu, Jun 26, 2014 at 4:51 AM, Kevin Hilman khil...@linaro.org wrote: Doug Anderson diand...@google.com writes: Tushar, On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote: Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by: Tushar Behera tusha...@samsung.com Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com Reported-by: Kevin Hilman khil...@linaro.org --- arch/arm/boot/dts/exynos5420.dtsi |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) I've tested this myself now as well. Tested-by: Doug Anderson diand...@chromium.org For me, this patch alone (on top of -next) doesn't solve the boot hang. I still need clk_ignore_unused for a successful boot. So, this patch might be correct, but it doesn't prevent a boot hang using a chain-loaded nv_uboot on peach-pi. There's still another clock being disabled that causes a hang. Kevin Kevin, Can you please check if adding patch 1/3 alongwith patch 2/3 fixes the issue for you? Also can you please confirm that setting CLK_IGNORE_UNUSED flag CLK_MAU_EPLL alone fixes the issue, without any need for clk_ignore_unused in u-boot bootargs? -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] usb: host: Kconfig: Select PHY drivers for Exynos EHCI/OHCI
On 06/26/2014 11:09 AM, Sachin Kamat wrote: EHCI and OHCI drivers on Exynos platforms do not work without their corresponding SoC specific phy drivers. Hence it makes no sense to keep these phy drivers as user selectable. Instead select them from the respective USB configs to make things easier for the end user. While at it enable 5250 phy for Exynos 5420 SoC too. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com Cc: Kishon Vijay Abraham I kis...@ti.com --- Reviewed-by: Tushar Behera tusha...@samsung.com drivers/phy/Kconfig | 37 +++-- drivers/usb/host/Kconfig | 10 ++ 2 files changed, 13 insertions(+), 34 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 16a2f067c242..7fe7ef5f1322 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -121,44 +121,21 @@ config PHY_SUN4I_USB parts, as well as the 2 regular USB 2 host PHYs. config PHY_SAMSUNG_USB2 - tristate Samsung USB 2.0 PHY driver + tristate select GENERIC_PHY select MFD_SYSCON - help - Enable this to support the Samsung USB 2.0 PHY driver for Samsung - SoCs. This driver provides the interface for USB 2.0 PHY. Support for - particular SoCs has to be enabled in addition to this driver. Number - and type of supported phys depends on the SoC. + select PHY_EXYNOS4210_USB2 if CPU_EXYNOS4210 + select PHY_EXYNOS4X12_USB2 if (SOC_EXYNOS4212 || SOC_EXYNOS4412) + select PHY_EXYNOS5250_USB2 if (SOC_EXYNOS5250 || SOC_EXYNOS5420) config PHY_EXYNOS4210_USB2 - bool Support for Exynos 4210 - depends on PHY_SAMSUNG_USB2 - depends on CPU_EXYNOS4210 - help - Enable USB PHY support for Exynos 4210. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 4210 four - phys are available - device, host, HSIC0 and HSIC1. + bool config PHY_EXYNOS4X12_USB2 - bool Support for Exynos 4x12 - depends on PHY_SAMSUNG_USB2 - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) - help - Enable USB PHY support for Exynos 4x12. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 4x12 four - phys are available - device, host, HSIC0 and HSIC1. + bool config PHY_EXYNOS5250_USB2 - bool Support for Exynos 5250 - depends on PHY_SAMSUNG_USB2 - depends on SOC_EXYNOS5250 - help - Enable USB PHY support for Exynos 5250. This option requires that - Samsung USB 2.0 PHY driver is enabled and means that support for this - particular SoC is compiled in the driver. In case of Exynos 5250 four - phys are available - device, host, HSIC0 and HSIC. + bool config PHY_EXYNOS5_USBDRD tristate Exynos5 SoC series USB DRD PHY driver diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 61b7817bd66b..2938807331de 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -211,10 +211,11 @@ config USB_EHCI_SH If you use the PCI EHCI controller, this option is not necessary. config USB_EHCI_EXYNOS - tristate EHCI support for Samsung S5P/EXYNOS SoC Series - depends on PLAT_S5P || ARCH_EXYNOS - help - Enable support for the Samsung Exynos SOC's on-chip EHCI controller. + tristate EHCI support for Samsung S5P/EXYNOS SoC Series + depends on PLAT_S5P || ARCH_EXYNOS + select PHY_SAMSUNG_USB2 if ARCH_EXYNOS + help + Enable support for the Samsung Exynos SOC's on-chip EHCI controller. config USB_EHCI_MV bool EHCI support for Marvell PXA/MMP USB controller @@ -520,6 +521,7 @@ config USB_OHCI_SH config USB_OHCI_EXYNOS tristate OHCI support for Samsung S5P/EXYNOS SoC Series depends on PLAT_S5P || ARCH_EXYNOS + select PHY_SAMSUNG_USB2 if ARCH_EXYNOS help Enable support for the Samsung Exynos SOC's on-chip OHCI controller. -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] usb: dwc3: Kconfig: Select PHY drivers for Exynos DWC3
On 06/26/2014 11:09 AM, Sachin Kamat wrote: USB DWC3 driver on Exynos platforms does not work without its corresponding phy driver. Hence it makes no sense to keep the phy driver as user selectable. Instead select it from USB config to make things easier for the end user. While at it make the config depend on ARCH_EXYNOS5 instead of ARCH_EXYNOS as this IP is available only on Exynos5 platforms. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com Cc: Kishon Vijay Abraham I kis...@ti.com --- Reviewed-by: Tushar Behera tusha...@samsung.com drivers/phy/Kconfig |8 +--- drivers/usb/dwc3/Kconfig |3 ++- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 7fe7ef5f1322..6be353c9dc4c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -138,15 +138,9 @@ config PHY_EXYNOS5250_USB2 bool config PHY_EXYNOS5_USBDRD - tristate Exynos5 SoC series USB DRD PHY driver - depends on ARCH_EXYNOS5 OF - depends on HAS_IOMEM + tristate select GENERIC_PHY select MFD_SYSCON - help - Enable USB DRD PHY support for Exynos 5 SoC series. - This driver provides PHY interface for USB 3.0 DRD controller - present on Exynos5 SoC series. config PHY_XGENE tristate APM X-Gene 15Gbps PHY support diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 261c3b428220..501477452ad8 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -55,7 +55,8 @@ config USB_DWC3_OMAP config USB_DWC3_EXYNOS tristate Samsung Exynos Platform - depends on ARCH_EXYNOS || COMPILE_TEST + depends on ARCH_EXYNOS5 || COMPILE_TEST + select PHY_EXYNOS5_USBDRD default USB_DWC3 help Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside, -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Add cros_ec to exynos5420-peach-pit and exynos5800-peach-pi
On 06/24/2014 02:19 AM, Doug Anderson wrote:
This adds cros_ec to exynos5420-peach-pit and exynos5800-peach-pi,
including:
* The keyboard
* The i2c tunnel
* The tps65090 under the i2c tunnel
* The battery under the i2c tunnel
To add extra motivation, it should be noted that tps65090 is one of
the things needed to get display-related FETs turned on for pit and
pi.
Note that this relies on a few outstanding changes:
* Needs (spi: s3c64xx: fix broken cs_gpios usage in the driver) and
(spi: s3c64xx: for DT platofrms always get the chipselect info from
DT node) to work properly and match the documented bindings. See
https://patchwork.kernel.org/patch/4346701/ and
https://patchwork.kernel.org/patch/4346711/
Signed-off-by: Doug Anderson diand...@chromium.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Along with the dependency patches on next-20140623, tested keyboard on
Peach-Pi board.
Tested-by: Tushar Behera tusha...@samsung.com
Some comments below.
---
Changes in v2:
- Now just one patch since mfd patch landed.
- Rebased to ToT linux-next
arch/arm/boot/dts/exynos5420-peach-pit.dts | 145
+
arch/arm/boot/dts/exynos5800-peach-pi.dts | 145
+
2 files changed, 290 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 7649982..581f385 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
+ regulators {
+ dcdc1 {
+ ti,enable-ext-control;
+ };
+ dcdc2 {
+ ti,enable-ext-control;
+ };
+ dcdc3 {
+ ti,enable-ext-control;
+ };
+ fet1 {
tps65090_fet1: fet1 { ?
+ regulator-name = vcd_led;
+ };
+ tps65090_fet2: fet2 {
I would suggest we add similar labels to fet1, fet3, fet4, fet5 and fet6
also. That way it would be easy to reference them in subsequent DT nodes.
Same comment for Peach-Pi dts file too.
--
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Re: [PATCH 3/3] ARM: exynos: activate the CCI on boot CPU/cluster with the MCPM loopback
On 06/24/2014 09:41 AM, Nicolas Pitre wrote:
The Chromebook firmware doesn't enable the CCI for the boot cpu, and
arguably it shouldn't have to either. Let's have the kernel handle the
CCI on its own for the boot CPU the same way it does it for secondary CPUs
by using the MCPM loopback.
Signed-off-by: Nicolas Pitre n...@linaro.org
---
Tested on top of next-20140623. Verified that all 8 cores are coming up
on Exynos5800 based Peach-pi board.
Tested-by: Tushar Behera tusha...@samsung.com
arch/arm/mach-exynos/mcpm-exynos.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index 0498d0b887..0c839f94ec 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -290,6 +290,19 @@ static void __naked exynos_pm_power_up_setup(unsigned
int affinity_level)
b cci_enable_port_for_self);
}
+static void __init exynos_cache_off(void)
+{
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+ /* disable L2 prefetching on the Cortex-A15 */
+ asm volatile(
+ mcrp15, 1, %0, c15, c0, 3\n\t
+ isb\n\t
+ dsb
+ : : r (0x400));
+ }
+ exynos_v7_exit_coherency_flush(all);
+}
+
static const struct of_device_id exynos_dt_mcpm_match[] = {
{ .compatible = samsung,exynos5420 },
{ .compatible = samsung,exynos5800 },
@@ -333,6 +346,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
+ if (!ret)
+ ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
--
Tushar Behera
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Re: [PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
On 06/25/2014 04:29 AM, Doug Anderson wrote: Tushar, On Thu, Jun 12, 2014 at 12:40 AM, Tushar Behera tusha...@samsung.com wrote: On Wed, Jun 11, 2014 at 10:20 PM, Kevin Hilman khil...@linaro.org wrote: Tushar Behera tusha...@samsung.com writes: When the output clock of AUDSS mux is disabled, we are getting kernel oops while doing a clk_get() on other clocks provided by AUDSS. Though user manual doesn't specify this dependency, we came across this issue while disabling the parent of AUDSS mux clocks. Keeping the parents of AUDSS mux always enabled fixes this issue. While this patch works (and fixes the boot problem for me), it seems like it's papering over the real problem. Thanks for testing. Seems like the right fix is actually modelling the clocks properly so that enabling a child clock ensures that the parent is also enabled. Patch 2/3 was to ensure we have proper clock tree defined for Exynos5420. While testing with audio disabled, that patch alone fixed the issue. But when audio was enabled (and hence I2S0 was trying to access the clocks), we got some kernel oops during late booting, hence I came up this solution. The solution might be a little half-baked because of the urgency to push the fix, but will try to dig more into the issue on Monday when I resume office. Which Monday were you referring to? ;) Sorry that I couldn't get deeper into this issue. Thanks for reminding though. ...but in all seriousness do you have an official status update on this patch? It seems as if it's not needed and all you need is https://patchwork.kernel.org/patch/4333581/, but it would be nice to get an official confirmation. I have tested various scenarios with only patch 2/3, which seems to be sufficient for the time being. I have not encountered the older issue till now. I was thinking of testing a bit further, but given that you have already asked for, we can go ahead with only patch 2/3 right now. In case any further issue comes up, I will post patch 1/3 as per the review comments that I have got. Thanks! -Doug -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH V2 1/2] ASoC: samsung: Add machine driver for Odroid X2/U3
On 06/18/2014 09:52 PM, Sylwester Nawrocki wrote:
This patch adds the sound subsystem driver for Odroid-X2 and
Odroid-U3 boards. The codec works in I2S master mode; there are
2 separate audio routing paths defined as there are differences
in the signal routing between the X2 and U3 boards, i.e. U3 uses
single jack for headphones and microphone.
Signed-off-by: Chen Zhen zhen1.c...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
sound/soc/samsung/Kconfig |8 ++
sound/soc/samsung/Makefile|2 +
sound/soc/samsung/odroidx2_max98090.c | 191
+
3 files changed, 201 insertions(+)
create mode 100644 sound/soc/samsung/odroidx2_max98090.c
[ ... ]
+static int odroidx2_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream-private_data;
+ struct snd_soc_dai *cpu_dai = rtd-cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd-codec_dai;
+ int ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, MAX98090_MCLK,
+ SND_SOC_CLOCK_IN);
+ if (ret 0) {
+ dev_err(codec_dai-dev,
+ Unable to switch to FLL1: %d\n, ret);
+ return ret;
+ }
+
+ /* Set the cpu DAI configuration in order to use CDCLK */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK,
+ 0, SND_SOC_CLOCK_OUT);
+ if (ret 0)
+ return ret;
+
While upstreaming sound-card driver for Snow board, I had a comment from
Mark to move this to probe, if possible. That way, the clock operations
would be done only once and this function and odroidx2_ops can be
removed altogether.
+ dev_dbg(codec_dai-dev, HiFi DAI %s params: channels: %d, rate: %d\n,
+ snd_pcm_stream_str(substream), params_channels(params),
+ params_rate(params));
+
+ return 0;
+}
+
+static struct snd_soc_ops odroidx2_ops = {
+ .hw_params = odroidx2_hw_params,
+};
+
[ ... ]
+
+ ret = snd_soc_register_card(card);
devm_snd_soc_register_card ?
+ if (ret) {
+ dev_err(pdev-dev, snd_soc_register_card failed: %d\n, ret);
+ goto err_put_cpu_n;
+ }
+
+ return 0;
+
+err_put_cpu_n:
+ of_node_put(odroidx2_dai[0].cpu_of_node);
+err_put_cod_n:
+ of_node_put(odroidx2_dai[0].codec_of_node);
+ return ret;
+}
+
+static int odroidx2_audio_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(card);
This can be removed when devm_snd_soc_register_card is used.
--
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Re: [PATCH 1/2] ASoC: max98090: Add max98091 compatible string
On 06/21/2014 02:02 AM, Doug Anderson wrote:
Tushar,
On Fri, Jun 20, 2014 at 1:03 AM, Tushar Behera tusha...@samsung.com wrote:
From: Wonjoon Lee woojoo@samsung.com
The MAX98091 CODEC is the same as MAX98090 CODEC, but with an extra
microphone. Existing driver for MAX98090 CODEC already has support
for MAX98091 CODEC. Adding proper compatible string so that MAX98091
CODEC can be specified from device tree.
Signed-off-by: Wonjoon Lee woojoo@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Picked from https://chromium-review.googlesource.com/#/c/184091/
.../devicetree/bindings/sound/max98090.txt |2 +-
sound/soc/codecs/max98090.c|2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/max98090.txt
b/Documentation/devicetree/bindings/sound/max98090.txt
index a5e63fa..c454e67 100644
--- a/Documentation/devicetree/bindings/sound/max98090.txt
+++ b/Documentation/devicetree/bindings/sound/max98090.txt
@@ -4,7 +4,7 @@ This device supports I2C only.
Required properties:
-- compatible : maxim,max98090.
+- compatible : maxim,max98090 or maxim,max98091.
- reg : The I2C address of the device.
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index f5fccc7..4f5534d 100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -2460,12 +2460,14 @@ static const struct dev_pm_ops max98090_pm = {
static const struct i2c_device_id max98090_i2c_id[] = {
{ max98090, MAX98090 },
+ { max98091, MAX98091 },
optional: This would allow you to add some extra error checking in
max98090_probe() to make sure that the device-tree specified device
matched the device that was detected. That could be in a future
patch, though.
Reviewed-by: Doug Anderson diand...@chromium.org
Okay. I will add that in a follow-up patch.
Thanks for reviewing.
--
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Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On Mon, Jun 16, 2014 at 4:56 PM, Tushar Behera trbli...@gmail.com wrote: On 06/11/2014 09:28 PM, Javier Martinez Canillas wrote: On Wed, Jun 11, 2014 at 7:32 AM, Tushar Behera tusha...@samsung.com wrote: Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by: Tushar Behera tusha...@samsung.com Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com Reported-by: Kevin Hilman khil...@linaro.org --- arch/arm/boot/dts/exynos5420.dtsi |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e385322..79e9119 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -167,7 +167,7 @@ compatible = samsung,exynos5420-audss-clock; reg = 0x0381 0x0C; #clock-cells = 1; - clocks = clock CLK_FIN_PLL, clock CLK_FOUT_EPLL, + clocks = clock CLK_FIN_PLL, clock CLK_MAU_EPLL, clock CLK_SCLK_MAUDIO0, clock CLK_SCLK_MAUPCM0; clock-names = pll_ref, pll_in, sclk_audio, sclk_pcm_in; }; -- 1.7.9.5 -- Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Kukjin, Would you please take this patch as a fix for 3.16? -- Tushar Behera Kukjin, Please pick this patch for 3.16. This is an essential fix required for Peach-pit/Peach-pi board. -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: mainline boot: 64 boots: 62 pass, 2 fail (v3.16-rc1-2-gebe0618)
Adding linux-samsung-soc and linux-arm-kernel ML for wider audience. On 06/19/2014 04:12 PM, Tushar Behera wrote: On 06/19/2014 03:02 PM, Tushar Behera wrote: On 06/18/2014 09:22 AM, Kevin Hilman wrote: On Tue, Jun 17, 2014 at 8:26 PM, Tushar Behera trbli...@gmail.com wrote: On 06/17/2014 10:23 PM, Kevin Hilman wrote: Sachin, On Mon, Jun 16, 2014 at 11:16 PM, Kevin's boot bot khil...@linaro.org wrote: Tree/Branch: mainline Git describe: v3.16-rc1-2-gebe0618 Failed boot tests (console logs at the end) === exynos5420-arndale-octa: FAIL:arm-exynos_defconfig ste-snowball: FAIL:arm-u8500_defconfig FYI... these failures are getting more consistent on my octa board, but still not failing every time. Kevin Hi Kevin, Same here. Observation: If you soft-reset the board (through the jumpers) after getting this problem, the problem keeps repeating. But if you hard-reset the board (by removing the power cord), the problem doesn't occur during next iteration. I don't ever use the soft-reset, I only toggle the wall power. I don't ever actually remove the power cord though, I'm using a USB-controlled relay to toggle the wall power. Kevin Laura, We are getting following kernel panic [1] (not always, but quite regularly) while booting Arndale-Octa (based on Samsung's Exynos5420) board with upstream kernel. I haven't observed this issue with other boards yet. This issue is observed when I am booting with uImage + dtb (within roughly ~10 iterations). Some more information: The boot logs are provided in pastebin, okay[2] and failed[3]. In case of boot failures, I am getting a higher value for vm_total_pages (684424 in [3]). In case of successful boot on my board, it is always 521232 [2] on my board. [2] http://pastebin.com/1iLaizuL [3] http://pastebin.com/5tdDt4GL There is no issue when I am booting appended zImage (zImage+dtb). I tried running it over 200 cycles, but without any failure. 'git bisect' points to this commit. commit 1c2f87c22566 ARM: 8025/1: Get rid of meminfo Reverting this commit on top of v3.16-rc1-17-ge99cfa2, I tested for around 100 iterations of booting with uImage+dtb, without any failure. [1] Kernel log Unhandled fault: external abort on non-linefetch (0x008) at 0xffc0 Internal error: : 8 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1136 Comm: kworker/u16:0 Not tainted 3.15.0-rc1-00027-g1c8c3cf-dirty #5 task: ed0f5800 ti: eda52000 task.ti: eda52000 PC is at __copy_to_user_std+0x4c/0x3a8 LR is at copy_page_to_iter+0xb0/0x26c pc : [c01b858c]lr : [c00982c0]psr: 6113 sp : eda53de4 ip : fp : ee103040 r10: ed9fb700 r9 : 0080 r8 : eda53eb8 r7 : ffc0 r6 : r5 : 0080 r4 : eda53e78 r3 : r2 : r1 : ffc0 r0 : ed9fb700 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 2000406a DAC: 0015 Process kworker/u16:0 (pid: 1136, stack limit = 0xeda52240) -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Boot regression on Arndale Octa
] (do_sys_open) from [c0553d20] (kernel_init_freeable+0x160/0x1d8) [6.696017] [c0553d20] (kernel_init_freeable) from [c03dff9c] (kernel_ini[6.704165] [c03dff9c] (kernel_init) from [c001c9b8] (ret_from_fork+0x14/0x3c) [6.711698] Code: e34c104d e34c2061 ebf8d227 e5864224 (e5d4303d) [6.717766] ---[ end trace 67957db0672cb23f ]--- [6.722430] Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b [6.722430] [6.ӊ���CPU3: stpping [6.734141] CPU: 3 PID: 0 Comm: swapper/3 Tainted: G D 3.16.0-rc1-00330-g401c58f #2 [6.742730] [c00226d4] (unwind_backtrace) from [c001f890] (show_stack+0x10/0x14) [6.750439] [c001f890] (show_stack) from [c03e38cc] (dump_stack+0x80/0xc0) [6.757628] [c03e38cc] (dump_stack) from [c0021978] (handle_IPI+0x17c/0x38c) [6.764992] [c0021978] (handle_IPI) from [c0008640] (gic_handle_irq+0x64/0x68) [6.772530] [c0008640] (gic_handle_irq) from [c00203c0] (__irq_svc+0x40/0x70) [6.779977] Exception stack(0xeccc3f70 to 0xeccc3fb8) [6.785006] 3f60: �*fb8 0018 112a90e 0001 [6.793152] 3f80: 908bb587 001af8 c0ce558 p000 c05d65f3 eccc2000 [6.801296] 3fa0: fff8 eccc3fb8 c0077c4c c0301c5g 6113 [6.807888] [c00203c0] (__irq_svc) from [c0301c5c] (cpuidle_enter_state+0x50/0xe0) [6.815773] [c0301c5c] (cpuidle_enter_state) from [c006185c] (cpu_startup_entry+0x204/0x228) [6.824523] [c006185c] (cpu_startup_entry) from [200086e4] (0x200086e4) [6.83145�WAU�: stpping [6.834139] CPU: 2 PID: 0 Comm: swapper/2 Tainted: G D 3.16.0-rc1-00330-g401c58f #2 [6.842726] [c00226d4] (unwind_backtrace) from [c001f890] (show_stack+0x10/0x14) [6.x50436] [c001f890] (show_stack) from [c03e38cc] (dump_stack+0x80/0xc0) [6.857627] [c03e38cc] (dump_stack) from [c0021978] (handle_IPI+0x17c/0x18c) [6.864991] [c0021978] (handle_IPI) from [c0008640] (gic_handle_irq+0x64/0x68) [6.8w2529] [c000���(gic_hndle_irq) from [c00203c0] (__irq_svc+0x40/0x70) [6.879976] ExcYѥ���stac(0xeccc1f70 to 0xeccc1fb8+ [6.885004] 1f60: eccc1fb8 p018 9112a867 0001 [6.893151] 1f80: 90da86f0 0001 ebb89af8 c05ce558 c05d65f3 eccg [6.901295] 1fa0: fff8 eccc1fb8 c0077c4c c0301c5c 6113 [6.907886] [c00203c0] (__irq_svc) from [c0301c5c] (cpuidle_enter_state+0x50/0xe0) [6.915771] [c0301c5c] (cpuidle_enter_state) from [c006185c] (cpu_startup_entry+0x204/0x228) [6.924520] [c006185c] (cpu_startup_entry) from [200086e4] (��00086e4) 6.931450] CPU1: stopping [6.934138] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 3.16.0-rc1-00330-g401c58f #2 [6.942724] [c00226d4]���ݹ�}�Ʌ��� from [c01f890] (show_stack+0x10/0x14) [6.950434] [c001f890] (show_stack) from [c03e38cc] (dump_stack+0x80/0�,Jj[6.95726] [c03e38cc] (dump_stack) from [c0021978] (handle_IPI+0x17c/0x18c) [6.964989] [c0021978] (handle_IPI) from [c0008640] (gic_handle_irq+0x64/0x68) [6.972527] [c0008640] (gic_handle_irq) from [c00203c0] (__irq_svc+0x40/0x70) [6.979975] Exception stack(0xeccbff70 to 0xeccbffb8) [6.985003] ff60: eccbffb8 0018 9112ab55 0001 [6.993150] ff80: 77eb4196 0001 ebb81af8 c05ce558 c05d65f3 eccbe000 [7.001294] ffa0: f�*�� c0077c4c 0301c5c 6113 fff�C�+�r���¢�[c0203,��(_irq_svc) from [c0301c5c] �,ե��}��ѕ�}�хѕ�0x50/0xe0 [7.015768] [c0301c5c] (cpuidle_enter_state) from [c006185c] (cpu_startup_entry+0x204/0x228) [7.024519] [c006185c] (cpu_startup_entry) from [200086e4]� �00086e4) 7.031454] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b [7.031454] [ 275.976162} random: nonblocking pool is initialized NB: The serial debug board's output seems unreliable, so take with a grain of salt (cloco - clock, X??? etc.). Anyone any idea what this external abort may be related to? Could you please check if following commit has anything to do with your issue? 'git bisect' points to this commit. commit 1c2f87c22566 ARM: 8025/1: Get rid of meminfo Also please confirm if there is any change in behavior when you use uImage/zImage. I want to confirm whether this is same as [1]. [1] http://www.spinics.net/lists/arm-kernel/msg340668.html Regards, Andreas -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: Move display-timings node under fimd node
'display-timings' should be a subnode for fimd node. Moving this
node appropriately gets the display back on Origen/Origen-Quad boards.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Based on next-20140620.
Tested on Exynos4210-Origen board. Looks like there are still some pending
bits on Exynos4412-Origen to get display working.
arch/arm/boot/dts/exynos4210-origen.dts | 26 +-
arch/arm/boot/dts/exynos4412-origen.dts | 26 +-
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..a39323f 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -317,20 +317,20 @@
pinctrl-0 = lcd_en lcd_clk lcd_data24 pwm0_out;
pinctrl-names = default;
status = okay;
- };
- display-timings {
- native-mode = timing0;
- timing0: timing {
- clock-frequency = 4750;
- hactive = 1024;
- vactive = 600;
- hfront-porch = 64;
- hback-porch = 16;
- hsync-len = 48;
- vback-porch = 64;
- vfront-porch = 16;
- vsync-len = 3;
+ display-timings {
+ native-mode = timing0;
+ timing0: timing {
+ clock-frequency = 4750;
+ hactive = 1024;
+ vactive = 600;
+ hfront-porch = 64;
+ hback-porch = 16;
+ hsync-len = 48;
+ vback-porch = 64;
+ vfront-porch = 16;
+ vsync-len = 3;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..0604220 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -160,20 +160,20 @@
pinctrl-0 = lcd_clk lcd_data24 pwm1_out;
pinctrl-names = default;
status = okay;
- };
- display-timings {
- native-mode = timing0;
- timing0: timing {
- clock-frequency = 4750;
- hactive = 1024;
- vactive = 600;
- hfront-porch = 64;
- hback-porch = 16;
- hsync-len = 48;
- vback-porch = 64;
- vfront-porch = 16;
- vsync-len = 3;
+ display-timings {
+ native-mode = timing0;
+ timing0: timing {
+ clock-frequency = 4750;
+ hactive = 1024;
+ vactive = 600;
+ hfront-porch = 64;
+ hback-porch = 16;
+ hsync-len = 48;
+ vback-porch = 64;
+ vfront-porch = 16;
+ vsync-len = 3;
+ };
};
};
--
1.7.9.5
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[PATCH 2/2] ASoC: samsung: Extend snow driver to support MAX98091
Peach-pi board has MAX98091 CODEC. Extend snow machine driver to support
this board.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Documentation/devicetree/bindings/sound/snow.txt |1 +
sound/soc/samsung/snow.c |1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/snow.txt
b/Documentation/devicetree/bindings/sound/snow.txt
index 678b191..e0b7a82 100644
--- a/Documentation/devicetree/bindings/sound/snow.txt
+++ b/Documentation/devicetree/bindings/sound/snow.txt
@@ -3,6 +3,7 @@ Audio Binding for Snow boards
Required properties:
- compatible : Can be one of the following,
google,snow-audio-max98090 or
+ google,snow-audio-max98091 or
google,snow-audio-max98095
- samsung,i2s-controller: The phandle of the Samsung I2S controller
- samsung,audio-codec: The phandle of the audio codec
diff --git a/sound/soc/samsung/snow.c b/sound/soc/samsung/snow.c
index 014c177..8bbd348 100644
--- a/sound/soc/samsung/snow.c
+++ b/sound/soc/samsung/snow.c
@@ -103,6 +103,7 @@ static int snow_probe(struct platform_device *pdev)
static const struct of_device_id snow_of_match[] = {
{ .compatible = google,snow-audio-max98090, },
+ { .compatible = google,snow-audio-max98091, },
{ .compatible = google,snow-audio-max98095, },
{},
};
--
1.7.9.5
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[PATCH 1/2] ASoC: max98090: Add max98091 compatible string
From: Wonjoon Lee woojoo@samsung.com
The MAX98091 CODEC is the same as MAX98090 CODEC, but with an extra
microphone. Existing driver for MAX98090 CODEC already has support
for MAX98091 CODEC. Adding proper compatible string so that MAX98091
CODEC can be specified from device tree.
Signed-off-by: Wonjoon Lee woojoo@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Picked from https://chromium-review.googlesource.com/#/c/184091/
.../devicetree/bindings/sound/max98090.txt |2 +-
sound/soc/codecs/max98090.c|2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/max98090.txt
b/Documentation/devicetree/bindings/sound/max98090.txt
index a5e63fa..c454e67 100644
--- a/Documentation/devicetree/bindings/sound/max98090.txt
+++ b/Documentation/devicetree/bindings/sound/max98090.txt
@@ -4,7 +4,7 @@ This device supports I2C only.
Required properties:
-- compatible : maxim,max98090.
+- compatible : maxim,max98090 or maxim,max98091.
- reg : The I2C address of the device.
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index f5fccc7..4f5534d 100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -2460,12 +2460,14 @@ static const struct dev_pm_ops max98090_pm = {
static const struct i2c_device_id max98090_i2c_id[] = {
{ max98090, MAX98090 },
+ { max98091, MAX98091 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
static const struct of_device_id max98090_of_match[] = {
{ .compatible = maxim,max98090, },
+ { .compatible = maxim,max98091, },
{ }
};
MODULE_DEVICE_TABLE(of, max98090_of_match);
--
1.7.9.5
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[PATCH v2 0/2] ARM: dts: Peach-pi audio support and cleanup
The patchset is dependent on following patch. [1] ARM: dts: Update the parent for Audss clocks in Exynos5420 https://lkml.org/lkml/2014/6/11/36 During the review of v1, it was pointed out that it would be better to sort DTS files for Peach-pit and Peach-pi boards. Patch 2 is a step towards that activity. Tushar Behera (2): ARM: dts: Enable audio support for Peach-pi board ARM: dts: Sort nodes within Peach-pit/Peach-pi dts files arch/arm/boot/dts/exynos5420-peach-pit.dts | 236 ++-- arch/arm/boot/dts/exynos5800-peach-pi.dts | 218 ++--- 2 files changed, 245 insertions(+), 209 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] ARM: dts: Enable audio support for Peach-pi board
Peach-pi board has MAX98091 audio codec connected on HSI2C-7 bus.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changes for v2:
* Replaced max98090 with max98091.
arch/arm/boot/dts/exynos5800-peach-pi.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3af207..ef94ab8 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -57,6 +57,13 @@
pinctrl-names = default;
};
+ sound {
+ compatible = google,snow-audio-max98091;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = max98091;
+ };
+
usb300_vbus_reg: regulator-usb300 {
compatible = regulator-fixed;
regulator-name = P5.0V_USB3CON0;
@@ -81,6 +88,13 @@
};
pinctrl_0 {
+ max98091_irq: max98091-irq {
+ samsung,pins = gpx0-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
tpm_irq: tpm-irq {
samsung,pins = gpx1-0;
samsung,pin-function = 0;
@@ -207,6 +221,19 @@
samsung,invert-vclk;
};
+hsi2c_7 {
+ status = okay;
+
+ max98091: codec@10 {
+ compatible = maxim,max98091;
+ reg = 0x10;
+ interrupts = 2 0;
+ interrupt-parent = gpx0;
+ pinctrl-names = default;
+ pinctrl-0 = max98091_irq;
+ };
+};
+
hsi2c_9 {
status = okay;
clock-frequency = 40;
@@ -251,3 +278,7 @@
watchdog {
timeout-sec = 32;
};
+
+i2s0 {
+ status = okay;
+};
--
1.7.9.5
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[PATCH 2/2] ARM: dts: Sort nodes within Peach-pit/Peach-pi dts files
Peach-pit and Peach-pi boards are almost similar, hence the DTS file
is also very similar. Sorting nodes in both these files will allow
us to figure out the difference easily.
All the node aliases are sorted in alphabetically increasing order.
There is no functional change with this patch.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 236 ++--
arch/arm/boot/dts/exynos5800-peach-pi.dts | 225 +-
2 files changed, 233 insertions(+), 228 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 1c5b8f9..7649982 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -25,8 +25,13 @@
google,pit, google,peach,samsung,exynos5420,
samsung,exynos5;
- memory {
- reg = 0x2000 0x8000;
+ backlight {
+ compatible = pwm-backlight;
+ pwms = pwm 0 100 0;
+ brightness-levels = 0 100 500 1000 1500 2000 2500 2800;
+ default-brightness-level = 7;
+ pinctrl-0 = pwm0_out;
+ pinctrl-names = default;
};
fixed-rate-clocks {
@@ -50,13 +55,8 @@
};
};
- backlight {
- compatible = pwm-backlight;
- pwms = pwm 0 100 0;
- brightness-levels = 0 100 500 1000 1500 2000 2500 2800;
- default-brightness-level = 7;
- pinctrl-0 = pwm0_out;
- pinctrl-names = default;
+ memory {
+ reg = 0x2000 0x8000;
};
sound {
@@ -89,64 +89,83 @@
};
};
-pinctrl_0 {
- max98090_irq: max98090-irq {
- samsung,pins = gpx0-2;
- samsung,pin-function = 0;
- samsung,pin-pud = 0;
- samsung,pin-drv = 0;
- };
+dp {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = dp_hpd_gpio;
+ samsung,color-space = 0;
+ samsung,dynamic-range = 0;
+ samsung,ycbcr-coeff = 0;
+ samsung,color-depth = 1;
+ samsung,link-rate = 0x06;
+ samsung,lane-count = 2;
+ samsung,hpd-gpio = gpx2 6 0;
- tpm_irq: tpm-irq {
- samsung,pins = gpx1-0;
- samsung,pin-function = 0;
- samsung,pin-pud = 0;
- samsung,pin-drv = 0;
- };
+ display-timings {
+ native-mode = timing1;
- power_key_irq: power-key-irq {
- samsung,pins = gpx1-2;
- samsung,pin-function = 0;
- samsung,pin-pud = 0;
- samsung,pin-drv = 0;
+ timing1: timing@1 {
+ clock-frequency = 70589280;
+ hactive = 1366;
+ vactive = 768;
+ hfront-porch = 40;
+ hback-porch = 40;
+ hsync-len = 32;
+ vback-porch = 10;
+ vfront-porch = 12;
+ vsync-len = 6;
+ };
};
+};
- hdmi_hpd_irq: hdmi-hpd-irq {
- samsung,pins = gpx3-7;
- samsung,pin-function = 0;
- samsung,pin-pud = 1;
- samsung,pin-drv = 0;
- };
+fimd {
+ status = okay;
+ samsung,invert-vclk;
+};
- dp_hpd_gpio: dp_hpd_gpio {
- samsung,pins = gpx2-6;
- samsung,pin-function = 0;
- samsung,pin-pud = 3;
- samsung,pin-drv = 0;
- };
+hdmi {
+ status = okay;
+ hpd-gpio = gpx3 7 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = hdmi_hpd_irq;
+ ddc = i2c_2;
};
-pinctrl_3 {
- usb300_vbus_en: usb300-vbus-en {
- samsung,pins = gph0-0;
- samsung,pin-function = 1;
- samsung,pin-pud = 0;
- samsung,pin-drv = 0;
+hsi2c_7 {
+ status = okay;
+
+ max98090: codec@10 {
+ compatible = maxim,max98090;
+ reg = 0x10;
+ interrupts = 2 0;
+ interrupt-parent = gpx0;
+ pinctrl-names = default;
+ pinctrl-0 = max98090_irq;
};
+};
- usb301_vbus_en: usb301-vbus-en {
- samsung,pins = gph0-1;
- samsung,pin-function = 1;
- samsung,pin-pud = 0;
- samsung,pin-drv = 0;
+hsi2c_9 {
+ status = okay;
+ clock-frequency = 40;
+
+ tpm@20 {
+ compatible = infineon,slb9645tt;
+ reg = 0x20;
+
+ /* Unused irq; but still need to configure the pins */
+ pinctrl-names = default;
+ pinctrl-0 = tpm_irq;
};
};
-rtc {
+i2c_2 {
status = okay;
+ samsung,i2c-sda
Re: [PATCH 3/3] ARM: dts: Enable audio support for Peach-pi board
On 06/13/2014 10:33 PM, Doug Anderson wrote:
Tushar,
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote:
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
If you want to be a stickler about it, peach-pi actually has a
max98091. That requires code changes to the i2c driver, though.
...and unfortunately listing two compatible strings for i2c devices is
broken. :(
Hi Doug,
You are right. I checked the boot logs, the detected codec type is
MAX98091. Since both these CODECs are supported through a single driver
and the detection of chip is done during runtime, I would suggest we go
ahead with max98090 compatible string. I will update the commit
message accordingly.
Does that sound okay to you?
Signed-off-by: Tushar Behera tusha...@samsung.com
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 31
+
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3af207..76f5966 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -78,9 +78,27 @@
pinctrl-0 = usb301_vbus_en;
enable-active-high;
};
+
+ sound {
+ compatible = google,snow-audio-max98090;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = max98090;
+ };
+};
+
+i2s0 {
+ status = okay;
It would be awfully nice to keep diffs between exynos5420-peach-pit
and exynos5800-peach-pi clean. They're 99% the same. I know this has
already gotten messed up with DP/HDMI were added, but there's no need
to make it worse.
If you so desire, I will submit a patch to sort peach-pi device-tree
nodes (w.r.t. peach-pit dts file).
Could you add these nodes in the same place within the dts they were
added in exynos5420-peach-pit?
Okay, I will add it after watchdog node.
--
Tushar Behera
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Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 06/11/2014 09:28 PM, Javier Martinez Canillas wrote: On Wed, Jun 11, 2014 at 7:32 AM, Tushar Behera tusha...@samsung.com wrote: Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by: Tushar Behera tusha...@samsung.com Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com Reported-by: Kevin Hilman khil...@linaro.org --- arch/arm/boot/dts/exynos5420.dtsi |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e385322..79e9119 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -167,7 +167,7 @@ compatible = samsung,exynos5420-audss-clock; reg = 0x0381 0x0C; #clock-cells = 1; - clocks = clock CLK_FIN_PLL, clock CLK_FOUT_EPLL, + clocks = clock CLK_FIN_PLL, clock CLK_MAU_EPLL, clock CLK_SCLK_MAUDIO0, clock CLK_SCLK_MAUPCM0; clock-names = pll_ref, pll_in, sclk_audio, sclk_pcm_in; }; -- 1.7.9.5 -- Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Kukjin, Would you please take this patch as a fix for 3.16? -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add missing clock/pin-control entries for I2S0 on Exynos4
On 06/09/2014 04:36 PM, Sylwester Nawrocki wrote: On 09/06/14 12:44, Tushar Behera wrote: IMHO, the clock entries belong here as the audss clock provider essentially remains same for all Exynos4 based systems. As for pin-control entry, I believe we can move them to respective SoC dtsi files. Does that sound okay to you? I guess that's fine, I tend to agree with you about the clocks. As I was going ahead with the implementation, it felt like repetition with the same code. Would it be acceptable to you if we go ahead with the earlier approach of adding both clock and pin-control entry to exynos4.dtsi? I can see i2c_n and spi_n adding pin-control entries in exynos4.dtsi itself. -- Thanks, Sylwester -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add missing clock/pin-control entries for I2S0 on Exynos4
On Mon, Jun 16, 2014 at 5:20 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: On 16/06/14 13:43, Tushar Behera wrote: On 06/09/2014 04:36 PM, Sylwester Nawrocki wrote: On 09/06/14 12:44, Tushar Behera wrote: IMHO, the clock entries belong here as the audss clock provider essentially remains same for all Exynos4 based systems. As for pin-control entry, I believe we can move them to respective SoC dtsi files. Does that sound okay to you? I guess that's fine, I tend to agree with you about the clocks. As I was going ahead with the implementation, it felt like repetition with the same code. Would it be acceptable to you if we go ahead with the earlier approach of adding both clock and pin-control entry to exynos4.dtsi? I can see i2c_n and spi_n adding pin-control entries in exynos4.dtsi itself. OK, I don't mind, I'll leave it up to the maintainers. -- Regards, Sylwester Kukjin, Any comments on this? If not, I will resend this patch based on v3.16-rc1. -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: Enable audio support for Peach-pi board
On Mon, Jun 16, 2014 at 10:32 PM, Doug Anderson diand...@google.com wrote:
Mark,
On Mon, Jun 16, 2014 at 9:51 AM, Mark Brown broo...@kernel.org wrote:
On Mon, Jun 16, 2014 at 09:49:26AM -0700, Doug Anderson wrote:
Yes please. I think there's supposed to be some official ordering of
things. If anyone reading this has a pointer to the official sort
order of things in the device tree I'd love to see it! ;)
Most exact first I believe?
More specifically I'm looking for the ordering between nodes and
between properties in a node. For instance:
1. It appears to be convention to sort children of the pinctrl nodes
by the first pin number in that group. That is:
ec_spi_cs: ec-spi-cs {
samsung,pins = gpb1-2;
...
};
...comes before:
usb300_vbus_en: usb300-vbus-en {
samsung,pins = gph0-0;
...
};
...that's one really good and well-defined ordering.
2. I have no idea how general properties should be sorted. I tend to
see compatible first but that's above the only rule I've seen.
Sometimes I've seen status first, sometimes last, sometimes
alphabetically sorted, and sometimes in a random place. Examples:
usb301_vbus_reg: regulator-usb301 {
compatible = regulator-fixed;
regulator-name = P5.0V_USB3CON1;
regulator-min-microvolt = 500;
regulator-max-microvolt = 500;
gpio = gph0 1 0;
pinctrl-names = default;
pinctrl-0 = usb301_vbus_en;
enable-active-high;
};
hdmi {
status = okay;
hpd-gpio = gpx3 7 GPIO_ACTIVE_HIGH;
pinctrl-names = default;
pinctrl-0 = hdmi_hpd_irq;
ddc = i2c_2;
};
3. I have no idea how to sort nodes. In theory you could say that
they should be sorted by base address:
i2s0: i2s@0383 {
...
};
hsi2c_7: i2c@12CD {
...
};
i2s1: i2s@12D6 {
...
};
...that works until someone argues that all of the i2s nodes should
be together. It also doesn't work so well with the board convention
of using aliases to refer to things in the SoC, like:
i2s0 {
status = okay;
};
hsi2c_7 {
status = okay;
};
...it's not at all obvious in the board file what the base address in
the SoC was.
In case where we are using only aliases in board file, sorting them
alphabetically would be reasonable. This rule would be easy to
reinforce.
---
Anyway, none of this is earth shattering and it doesn't matter all
that much. It's just nice to have an official order to make diffing
easier and also to avoid merge conflicts (unlikely someone changing
different properties will both add them in the same place in the
ordering).
-Doug
--
Tushar Behera
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Re: [PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
On Wed, Jun 11, 2014 at 10:20 PM, Mike Turquette mturque...@linaro.org wrote: Quoting Tushar Behera (2014-06-10 22:32:17) When the output clock of AUDSS mux is disabled, we are getting kernel oops while doing a clk_get() on other clocks provided by AUDSS. Though user manual doesn't specify this dependency, we came across this issue while disabling the parent of AUDSS mux clocks. Hi Tushar, Can you help me understand better what the actual problem is? What is the root cause of the kernel oops? Currently AUDSS mux has two parents, XXTI crystal and MAU_EPLL clock. As per observation, when the output of AUDSS mux is gated, we are not able to do any operation on the clocks provided by MAU block (mostly the clocks used by ADMA and audio blocks). You mention calling clk_get on child clocks of the AUDSS mux fails, but I cannot imagine why. How can the enable/disable state of a clock affect the ability to clk_get other clocks? I might have a little vogue while updating the commit message (mentioning about clk_get which surely is only a s/w operation), but there is definitely some issue with handling those clocks under given scenario. I am on leave till end of this week, so I will update you more with the logs on Monday. Thanks, -- Tushar -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
On Wed, Jun 11, 2014 at 10:58 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tushar, On 11.06.2014 07:32, Tushar Behera wrote: When the output clock of AUDSS mux is disabled, we are getting kernel oops while doing a clk_get() on other clocks provided by AUDSS. Though user manual doesn't specify this dependency, we came across this issue while disabling the parent of AUDSS mux clocks. Could you provide more data about this oops? E.g. kernel log, platforms it affects (just peach-pit or also others), test case, extra patches applied on top of mainline (if any). I don't like this solution, because keeping a clock always enabled is usually not desirable and this driver is also used on other platforms than peach-pit, so this change will affect all of them. I will update later after doing similar tests on other platforms. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
On Wed, Jun 11, 2014 at 10:20 PM, Kevin Hilman khil...@linaro.org wrote: Tushar Behera tusha...@samsung.com writes: When the output clock of AUDSS mux is disabled, we are getting kernel oops while doing a clk_get() on other clocks provided by AUDSS. Though user manual doesn't specify this dependency, we came across this issue while disabling the parent of AUDSS mux clocks. Keeping the parents of AUDSS mux always enabled fixes this issue. While this patch works (and fixes the boot problem for me), it seems like it's papering over the real problem. Thanks for testing. Seems like the right fix is actually modelling the clocks properly so that enabling a child clock ensures that the parent is also enabled. Patch 2/3 was to ensure we have proper clock tree defined for Exynos5420. While testing with audio disabled, that patch alone fixed the issue. But when audio was enabled (and hence I2S0 was trying to access the clocks), we got some kernel oops during late booting, hence I came up this solution. The solution might be a little half-baked because of the urgency to push the fix, but will try to dig more into the issue on Monday when I resume office. Kevin Thanks, -- Tushar -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] Fix boot-hang on Peach-pit and Enable audio
With next-20140610, Peach-pit/Peach-pi board hangs during boot if we run 'sound init' during u-boot. The issue is fixed in following patches. While at it, also enable audio support for Peach-pi board. How to test audio on Peach-pi: * On top of exynos_defconfig, enable SND_SOC_SNOW and PL330_DMA. * Run 'sound init' at u-boot prompt. Tushar Behera (3): clk: exynos-audss: Keep the parent of mout_audss always enabled ARM: dts: Update the parent for Audss clocks in Exynos5420 ARM: dts: Enable audio support for Peach-pi board arch/arm/boot/dts/exynos5420.dtsi |2 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 31 + drivers/clk/samsung/clk-exynos-audss.c| 17 +--- 3 files changed, 46 insertions(+), 4 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
When the output clock of AUDSS mux is disabled, we are getting kernel
oops while doing a clk_get() on other clocks provided by AUDSS. Though
user manual doesn't specify this dependency, we came across this issue
while disabling the parent of AUDSS mux clocks.
Keeping the parents of AUDSS mux always enabled fixes this issue.
Signed-off-by: Tushar Behera tusha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
drivers/clk/samsung/clk-exynos-audss.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 13eae14c..1542f30 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -30,6 +30,8 @@ static struct clk **clk_table;
static void __iomem *reg_base;
static struct clk_onecell_data clk_data;
+static struct clk *pll_ref, *pll_in;
+
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8
@@ -83,7 +85,7 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
const char *sclk_pcm_p = sclk_pcm0;
- struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
+ struct clk *cdclk, *sclk_audio, *sclk_pcm_in;
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
@@ -113,10 +115,14 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
pll_ref = devm_clk_get(pdev-dev, pll_ref);
pll_in = devm_clk_get(pdev-dev, pll_in);
- if (!IS_ERR(pll_ref))
+ if (!IS_ERR(pll_ref)) {
mout_audss_p[0] = __clk_get_name(pll_ref);
- if (!IS_ERR(pll_in))
+ clk_prepare_enable(pll_ref);
+ }
+ if (!IS_ERR(pll_in)) {
mout_audss_p[1] = __clk_get_name(pll_in);
+ clk_prepare_enable(pll_in);
+ }
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
@@ -217,6 +223,11 @@ static int exynos_audss_clk_remove(struct platform_device
*pdev)
clk_unregister(clk_table[i]);
}
+ if (!IS_ERR(pll_in))
+ clk_disable_unprepare(pll_in);
+ if (!IS_ERR(pll_ref))
+ clk_disable_unprepare(pll_ref);
+
return 0;
}
--
1.7.9.5
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[PATCH 3/3] ARM: dts: Enable audio support for Peach-pi board
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3af207..76f5966 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -78,9 +78,27 @@
pinctrl-0 = usb301_vbus_en;
enable-active-high;
};
+
+ sound {
+ compatible = google,snow-audio-max98090;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = max98090;
+ };
+};
+
+i2s0 {
+ status = okay;
};
pinctrl_0 {
+ max98090_irq: max98090-irq {
+ samsung,pins = gpx0-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
tpm_irq: tpm-irq {
samsung,pins = gpx1-0;
samsung,pin-function = 0;
@@ -207,6 +225,19 @@
samsung,invert-vclk;
};
+hsi2c_7 {
+ status = okay;
+
+ max98090: codec@10 {
+ compatible = maxim,max98090;
+ reg = 0x10;
+ interrupts = 2 0;
+ interrupt-parent = gpx0;
+ pinctrl-names = default;
+ pinctrl-0 = max98090_irq;
+ };
+};
+
hsi2c_9 {
status = okay;
clock-frequency = 40;
--
1.7.9.5
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Re: [PATCH] ARM: dts: Add missing clock/pin-control entries for I2S0 on Exynos4
On 06/09/2014 03:23 PM, Sylwester Nawrocki wrote:
Hi Tushar,
On 07/06/14 11:30, Tushar Behera wrote:
I2S driver uses 3 clocks under different conditions. Added two
missing clocks.
Additionally updated pin-control property for this node.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Based on next-20140606.
Tested on Exynos4210-based Origen boards with private patches for
codec/machine driver.
arch/arm/boot/dts/exynos4.dtsi |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426..10bb081 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -55,11 +55,15 @@
i2s0: i2s@0383 {
compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
-clocks = clock_audss EXYNOS_I2S_BUS;
-clock-names = iis;
+clocks = clock_audss EXYNOS_I2S_BUS,
+clock_audss EXYNOS_I2S_BUS,
+clock_audss EXYNOS_SCLK_I2S;
+clock-names = iis, i2s_opclk0, i2s_opclk1;
dmas = pdma0 12, pdma0 11, pdma0 10;
dma-names = tx, rx, tx-sec;
samsung,idma-addr = 0x0300;
+pinctrl-0 = i2s0_bus;
+pinctrl-names = default;
status = disabled;
};
I assumed those properties you're adding here belong to board or
to SoC type specific dts. It doesn't hurt ot have it like this,
but what do you think about moving this to arch/arm/boot/dts/
exynos4210(4x12).dtsi ? For instance pinctrl definitions are
in SoC specific dts.
IMHO, the clock entries belong here as the audss clock provider
essentially remains same for all Exynos4 based systems.
As for pin-control entry, I believe we can move them to respective SoC
dtsi files.
Does that sound okay to you?
--
Thanks,
Sylwester
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--
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[PATCH] ARM: dts: Add missing clock/pin-control entries for I2S0 on Exynos4
I2S driver uses 3 clocks under different conditions. Added two
missing clocks.
Additionally updated pin-control property for this node.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Based on next-20140606.
Tested on Exynos4210-based Origen boards with private patches for
codec/machine driver.
arch/arm/boot/dts/exynos4.dtsi |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426..10bb081 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -55,11 +55,15 @@
i2s0: i2s@0383 {
compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
- clocks = clock_audss EXYNOS_I2S_BUS;
- clock-names = iis;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
dmas = pdma0 12, pdma0 11, pdma0 10;
dma-names = tx, rx, tx-sec;
samsung,idma-addr = 0x0300;
+ pinctrl-0 = i2s0_bus;
+ pinctrl-names = default;
status = disabled;
};
--
1.7.9.5
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Re: Problems booting exynos5420 with 1 CPU
On 06/06/2014 06:38 AM, Doug Anderson wrote: Hi, When I try to boot linuxnext on my exynos5420-peach-pit chromebook I have problems bringing up extra CPUs: 1. They don't come up [ ... ] [1.125030] CPU1: failed to boot: -38 [2.130043] CPU2: failed to boot: -38 [3.135059] CPU3: failed to boot: -38 With following config modifications over exynos_defconfig, I can see 4 big cores coming up. CONFIG_MCPM=y CONFIG_EXYNOS5420_MCPM=y [0.030919] Exynos MCPM support installed [0.060233] CPU1: Booted secondary processor [0.090006] CPU1: update cpu_power 1535 [0.090010] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 [0.100234] CPU2: Booted secondary processor [0.130007] CPU2: update cpu_power 1535 [0.130011] CPU2: thread -1, cpu 2, socket 0, mpidr 8002 [0.140233] CPU3: Booted secondary processor [0.170008] CPU3: update cpu_power 1535 [0.170012] CPU3: thread -1, cpu 3, socket 0, mpidr 8003 -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 0/3] Exynos 5410 support
On Thu, May 29, 2014 at 11:30 PM, Andreas Färber afaer...@suse.de wrote: Hi Tarek, And I reproducibly get failures for CPUs 1-3, resulting in only one CPU in /proc/cpuinfo (compared to 4 on downstream 3.14): [0.045778] CPU: Testing write buffer coherency: ok [0.045968] /cpus/cpu@0 missing clock-frequency property [0.045993] /cpus/cpu@1 missing clock-frequency property [0.046016] /cpus/cpu@2 missing clock-frequency property [0.046040] /cpus/cpu@3 missing clock-frequency property [0.046059] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.046135] Setting up static identity map for 0x403a8920 - 0x403a8978 [2.075052] CPU1: failed to come online [4.085095] CPU2: failed to come online [6.095142] CPU3: failed to come online [6.095237] Brought up 1 CPUs [6.095269] SMP: Total of 1 processors activated. [6.095303] CPU: All CPU(s) started in HYP mode. [6.095336] CPU: Virtualization extensions available. I also notice another apparent device tree issue: [7.341814] of_get_named_gpiod_flags: can't parse gpios property of node '/soc/mmc@1222/slot@0[0]' [7.341850] of_get_named_gpiod_flags: can't parse gpios property of node '/soc/mmc@1222/slot@0[0]' Are any of those known issues and being worked on? (The CPU failures affected 5420 Arndale Octa as well iirc.) Can you check after applying following two patches for Arndale-Octa ([1],[2])? In other words, a patch similar to [2] might be required for this board too if it is booting under secure mode. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31776.html [PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode [2] http://www.spinics.net/lists/linux-samsung-soc/msg31777.html [PATCH v2 Resend 2/2] ARM: dts: Add secure firmware support for Arndale-octa -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add mclk entry for Snow/Peach-pit boards
On 20 May 2014 10:19, Tushar Behera tushar.beh...@linaro.org wrote:
On Snow/Peach-pit boards, XCLKOUT provides master clock (mclk) to codec.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
This patch is obsolete now because the proposed clock bindings for
XCLKOUT is now different (change in #clock-cells). Updated patch will
be sent once the XCLKOUT drivers are accepted.
Dependency:
1. Driver side changes have been posted here.
https://lkml.org/lkml/2014/5/20/4
2. XCLKOUT clock driver support
https://lkml.org/lkml/2014/5/15/530
arch/arm/boot/dts/exynos5250-snow.dts |3 +++
arch/arm/boot/dts/exynos5420-peach-pit.dts |3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index 67391b9..1014ce0 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -346,6 +346,9 @@
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98095;
+
+ clocks = pmu_system_controller;
+ clock-names = mclk;
};
usb@1211 {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index f4b2a16..c0664e9 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -64,6 +64,9 @@
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98090;
+
+ clocks = pmu_system_controller;
+ clock-names = mclk;
};
};
--
1.7.9.5
--
Tushar Behera
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Re: [PATCH 1/3] mmc: host: add slot argument to mmc_of_parse
On 23 May 2014 15:55, Jaehoon Chung jh80.ch...@samsung.com wrote: From: Ludovic Desroches ludovic.desroc...@atmel.com Some hosts manage several slots. In these case information such as the bus width, chi detect and others are into the slot node. So we have to parse child node. If not NULL, slot node will be used instead of the device node. Signed-off-by: Ludovic Desroches ludovic.desroc...@atmel.com Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com --- drivers/mmc/core/host.c | 13 + include/linux/mmc/host.h | 10 +- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 95cceae..0f677b3 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -298,15 +298,17 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host) #endif /** - * mmc_of_parse() - parse host's device-tree node + * __mmc_of_parse() - parse host's device-tree node IMO it would be better to rename this function, something like mmc_of_parse_slot(). -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: samsung: Use params_width()
commit 8c5178fca4ce (ALSA: Add params_width() helpers) introduces
a helper to get the sample width. Updating Samsung related sound
drivers to use this helper.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/i2s.c |8
sound/soc/samsung/pcm.c |4 ++--
sound/soc/samsung/s3c-i2s-v2.c |8
sound/soc/samsung/s3c2412-i2s.c |6 +++---
sound/soc/samsung/s3c24xx-i2s.c |6 +++---
sound/soc/samsung/smdk_wm8580.c |8 +++-
sound/soc/samsung/smdk_wm8994.c |2 +-
sound/soc/samsung/spdif.c |4 ++--
8 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 07ff3e7..6b96168 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -672,8 +672,8 @@ static int i2s_hw_params(struct snd_pcm_substream
*substream,
if (is_manager(i2s))
mod = ~MOD_BLC_MASK;
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
if (is_secondary(i2s))
mod |= MOD_BLCS_8BIT;
else
@@ -681,7 +681,7 @@ static int i2s_hw_params(struct snd_pcm_substream
*substream,
if (is_manager(i2s))
mod |= MOD_BLC_8BIT;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
if (is_secondary(i2s))
mod |= MOD_BLCS_16BIT;
else
@@ -689,7 +689,7 @@ static int i2s_hw_params(struct snd_pcm_substream
*substream,
if (is_manager(i2s))
mod |= MOD_BLC_16BIT;
break;
- case SNDRV_PCM_FORMAT_S24_LE:
+ case 24:
if (is_secondary(i2s))
mod |= MOD_BLCS_24BIT;
else
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index a3c9c9c..4c5f97f 100644
--- a/sound/soc/samsung/pcm.c
+++ b/sound/soc/samsung/pcm.c
@@ -283,8 +283,8 @@ static int s3c_pcm_hw_params(struct snd_pcm_substream
*substream,
dev_dbg(pcm-dev, Entered %s\n, __func__);
/* Strictly check for sample size */
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S16_LE:
+ switch (params_width(params)) {
+ case 16:
break;
default:
return -EINVAL;
diff --git a/sound/soc/samsung/s3c-i2s-v2.c b/sound/soc/samsung/s3c-i2s-v2.c
index 77a2ae5..0ff4bbe 100644
--- a/sound/soc/samsung/s3c-i2s-v2.c
+++ b/sound/soc/samsung/s3c-i2s-v2.c
@@ -322,13 +322,13 @@ static int s3c_i2sv2_hw_params(struct snd_pcm_substream
*substream,
iismod = ~S3C64XX_IISMOD_BLC_MASK;
/* Sample size */
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
iismod |= S3C64XX_IISMOD_BLC_8BIT;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
break;
- case SNDRV_PCM_FORMAT_S24_LE:
+ case 24:
iismod |= S3C64XX_IISMOD_BLC_24BIT;
break;
}
diff --git a/sound/soc/samsung/s3c2412-i2s.c b/sound/soc/samsung/s3c2412-i2s.c
index 843f315..08c059b 100644
--- a/sound/soc/samsung/s3c2412-i2s.c
+++ b/sound/soc/samsung/s3c2412-i2s.c
@@ -120,11 +120,11 @@ static int s3c2412_i2s_hw_params(struct snd_pcm_substream
*substream,
iismod = readl(i2s-regs + S3C2412_IISMOD);
pr_debug(%s: r: IISMOD: %x\n, __func__, iismod);
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
iismod |= S3C2412_IISMOD_8BIT;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
iismod = ~S3C2412_IISMOD_8BIT;
break;
}
diff --git a/sound/soc/samsung/s3c24xx-i2s.c b/sound/soc/samsung/s3c24xx-i2s.c
index 4a6d206..9aba9fb 100644
--- a/sound/soc/samsung/s3c24xx-i2s.c
+++ b/sound/soc/samsung/s3c24xx-i2s.c
@@ -248,12 +248,12 @@ static int s3c24xx_i2s_hw_params(struct snd_pcm_substream
*substream,
iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
pr_debug(hw_params r: IISMOD: %x\n, iismod);
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
+ switch (params_width(params)) {
+ case 8:
iismod = ~S3C2410_IISMOD_16BIT;
dma_data-dma_size = 1;
break;
- case SNDRV_PCM_FORMAT_S16_LE:
+ case 16:
iismod |= S3C2410_IISMOD_16BIT;
dma_data-dma_size = 2;
break;
diff --git a/sound/soc/samsung/smdk_wm8580.c b/sound/soc/samsung/smdk_wm8580.c
index 7a16b32..b1a519f 100644
--- a/sound/soc/samsung/smdk_wm8580.c
+++ b/sound/soc/samsung/smdk_wm8580.c
@@ -37,13 +37,11 @@ static int smdk_hw_params(struct snd_pcm_substream
*substream
Re: [PATCH 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
On 22 May 2014 16:04, Tomasz Figa t.f...@samsung.com wrote: On 22.05.2014 07:13, Tushar Behera wrote: On 05/20/2014 10:13 PM, Tomasz Figa wrote: This patch introduces a driver that handles configuration of CLKOUT pin of Exynos SoCs that can be used to output certain clocks from inside of the SoC to a dedicated output pin. Signed-off-by: Tomasz Figa t.f...@samsung.com --- .../devicetree/bindings/arm/samsung/pmu.txt| 30 drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos-clkout.c| 153 + 3 files changed, 184 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos-clkout.c [ ... ] +clkout-clk_table[0] = clk_register_composite(NULL, clkout, +parent_names, parent_count, clkout-mux.hw, +clk_mux_ops, NULL, NULL, clkout-gate.hw, +clk_gate_ops, CLK_SET_RATE_PARENT +| CLK_SET_RATE_NO_REPARENT); Would you please remove CLK_SET_RATE_NO_REPARENT flag from here? Let me know if you have reservations against this. The problem with clock reparenting is that there are certain parent clocks of CLKOUT, rate of which changes at runtime, e.g. clocks derived from APLL or bus clocks, which can be reconfigured by cpufreq or devfreq. +CC: Sylwester Nawrocki Okay. But in cases where there is only 1 valid parent clock provided through DT (at the moment for Exynos5250/Exynos5420), would it be safe to set that clock as the parent of CLKOUT? Otherwise, this clock is not usable ATM. With RFC patches, I am able to do a clk_set_rate() on this clock to get a 24MHz output to the codec clock. With this flag set, I again have to rely on the default value set to this register in bootloader. This problem should be handled by initializing clocks from DT. I'm not sure why it hasn't been implemented yet... I would be happy to get it done that way. I can see a patch from Sylwester regarding this, but there hasn't been a conclusion as of yet. https://lkml.org/lkml/2014/4/9/173 Thanks, -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
On 22 May 2014 17:31, Tomasz Figa t.f...@samsung.com wrote: On 22.05.2014 13:44, Tushar Behera wrote: On 22 May 2014 16:04, Tomasz Figa t.f...@samsung.com wrote: On 22.05.2014 07:13, Tushar Behera wrote: On 05/20/2014 10:13 PM, Tomasz Figa wrote: This patch introduces a driver that handles configuration of CLKOUT pin of Exynos SoCs that can be used to output certain clocks from inside of the SoC to a dedicated output pin. Signed-off-by: Tomasz Figa t.f...@samsung.com --- .../devicetree/bindings/arm/samsung/pmu.txt| 30 drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos-clkout.c| 153 + 3 files changed, 184 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos-clkout.c [ ... ] +clkout-clk_table[0] = clk_register_composite(NULL, clkout, +parent_names, parent_count, clkout-mux.hw, +clk_mux_ops, NULL, NULL, clkout-gate.hw, +clk_gate_ops, CLK_SET_RATE_PARENT +| CLK_SET_RATE_NO_REPARENT); Would you please remove CLK_SET_RATE_NO_REPARENT flag from here? Let me know if you have reservations against this. The problem with clock reparenting is that there are certain parent clocks of CLKOUT, rate of which changes at runtime, e.g. clocks derived from APLL or bus clocks, which can be reconfigured by cpufreq or devfreq. +CC: Sylwester Nawrocki Okay. But in cases where there is only 1 valid parent clock provided through DT (at the moment for Exynos5250/Exynos5420), would it be safe to set that clock as the parent of CLKOUT? This is not something to rely on. I have simply omitted remaining CLKOUT parents on Exynos 5 SoCs, as I don't have any board with them on which I could test this. Eventually they will be added. Otherwise, this clock is not usable ATM. On many boards it is already configured properly by the bootloader. Although I don't see any reason why you couldn't reparent it in (board-specific) sound card driver right now. Mark, Is this (clock reparenting in sound card driver) an acceptable solution for you? -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] sound: soc: samsung: dma.c: Fix to remove null pointer checks that could never happen
On 23 May 2014 01:51, Rickard Strandqvist
rickard_strandqv...@spectrumdigital.se wrote:
Removal of null pointer checks that could never happen
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
---
The subject should probably be (at least should start with ASoC: samsung:)
ASoC: samsung: Remove redundant null pointer check from dma.c
With that change,
Reviewed-by: Tushar Behera tushar.beh...@linaro.org
sound/soc/samsung/dma.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index dc09b71..0f17ae0 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -124,8 +124,7 @@ static void audio_buffdone(void *data)
if (prtd-dma_pos = prtd-dma_end)
prtd-dma_pos = prtd-dma_start;
- if (substream)
- snd_pcm_period_elapsed(substream);
+ snd_pcm_period_elapsed(substream);
spin_lock(prtd-lock);
if (!samsung_dma_has_circular()) {
--
1.7.10.4
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Re: [PATCH V2 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode
On 20 May 2014 09:20, Tushar Behera tushar.beh...@linaro.org wrote: From: Sachin Kamat sachin.ka...@linaro.org Almost all Exynos-series of SoCs that run in secure mode don't need additional offset for every CPU, with Exynos4412 being the only exception. Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420). While at it, fix the coding style (space around *). Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Tushar Behera tushar.beh...@linaro.org --- Changes for V2: * Changed the condition statement as per review comment * Fixed coding style arch/arm/mach-exynos/firmware.c |9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) Kukjin, Would you please pick this patch and patch 2/2 for this merge window? [PATCH RESEND 2/2] ARM: dts: Add secure firmware support for Arndale-octa diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..7d18103 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,8 +50,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) - boot_reg += 4*cpu; + /* +* Almost all Exynos-series of SoCs that run in secure mode don't need +* additional offset for every CPU, with Exynos4412 being the only +* exception. +*/ + if (soc_is_exynos4412()) + boot_reg += 4 * cpu; __raw_writel(boot_addr, boot_reg); return 0; -- 1.7.9.5 -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] ARM: EXYNOS: Fix compilation warning
On 05/21/2014 04:56 PM, Sachin Kamat wrote:
On 5 May 2014 14:56, Sachin Kamat sachin.ka...@linaro.org wrote:
of_get_flat_dt_prop return type is now const.
Fixes the following compilation warning introduced by commit 9d0c4dfedd96
(of/fdt: update of_get_flat_dt_prop in prep for libfdt)
arch/arm/mach-exynos/exynos.c:259:6: warning:
assignment discards ‘const’ qualifier from pointer target type [enabled by
default]
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Rob Herring r...@kernel.org
---
Change looks good.
Reviewed-by: Tushar Behera tushar.beh...@linaro.org
Based on linux-next (20140505)
---
arch/arm/mach-exynos/exynos.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 77293d39dfc9..f356c67a1fa9 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -249,7 +249,7 @@ static int __init exynos_fdt_map_chipid(unsigned long
node, const char *uname,
int depth, void *data)
{
struct map_desc iodesc;
- __be32 *reg;
+ const __be32 *reg;
int len;
if (!of_flat_dt_is_compatible(node, samsung,exynos4210-chipid)
--
1.7.9.5
Ping. This warning is still seen in latest linux-next.
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Re: [PATCH 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
On 05/20/2014 10:13 PM, Tomasz Figa wrote:
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/arm/samsung/pmu.txt| 30
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos-clkout.c| 153
+
3 files changed, 184 insertions(+)
create mode 100644 drivers/clk/samsung/clk-exynos-clkout.c
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index b562634..5ed94a9 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -11,8 +11,38 @@ Properties:
- reg : offset and length of the register set.
+ - #clock-cells : must be 1, since PMU requires once cell as clock
specifier.
s/once/one
+ The single specifier cell is used as index to list of clocks
+ provided by PMU, which is currently:
+ 0 : SoC clock output (CLKOUT pin)
Will it make more sense if we add a macro for this clock number that
would be referred in the device tree files?
+Example of clock consumer :
+
+usb3503: usb3503@08 {
+ /* ... */
+ clock-names = refclk;
+ clocks = pmu_system_controller 0;
+ /* ... */
};
--
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Re: [PATCH 4/4] ARM: dts: exynos: Update PMU node with CLKOUT related data
On 05/20/2014 10:13 PM, Tomasz Figa wrote:
[...]
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..b7956cc 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,15 @@
pinctrl2 = pinctrl_2;
};
+ pmu_system_controller: system-controller@1002 {
#clock-cells = 1;
+ clock-names = clkout0, clkout1, clkout2, clkout3,
+ clkout4, clkout8, clkout9;
+ clocks = clock CLK_OUT_DMC, clock CLK_OUT_TOP,
+ clock CLK_OUT_LEFTBUS, clock CLK_OUT_RIGHTBUS,
+ clock CLK_OUT_CPU, clock CLK_XXTI,
+ clock CLK_XUSBXTI;
+ };
+
sysram@0202 {
compatible = mmio-sram;
reg = 0x0202 0x2;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 264a28f..d9651fa 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -139,6 +139,12 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4212-pmu, syscon;
#clock-cells = 1;
+ clock-names = clkout0, clkout1, clkout2, clkout3,
+ clkout4, clkout5, clkout8, clkout9;
+ clocks = clock CLK_OUT_DMC, clock CLK_OUT_TOP,
+ clock CLK_OUT_LEFTBUS, clock CLK_OUT_RIGHTBUS,
+ clock CLK_OUT_CPU, clock CLK_OUT_ISP,
+ clock CLK_XXTI, clock CLK_XUSBXTI;
};
g2d@1080 {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 68a3e6f..cb939ef 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -191,6 +191,9 @@
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ #clock-cells = 0;
#clock-cells = 1;
+ clock-names = clkout16;
+ clocks = clock CLK_FIN_PLL;
};
watchdog@101D {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 8e7e35c..23d0ebb 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -723,6 +723,9 @@
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5420-pmu, syscon;
reg = 0x1004 0x5000;
+ #clock-cells = 0;
#clock-cells = 1;
+ clock-names = clkout16;
+ clocks = clock CLK_FIN_PLL;
};
tmu_cpu0: tmu@1006 {
--
Tushar Behera
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Re: [PATCH 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
On 05/20/2014 10:13 PM, Tomasz Figa wrote: This patch introduces a driver that handles configuration of CLKOUT pin of Exynos SoCs that can be used to output certain clocks from inside of the SoC to a dedicated output pin. Signed-off-by: Tomasz Figa t.f...@samsung.com --- .../devicetree/bindings/arm/samsung/pmu.txt| 30 drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos-clkout.c| 153 + 3 files changed, 184 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos-clkout.c [ ... ] + clkout-clk_table[0] = clk_register_composite(NULL, clkout, + parent_names, parent_count, clkout-mux.hw, + clk_mux_ops, NULL, NULL, clkout-gate.hw, + clk_gate_ops, CLK_SET_RATE_PARENT + | CLK_SET_RATE_NO_REPARENT); Would you please remove CLK_SET_RATE_NO_REPARENT flag from here? Let me know if you have reservations against this. With RFC patches, I am able to do a clk_set_rate() on this clock to get a 24MHz output to the codec clock. With this flag set, I again have to rely on the default value set to this register in bootloader. -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: samsung: Allow setting OP_CLK of the IIS Multi Audio Interface
On 05/20/2014 02:40 PM, Sylwester Nawrocki wrote:
On 20/05/14 07:14, Tushar Behera wrote:
On 05/19/2014 11:00 PM, Sylwester Nawrocki wrote:
This patch adds support for setting source clock of the Core CLK
of the IIS Multi Audio Interface.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
sound/soc/samsung/i2s.c |4
sound/soc/samsung/i2s.h |1 +
2 files changed, 5 insertions(+)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 048ead9..ae02811 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -451,6 +451,10 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
u32 mod = readl(i2s-addr + I2SMOD);
switch (clk_id) {
+ case SAMSUNG_I2S_OPCLK:
+ mod = ~MOD_OPCLK_MASK;
+ mod |= dir;
I am assuming here that dir is one of SND_SOC_CLOCK_IN or
SND_SOC_CLOCK_OUT. In that case, you need to take care of offset (30).
And that's not a correct assumption. I also got similarly confused when
first seeing this in our downstream kernels. 'dir' is supposed to be one
of the MOD_OPCLK_* constants, as defined in sound/soc/samsung/i2s-regs.h.
#define MOD_OPCLK_CDCLK_OUT (0 30)
#define MOD_OPCLK_CDCLK_IN(1 30)
#define MOD_OPCLK_BCLK_OUT(2 30)
#define MOD_OPCLK_PCLK(3 30)
#define MOD_OPCLK_MASK(3 30)
So the clock is reconfigured with calls like:
snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK, 0, MOD_OPCLK_PCLK);
Ok.
Also the value of this bit-field doesn't match with SND_SOC_CLOCK_XXX
macros.
Bit-field (2'b):
00 Codec Clock out
01 Codec Clock in
10 Bit clock out
11 Audio bus clock
Value of macros:
SND_SOC_CLOCK_IN 0
SND_SOC_CLOCK_OUT1
In the manual, this field is suggested to be Audio bus clock always. Is
there an use-case where we might need to update this?
I've checked couple boards and AFAICS we're always setting MOD_OPCLK_PCLK,
however it's still different from the default value after reset -
MOD_OPCLK_CDCLK_OUT.
So how do you think this should be addressed ? Isn't it better to give
options to the machine drivers to alter these clock settings, rather than
hard coding it in the I2S driver ? Let's not forget it covers multiple
Samsung SoC series.
I don't have any objection to this patch. Just that, I could not find
any use-case where we would not like to set the value as MOD_OPCLK_PCLK.
The default value for audio playback right now is 00 (2'b), which needs
to be fixed anyways.
--
Regards,
Sylwester
--
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[PATCH 0/4] ASoC: samsung: Add devres APIs
Adding devres APIs to various files in sound/soc/samsung saves us close to 150 lines of code. The patches are based on next-20140519 and have been build tested. Tushar Behera (4): ASoC: samsung: Use devm_snd_soc_register_card ASoC: samsung: Use devm_snd_soc_register_platform ASoC: samsung: Use devm_snd_soc_register_component ASoC: samsung: Add devm_clk_get to pcm.c sound/soc/samsung/ac97.c |9 ++--- sound/soc/samsung/bells.c | 16 +++- sound/soc/samsung/dma.c|8 +--- sound/soc/samsung/dma.h|1 - sound/soc/samsung/dmaengine.c | 13 - sound/soc/samsung/goni_wm8994.c|9 +++-- sound/soc/samsung/i2s.c|2 -- sound/soc/samsung/idma.c |9 + sound/soc/samsung/littlemill.c | 18 +++--- sound/soc/samsung/lowland.c| 18 +++--- sound/soc/samsung/pcm.c| 17 - sound/soc/samsung/s3c-i2s-v2.c |2 +- sound/soc/samsung/s3c2412-i2s.c| 15 +-- sound/soc/samsung/s3c24xx-i2s.c| 19 +++ sound/soc/samsung/smdk_wm8580pcm.c | 15 +++ sound/soc/samsung/smdk_wm8994pcm.c | 15 +++ sound/soc/samsung/spdif.c | 11 +++ sound/soc/samsung/speyside.c | 18 +++--- sound/soc/samsung/tobermory.c | 18 +++--- 19 files changed, 44 insertions(+), 189 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] ASoC: samsung: Use devm_snd_soc_register_platform
Replaced snd_soc_register_platform with devm_snd_soc_register_platform
in samsung_asoc_dma_platform_register(). This makes the function
samsung_asoc_dma_platform_unregister() redundant. This is removed and
all its users are updated.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/ac97.c|1 -
sound/soc/samsung/dma.c |8 +---
sound/soc/samsung/dma.h |1 -
sound/soc/samsung/dmaengine.c | 13 -
sound/soc/samsung/i2s.c |2 --
sound/soc/samsung/idma.c|9 +
sound/soc/samsung/pcm.c |1 -
sound/soc/samsung/s3c2412-i2s.c |1 -
sound/soc/samsung/s3c24xx-i2s.c |1 -
sound/soc/samsung/spdif.c |1 -
10 files changed, 6 insertions(+), 32 deletions(-)
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index 76b072b..fbce03b 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -461,7 +461,6 @@ static int s3c_ac97_remove(struct platform_device *pdev)
{
struct resource *irq_res;
- samsung_asoc_dma_platform_unregister(pdev-dev);
snd_soc_unregister_component(pdev-dev);
irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index dc09b71..d9dc7bc 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -445,16 +445,10 @@ EXPORT_SYMBOL_GPL(samsung_asoc_init_dma_data);
int samsung_asoc_dma_platform_register(struct device *dev)
{
- return snd_soc_register_platform(dev, samsung_asoc_platform);
+ return devm_snd_soc_register_platform(dev, samsung_asoc_platform);
}
EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_register);
-void samsung_asoc_dma_platform_unregister(struct device *dev)
-{
- snd_soc_unregister_platform(dev);
-}
-EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_unregister);
-
MODULE_AUTHOR(Ben Dooks, b...@simtec.co.uk);
MODULE_DESCRIPTION(Samsung ASoC DMA Driver);
MODULE_LICENSE(GPL);
diff --git a/sound/soc/samsung/dma.h b/sound/soc/samsung/dma.h
index ad7c0f0..070ab0f 100644
--- a/sound/soc/samsung/dma.h
+++ b/sound/soc/samsung/dma.h
@@ -33,6 +33,5 @@ void samsung_asoc_init_dma_data(struct snd_soc_dai *dai,
struct s3c_dma_params *playback,
struct s3c_dma_params *capture);
int samsung_asoc_dma_platform_register(struct device *dev);
-void samsung_asoc_dma_platform_unregister(struct device *dev);
#endif
diff --git a/sound/soc/samsung/dmaengine.c b/sound/soc/samsung/dmaengine.c
index 750ce58..a0e4e79 100644
--- a/sound/soc/samsung/dmaengine.c
+++ b/sound/soc/samsung/dmaengine.c
@@ -66,18 +66,13 @@ EXPORT_SYMBOL_GPL(samsung_asoc_init_dma_data);
int samsung_asoc_dma_platform_register(struct device *dev)
{
- return snd_dmaengine_pcm_register(dev, samsung_dmaengine_pcm_config,
-
SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME |
- SND_DMAENGINE_PCM_FLAG_COMPAT);
+ return devm_snd_dmaengine_pcm_register(dev,
+ samsung_dmaengine_pcm_config,
+ SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME |
+ SND_DMAENGINE_PCM_FLAG_COMPAT);
}
EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_register);
-void samsung_asoc_dma_platform_unregister(struct device *dev)
-{
- return snd_dmaengine_pcm_unregister(dev);
-}
-EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_unregister);
-
MODULE_AUTHOR(Mark Brown broo...@linaro.org);
MODULE_DESCRIPTION(Samsung dmaengine ASoC driver);
MODULE_LICENSE(GPL);
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 6e61db7..f6e2842 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -1291,8 +1291,6 @@ static int samsung_i2s_remove(struct platform_device
*pdev)
i2s-pri_dai = NULL;
i2s-sec_dai = NULL;
- samsung_asoc_dma_platform_unregister(pdev-dev);
-
return 0;
}
diff --git a/sound/soc/samsung/idma.c b/sound/soc/samsung/idma.c
index e9891b4..8cc5770 100644
--- a/sound/soc/samsung/idma.c
+++ b/sound/soc/samsung/idma.c
@@ -413,13 +413,7 @@ static int asoc_idma_platform_probe(struct platform_device
*pdev)
if (idma_irq 0)
return idma_irq;
- return snd_soc_register_platform(pdev-dev, asoc_idma_platform);
-}
-
-static int asoc_idma_platform_remove(struct platform_device *pdev)
-{
- snd_soc_unregister_platform(pdev-dev);
- return 0;
+ return devm_snd_soc_register_platform(pdev-dev, asoc_idma_platform);
}
static struct platform_driver asoc_idma_driver = {
@@ -429,7 +423,6 @@ static struct platform_driver asoc_idma_driver = {
},
.probe = asoc_idma_platform_probe,
- .remove = asoc_idma_platform_remove,
};
module_platform_driver(asoc_idma_driver);
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index ab54e29..38df2a8 100644
[PATCH 4/4] ASoC: samsung: Add devm_clk_get to pcm.c
clk_get in probe function can be safely replaced with devm_clk_get.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/pcm.c |8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index 90fcd52..a3c9c9c 100644
--- a/sound/soc/samsung/pcm.c
+++ b/sound/soc/samsung/pcm.c
@@ -542,7 +542,7 @@ static int s3c_pcm_dev_probe(struct platform_device *pdev)
/* Default is 128fs */
pcm-sclk_per_fs = 128;
- pcm-cclk = clk_get(pdev-dev, audio-bus);
+ pcm-cclk = devm_clk_get(pdev-dev, audio-bus);
if (IS_ERR(pcm-cclk)) {
dev_err(pdev-dev, failed to get audio-bus\n);
ret = PTR_ERR(pcm-cclk);
@@ -567,7 +567,7 @@ static int s3c_pcm_dev_probe(struct platform_device *pdev)
goto err3;
}
- pcm-pclk = clk_get(pdev-dev, pcm);
+ pcm-pclk = devm_clk_get(pdev-dev, pcm);
if (IS_ERR(pcm-pclk)) {
dev_err(pdev-dev, failed to get pcm_clock\n);
ret = -ENOENT;
@@ -605,14 +605,12 @@ static int s3c_pcm_dev_probe(struct platform_device *pdev)
err5:
clk_disable_unprepare(pcm-pclk);
- clk_put(pcm-pclk);
err4:
iounmap(pcm-regs);
err3:
release_mem_region(mem_res-start, resource_size(mem_res));
err2:
clk_disable_unprepare(pcm-cclk);
- clk_put(pcm-cclk);
err1:
return ret;
}
@@ -631,8 +629,6 @@ static int s3c_pcm_dev_remove(struct platform_device *pdev)
clk_disable_unprepare(pcm-cclk);
clk_disable_unprepare(pcm-pclk);
- clk_put(pcm-pclk);
- clk_put(pcm-cclk);
return 0;
}
--
1.7.9.5
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[PATCH 1/4] ASoC: samsung: Use devm_snd_soc_register_card
Replace snd_soc_register_card with devm_snd_soc_register_card.
With this change, we can delete the empty remove functions.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/bells.c | 16 +++-
sound/soc/samsung/littlemill.c | 18 +++---
sound/soc/samsung/lowland.c| 18 +++---
sound/soc/samsung/smdk_wm8580pcm.c | 15 +++
sound/soc/samsung/smdk_wm8994pcm.c | 15 +++
sound/soc/samsung/speyside.c | 18 +++---
sound/soc/samsung/tobermory.c | 18 +++---
7 files changed, 21 insertions(+), 97 deletions(-)
diff --git a/sound/soc/samsung/bells.c b/sound/soc/samsung/bells.c
index 84f5d8b..5b21207 100644
--- a/sound/soc/samsung/bells.c
+++ b/sound/soc/samsung/bells.c
@@ -433,22 +433,13 @@ static int bells_probe(struct platform_device *pdev)
bells_cards[pdev-id].dev = pdev-dev;
- ret = snd_soc_register_card(bells_cards[pdev-id]);
- if (ret) {
+ ret = devm_snd_soc_register_card(pdev-dev, bells_cards[pdev-id]);
+ if (ret)
dev_err(pdev-dev,
snd_soc_register_card(%s) failed: %d\n,
bells_cards[pdev-id].name, ret);
- return ret;
- }
-
- return 0;
-}
-
-static int bells_remove(struct platform_device *pdev)
-{
- snd_soc_unregister_card(bells_cards[pdev-id]);
- return 0;
+ return ret;
}
static struct platform_driver bells_driver = {
@@ -458,7 +449,6 @@ static struct platform_driver bells_driver = {
.pm = snd_soc_pm_ops,
},
.probe = bells_probe,
- .remove = bells_remove,
};
module_platform_driver(bells_driver);
diff --git a/sound/soc/samsung/littlemill.c b/sound/soc/samsung/littlemill.c
index bfb91f3..840787e 100644
--- a/sound/soc/samsung/littlemill.c
+++ b/sound/soc/samsung/littlemill.c
@@ -304,23 +304,12 @@ static int littlemill_probe(struct platform_device *pdev)
card-dev = pdev-dev;
- ret = snd_soc_register_card(card);
- if (ret) {
+ ret = devm_snd_soc_register_card(pdev-dev, card);
+ if (ret)
dev_err(pdev-dev, snd_soc_register_card() failed: %d\n,
ret);
- return ret;
- }
-
- return 0;
-}
-
-static int littlemill_remove(struct platform_device *pdev)
-{
- struct snd_soc_card *card = platform_get_drvdata(pdev);
- snd_soc_unregister_card(card);
-
- return 0;
+ return ret;
}
static struct platform_driver littlemill_driver = {
@@ -330,7 +319,6 @@ static struct platform_driver littlemill_driver = {
.pm = snd_soc_pm_ops,
},
.probe = littlemill_probe,
- .remove = littlemill_remove,
};
module_platform_driver(littlemill_driver);
diff --git a/sound/soc/samsung/lowland.c b/sound/soc/samsung/lowland.c
index 570cf52..bd5f0d6 100644
--- a/sound/soc/samsung/lowland.c
+++ b/sound/soc/samsung/lowland.c
@@ -187,23 +187,12 @@ static int lowland_probe(struct platform_device *pdev)
card-dev = pdev-dev;
- ret = snd_soc_register_card(card);
- if (ret) {
+ ret = devm_snd_soc_register_card(pdev-dev, card);
+ if (ret)
dev_err(pdev-dev, snd_soc_register_card() failed: %d\n,
ret);
- return ret;
- }
-
- return 0;
-}
-
-static int lowland_remove(struct platform_device *pdev)
-{
- struct snd_soc_card *card = platform_get_drvdata(pdev);
- snd_soc_unregister_card(card);
-
- return 0;
+ return ret;
}
static struct platform_driver lowland_driver = {
@@ -213,7 +202,6 @@ static struct platform_driver lowland_driver = {
.pm = snd_soc_pm_ops,
},
.probe = lowland_probe,
- .remove = lowland_remove,
};
module_platform_driver(lowland_driver);
diff --git a/sound/soc/samsung/smdk_wm8580pcm.c
b/sound/soc/samsung/smdk_wm8580pcm.c
index 23a9204..e119aaa 100644
--- a/sound/soc/samsung/smdk_wm8580pcm.c
+++ b/sound/soc/samsung/smdk_wm8580pcm.c
@@ -164,19 +164,11 @@ static int snd_smdk_probe(struct platform_device *pdev)
xtal_freq = mclk_freq = SMDK_WM8580_EXT_VOICE;
smdk_pcm.dev = pdev-dev;
- ret = snd_soc_register_card(smdk_pcm);
- if (ret) {
+ ret = devm_snd_soc_register_card(pdev-dev, smdk_pcm);
+ if (ret)
dev_err(pdev-dev, snd_soc_register_card failed %d\n, ret);
- return ret;
- }
- return 0;
-}
-
-static int snd_smdk_remove(struct platform_device *pdev)
-{
- snd_soc_unregister_card(smdk_pcm);
- return 0;
+ return ret;
}
static struct platform_driver snd_smdk_driver = {
@@ -185,7 +177,6 @@ static struct platform_driver snd_smdk_driver = {
.name = samsung-smdk-pcm,
},
.probe = snd_smdk_probe,
- .remove = snd_smdk_remove
[PATCH 3/4] ASoC: samsung: Use devm_snd_soc_register_component
Replaced snd_soc_register_component with its devres equivalent,
devm_snd_soc_register_component.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/ac97.c|8 ++--
sound/soc/samsung/goni_wm8994.c |9 +++--
sound/soc/samsung/pcm.c |8 ++--
sound/soc/samsung/s3c-i2s-v2.c |2 +-
sound/soc/samsung/s3c2412-i2s.c | 14 +-
sound/soc/samsung/s3c24xx-i2s.c | 18 +++---
sound/soc/samsung/spdif.c | 10 +++---
7 files changed, 15 insertions(+), 54 deletions(-)
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index fbce03b..68d9303 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -433,7 +433,7 @@ static int s3c_ac97_probe(struct platform_device *pdev)
goto err4;
}
- ret = snd_soc_register_component(pdev-dev, s3c_ac97_component,
+ ret = devm_snd_soc_register_component(pdev-dev, s3c_ac97_component,
s3c_ac97_dai,
ARRAY_SIZE(s3c_ac97_dai));
if (ret)
goto err5;
@@ -441,12 +441,10 @@ static int s3c_ac97_probe(struct platform_device *pdev)
ret = samsung_asoc_dma_platform_register(pdev-dev);
if (ret) {
dev_err(pdev-dev, failed to get register DMA: %d\n, ret);
- goto err6;
+ goto err5;
}
return 0;
-err6:
- snd_soc_unregister_component(pdev-dev);
err5:
free_irq(irq_res-start, NULL);
err4:
@@ -461,8 +459,6 @@ static int s3c_ac97_remove(struct platform_device *pdev)
{
struct resource *irq_res;
- snd_soc_unregister_component(pdev-dev);
-
irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (irq_res)
free_irq(irq_res-start, NULL);
diff --git a/sound/soc/samsung/goni_wm8994.c b/sound/soc/samsung/goni_wm8994.c
index 415ad81..9506d76 100644
--- a/sound/soc/samsung/goni_wm8994.c
+++ b/sound/soc/samsung/goni_wm8994.c
@@ -274,8 +274,8 @@ static int __init goni_init(void)
return -ENOMEM;
/* register voice DAI here */
- ret = snd_soc_register_component(goni_snd_device-dev,
voice_component,
-voice_dai, 1);
+ ret = devm_snd_soc_register_component(goni_snd_device-dev,
+ voice_component, voice_dai, 1);
if (ret) {
platform_device_put(goni_snd_device);
return ret;
@@ -284,17 +284,14 @@ static int __init goni_init(void)
platform_set_drvdata(goni_snd_device, goni);
ret = platform_device_add(goni_snd_device);
- if (ret) {
- snd_soc_unregister_component(goni_snd_device-dev);
+ if (ret)
platform_device_put(goni_snd_device);
- }
return ret;
}
static void __exit goni_exit(void)
{
- snd_soc_unregister_component(goni_snd_device-dev);
platform_device_unregister(goni_snd_device);
}
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index 38df2a8..90fcd52 100644
--- a/sound/soc/samsung/pcm.c
+++ b/sound/soc/samsung/pcm.c
@@ -588,7 +588,7 @@ static int s3c_pcm_dev_probe(struct platform_device *pdev)
pm_runtime_enable(pdev-dev);
- ret = snd_soc_register_component(pdev-dev, s3c_pcm_component,
+ ret = devm_snd_soc_register_component(pdev-dev, s3c_pcm_component,
s3c_pcm_dai[pdev-id], 1);
if (ret != 0) {
dev_err(pdev-dev, failed to get register DAI: %d\n, ret);
@@ -598,13 +598,11 @@ static int s3c_pcm_dev_probe(struct platform_device *pdev)
ret = samsung_asoc_dma_platform_register(pdev-dev);
if (ret) {
dev_err(pdev-dev, failed to get register DMA: %d\n, ret);
- goto err6;
+ goto err5;
}
return 0;
-err6:
- snd_soc_unregister_component(pdev-dev);
err5:
clk_disable_unprepare(pcm-pclk);
clk_put(pcm-pclk);
@@ -624,8 +622,6 @@ static int s3c_pcm_dev_remove(struct platform_device *pdev)
struct s3c_pcm_info *pcm = s3c_pcm[pdev-id];
struct resource *mem_res;
- snd_soc_unregister_component(pdev-dev);
-
pm_runtime_disable(pdev-dev);
iounmap(pcm-regs);
diff --git a/sound/soc/samsung/s3c-i2s-v2.c b/sound/soc/samsung/s3c-i2s-v2.c
index 79e7efb..77a2ae5 100644
--- a/sound/soc/samsung/s3c-i2s-v2.c
+++ b/sound/soc/samsung/s3c-i2s-v2.c
@@ -745,7 +745,7 @@ int s3c_i2sv2_register_component(struct device *dev, int id,
dai_drv-suspend = s3c2412_i2s_suspend;
dai_drv-resume = s3c2412_i2s_resume;
- return snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
+ return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);
diff --git a/sound/soc/samsung/s3c2412-i2s.c b/sound/soc/samsung/s3c2412-i2s.c
index f42da8d..843f315
Re: [PATCH] ASoC: samsung: Add 'mclk' handling for Snow sound-card driver
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 05/20/2014 04:46 PM, Mark Brown wrote: On Tue, May 20, 2014 at 09:55:42AM +0530, Tushar Behera wrote: For audio to work on Snow board, we need the codec master clock 'mclk' to be properly configured. Currently XCLKOUT is configured as 'mclk' for codec chip and it is required to be clocked at 24MHz for the codec to work properly. Add appropriate clock handling within Snow sound-card driver to set 'mclk' to operate at 24MHz. The clock here is connected to the CODEC on the board so it should be connected to the CODEC in the device tree too. Ok. I will move 'mclk' clock handling to respective CODEC drivers. - -- Tushar Behera -BEGIN PGP SIGNATURE- Version: GnuPG v1 Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTfDxtAAoJELqclMPPkq4NkPcH/2fOwVTGgmGFarm2RSoxJcON QcSQlNpVXEpAqslVdz+ay7VkYCWy+wiuTq4Fe/Yw5RK/Pl7DdkEX/Ltj7/Q6+CbT 38r6o5PSbZLlPcBxVjGXBiOTpK7PZLumF8c1DK4/6HzsHYDzLGTvbWVi6cy9kZzj X3glD3PBiK/NL12IuOHsRg2wzBRE56RQCmfT2kPueWHEklebGzr/qv5UgdGWa+jb JRVDt11klGfvIFj+Ov28yave1epzFEzrNm4ixso8MJN7J9HxlufagTheS0HkDpuX +uY8PbRFTAdT7pjvZR4n2lPws940nk7aUqyVPTQaG9JVKk7R4FVZgBwmhMeIsMU= =eKSS -END PGP SIGNATURE- -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
On 05/15/2014 11:02 PM, Tomasz Figa wrote:
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Tested the series on Exynos5420-based peach-pit board for audio playback
(with an internal patch to set CLK_FIN_PLL as the parent of clkout).
Tested-by: Tushar Behera tushar.beh...@linaro.org
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ #clock-cells = 0;
+ clock-names = clkout0, clkout1, clkout2, clkout3,
+ clkout4, clkout8, clkout9;
+ clocks = clock CLK_OUT_DMC, clock CLK_OUT_TOP,
+ clock CLK_OUT_LEFTBUS, clock CLK_OUT_RIGHTBUS,
+ clock CLK_OUT_CPU, clock CLK_XXTI,
+ clock CLK_XUSBXTI;
};
Adding an usage example in the documentation would be helpful.
--
Tushar Behera
--
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[PATCH 1/2] ARM: EXYNOS: Add secure firmware support for Exynos5420
From: Sachin Kamat sachin.ka...@linaro.org Updated secondary boot register offset for Exynos5420 in case of secure booting. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Tushar Behera tushar.beh...@linaro.org --- The patches are based on top of next-20140519. With these two patches applied, we can get all A15 cores booting up on Arndale-Octa board. arch/arm/mach-exynos/firmware.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..5e0902e 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5420()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: Add secure firmware support for Arndale-octa
Arndale-Octa board is always configured to work with trustzone
firmware binary. Added DTS node entry to enable this support.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 896a2a6..253d101 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -26,6 +26,11 @@
bootargs = console=ttySAC3,115200;
};
+ firmware@02073000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x02073000 0x1000;
+ };
+
fixed-rate-clocks {
oscclk {
compatible = samsung,exynos5420-oscclk;
--
1.7.9.5
--
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Re: [PATCH V2] ASoC: SAMSUNG: Add sound card driver for Snow board
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 05/02/2014 10:26 PM, Mark Brown wrote: On Fri, May 02, 2014 at 10:26:08AM +0530, Tushar Behera wrote: On 05/01/2014 10:10 PM, Mark Brown wrote: There's patches been posted by (IIRC) Sylvester Nawrocki for this which I think Mike was basically happy with - I don't immediately see them in -next though, but I may be looking in the wrong place. Right, there are some patches from Sylwester regarding this. I dont' think the patches are accepted yet as Rob has some reservations against the clock parents. https://lkml.org/lkml/2014/4/9/173 Well, OK - that's the bit to fix. Speaking to Mike the other day he said there was also another competing implementation of this. Instead of setting the parent clock, setting the desired rate on XCLKOUT works for audio playback. Will it be okay to do a 'clk_set_rate(mclk, 2400)' in sound card driver or should we wait for Sylwester's patch to get merged? - -- Tushar Behera -BEGIN PGP SIGNATURE- Version: GnuPG v1 Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTefPOAAoJELqclMPPkq4N6UIH/i5W7KYjyKTQtX+AGdUmJwIx 3TTwyWVz5YQ6gFpLHwwy5AwIkj4mygox2e7l0qWU6yOXCMceaXrvzxOK+B/LRXlp +s8xjd+C+Idxhs0T6V4GkJRA9jtari3gcIGfz4tFtWY5O0l0eNTUduILhAvmE/Sw c4m8aOwK33P0kvkTIp/ShSujYa8v82XosMRuf4P0iEz9I3qw3syJkWWvqNZFrnPs B7i+9ZiZkyttsUVBOAWMBfOdLP5sMtxKDdk1GTkN1plxAE8lKdNVATR5htQL4bxo ZFcWJxE14pWQ770gEJVXkDT9o8dhmVNrDVp4eGe3m+43gN+Bssh+9kgdxb3vmIY= =gXaJ -END PGP SIGNATURE- -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: EXYNOS: Add secure firmware support for Exynos5420
On 05/19/2014 05:02 PM, Tomasz Figa wrote: Hi Tushar, Sachin, On 19.05.2014 13:09, Tushar Behera wrote: From: Sachin Kamat sachin.ka...@linaro.org Updated secondary boot register offset for Exynos5420 in case of secure booting. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Tushar Behera tushar.beh...@linaro.org --- The patches are based on top of next-20140519. With these two patches applied, we can get all A15 cores booting up on Arndale-Octa board. arch/arm/mach-exynos/firmware.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..5e0902e 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; -if (!soc_is_exynos4212()) +if (!soc_is_exynos4212() !soc_is_exynos5420()) boot_reg += 4*cpu; I think it is safe to change this simply to if (soc_is_exynos4412()), since this seems to be the only SoC on which the firmware requires this offset. Best regards, Tomasz Fair enough. Even Exynos3250 doesn't require this. I will resend this patch. -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode
From: Sachin Kamat sachin.ka...@linaro.org Almost all Exynos-series of SoCs that run in secure mode don't need additional offset for every CPU, with Exynos4412 being the only exception. Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420). While at it, fix the coding style (space around *). Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Tushar Behera tushar.beh...@linaro.org --- Changes for V2: * Changed the condition statement as per review comment * Fixed coding style arch/arm/mach-exynos/firmware.c |9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..7d18103 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,8 +50,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) - boot_reg += 4*cpu; + /* +* Almost all Exynos-series of SoCs that run in secure mode don't need +* additional offset for every CPU, with Exynos4412 being the only +* exception. +*/ + if (soc_is_exynos4412()) + boot_reg += 4 * cpu; __raw_writel(boot_addr, boot_reg); return 0; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND 2/2] ARM: dts: Add secure firmware support for Arndale-octa
Arndale-Octa board is always configured to work with trustzone
firmware binary. Added DTS node entry to enable this support.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 896a2a6..253d101 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -26,6 +26,11 @@
bootargs = console=ttySAC3,115200;
};
+ firmware@02073000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x02073000 0x1000;
+ };
+
fixed-rate-clocks {
oscclk {
compatible = samsung,exynos5420-oscclk;
--
1.7.9.5
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[PATCH] ASoC: samsung: Add 'mclk' handling for Snow sound-card driver
For audio to work on Snow board, we need the codec master clock 'mclk'
to be properly configured.
Currently XCLKOUT is configured as 'mclk' for codec chip and it is
required to be clocked at 24MHz for the codec to work properly.
Add appropriate clock handling within Snow sound-card driver to set
'mclk' to operate at 24MHz.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
Documentation/devicetree/bindings/sound/snow.txt |7 ++
sound/soc/samsung/snow.c | 26 +-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/snow.txt
b/Documentation/devicetree/bindings/sound/snow.txt
index 678b191..94dd29c 100644
--- a/Documentation/devicetree/bindings/sound/snow.txt
+++ b/Documentation/devicetree/bindings/sound/snow.txt
@@ -7,6 +7,10 @@ Required properties:
- samsung,i2s-controller: The phandle of the Samsung I2S controller
- samsung,audio-codec: The phandle of the audio codec
+Optional properties:
+- clocks: The phandle of the master clock to audio codec
+- clock-names: Should be mclk
+
Example:
sound {
@@ -14,4 +18,7 @@ sound {
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98095;
+
+ clocks = pmu_system_controller;
+ clock-names = mclk;
};
diff --git a/sound/soc/samsung/snow.c b/sound/soc/samsung/snow.c
index 014c177..c910739 100644
--- a/sound/soc/samsung/snow.c
+++ b/sound/soc/samsung/snow.c
@@ -15,13 +15,18 @@
#include linux/platform_device.h
#include linux/of.h
#include linux/of_device.h
+#include linux/clk.h
#include sound/soc.h
#include i2s.h
+/* Desired clock rate for codec mclk */
#define FIN_PLL_RATE 2400
+static struct clk *mclk;
+static unsigned long mclk_rate;
+
static struct snd_soc_dai_link snow_dai[] = {
{
.name = Primary,
@@ -41,7 +46,7 @@ static int snow_late_probe(struct snd_soc_card *card)
/* Set the MCLK rate for the codec */
ret = snd_soc_dai_set_sysclk(codec_dai, 0,
- FIN_PLL_RATE, SND_SOC_CLOCK_IN);
+ mclk_rate, SND_SOC_CLOCK_IN);
if (ret 0)
return ret;
@@ -68,6 +73,16 @@ static int snow_probe(struct platform_device *pdev)
struct device_node *i2s_node, *codec_node;
int i, ret;
+ /* The codec MCLK should be clocked at 24MHz */
+ mclk = devm_clk_get(pdev-dev, mclk);
+ if (!IS_ERR(mclk)) {
+ clk_prepare_enable(mclk);
+ clk_set_rate(mclk, FIN_PLL_RATE);
+ mclk_rate = clk_get_rate(mclk);
+ } else {
+ mclk_rate = FIN_PLL_RATE;
+ }
+
i2s_node = of_parse_phandle(pdev-dev.of_node,
samsung,i2s-controller, 0);
if (!i2s_node) {
@@ -101,6 +116,14 @@ static int snow_probe(struct platform_device *pdev)
return ret;
}
+static int snow_remove(struct platform_device *pdev)
+{
+ if (!IS_ERR(mclk))
+ clk_disable_unprepare(mclk);
+
+ return 0;
+}
+
static const struct of_device_id snow_of_match[] = {
{ .compatible = google,snow-audio-max98090, },
{ .compatible = google,snow-audio-max98095, },
@@ -115,6 +138,7 @@ static struct platform_driver snow_driver = {
.of_match_table = snow_of_match,
},
.probe = snow_probe,
+ .remove = snow_remove,
};
module_platform_driver(snow_driver);
--
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[PATCH] ARM: dts: Add mclk entry for Snow/Peach-pit boards
On Snow/Peach-pit boards, XCLKOUT provides master clock (mclk) to codec.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
Dependency:
1. Driver side changes have been posted here.
https://lkml.org/lkml/2014/5/20/4
2. XCLKOUT clock driver support
https://lkml.org/lkml/2014/5/15/530
arch/arm/boot/dts/exynos5250-snow.dts |3 +++
arch/arm/boot/dts/exynos5420-peach-pit.dts |3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index 67391b9..1014ce0 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -346,6 +346,9 @@
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98095;
+
+ clocks = pmu_system_controller;
+ clock-names = mclk;
};
usb@1211 {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index f4b2a16..c0664e9 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -64,6 +64,9 @@
samsung,i2s-controller = i2s0;
samsung,audio-codec = max98090;
+
+ clocks = pmu_system_controller;
+ clock-names = mclk;
};
};
--
1.7.9.5
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Re: [PATCH] ASoC: samsung: Allow setting OP_CLK of the IIS Multi Audio Interface
On 05/19/2014 11:00 PM, Sylwester Nawrocki wrote:
This patch adds support for setting source clock of the Core CLK
of the IIS Multi Audio Interface.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
sound/soc/samsung/i2s.c |4
sound/soc/samsung/i2s.h |1 +
2 files changed, 5 insertions(+)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 048ead9..ae02811 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -451,6 +451,10 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
u32 mod = readl(i2s-addr + I2SMOD);
switch (clk_id) {
+ case SAMSUNG_I2S_OPCLK:
+ mod = ~MOD_OPCLK_MASK;
+ mod |= dir;
I am assuming here that dir is one of SND_SOC_CLOCK_IN or
SND_SOC_CLOCK_OUT. In that case, you need to take care of offset (30).
Also the value of this bit-field doesn't match with SND_SOC_CLOCK_XXX
macros.
Bit-field (2'b):
00 Codec Clock out
01 Codec Clock in
10 Bit clock out
11 Audio bus clock
Value of macros:
SND_SOC_CLOCK_IN0
SND_SOC_CLOCK_OUT 1
In the manual, this field is suggested to be Audio bus clock always. Is
there an use-case where we might need to update this?
The default value for audio playback right now is 00 (2'b), which needs
to be fixed anyways.
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Re: [PATCH] sound: soc: samsung: dma.c: Fix for possible null pointer dereference
On 05/20/2014 03:07 AM, Rickard Strandqvist wrote:
There is otherwise a risk of a possible null pointer dereference.
Was largely found by using a static code analysis program called cppcheck.
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
---
sound/soc/samsung/dma.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index dc09b71..1d9bcaa 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -115,17 +115,19 @@ static void dma_enqueue(struct snd_pcm_substream
*substream)
static void audio_buffdone(void *data)
{
struct snd_pcm_substream *substream = data;
- struct runtime_data *prtd = substream-runtime-private_data;
+ struct runtime_data *prtd = NULL;
I am not sure if this check is required as audio_buffdone() is set as a
callback function with known valid parameter during dma_enqueue().
pr_debug(Entered %s\n, __func__);
- if (prtd-state ST_RUNNING) {
+ if (substream)
+ prtd = substream-runtime-private_data;
+
+ if (prtd prtd-state ST_RUNNING) {
ditto as above
prtd-dma_pos += prtd-dma_period;
if (prtd-dma_pos = prtd-dma_end)
prtd-dma_pos = prtd-dma_start;
- if (substream)
- snd_pcm_period_elapsed(substream);
+ snd_pcm_period_elapsed(substream);
This check certainly can be removed as snd_pcm_period_elapsed() also
checks the validity of the argument.
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Re: [PATCH 1/4] clk: samsung: out: Add infrastructure to register CLKOUT
On 15 May 2014 19:37, Tomasz Figa t.f...@samsung.com wrote: Hi Rahul, Tushar, On 15.05.2014 15:44, Rahul Sharma wrote: Hi Tushar, Basically you are adding a new clock-type for Clkout. IMO clkout is not a special hardware. Existing clock types can be reused to support clkout. I see 3 major problem here: 1) Clkout - (Mux + Gate). You clubbed mux and gate together, and exposing as a single clock which is something like a composite clock. IMO this is not a recommended way in CCF. 2) New Clock Type: Since clkout is just a combination of a simple mux and gate which are already supported, it is a unnecessary duplication. 3) Clkout registered along with CMU: which is not correct. Clkout is in PMU (Separate physical IP) and should be registered as a independent Clock provider which provides 1 mux and 1 gate clock (As if now). It should also be well connected with main CMU. I understand the challenge in using regmap interface for a clock provider. But we need to identify a clean solution. IMHO a independent clock provider with iomap, is relatively cleaner approach till CCF is not ready with regmap based reg access for clock registers. Experts!! please comment. It's quite unfortunate that Tushar has duplicated the effort to create a clkout driver, considering the fact that we did have such driver internally at SRPOL and it was quite nice and simple. I had no idea that you had some solutions to this available to be posted :( Now that the new series is posted, I will test that at my end and update you later. I will post a cleaned-up version today, that is about 2 times smaller in terms of lines of added code and provides the same functionality, without introducing custom clock types. In addition, it models the clkout properly as a feature of PMU, not CMU (CMU only provides outputs of particular sub-blocks that are fed into the PMU). Best regards, Tomasz -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
On 05/13/2014 03:37 PM, Paul Bolle wrote: Kukjin, On Tue, 2014-05-13 at 12:12 +0900, Kukjin Kim wrote: Tomasz Figa wrote: You mean s/sram/sysram/ in compatible strings of Exynos-specific reserved areas? If yes, I'm fine, it might be even better. Just remember to update documentation in patch 2/2 as well. Done. If any problems in my tree, please let me know. It seems this one just hit linux-next (in next-20140513) as ARM: EXYNOS: Map SYSRAM through generic DT bindings. Its commit now contains this hunk: --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -843,6 +843,7 @@ config ARCH_EXYNOS select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_MEMORY_H select SPARSE_IRQ + select SYSRAM select USE_OF help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) But there's no Kconfig symbol SYSRAM. However, there is a Kconfig symbol SRAM. Did you perhaps do one s/sram/sysram/ too many on the original patch? Also the compatible string name should be 'mmio-sram' on the DTS files. Paul Bolle -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: samsung: Add missing pm ops for Snow sound card driver
Adding missing pm ops so that audio playback works across
suspend and resume cycle.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/snow.c |1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/samsung/snow.c b/sound/soc/samsung/snow.c
index 0fa89a4..014c177 100644
--- a/sound/soc/samsung/snow.c
+++ b/sound/soc/samsung/snow.c
@@ -111,6 +111,7 @@ static struct platform_driver snow_driver = {
.driver = {
.name = snow-audio,
.owner = THIS_MODULE,
+ .pm = snd_soc_pm_ops,
.of_match_table = snow_of_match,
},
.probe = snow_probe,
--
1.7.9.5
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Re: [PATCH 0/4] Add framework to support clkout
On 05/10/2014 09:09 AM, Pankaj Dubey wrote:
Hi Tushar,
[ ... ]
Also we need to find a suitable place to call early_syscon_init(), after
the device tree has been unflattened and before clock initialization.
While testing, I called this before of_clk_init() in
arch/arm/kernel/time.c,
but that place is too generic. Calling anywhere from exynos.c is not
working ATM.
IMO we do not need to, or if I am not wrong we should not change time.c.
The above solution is definitely a hack and just to test my stuff. The
below solution looks good.
It's possible if we have exynos specific init_time with following changes.
FYI, In my patch series for Exynos PMU [1], currently I am handling this in
exynos_dt_machine_init. But definitely it can be handled as below and it
works
without any side effect and I have tested it. Only reason I do not
adopted this
as for Exynos PMU patch support I had other options. But if required and if
following change is acceptable I can include this in my next version of
Exynos
PMU patch series.
[1]: https://lkml.org/lkml/2014/4/30/18
+static void __init exynos_init_time(void)
+{
+/* Nothing to do timer specific
+ * as early_syscon_init requires DT to be unflattened and
+ * system should be able to allocate memory we need to
+ * postpone until init_time, but it should be done before
+ * init_machine. Because before init_machine, secondary
+ * core boot starts and it uses PMU registers.
+ */
+
+exynos_map_pmu();
+
Instead of calling early_syscon_init() from within exynos_map_pmu(), it
would be good to call it explicitly here before exynos_map_pmu().
+of_clk_init(NULL);
+clocksource_of_init();
+
+}
+
--
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Re: [PATCH 1/4] clk: samsung: out: Add infrastructure to register CLKOUT
On 05/10/2014 09:21 AM, Pankaj Dubey wrote:
On 05/09/2014 10:00 PM, Tushar Behera wrote:
All SoC in Exynos-series have a clock with name XCLKOUT to provide
debug information about various clocks available in the SoC. The register
controlling the MUX and GATE of this clock is provided within PMU domain.
Since PMU domain can't be dedicatedly mapped by every driver, the
register
needs to be handled through a regmap handle provided by PMU syscon
controller. Right now, CCF doesn't allow regmap based MUX and GATE
clocks,
hence a dedicated clock provider for XCLKOUT is added here.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
CC: Tomasz Figa t.f...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-out.c | 181
+
drivers/clk/samsung/clk.h | 33
3 files changed, 215 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-out.c
[ ... ]
+/**
+ * struct samsung_clkout_soc_data: SoC specific register details
+ * @reg: Offset of CLKOUT register from PMU base
how about naming this variable as offset instead of reg.
Okay, I will change that.
[ ... ]
+u8 samsung_clkout_get_parent(struct clk_hw *hw)
+{
+struct samsung_clkout *clkout = to_clk_out(hw);
+const struct samsung_clkout_soc_data *soc_data = clkout-soc_data;
+unsigned int parent_mask = BIT(soc_data-mux_width) - 1;
+unsigned int val;
+int ret;
+
+ret = regmap_read(clkout-regmap, soc_data-reg, val);
Do we really need to keep return value in ret as I can't see you are
using it anywhere?
Right, we are not using that and can be removed.
+
+return (val soc_data-mux_shift) parent_mask;
+}
+
[ ... ]
+/* All existing Exynos serial of SoCs have common values for this
offsets. */
typo: serial/series/
Sure. Thanks for your review.
--
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Re: [PATCH] thermal: samsung: Only update available threshold limits
On 04/24/2014 11:48 AM, Amit Kachhap wrote:
On 4/14/14, Tushar Behera tushar.beh...@linaro.org wrote:
Currently the threshold limits are updated in 2 stages, once for all
software trigger levels and again for hardware trip point.
I guess the first stage is bootloader as could not find this in this file.
Anyways the changes looks fine to me.
Acked-by: Amit Daniel Kachhap amit.dan...@samsung.com
Can this the patch be merged now?
While updating the software trigger levels, it overwrites the threshold
limit for hardware trip point thereby forcing the Exynos core to issue
an emergency shutdown.
Updating only the required fields in threshold register fixes this issue.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
Based on v3.15-rc1.
drivers/thermal/samsung/exynos_tmu.c |4
1 file changed, 4 insertions(+)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index 0d96a51..ffccc89 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -225,6 +225,8 @@ skip_calib_data:
trigger_levs++;
}
+rising_threshold = readl(data-base + reg-threshold_th0);
+
if (data-soc == SOC_ARCH_EXYNOS4210) {
/* Write temperature code for threshold */
threshold_code = temp_to_code(data, pdata-threshold);
@@ -249,6 +251,7 @@ skip_calib_data:
ret = threshold_code;
goto out;
}
+rising_threshold = ~(0xff 8 * i);
rising_threshold |= threshold_code 8 * i;
if (pdata-threshold_falling) {
threshold_code = temp_to_code(data,
@@ -281,6 +284,7 @@ skip_calib_data:
}
if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
/* 1-4 level to be assigned in th0 reg */
+rising_threshold = ~(0xff 8 * i);
rising_threshold |= threshold_code 8 * i;
writel(rising_threshold,
data-base + reg-threshold_th0);
--
1.7.9.5
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[PATCH 3/4] clk: samsung: exynos5250: Add xclkout debug clock
A new clock provider has been added to configure the XCLKOUT debug
clock. Added a minimal implemetation for Exynos5420 clock driver.
Right now, only one valid parent clock from XCLKOUT is defined
in existing clock driver. The driver will be updated later for other
for other parent clocks.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
CC: Tomasz Figa t.f...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c | 14 ++
include/dt-bindings/clock/exynos5250.h |3 +++
2 files changed, 17 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index e7ee442..2637aea 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -225,6 +225,13 @@ PNAME(mout_audio2_p) = { cdclk2, fin_pll,
sclk_hdmi27m, sclk_dptxphy,
PNAME(mout_spdif_p)= { sclk_audio0, sclk_audio1, sclk_audio2,
spdif_extclk };
+PNAME(xclkout_p) = {
+ dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy,
+ fin_pll, dummy, dummy };
+
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[]
__initdata = {
FRATE(CLK_FIN_PLL, fin_pll, NULL, CLK_IS_ROOT, 0),
@@ -236,6 +243,7 @@ static struct samsung_fixed_rate_clock
exynos5250_fixed_rate_clks[] __initdata =
FRATE(0, sclk_hdmi27m, NULL, CLK_IS_ROOT, 2700),
FRATE(0, sclk_dptxphy, NULL, CLK_IS_ROOT, 2400),
FRATE(0, sclk_uhostphy, NULL, CLK_IS_ROOT, 4800),
+ FRATE(0, dummy, NULL, CLK_IS_ROOT, 0),
};
static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[]
__initdata = {
@@ -678,6 +686,10 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static struct samsung_out_clock exynos5250_clkout[] __initdata = {
+ CLKOUT(CLK_XCLKOUT, xclkout, xclkout_p),
+};
+
static struct of_device_id ext_clk_match[] __initdata = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
@@ -721,6 +733,8 @@ static void __init exynos5250_clk_init(struct device_node
*np)
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks));
+ samsung_clk_register_clkout(np,
+ exynos5250_clkout, ARRAY_SIZE(exynos5250_clkout));
exynos5250_clk_sleep_init();
diff --git a/include/dt-bindings/clock/exynos5250.h
b/include/dt-bindings/clock/exynos5250.h
index 922f2dc..7c1cd0b 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -151,6 +151,9 @@
#define CLK_MDMA0 346
#define CLK_SMMU_MDMA0 347
+/* debug clocks */
+#define CLK_XCLKOUT896
+
/* mux clocks */
#define CLK_MOUT_HDMI 1024
--
1.7.9.5
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