Re: [PATCH] ARM: EXYNOS: reset KFC cores when cpu is up
Hi,
On Tue, Sep 1, 2015 at 5:51 AM, Krzysztof Kozlowski
<k.kozlow...@samsung.com> wrote:
> On 01.09.2015 07:46, Javier Martinez Canillas wrote:
>>
>> [adding Krzysztof Kozlowski to cc list]
>>
>> Hello Kevin,
>>
>> On 09/01/2015 12:11 AM, Kevin Hilman wrote:
>>> Chanho Park <parkc...@gmail.com> writes:
>>>
>>>> The cpu booting of exynos5422 has been still broken since we discussed
>>>> it in last year[1]. This patch is inspired from odroid xu3
>>>> code(Actually, it was from samsung exynos vendor kernel)[2]. This weird
>>>> reset code was founded exynos5420 octa cores series SoCs and only
>>>> required for the first boot core is the little core(kingfisher core).
>>>> Some of the exynos5420 boards and all of the exynos5422 boards will be
>>>> required this code.
>>>> There is two ways to check the little core is the first cpu. One is
>>>> checking GPG2CON[1] gpio value and the other is checking the cluster
>>>> number of the first cpu. I selected the latter because it's more easier
>>>> than the former.
>>>>
>>>> Changes since RFC[3]:
>>>> - drop checking soc_is_exynos5800 to extend this codes to
>>>> exynos5420/5422 boards.
>>>> - kfc cores will be reset only if the cpu0 is kfc core.
>>>> - Rebase top of the kukjin's for-next branch
>>>>
>>>> [1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html
>>>> [2]:https://patchwork.kernel.org/patch/6782891/
>>>> [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
>>>>
>>>> Cc: Joonyoung Shim <jy0922.s...@samsung.com>
>>>> Cc: Chanwoo Choi <cw00.c...@samsung.com>
>>>> Cc: Kevin Hilman <khil...@kernel.org>
>>>> Cc: Heesub Shin <heesub.s...@samsung.com>
>>>> Cc: Mauro Ribeiro <mauro.ribe...@hardkernel.com>
>>>> Cc: Abhilash Kesavan <a.kesa...@samsung.com>
>>>> Cc: Przemyslaw Marczak <p.marc...@samsung.com>
>>>> Cc: Marek Szyprowski <m.szyprow...@samsung.com>
>>>> Cc: Krzysztof Kozlowski <k.kozlow...@samsung.com>
>>>> Signed-off-by: Chanho Park <parkc...@gmail.com>
>>>
>>>> ---
>>>> arch/arm/mach-exynos/mcpm-exynos.c | 18 +-
>>>> arch/arm/mach-exynos/regs-pmu.h| 6 ++
>>>> 2 files changed, 23 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
>>>> b/arch/arm/mach-exynos/mcpm-exynos.c
>>>> index 9bdf547..5b69ed2 100644
>>>> --- a/arch/arm/mach-exynos/mcpm-exynos.c
>>>> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
>>>> @@ -20,6 +20,7 @@
>>>> #include
>>>> #include
>>>> #include
>>>> +#include
>>>>
>>>> #include "regs-pmu.h"
>>>> #include "common.h"
>>>> @@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu,
>>>> unsigned int cluster)
>>>> cluster >= EXYNOS5420_NR_CLUSTERS)
>>>> return -EINVAL;
>>>>
>>>> - exynos_cpu_power_up(cpunr);
>>>> + if (!exynos_cpu_power_state(cpunr)) {
>>>> + exynos_cpu_power_up(cpunr);
>>>> +
>>>> + /* This assumes the cluster number of the eagle is 0 and the
>>>> +* kfc is 1. When the system was booted from the kfc core,
>>>> +* they should be reset */
>>>
>>> minor: fix multi-line comment style (search for 'multi-line' in
>>> Documentation/CodingStyle)
>>>
>>> Also minor, but personally, I prefer seeing A15/A7 instead of eagle/KFC
>>> as those names are fading from my memory and I can't seem to remember
>>> which one is which. :/
>>>
>>>> + if (cluster &&
>>>> + cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
>>>> + while (!pmu_raw_readl(S5P_PMU_SPARE2))
>>>> + udelay(10);
>>>> +
>>>> + pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
>>>> + EXYNOS_SWRESET);
>>>> + }
>>>> + }
>>>> +
>>>> return 0;
>>>> }
>>>
>>> I tested this on top of mainline (v4.2) using exynos_defco
Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend
Hi Javier,
On Tue, Apr 7, 2015 at 7:41 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Tomasz,
On 04/07/2015 02:46 PM, Tomasz Figa wrote:
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
So I disabled the sss clock before trying a S2R:
# devmem 0x10018800 32 0xFFFB
(CLK_SSS in CLK_GATE_IP_G2D is gated)
and S2R worked anyways but I see that CLK_GATE_IP_G2D is reset to
its default value on S2R so maybe that is why it works anyways?
Does the driver restore its value on resume (i.e. has it in the
save/restore array)? Remember that suspend causes all clock registers
to be reset. Then some of them will be configured by the lowest
No, GATE_IP_G2D is not in the exynos5x_gate_clks array so it looses
the kernel after a suspend/resume cycle.
bootloader stage after wake-up reset, but the kernel needs to restore
all of them.
I see, thanks for the clarification. Then I think that is a bug and
GATE_IP_G2D needs to be added to the list of clocks to be saved and
restored right? That's a separate issue from our current S2R problem
though so it can be done later as a separate patch.
# devmem 0x10018800
0x (all CLK_GATE_IP_G2D clocks enabled including CLK_SSS)
Does this shed any more light? Could the problem be that the sss
clock parent (aclk266_g2d) is gated during S2R? Is the SSS module
required for S2R or is just that CLK_SSS prevents the parent to
be gated and so it is another red herring?
Does the board use secure firmware? If yes, it might require to do
some encryption on suspend, so if the firmware is broken and doesn't
control the clock itself, it might need the SSS clock to be running,
when the SLEEP SMC operation is called.
No, the Chromebooks don't use secure firmware AFAIK.
Anyway, I just realized that Exynos4 also need several clocks to be
ungated on suspend and this is handled by code [1] based on arrays
[2].
[1]
http://lxr.free-electrons.com/source/drivers/clk/samsung/clk-exynos4.c#L309
[2]
http://lxr.free-electrons.com/source/drivers/clk/samsung/clk-exynos4.c#L276
Yes I noticed that the Exynos5420 driver also does the same but did not
want to do it there because I didn't know what value should had been used
for all the other clocks in the CLK_GATE_BUS_TOP register. But if I get
your explanation right, it is safe to do so since the register is going to
be reset to its default values anyways.
Could this method work for your case as well? There would be no need
to call any clock API at all, just low level register writes, which is
okay, since this is a low level driver anyway.
Yes, the following patch [0] is enough to make S2R working. If you think
that is correct then I'll post it as a proper patch then.
Best regards,
Tomasz
Best regards,
Javier
[0]
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas javier.marti...@collabora.co.uk
Date: Tue, 7 Apr 2015 15:53:27 +0200
Subject: [RFC PATCH] clk: exynos5420: Restore GATE_BUS_TOP on suspend
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this in turn makes its parent clock aclk266_g2d to
be gated. But the clock needs to be ungated prior suspend to allow the
system to be suspend and resumed correctly.
Add GATE_BUS_TOP register to the list of registers to be restored when
the system enters into a suspend state so aclk266_g2d will be ungated.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk-exynos5420.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 07d666cc6a29..bea4a173eef5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -271,6 +271,7 @@ static const struct samsung_clk_reg_dump
exynos5420_set_clksrc[] = {
{ .offset = SRC_MASK_PERIC0,.value = 0x1110, },
{ .offset = SRC_MASK_PERIC1,.value = 0x1100, },
{ .offset = SRC_MASK_ISP, .value = 0x1000, },
+ { .offset = GATE_BUS_TOP, .value = 0x, },
{ .offset = GATE_BUS_DISP1, .value = 0x, },
{ .offset = GATE_IP_PERIC, .value = 0x, },
};
While there could be a concern that we are ungating all the clocks in
BUS_TOP, this looks like the least intrusive fix for the issue. Tested
this on Peach Pi, S2R works fine.
Thanks,
Abhilash
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Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend
Hi Javier, On Tue, Apr 7, 2015 at 4:29 PM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: Hello Abhilash, On 04/02/2015 02:22 PM, Abhilash Kesavan wrote: Hi, On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: Hello Sylwester, On 04/01/2015 07:31 PM, Sylwester Nawrocki wrote: On 01/04/15 13:44, Javier Martinez Canillas wrote: On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote: It's not clear what subsystems affect state of the CG_STATUSx registers, it would be good if we could get more information on that. They are in the PMU block and are related to LPI (Low Power Interface handshaking), but what subsystems/peripheral blocks exactly are associated with them it's not clear from the documentation. Yes, I've been looking at the docs again and found out a couple of things: * Each GC_STATUSx register bit is associated with an IP hw block * Some LPI_MASKx registers maps exactly with the GC_STATUSx (i.e: 0 and 1) and others maps only partially (i.e: LPI_MASK2 and GC_STATUS2) The CG_STATUSx and LPI_MASKx bits meaning is not matching according to documentation I have. I guess you've got something newer than REV0.00? My Exynos5420 UM is Revision 1.00 dated February 2014 and GC_STATUS0 bits maps LPI_MASK0 with the exception of bit 16 (NR3D) that is not mentioned in GC_STATUS0, there is a hole between 15 (DIS) and 17 (FIMC_SCALERP). GC_STATUS1 maps exactly with LPI_MASK1 and GC_STATUS2 and LPI_MASK2 have the same bits from 0 to 5 and then differ from there. So it is related to LPI as you said and both LPI_MASKx and GC_STATUSx are part of the PMU register address space. In the particular case of aclk266_g2d, the doc says that the clock can only be gated when CG_STATUS0[20] and CG_STATUS0[21] are 0. These are associated with the SSS and SSS_SLIM respectively which AFAIU are crypto h/w modules. In my Exynos5420 UM ACLK_266_G2D is associated with CG_STATUS0 register bits 22, 21, which in turn correspond to NR3D and DIS IP blocks, i.e. the camera subsystem. Such a dependency would be rather surprising. Sorry, it was a typo error and I actually meant CG_STATUS0 21 and 22 but these correspond in the documentation I've to 21 (SSS) and 22 (SSS_SLIM). As I mentioned before, DIS correspond to CG_STATUS0 15 and NR3D doesn't have a corresponding bit in CG_STATUS0. But I don't know if that is an error in the doc I've since is suspicious that is the only difference between LPI_MASK0 and CG_STATUS0. I think it's essential to understand what triggers changes in CG_STATUSx registers, before we start checking their value in the clock driver. Indeed, we should really understand what the status on these registers means. Also is not clear from the docs how much time should be waited, how long until giving up, etc. Exactly, I checked some kernels from http://opensource.samsung.com (e.g. SM-N900_JB_Opensource.zip) for CG_STATUSx, but I didn't find anything related to these registers yet, except the address macro definitions and debug traces in the power domains driver. Yes, I also looked in the ChromiumOS v3.8 kernel but didn't find anything. Also it might be that there are indeed some clocks which must stay enabled over suspend/resume cycle, then the approach with enabling/disabling clocks in the clock driver might not be such a hack as it looks at first sight. Having a clock driver to both a provider and consumer feels hacky to me as well but I didn't find a better way to solve this issue... another option is to have this workaround to solve the S2R issue while we figure out what the the state in the CG_STATUSx really mean. Let's try to diagnose the issue best we can, then we would choose the most accurate bug fix. Sounds good to me. Based on the earlier comments I was trying to isolate if: 1) s2r fails because we gate aclk266_g2d (but it is one of those clocks that needs to be always on prior to suspend). 2) s2r fails because we gate aclk266_g2d when CG_STATUS0[21:20] bits are not 0 (thus not following the spec). Thanks a lot for continue looking at this. I didn't have time to dig deeper on this since last week. As I did not have access to the hardware guys who could possibly confirm 1), I decided to a) find a configuration where CG_STATUS0 allows gating of the aclk266_g2d clock (i.e. CG_STATUS0[22:21] are 0). b) disable the aclk266_g2d clock using such a configuration. c) check s2r. I found a configuration [1] which gave the following after boot-up: I think you forgot the reference for [1] right? Since with latest Yes, looks like I missed that. There are the changes I had: diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c0e98cf..3a9e21a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -379,6 +379,7 @@ #dma-cells = 1; #dma
Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend
Hi Javier,
On Tue, Apr 7, 2015 at 8:30 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 04/07/2015 04:38 PM, Abhilash Kesavan wrote:
[0]
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas javier.marti...@collabora.co.uk
Date: Tue, 7 Apr 2015 15:53:27 +0200
Subject: [RFC PATCH] clk: exynos5420: Restore GATE_BUS_TOP on suspend
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this in turn makes its parent clock aclk266_g2d to
be gated. But the clock needs to be ungated prior suspend to allow the
system to be suspend and resumed correctly.
Add GATE_BUS_TOP register to the list of registers to be restored when
the system enters into a suspend state so aclk266_g2d will be ungated.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk-exynos5420.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 07d666cc6a29..bea4a173eef5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -271,6 +271,7 @@ static const struct samsung_clk_reg_dump
exynos5420_set_clksrc[] = {
{ .offset = SRC_MASK_PERIC0,.value = 0x1110, },
{ .offset = SRC_MASK_PERIC1,.value = 0x1100, },
{ .offset = SRC_MASK_ISP, .value = 0x1000, },
+ { .offset = GATE_BUS_TOP, .value = 0x, },
{ .offset = GATE_BUS_DISP1, .value = 0x, },
{ .offset = GATE_IP_PERIC, .value = 0x, },
};
While there could be a concern that we are ungating all the clocks in
Yes, I mentioned that but OTOH it will be even more dangerous to gate
clocks that should remain enabled so I used the register default values.
BUS_TOP, this looks like the least intrusive fix for the issue. Tested
this on Peach Pi, S2R works fine.
Thanks a lot for testing, does it mean I can add your Tested-by then when
posting it as a proper patch? I'll wait for Tomasz to comment before though.
Tested-by: Abhilash Kesavan a.kesa...@samsung.com.
Abhilash
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Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend
Hi, On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: Hello Sylwester, On 04/01/2015 07:31 PM, Sylwester Nawrocki wrote: On 01/04/15 13:44, Javier Martinez Canillas wrote: On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote: It's not clear what subsystems affect state of the CG_STATUSx registers, it would be good if we could get more information on that. They are in the PMU block and are related to LPI (Low Power Interface handshaking), but what subsystems/peripheral blocks exactly are associated with them it's not clear from the documentation. Yes, I've been looking at the docs again and found out a couple of things: * Each GC_STATUSx register bit is associated with an IP hw block * Some LPI_MASKx registers maps exactly with the GC_STATUSx (i.e: 0 and 1) and others maps only partially (i.e: LPI_MASK2 and GC_STATUS2) The CG_STATUSx and LPI_MASKx bits meaning is not matching according to documentation I have. I guess you've got something newer than REV0.00? My Exynos5420 UM is Revision 1.00 dated February 2014 and GC_STATUS0 bits maps LPI_MASK0 with the exception of bit 16 (NR3D) that is not mentioned in GC_STATUS0, there is a hole between 15 (DIS) and 17 (FIMC_SCALERP). GC_STATUS1 maps exactly with LPI_MASK1 and GC_STATUS2 and LPI_MASK2 have the same bits from 0 to 5 and then differ from there. So it is related to LPI as you said and both LPI_MASKx and GC_STATUSx are part of the PMU register address space. In the particular case of aclk266_g2d, the doc says that the clock can only be gated when CG_STATUS0[20] and CG_STATUS0[21] are 0. These are associated with the SSS and SSS_SLIM respectively which AFAIU are crypto h/w modules. In my Exynos5420 UM ACLK_266_G2D is associated with CG_STATUS0 register bits 22, 21, which in turn correspond to NR3D and DIS IP blocks, i.e. the camera subsystem. Such a dependency would be rather surprising. Sorry, it was a typo error and I actually meant CG_STATUS0 21 and 22 but these correspond in the documentation I've to 21 (SSS) and 22 (SSS_SLIM). As I mentioned before, DIS correspond to CG_STATUS0 15 and NR3D doesn't have a corresponding bit in CG_STATUS0. But I don't know if that is an error in the doc I've since is suspicious that is the only difference between LPI_MASK0 and CG_STATUS0. I think it's essential to understand what triggers changes in CG_STATUSx registers, before we start checking their value in the clock driver. Indeed, we should really understand what the status on these registers means. Also is not clear from the docs how much time should be waited, how long until giving up, etc. Exactly, I checked some kernels from http://opensource.samsung.com (e.g. SM-N900_JB_Opensource.zip) for CG_STATUSx, but I didn't find anything related to these registers yet, except the address macro definitions and debug traces in the power domains driver. Yes, I also looked in the ChromiumOS v3.8 kernel but didn't find anything. Also it might be that there are indeed some clocks which must stay enabled over suspend/resume cycle, then the approach with enabling/disabling clocks in the clock driver might not be such a hack as it looks at first sight. Having a clock driver to both a provider and consumer feels hacky to me as well but I didn't find a better way to solve this issue... another option is to have this workaround to solve the S2R issue while we figure out what the the state in the CG_STATUSx really mean. Let's try to diagnose the issue best we can, then we would choose the most accurate bug fix. Sounds good to me. Based on the earlier comments I was trying to isolate if: 1) s2r fails because we gate aclk266_g2d (but it is one of those clocks that needs to be always on prior to suspend). 2) s2r fails because we gate aclk266_g2d when CG_STATUS0[21:20] bits are not 0 (thus not following the spec). As I did not have access to the hardware guys who could possibly confirm 1), I decided to a) find a configuration where CG_STATUS0 allows gating of the aclk266_g2d clock (i.e. CG_STATUS0[22:21] are 0). b) disable the aclk266_g2d clock using such a configuration. c) check s2r. I found a configuration [1] which gave the following after boot-up: # devmem 0x10040914 0xFD800014 (CG_STATUS0[22:21] is 0) # devmem 0x10020700 0xC6F8DE9F (aclk266_g2d is enabled) At this point s2r works. I rebooted the board with the same config as above and then disabled aclk266_g2d. # devmem 0x10020700 32 0xC6F8DE9D # devmem 0x10020700 0xC6F8DE9D (aclk266_g2d is disabled) # devmem 0x10040914 0xFD800014 and tried s2r - It fails. From the results, disabling the clock seems to cause the issue rather than the CG_STATUS violation. This is all a little confusing, so please let me know if I have missed something. Regards, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo
Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend
Hi Kevin, On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman khil...@kernel.org wrote: Javier Martinez Canillas javier.marti...@collabora.co.uk writes: [...] Unfortunately I don't fully understand why this clock needs to be enabled. It would be good if someone at Samsung can explain in more detail what the real problem really is. +1 Maybe Abhilash can shed some light here? We really should know *why* this is needed because having the fix in the clock driver just doesn't seem right. It seems like the DMA driver should be managing this clock. I think my last mail might not have reached you (was accidentally sent as html). We are gating the aclk266_g2d clock without checking the CG_STATUS0 register bits as specified in the UM. It looks like we need to keep several clocks alive or gate them only after checking the CG_STATUSx register bits. Regards, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5800-peach-pi: suspend/resume (still) broken
Hello Javier,
On Fri, Mar 27, 2015 at 6:59 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
I had time today again to work on this issue and the best
place I found to enable and disable the mdma0 clock is in
exynos5420_pm_{prepare,resume}. Please let me know if you
have a better idea of where the clock should be managed.
Modifying exynos5420_clk_suspend in
drivers/clk/samsung/clk-exynos5420.c would be another way to go,
however I have not tested if this actually works.
I'll send a RFC patch-set soon.
Thanks for the effort.
Regards,
Abhilash
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Re: exynos5800-peach-pi: suspend/resume (still) broken
Hello, On Wed, Mar 18, 2015 at 4:01 PM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: +people involved in Exynos5420 S2R support (Abhilash, Vikas and Pankaj) Hello Kevin, On 03/17/2015 06:35 PM, Kevin Hilman wrote: I've tried suspend/resume on peach-pi using v4.0-rc4, next/master and samsung/for-next, and it doesn't seem to work on any of them. The first problem was the exynos DRM driver is faulting so I had to set CONFIG_\ DRM_EXYNOS=n for testing in mainline, this is fixed in -next. Note that RTC wake from suspend to idle seems to work, which suggests that the RTC wake alarms are working fine. I tried with both the s3c and the max77802 RTC drivers (e.g. rtcwake -d rtc0 -m freeze -s4) Indeed, both max77802 and S3C RTCs wake alarm IRQ are being triggered: # echo +1 /sys/class/rtc/rtc0/wakealarm # echo +1 /sys/class/rtc/rtc1/wakealarm # grep alarm /proc/interrupts 62: 1 0 0 0 PMU 43 s3c2410-rtc alarm 124: 0 0 1 0 max77802-rtc 1 rtc-alarm1 and also as you said suspend-to-idle and resume works: # echo +5 /sys/class/rtc/rtc1/wakealarm echo freeze /sys/power/state However, trying suspend to RAM (rtcwake -d rtc0 -m mem -s4), it never resumes, and adding no_console_suspend doesn't give anything useful. Anyone else having better luck with suspend/resume on peach-pi? # echo +2 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state Suspend and CPUs shutdown seems to succeed according to [0] but the system never wakes up... I also tried to wakeup the system with the keyboard and the trackpad that is a wake up source but it does not work either. I remember that when the 5420 s2r support series were posted, aclk200_disp1 and aclk300_disp1 clocks needed to be marked as CLK_IGNORE_UNUSED but afaiu that was only because display support was not yet merged but it is now. I tried anyways both marking those clocks as CLK_IGNORE_UNUSED and passing the clk_ignore_unused to the kernel command line but did not work either. Abhilash, Vikas, Pankaj, Any ideas of what could be causing this regression? It seems that by the time the Exynos5420 S2R support landed in mainline, it was already not working which makes it hard to bisect what caused the issue. I remember the Pi power LED changing color from blue on suspend. Does that happen ? I'll try reproducing the issue and then probably use an old working s2r branch in one of my local repos to track this down. Regards, Abhilash I also tried on exynos5422-odroid-xu3, but that doesn't seem to have any working RTC drivers. :( Kevin Best regards, Javier [0]: [ 517.448354] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 517.453827] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 517.547922] wake enabled for irq 123 [ 517.551373] wake enabled for irq 120 [ 518.285645] wake enabled for irq 129 [ 518.287762] wake enabled for irq 130 [ 518.291901] PM: suspend of devices complete after 827.494 msecs [ 518.297218] ldo_35: No configuration [ 518.300769] ldo_34: No configuration [ 518.304327] ldo_33: No configuration [ 518.307899] ldo_32: No configuration [ 518.311513] ldo_29: No configuration [ 518.315000] ldo_28: No configuration [ 518.318554] ldo_27: No configuration [ 518.322090] ldo_26: No configuration [ 518.325667] ldo_25: No configuration [ 518.329224] ldo_24: No configuration [ 518.332780] ldo_23: No configuration [ 518.336317] ldo_21: No configuration [ 518.339894] ldo_20: No configuration [ 518.343451] ldo_19: No configuration [ 518.346988] ldo_18: No configuration [ 518.351369] vdd_1v8_7: No configuration [ 518.354739] vdd_1v2_2: No configuration [ 518.362718] PM: late suspend of devices complete after 3.781 msecs [ 518.371062] PM: noirq suspend of devices complete after 3.631 msecs [ 518.375863] Disabling non-boot CPUs ... [ 518.380035] IRQ50 no longer affine to CPU1 [ 518.380266] CPU1: shutdown [ 518.399253] IRQ51 no longer affine to CPU2 [ 518.399472] CPU2: shutdown [ 518.418914] IRQ52 no longer affine to CPU3 [ 518.419121] CPU3: shutdown ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5800-peach-pi: suspend/resume (still) broken
Hi,
On Fri, Mar 20, 2015 at 9:59 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Javier,
On Fri, Mar 20, 2015 at 9:46 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 03:23 PM, Abhilash Kesavan wrote:
On 03/17/2015 06:35 PM, Kevin Hilman wrote:
Anyone else having better luck with suspend/resume on peach-pi?
# echo +2 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state
Suspend and CPUs shutdown seems to succeed according to [0] but the system
never wakes up...
I also tried to wakeup the system with the keyboard and the trackpad that
is
a wake up source but it does not work either.
I remember that when the 5420 s2r support series were posted, aclk200_disp1
and aclk300_disp1 clocks needed to be marked as CLK_IGNORE_UNUSED but afaiu
that was only because display support was not yet merged but it is now.
I tried anyways both marking those clocks as CLK_IGNORE_UNUSED and passing
the clk_ignore_unused to the kernel command line but did not work either.
Abhilash, Vikas, Pankaj,
Any ideas of what could be causing this regression? It seems that by the
time the Exynos5420 S2R support landed in mainline, it was already not
working which makes it hard to bisect what caused the issue.
I remember the Pi power LED changing color from blue on suspend. Does
Thanks a lot for answering. Who manages that LED? is the kernel or the
firwmare in the EC? I tried suspend to ram using ChromeOS 3.8 kernel and
I see that the blue LED is indeed turned off on suspend but that does not
happen in mainline.
I am not too sure. It was just something I remembered from earlier.
that happen ? I'll try reproducing the issue and then probably use an
old working s2r branch in one of my local repos to track this down.
If I checkout mainline with HEAD in your commit adc548d77c22
(ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420) + the
patch you mentioned back then to keep the aclk200_disp1 and aclk300_disp1
clocks enabled even when not used [0], I have S2R working. But even with
that commit, I don't see the blue LED to be turn off like is the case in
the ChromeOS 3.8 kernel.
So I think you can use that as a base. I tried bisecting but it is tricky
due other issues masking the S2R regression. I also tried to compare the
diff between adc548d77c22 and v3.19-rc1 that is the first known bad afaict
but didn't find any relevant either.
By adding printouts I can tell that all the CPUs enter exynos_power_down()
in arch/arm/mach-exynos/mcpm-exynos.c and also the last man disables the
cluster for both Cortex A-15 and A-7 clusters.
So it seems that the problem is on the resume path.
I have made some progress on this. This is the current state:
If I use next-20141114 (which was when the S2R code first appeared in
linux-next), then all is good. next-20141117 is fine too but things
are broken in next-20141118.
I have narrowed it down to the commit: ae43b32 ARM: 8202/1:
dmaengine: pl330: Add runtime Power Management support v12. The only
way I see this impacting s2r is because it disables the dma pclk while
suspending or before.
Checking further, will update in a bit.
OK, so disabling the mdma0 node in arch/arm/boot/dts/exynos5420.dtsi
gets things working. Like Kevin mentioned in the initial report, I
need to disable DRM else there is a crash while suspending. With these
two changes, on linus' tree and kgene's for-next s2r works fine.
On linux-next, I need to disable CONFIG_MWIFIEX too.
Also, I observe cros-ec-spi transfer failures during resume and
sometimes it is unable to re-enable the tps fets causing a crash.
However, that would be a driver specific issue.
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
Regards,
Abhilash
Regards,
Abhilash
Best regards,
Javier
[0]:
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 848d602efc06..d8b66339d564 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -932,14 +932,14 @@ static struct samsung_gate_clock exynos5x_gate_clks[]
__initdata = {
GATE(0, aclk400_mscl, mout_user_aclk400_mscl,
GATE_BUS_TOP, 17, 0, 0),
GATE(0, aclk200_disp1, mout_user_aclk200_disp1,
- GATE_BUS_TOP, 18, 0, 0),
+ GATE_BUS_TOP, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_MPHY_IXTAL24, sclk_mphy_ixtal24,
mphy_refclk_ixtal24,
GATE_BUS_TOP, 28, 0, 0),
GATE(CLK_SCLK_HSIC_12M, sclk_hsic_12m, ff_hsic_12m,
GATE_BUS_TOP, 29, 0, 0),
GATE(0, aclk300_disp1, mout_user_aclk300_disp1,
- SRC_MASK_TOP2, 24, 0, 0),
+ SRC_MASK_TOP2, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_MAU_EPLL, mau_epll, mout_mau_epll_clk
Re: exynos5800-peach-pi: suspend/resume (still) broken
Hi Javier,
On Fri, Mar 20, 2015 at 9:46 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 03:23 PM, Abhilash Kesavan wrote:
On 03/17/2015 06:35 PM, Kevin Hilman wrote:
Anyone else having better luck with suspend/resume on peach-pi?
# echo +2 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state
Suspend and CPUs shutdown seems to succeed according to [0] but the system
never wakes up...
I also tried to wakeup the system with the keyboard and the trackpad that is
a wake up source but it does not work either.
I remember that when the 5420 s2r support series were posted, aclk200_disp1
and aclk300_disp1 clocks needed to be marked as CLK_IGNORE_UNUSED but afaiu
that was only because display support was not yet merged but it is now.
I tried anyways both marking those clocks as CLK_IGNORE_UNUSED and passing
the clk_ignore_unused to the kernel command line but did not work either.
Abhilash, Vikas, Pankaj,
Any ideas of what could be causing this regression? It seems that by the
time the Exynos5420 S2R support landed in mainline, it was already not
working which makes it hard to bisect what caused the issue.
I remember the Pi power LED changing color from blue on suspend. Does
Thanks a lot for answering. Who manages that LED? is the kernel or the
firwmare in the EC? I tried suspend to ram using ChromeOS 3.8 kernel and
I see that the blue LED is indeed turned off on suspend but that does not
happen in mainline.
I am not too sure. It was just something I remembered from earlier.
that happen ? I'll try reproducing the issue and then probably use an
old working s2r branch in one of my local repos to track this down.
If I checkout mainline with HEAD in your commit adc548d77c22
(ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420) + the
patch you mentioned back then to keep the aclk200_disp1 and aclk300_disp1
clocks enabled even when not used [0], I have S2R working. But even with
that commit, I don't see the blue LED to be turn off like is the case in
the ChromeOS 3.8 kernel.
So I think you can use that as a base. I tried bisecting but it is tricky
due other issues masking the S2R regression. I also tried to compare the
diff between adc548d77c22 and v3.19-rc1 that is the first known bad afaict
but didn't find any relevant either.
By adding printouts I can tell that all the CPUs enter exynos_power_down()
in arch/arm/mach-exynos/mcpm-exynos.c and also the last man disables the
cluster for both Cortex A-15 and A-7 clusters.
So it seems that the problem is on the resume path.
I have made some progress on this. This is the current state:
If I use next-20141114 (which was when the S2R code first appeared in
linux-next), then all is good. next-20141117 is fine too but things
are broken in next-20141118.
I have narrowed it down to the commit: ae43b32 ARM: 8202/1:
dmaengine: pl330: Add runtime Power Management support v12. The only
way I see this impacting s2r is because it disables the dma pclk while
suspending or before.
Checking further, will update in a bit.
Regards,
Abhilash
Regards,
Abhilash
Best regards,
Javier
[0]:
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 848d602efc06..d8b66339d564 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -932,14 +932,14 @@ static struct samsung_gate_clock exynos5x_gate_clks[]
__initdata = {
GATE(0, aclk400_mscl, mout_user_aclk400_mscl,
GATE_BUS_TOP, 17, 0, 0),
GATE(0, aclk200_disp1, mout_user_aclk200_disp1,
- GATE_BUS_TOP, 18, 0, 0),
+ GATE_BUS_TOP, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_MPHY_IXTAL24, sclk_mphy_ixtal24,
mphy_refclk_ixtal24,
GATE_BUS_TOP, 28, 0, 0),
GATE(CLK_SCLK_HSIC_12M, sclk_hsic_12m, ff_hsic_12m,
GATE_BUS_TOP, 29, 0, 0),
GATE(0, aclk300_disp1, mout_user_aclk300_disp1,
- SRC_MASK_TOP2, 24, 0, 0),
+ SRC_MASK_TOP2, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_MAU_EPLL, mau_epll, mout_mau_epll_clk,
SRC_MASK_TOP7, 20, 0, 0),
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Re: [PATCH] pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
Hi Tomasz, On Mon, Mar 9, 2015 at 3:54 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Abhilash, Linus, 2015-03-02 1:21 GMT+09:00 Abhilash Kesavan a.kesa...@samsung.com: The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: samsung-pinctrl 1058.pinctrl: irq number not available As long as external gpio interrupts refer to non-wake-up-capable GPIO interrupts I'm fine with this patch. Yes, that was the intention. Thanks for the review. Regards, Abhilash Acked-by: Tomasz Figa tomasz.f...@gmail.com Thanks Linus for pinging and sorry for delay. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND] ARM: EXYNOS: Remove ARCH_HAS_BANDGAP selection
Now that the samsung thermal driver dependency on ARCH_HAS_BANDGAP has been removed, fix the arch code selection too. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Acked-by: Lukasz Majewski l.majew...@samsung.com --- arch/arm/mach-exynos/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 603820e..a4abcae 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -9,7 +9,6 @@ menuconfig ARCH_EXYNOS bool Samsung EXYNOS if ARCH_MULTI_V7 - select ARCH_HAS_BANDGAP select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_REQUIRE_GPIOLIB select ARM_AMBA -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
The alive pin controller on exynos7 does not support external gpio
interrupts. Hence, remove the eint_gpio_init call-back for it. This
fixes the following error message seen during exynos7 boot-up:
samsung-pinctrl 1058.pinctrl: irq number not available
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index c8f83f9..a7e9c42 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1324,7 +1324,6 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[]
__initconst = {
/* pin-controller instance 0 Alive data */
.pin_banks = exynos7_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
- .eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
}, {
/* pin-controller instance 1 BUS0 data */
--
2.1.0
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Re: [PATCH 1/2] thermal: exynos: Fix wrong control of power down detection mode for Exynos7
Hi Lukasz,
On Wed, Feb 25, 2015 at 2:33 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Abhilash,
This patch fixes the wrong control of PD_DET_EN (power down detection
mode) for Exynos7 because exynos7_tmu_control() always enables the
power down detection mode regardless 'on' parameter.
Cc: Zhang Rui rui.zh...@intel.com
Cc: Eduardo Valentin edubez...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 933cd80..a60f527 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -682,6 +682,7 @@ static void exynos7_tmu_control(struct
platform_device *pdev, bool on)
if (on) {
con |= (1 EXYNOS_TMU_CORE_EN_SHIFT);
+ con |= (1 EXYNOS7_PD_DET_EN_SHIFT);
interrupt_en =
(of_thermal_is_trip_valid(tz, 7)
EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
@@ -704,9 +705,9 @@ static void exynos7_tmu_control(struct
platform_device *pdev, bool on) interrupt_en
EXYNOS_TMU_INTEN_FALL0_SHIFT; } else {
con = ~(1 EXYNOS_TMU_CORE_EN_SHIFT);
+ con = ~(1 EXYNOS7_PD_DET_EN_SHIFT);
interrupt_en = 0; /* Disable all interrupts */
}
- con |= 1 EXYNOS7_PD_DET_EN_SHIFT;
writel(interrupt_en, data-base + EXYNOS7_TMU_REG_INTEN);
writel(con, data-base + EXYNOS_TMU_REG_CONTROL);
Could you test this patch if it isn't introducing any regression on your
HW?
The patch does not cause any regression on exynos7 and seems logically correct.
Tested-by: Abhilash Kesavan a.kesa...@samsung.com
Regards,
Abhilash
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [PATCH] thermal: exynos: fix: Check if data-tmu_read callback is present before read
Hi Lukasz,
On Mon, Feb 16, 2015 at 3:23 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Eduardo,
The exynos_tmu_data() function should on entrance test not only for
valid data pointer, but also for data-tmu_read one.
It is important, since afterwards it is dereferenced to get
temperature code.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 3a19353..a86e0495e 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -717,7 +717,7 @@ static int exynos_get_temp(void *p, long *temp)
{
struct exynos_tmu_data *data = p;
- if (!data)
+ if (!data || !data-tmu_read)
return -EINVAL;
mutex_lock(data-lock);
This fix shall be added to v3.20.
Thanks for looking into this. This fixes the incorrect temperature at
boot-up I was seeing on Exynos7 and Exynos5420.
Tested-by: Abhilash Kesavan a.kesa...@samsung.com
Test HW: Peach-Pit (Exynos5420 based chromebook) and Exynos7 based
Espresso board.
Regards,
Abhilash
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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[PATCH v2 3/3] clk: samsung: add cpu clock configuration data and instantiate cpu clock
Add the Atlas CPU clock configuration data and instantiate the CPU clock
type for Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.h |5 +
drivers/clk/samsung/clk-exynos7.c | 33 ++-
include/dt-bindings/clock/exynos7-clk.h |3 ++-
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 24e844e..1fd7f51 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -31,6 +31,11 @@
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) 24) | ((pclk) 20) | ((aclk) 4)))
+#define EXYNOS7_ATL_DIV0(aclk, pclk, atclk, pclk_dbg) \
+ ((aclk 8) | (pclk 12) | (atclk 20) | (pclk_dbg 26))
+#define EXYNOS7_ATL_DIV1(pll, hpm, cntclk) \
+ ((pll 0) | (hpm 4) | (cntclk 8))
+
/**
* struct exynos_cpuclk_data: config data to setup cpu clocks.
* @prate: frequency of the primary parent clock (in KHz).
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index cec026c..f2a9895 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -14,6 +14,7 @@
#include linux/of.h
#include clk.h
+#include clk-cpu.h
#include dt-bindings/clock/exynos7-clk.h
/* Register Offset definitions for CMU_TOPC (0x1057) */
@@ -64,6 +65,30 @@ static const struct samsung_pll_rate_table
pll1450x_24mhz_tbl[] = {
PLL_35XX_RATE(2, 200, 3, 3),
};
+static const struct exynos_cpuclk_cfg_data exynos7_atlclk_d[] __initconst = {
+ { 210, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 5, 6), },
+ { 200, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 5, 6), },
+ { 1896000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 180, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 1704000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 160, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 150, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 140, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 130, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), },
+ { 120, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), },
+ { 110, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), },
+ { 100, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), },
+ { 90, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), },
+ { 80, EXYNOS7_ATL_DIV0(2, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 3, 5), },
+ { 70, EXYNOS7_ATL_DIV0(2, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 3, 5), },
+ { 60, EXYNOS7_ATL_DIV0(2, 4, 4, 4), EXYNOS7_ATL_DIV1(1, 3, 4), },
+ { 50, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 40, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 30, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 20, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 1, 3), },
+ { 0 },
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -620,7 +645,13 @@ static struct samsung_cmu_info atlas_cmu_info __initdata =
{
static void __init exynos7_clk_atlas_init(struct device_node *np)
{
- samsung_cmu_register_one(np, atlas_cmu_info);
+ struct samsung_clk_provider *ctx;
+
+ ctx = samsung_cmu_register_one(np, atlas_cmu_info);
+ exynos_register_cpu_clock(ctx, CLK_ATLAS_CLK, atlclk,
+ mout_atlas_p[0], mout_atlas_p[1], 0,
+ exynos7_atlclk_d, ARRAY_SIZE(exynos7_atlclk_d),
+ 0, np);
}
CLK_OF_DECLARE(exynos7_clk_atlas, samsung,exynos7-clock-atlas,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 6b9465c..6df64ef 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -67,7 +67,8 @@
#define CLK_ATLAS 12
#define DOUT_SCLK_HPM_ATLAS13
#define DOUT_ATLAS_PLL 14
-#define ATLAS_NR_CLK 15
+#define CLK_ATLAS_CLK 15
+#define ATLAS_NR_CLK 16
/* CCORE */
#define PCLK_RTC 1
--
1.7.9.5
--
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[PATCH v2 0/3] Add CPU clock support for Exynos7
This patch set adds the atlas clock hierarchy on Exynos7. It also modifies the existing cpu clock infrastructure to handle exynos7 differences. These patches are a pre-requisite for enabling CPUFreq on Exynos7. This patch set has been tested on next-20150202 with samsung clk tree (for-v3.20/clk/next branch) merged. Following are the dependencies: 1) cpufreq: use generic cpufreq drivers for exynos platforms (v12) http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/304975.html For testing I have applied the following: 1) mfd: sec: add S2MPS15 PMIC support https://lkml.org/lkml/2014/10/14/50 2) regulator: s2mps11: add support for S2MPS15 regulators https://lkml.org/lkml/2014/10/14/52 3) Regulators dt nodes were added in the espresso dts file and I2C channel 4 which has the PMIC on it was tested. Abhilash Kesavan (3): clk: samsung: exynos7: add clocks for CPU block clk: samsung: add cpu clock support for Exynos7 clk: samsung: add cpu clock configuration data and instantiate cpu clock .../devicetree/bindings/clock/exynos7-clock.txt|6 + drivers/clk/samsung/clk-cpu.c | 147 ++- drivers/clk/samsung/clk-cpu.h | 38 - drivers/clk/samsung/clk-exynos4.c |2 +- drivers/clk/samsung/clk-exynos5250.c |2 +- drivers/clk/samsung/clk-exynos5420.c |4 +- drivers/clk/samsung/clk-exynos7.c | 152 include/dt-bindings/clock/exynos7-clk.h| 21 ++- 8 files changed, 363 insertions(+), 9 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/3] clk: samsung: exynos7: add clocks for CPU block
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h| 20 +++-
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6bf1e74..bcf274b5 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-atlas
- samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
@@ -64,6 +65,11 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for atlas clock controller:
+ - fin_pll
+ - fout_atlas_pll
+ - mout_sclk_bus0_pll_atlas
+
Input clocks for ccore clock controller:
- fin_pll
- dout_aclk_ccore_133
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index b61724b..cec026c 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -36,6 +36,34 @@
#define DIV_TOPC3 0x060C
#define ENABLE_ACLK_TOPC1 0x0804
+static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = {
+ /* rate, m, p, s */
+ PLL_35XX_RATE(249600, 208, 2, 0),
+ PLL_35XX_RATE(24, 200, 2, 0),
+ PLL_35XX_RATE(230400, 192, 2, 0),
+ PLL_35XX_RATE(22, 275, 3, 0),
+ PLL_35XX_RATE(21, 175, 2, 0),
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(189600, 158, 2, 0),
+ PLL_35XX_RATE(18, 150, 2, 0),
+ PLL_35XX_RATE(170400, 142, 2, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 2, 1),
+ PLL_35XX_RATE(14, 350, 3, 1),
+ PLL_35XX_RATE(13, 325, 3, 1),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 350, 3, 2),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -57,6 +85,8 @@ PNAME(mout_bus1_pll_ctrl_p) = { fin_pll, fout_bus1_pll
};
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
PNAME(mout_mfc_pll_ctrl_p) = { fin_pll, fout_mfc_pll };
+PNAME(mout_topc_group1)= { mout_bus0_pll_ctrl,
ffac_topc_bus0_pll_div2,
+mout_bus1_pll_ctrl, mout_cc_pll_ctrl };
PNAME(mout_topc_group2) = { mout_sclk_bus0_pll_cmuc,
mout_sclk_bus1_pll_cmuc, mout_sclk_cc_pll_cmuc,
mout_sclk_mfc_pll_cmuc };
@@ -111,6 +141,8 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(MOUT_SCLK_BUS0_PLL_ATLAS, mout_sclk_bus0_pll_atlas,
+ mout_topc_group1, MUX_SEL_TOPC1, 4, 2),
MUX(0, mout_aud_pll_ctrl, mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -504,6 +536,95 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_ATLAS (0x1180) */
+#defineATLAS_PLL_LOCK 0x
+#defineATLAS_PLL_CON0 0x0100
+#defineMUX_SEL_ATLAS0 0x0200
+#defineMUX_SEL_ATLAS1 0x0204
+#defineMUX_SEL_ATLAS2 0x0208
+#defineDIV_ATLAS0 0x0600
+#defineDIV_ATLAS1 0x0604
+#defineENABLE_SCLK_ATLAS 0x0A00
+
+/* List of parent clocks for Muxes in CMU_ATLAS */
+PNAME(mout_atlas_pll_ctrl_p) = { fin_pll, fout_atlas_pll };
+PNAME(mout_bus_pll_atlas_p) = { fin_pll, mout_sclk_bus0_pll_atlas };
+PNAME(mout_atlas_p) = { mout_atlas_pll_ctrl, mout_bus_pll_atlas };
+
+static unsigned long atlas_clk_regs[] __initdata = {
+ ATLAS_PLL_LOCK,
+ ATLAS_PLL_CON0
[PATCH v2 2/3] clk: samsung: add cpu clock support for Exynos7
The divider and mux register offsets and bits are different on
Exynos7 from the older SoCs. Add new pre/post rate change callbacks
for Exynos7 to handle these differences. To do this:
- Add a new exynos_cpuclk_soc_data structure that will hold
the SoC-specific pre/post rate change call-backs
- Modify exynos_register_cpu_clock() prototype to include a
node pointer
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.c| 147 +-
drivers/clk/samsung/clk-cpu.h| 33 +++-
drivers/clk/samsung/clk-exynos4.c|2 +-
drivers/clk/samsung/clk-exynos5250.c |2 +-
drivers/clk/samsung/clk-exynos5420.c |4 +-
5 files changed, 180 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 009a21b..743 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -51,6 +51,13 @@
#define DIV_MASK_ALL 0x
#define MUX_MASK 7
+#define EXYNOS7_SRC_CPU0x208
+#define EXYNOS7_STAT_CPU 0x408
+#define EXYNOS7_DIV_CPU0 0x600
+#define EXYNOS7_DIV_CPU1 0x604
+#define EXYNOS7_DIV_STAT_CPU0 0x700
+#define EXYNOS7_DIV_STAT_CPU1 0x704
+
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
@@ -232,6 +239,105 @@ static int exynos_cpuclk_post_rate_change(struct
clk_notifier_data *ndata,
return 0;
}
+/* Exynos7 helper function to set the 'safe' dividers for the CPU clock. The
+ * parameters div and mask contain the divider value and the register bit mask
+ * of the dividers to be programmed.
+ */
+static void exynos7_set_safe_div(void __iomem *base, unsigned long div,
+ unsigned long mask)
+{
+ unsigned long div1;
+
+ div1 = readl(base + EXYNOS7_DIV_CPU1);
+ div1 = (div1 ~mask) | (div mask);
+ writel(div1, base + EXYNOS7_DIV_CPU1);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU1, mask);
+}
+
+/* Exynos7 handler for pre-rate change notification from parent clock */
+static int exynos7_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk-cfg;
+ unsigned long alt_prate = clk_get_rate(cpuclk-alt_parent);
+ unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
+ unsigned long div0, div1 = 0, mux_reg;
+
+ /* find out the divider values to use for clock data */
+ while ((cfg_data-prate * 1000) != ndata-new_rate) {
+ if (cfg_data-prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+
+ spin_lock(cpuclk-lock);
+
+ div0 = cfg_data-div0;
+ div1 = cfg_data-div1;
+
+ /*
+* If the new and old parent clock speed is less than the clock speed
+* of the alternate parent, then it should be ensured that at no point
+* the armclk speed is more than the old_prate until the dividers are
+* set.
+*/
+ if (alt_prate ndata-old_rate) {
+ alt_div = DIV_ROUND_UP(alt_prate, ndata-old_rate) - 1;
+ WARN_ON(alt_div = MAX_DIV);
+ alt_div |= E4210_DIV1_HPM_MASK;
+ alt_div_mask |= E4210_DIV1_HPM_MASK;
+
+ exynos7_set_safe_div(base, alt_div, alt_div_mask);
+ div1 |= alt_div;
+ }
+
+ /* select mout_bus0_pll_atlas as the alternate parent */
+ mux_reg = readl(base + EXYNOS7_SRC_CPU);
+ writel(mux_reg | (1 0), base + EXYNOS7_SRC_CPU);
+ wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 1);
+
+ /* alternate parent is active now. set the dividers */
+ writel(div0, base + EXYNOS7_DIV_CPU0);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, DIV_MASK_ALL);
+
+ writel(div1, base + EXYNOS7_DIV_CPU1);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU1,
+ DIV_MASK_ALL);
+
+ spin_unlock(cpuclk-lock);
+ return 0;
+}
+
+/* Exynos7 handler for post-rate change notification from parent clock */
+static int exynos7_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk-cfg;
+ unsigned long div = 0, div_mask = DIV_MASK;
+ unsigned long mux_reg;
+
+ spin_lock(cpuclk-lock);
+
+ /* select mout_atlas_pll as the alternate parent */
+ mux_reg = readl(base + EXYNOS7_SRC_CPU);
+ writel(mux_reg ~(1 0), base + EXYNOS7_SRC_CPU);
+ wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 0);
+
+ /* find out the divider values to use for clock data */
+ while ((cfg_data-prate * 1000) != ndata-new_rate
Re: [PATCH 1/2] thermal: exynos: Reorder exynos_map_dt_data() function
Hi Lukasz,
On Wed, Feb 4, 2015 at 4:06 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Abhilash,
Hi Lukasz,
On Fri, Jan 30, 2015 at 8:36 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Lukasz,
On Fri, Jan 30, 2015 at 1:44 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Eduardo, Abhilash,
On Thu, Jan 22, 2015 at 06:02:07PM +0530, Abhilash Kesavan wrote:
Hi Lukasz,
On Thu, Jan 22, 2015 at 2:31 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Abhilash,
Hi Lukasz,
On Mon, Jan 19, 2015 at 5:14 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
The exynos_map_dt_data() function must be called before
thermal_zone_of_sensor_register(), and hence provide
tmu_read() function, before it is needed.
This change is driven by adding support for enabling
thermal_zoneX when it is properly initialized.
One can read the mode of operation
at /sys/class/thermal/thermal_zone0/mode Such
functionality was missing in the of-thermal.c code.
Reported-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index
9d2d685..5d946ab 100644 ---
a/drivers/thermal/samsung/exynos_tmu.c +++
b/drivers/thermal/samsung/exynos_tmu.c @@ -975,15 +975,16
@@ static int exynos_tmu_probe(struct platform_device
*pdev) platform_set_drvdata(pdev, data);
mutex_init(data-lock);
+ ret = exynos_map_dt_data(pdev);
+ if (ret)
+ goto err_sensor;
+
data-tzd =
thermal_zone_of_sensor_register(pdev-dev, 0, data,
exynos_sensor_ops); if (IS_ERR(data-tzd)) {
pr_err(thermal: tz: %p ERROR\n,
data-tzd); return PTR_ERR(data-tzd);
}
- ret = exynos_map_dt_data(pdev);
- if (ret)
- goto err_sensor;
pdata = data-pdata;
I have been testing this along with your v5 patch set and am
seeing incorrect temperature being reported at boot-up on
exynos7.
Does it show a maximal temperature value (0x1FF)?
I did not print the current temperature register, but I
remember the message showing ~105C. Will give you the register
value when I test with more debug prints tomorrow.
It looks
like exynos_tmu_read gets called from
thermal_zone_of_device_update during boot-up, now that we
have it populated early. However, as the tmu initialization
function has not been called yet it returns a wrong value.
Does that sound correct ?
No, this is a mistake. However, I'm wondering why on Exynos4/5
this error didn't show up...
I have been lowering the software trip point temperature in the
exynos7 dts file (to 55C) for testing purposes. Hence, when the
temperature is read incorrectly as ~105C the board trips at
boot-up
this is a very unusual
value - I had problems with
reading 0xFF values with
similar symptom (but this
was caused by lack of vtmu).
itself. Maybe for exynos4/5 the incorrect value read during
boot-up is in the non-tripping range and once the tmu is
initialized later it continues to function properly thereafter ?
The reordering is needed to be able to call set_mode callback
at of-thermal.c to set the mode.
If this change causes problems, then another solution
(probably not so neat) must be found.
Please let me know if you need any further details.
Abhilash, could you provide more details (like relevant output from
dmesg) and point me a list of patches which shall I apply to test
this issue on Exynos4/5?
Sorry, I have not had the time to re-check this and provide you with
the current temperature register value. I will definitely do so on
Monday and also provide you the dmesg output. I applied the
following patches on linux-next:
bbf872d thermal: exynos: Add TMU support for Exynos7 SoC
b8190ac dts: Documentation: Add documentation for Exynos7 SoC
thermal bindings 9330ec1 thermal: exynos: Reorder
exynos_map_dt_data() function 4dd41c4 thermal: exynos: dts: Provide
device tree bindings identical to the one in exynos_tmu_data.c
a7b80b9 thermal: dts: exynos: Trip points and sensor configuration
data for Exynos5440
77d072e thermal: exynos: dts: Define default thermal-zones for
Exynos4 964dd36 thermal: dts: Default trip points definition for
Exynos5420 SoCs c1d2f97 thermal: exynos: dts: Add default
definition of the TMU sensor parameter 02a4496 arm: dts
Re: [PATCH 1/2] thermal: exynos: Reorder exynos_map_dt_data() function
Hi Lukasz,
On Fri, Jan 30, 2015 at 8:36 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Lukasz,
On Fri, Jan 30, 2015 at 1:44 PM, Lukasz Majewski l.majew...@samsung.com
wrote:
Hi Eduardo, Abhilash,
On Thu, Jan 22, 2015 at 06:02:07PM +0530, Abhilash Kesavan wrote:
Hi Lukasz,
On Thu, Jan 22, 2015 at 2:31 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Abhilash,
Hi Lukasz,
On Mon, Jan 19, 2015 at 5:14 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
The exynos_map_dt_data() function must be called before
thermal_zone_of_sensor_register(), and hence provide tmu_read()
function, before it is needed.
This change is driven by adding support for enabling
thermal_zoneX when it is properly initialized.
One can read the mode of operation
at /sys/class/thermal/thermal_zone0/mode Such functionality was
missing in the of-thermal.c code.
Reported-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 9d2d685..5d946ab
100644 --- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -975,15 +975,16 @@ static int exynos_tmu_probe(struct
platform_device *pdev) platform_set_drvdata(pdev, data);
mutex_init(data-lock);
+ ret = exynos_map_dt_data(pdev);
+ if (ret)
+ goto err_sensor;
+
data-tzd =
thermal_zone_of_sensor_register(pdev-dev, 0, data,
exynos_sensor_ops); if (IS_ERR(data-tzd)) {
pr_err(thermal: tz: %p ERROR\n, data-tzd);
return PTR_ERR(data-tzd);
}
- ret = exynos_map_dt_data(pdev);
- if (ret)
- goto err_sensor;
pdata = data-pdata;
I have been testing this along with your v5 patch set and am
seeing incorrect temperature being reported at boot-up on
exynos7.
Does it show a maximal temperature value (0x1FF)?
I did not print the current temperature register, but I remember the
message showing ~105C. Will give you the register value when I test
with more debug prints tomorrow.
It looks
like exynos_tmu_read gets called from
thermal_zone_of_device_update during boot-up, now that we have
it populated early. However, as the tmu initialization function
has not been called yet it returns a wrong value. Does that
sound correct ?
No, this is a mistake. However, I'm wondering why on Exynos4/5
this error didn't show up...
I have been lowering the software trip point temperature in the
exynos7 dts file (to 55C) for testing purposes. Hence, when the
temperature is read incorrectly as ~105C the board trips at boot-up
this is a very unusual
value - I had problems with
reading 0xFF values with
similar symptom (but this was
caused by lack of vtmu).
itself. Maybe for exynos4/5 the incorrect value read during boot-up
is in the non-tripping range and once the tmu is initialized later
it continues to function properly thereafter ?
The reordering is needed to be able to call set_mode callback at
of-thermal.c to set the mode.
If this change causes problems, then another solution (probably
not so neat) must be found.
Please let me know if you need any further details.
Abhilash, could you provide more details (like relevant output from
dmesg) and point me a list of patches which shall I apply to test this
issue on Exynos4/5?
Sorry, I have not had the time to re-check this and provide you with
the current temperature register value. I will definitely do so on
Monday and also provide you the dmesg output. I applied the following
patches on linux-next:
bbf872d thermal: exynos: Add TMU support for Exynos7 SoC
b8190ac dts: Documentation: Add documentation for Exynos7 SoC thermal bindings
9330ec1 thermal: exynos: Reorder exynos_map_dt_data() function
4dd41c4 thermal: exynos: dts: Provide device tree bindings identical
to the one in exynos_tmu_data.c
a7b80b9 thermal: dts: exynos: Trip points and sensor configuration
data for Exynos5440
77d072e thermal: exynos: dts: Define default thermal-zones for Exynos4
964dd36 thermal: dts: Default trip points definition for Exynos5420 SoCs
c1d2f97 thermal: exynos: dts: Add default definition of the TMU sensor
parameter
02a4496 arm: dts: Adding CPU cooling binding for Exynos SoCs
bfadff0 arm: dts: odroid: Enable TMU at Exynos4412 based Odroid U3 device
862764c arm: dts: odroid: Add LDO10 regulator node
Re: [PATCH v4 2/2] thermal: exynos: Add TMU support for Exynos7 SoC
Hi Eduardo, On Sun, Feb 1, 2015 at 12:54 AM, Eduardo Valentin edubez...@gmail.com wrote: On Tue, Jan 27, 2015 at 11:18:22AM +0530, Abhilash Kesavan wrote: Add registers, bit fields and compatible strings for Exynos7 TMU (Thermal Management Unit). Following are a few of the differences in the Exynos7 TMU from earlier SoCs: - 8 trigger levels - Different bit offsets and more registers for the rising and falling thresholds. - New power down detection bit in the TMU_CONTROL register which does not update the CURRENT_TEMP0 when tmu power down is detected. - Change in bit offset for the NEXT_DATA field of EMUL_CON register. EMUL_CON register address has also changed. - INTSTAT and INTCLEAR registers present in earlier SoCs have been combined into one INTPEND register. The register address for INTCLEAR and INTPEND is also different. - Since there are 8 rising/falling interrupts as against at most 4 in earlier SoCs the INTEN bit offsets are different. - Multiple probe support which is handled by a TMU_CONTROL1 register (No support for this in the current patch). This patch adds special clock support required only for Exynos7. It also updates the code_to_temp prototype as Exynos7 has 9 bit code-temp mapping. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Applied to my -fixes branch. However, I had to amend it myself to make checkpatch.pl --strict silent. In this version, it still outputs: CHECK: Alignment should match open parenthesis #209: FILE: drivers/thermal/samsung/exynos_tmu.c:558: + if (!data-temp_error1 || + (pdata-min_efuse_value data-temp_error1) || CHECK: multiple assignments should be avoided #366: FILE: drivers/thermal/samsung/exynos_tmu.c:882: + tmu_intstat = tmu_intclear = EXYNOS7_TMU_REG_INTPEND; total: 0 errors, 0 warnings, 2 checks, 314 lines checked next, make sure you run checkpatch.pl --strict before sending patches. Thanks for applying these patches. As this is adding support for a new SoC, should it not be part of your -next branch ? I generally just run checkpatch without the strict option. Will ensure that I run it with strict in the future. Regards, Abhilash --- This patch set has been tested on linux next-20150123 with Eduardo's thermal-next branch merged along with the arch-side exynos7 related dts changes applied. Changes since v3: Addressed comments from Lukasz Majewski: - Added more comments in the code setting the thresholds. - Split the documentation out into another patch. Changes since v2: - Rebased on top of Lukasz' latest exynos tmu series (v4). - Added new exynos7 soc_type. Changes since v1: - Rebased on top of Lukasz' latest exynos tmu series (v2). - Added sclk support to patch adding Exynos7 tmu support. Previously, it was a separate patch. - Used the SOC type to decide if sclk is present. drivers/thermal/samsung/exynos_tmu.c | 204 -- drivers/thermal/samsung/exynos_tmu.h |1 + 2 files changed, 197 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 852e622..660ff69 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -119,6 +119,26 @@ #define EXYNOS5440_TMU_TH_RISE4_SHIFT24 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 +/* Exynos7 specific registers */ +#define EXYNOS7_THD_TEMP_RISE7_6 0x50 +#define EXYNOS7_THD_TEMP_FALL7_6 0x60 +#define EXYNOS7_TMU_REG_INTEN0x110 +#define EXYNOS7_TMU_REG_INTPEND 0x118 +#define EXYNOS7_TMU_REG_EMUL_CON 0x160 + +#define EXYNOS7_TMU_TEMP_MASK0x1ff +#define EXYNOS7_PD_DET_EN_SHIFT 23 +#define EXYNOS7_TMU_INTEN_RISE0_SHIFT0 +#define EXYNOS7_TMU_INTEN_RISE1_SHIFT1 +#define EXYNOS7_TMU_INTEN_RISE2_SHIFT2 +#define EXYNOS7_TMU_INTEN_RISE3_SHIFT3 +#define EXYNOS7_TMU_INTEN_RISE4_SHIFT4 +#define EXYNOS7_TMU_INTEN_RISE5_SHIFT5 +#define EXYNOS7_TMU_INTEN_RISE6_SHIFT6 +#define EXYNOS7_TMU_INTEN_RISE7_SHIFT7 +#define EXYNOS7_EMUL_DATA_SHIFT 7 +#define EXYNOS7_EMUL_DATA_MASK 0x1ff + #define MCELSIUS 1000 /** * struct exynos_tmu_data : A structure to hold the private data of the TMU @@ -133,6 +153,7 @@ * @lock: lock to implement synchronization. * @clk: pointer to the clock structure. * @clk_sec: pointer to the clock structure for accessing the base_second. + * @sclk: pointer to the clock structure for accessing the tmu special clk. * @temp_error1: fused value of the first
Re: [PATCH 1/2] thermal: exynos: Reorder exynos_map_dt_data() function
Hi Lukasz,
On Fri, Jan 30, 2015 at 1:44 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Eduardo, Abhilash,
On Thu, Jan 22, 2015 at 06:02:07PM +0530, Abhilash Kesavan wrote:
Hi Lukasz,
On Thu, Jan 22, 2015 at 2:31 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Abhilash,
Hi Lukasz,
On Mon, Jan 19, 2015 at 5:14 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
The exynos_map_dt_data() function must be called before
thermal_zone_of_sensor_register(), and hence provide tmu_read()
function, before it is needed.
This change is driven by adding support for enabling
thermal_zoneX when it is properly initialized.
One can read the mode of operation
at /sys/class/thermal/thermal_zone0/mode Such functionality was
missing in the of-thermal.c code.
Reported-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 9d2d685..5d946ab
100644 --- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -975,15 +975,16 @@ static int exynos_tmu_probe(struct
platform_device *pdev) platform_set_drvdata(pdev, data);
mutex_init(data-lock);
+ ret = exynos_map_dt_data(pdev);
+ if (ret)
+ goto err_sensor;
+
data-tzd =
thermal_zone_of_sensor_register(pdev-dev, 0, data,
exynos_sensor_ops); if (IS_ERR(data-tzd)) {
pr_err(thermal: tz: %p ERROR\n, data-tzd);
return PTR_ERR(data-tzd);
}
- ret = exynos_map_dt_data(pdev);
- if (ret)
- goto err_sensor;
pdata = data-pdata;
I have been testing this along with your v5 patch set and am
seeing incorrect temperature being reported at boot-up on
exynos7.
Does it show a maximal temperature value (0x1FF)?
I did not print the current temperature register, but I remember the
message showing ~105C. Will give you the register value when I test
with more debug prints tomorrow.
It looks
like exynos_tmu_read gets called from
thermal_zone_of_device_update during boot-up, now that we have
it populated early. However, as the tmu initialization function
has not been called yet it returns a wrong value. Does that
sound correct ?
No, this is a mistake. However, I'm wondering why on Exynos4/5
this error didn't show up...
I have been lowering the software trip point temperature in the
exynos7 dts file (to 55C) for testing purposes. Hence, when the
temperature is read incorrectly as ~105C the board trips at boot-up
this is a very unusual
value - I had problems with
reading 0xFF values with
similar symptom (but this was
caused by lack of vtmu).
itself. Maybe for exynos4/5 the incorrect value read during boot-up
is in the non-tripping range and once the tmu is initialized later
it continues to function properly thereafter ?
The reordering is needed to be able to call set_mode callback at
of-thermal.c to set the mode.
If this change causes problems, then another solution (probably
not so neat) must be found.
Please let me know if you need any further details.
Abhilash, could you provide more details (like relevant output from
dmesg) and point me a list of patches which shall I apply to test this
issue on Exynos4/5?
Sorry, I have not had the time to re-check this and provide you with
the current temperature register value. I will definitely do so on
Monday and also provide you the dmesg output. I applied the following
patches on linux-next:
bbf872d thermal: exynos: Add TMU support for Exynos7 SoC
b8190ac dts: Documentation: Add documentation for Exynos7 SoC thermal bindings
9330ec1 thermal: exynos: Reorder exynos_map_dt_data() function
4dd41c4 thermal: exynos: dts: Provide device tree bindings identical
to the one in exynos_tmu_data.c
a7b80b9 thermal: dts: exynos: Trip points and sensor configuration
data for Exynos5440
77d072e thermal: exynos: dts: Define default thermal-zones for Exynos4
964dd36 thermal: dts: Default trip points definition for Exynos5420 SoCs
c1d2f97 thermal: exynos: dts: Add default definition of the TMU sensor parameter
02a4496 arm: dts: Adding CPU cooling binding for Exynos SoCs
bfadff0 arm: dts: odroid: Enable TMU at Exynos4412 based Odroid U3 device
862764c arm: dts: odroid: Add LDO10 regulator node necessary for TMU on Odroid
c064731 arm: dts: trats: Enable TMU on the Exynos4210 trats device
Along with the above list
Re: [PATCH v4 2/2] thermal: exynos: Add TMU support for Exynos7 SoC
Hi Lukasz,
On Thu, Jan 29, 2015 at 1:56 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Abhilash,
Add registers, bit fields and compatible strings for Exynos7 TMU
(Thermal Management Unit). Following are a few of the differences
in the Exynos7 TMU from earlier SoCs:
- 8 trigger levels
- Different bit offsets and more registers for the rising
and falling thresholds.
- New power down detection bit in the TMU_CONTROL register
which does not update the CURRENT_TEMP0 when tmu power down
is detected.
- Change in bit offset for the NEXT_DATA field of EMUL_CON
register. EMUL_CON register address has also changed.
- INTSTAT and INTCLEAR registers present in earlier SoCs
have been combined into one INTPEND register. The register
address for INTCLEAR and INTPEND is also different.
- Since there are 8 rising/falling interrupts as against
at most 4 in earlier SoCs the INTEN bit offsets are different.
- Multiple probe support which is handled by a TMU_CONTROL1
register (No support for this in the current patch).
This patch adds special clock support required only for Exynos7. It
also updates the code_to_temp prototype as Exynos7 has 9 bit
code-temp mapping.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
This patch set has been tested on linux next-20150123 with Eduardo's
thermal-next branch merged along with the arch-side exynos7 related
dts changes applied.
Changes since v3:
Addressed comments from Lukasz Majewski:
- Added more comments in the code setting the thresholds.
- Split the documentation out into another patch.
Changes since v2:
- Rebased on top of Lukasz' latest exynos tmu series (v4).
- Added new exynos7 soc_type.
Changes since v1:
- Rebased on top of Lukasz' latest exynos tmu series (v2).
- Added sclk support to patch adding Exynos7 tmu support.
Previously, it was a separate patch.
- Used the SOC type to decide if sclk is present.
drivers/thermal/samsung/exynos_tmu.c | 204
--
drivers/thermal/samsung/exynos_tmu.h |1 + 2 files changed, 197
insertions(+), 8 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 852e622..660ff69 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -119,6 +119,26 @@
#define EXYNOS5440_TMU_TH_RISE4_SHIFT24
#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
+/* Exynos7 specific registers */
+#define EXYNOS7_THD_TEMP_RISE7_6 0x50
+#define EXYNOS7_THD_TEMP_FALL7_6 0x60
+#define EXYNOS7_TMU_REG_INTEN0x110
+#define EXYNOS7_TMU_REG_INTPEND 0x118
+#define EXYNOS7_TMU_REG_EMUL_CON 0x160
+
+#define EXYNOS7_TMU_TEMP_MASK0x1ff
+#define EXYNOS7_PD_DET_EN_SHIFT 23
+#define EXYNOS7_TMU_INTEN_RISE0_SHIFT0
+#define EXYNOS7_TMU_INTEN_RISE1_SHIFT1
+#define EXYNOS7_TMU_INTEN_RISE2_SHIFT2
+#define EXYNOS7_TMU_INTEN_RISE3_SHIFT3
+#define EXYNOS7_TMU_INTEN_RISE4_SHIFT4
+#define EXYNOS7_TMU_INTEN_RISE5_SHIFT5
+#define EXYNOS7_TMU_INTEN_RISE6_SHIFT6
+#define EXYNOS7_TMU_INTEN_RISE7_SHIFT7
+#define EXYNOS7_EMUL_DATA_SHIFT 7
+#define EXYNOS7_EMUL_DATA_MASK 0x1ff
+
#define MCELSIUS 1000
/**
* struct exynos_tmu_data : A structure to hold the private data of
the TMU @@ -133,6 +153,7 @@
* @lock: lock to implement synchronization.
* @clk: pointer to the clock structure.
* @clk_sec: pointer to the clock structure for accessing the
base_second.
+ * @sclk: pointer to the clock structure for accessing the tmu
special clk.
* @temp_error1: fused value of the first point trim.
* @temp_error2: fused value of the second point trim.
* @regulator: pointer to the TMU regulator structure.
@@ -152,8 +173,8 @@ struct exynos_tmu_data {
enum soc_type soc;
struct work_struct irq_work;
struct mutex lock;
- struct clk *clk, *clk_sec;
- u8 temp_error1, temp_error2;
+ struct clk *clk, *clk_sec, *sclk;
+ u16 temp_error1, temp_error2;
struct regulator *regulator;
struct thermal_zone_device *tzd;
@@ -223,7 +244,7 @@ static int temp_to_code(struct exynos_tmu_data
*data, u8 temp)
* Calculate a temperature value from a temperature code.
* The unit of the temperature is degree Celsius.
*/
-static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
+static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
{
struct exynos_tmu_platform_data *pdata = data-pdata;
int temp;
@@ -513,6 +534,84 @@ static int
Re: [PATCH v4 1/2] dts: Documentation: Add documentation for Exynos7 SoC thermal bindings
Hi Eduardo, On Tue, Jan 27, 2015 at 11:18 AM, Abhilash Kesavan a.kesa...@samsung.com wrote: Add documentation for exynos7 thermal bindings including compatible name and special clock properties. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- .../devicetree/bindings/thermal/exynos-thermal.txt |4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 0f44932..695150a 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -12,6 +12,7 @@ samsung,exynos5420-tmu-ext-triminfo for TMU channels 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) samsung,exynos5440-tmu + samsung,exynos7-tmu - interrupt-parent : The phandle for the interrupt controller - reg : Address range of the thermal registers. For soc's which has multiple instances of TMU and some registers are shared across all TMU's like @@ -32,10 +33,13 @@ - clocks : The main clocks for TMU device -- 1. operational clock for TMU channel -- 2. optional clock to access the shared registers of TMU channel + -- 3. optional special clock for functional operation - clock-names : Thermal system clock name -- tmu_apbif operational clock for current TMU channel -- tmu_triminfo_apbif clock to access the shared triminfo register for current TMU channel + -- tmu_sclk clock for functional operation of the current TMU + channel - vtmu-supply: This entry is optional and provides the regulator node supplying voltage to TMU. If needed this entry can be placed inside board/platform specific dts file. Can you kindly consider applying these two patches to your next tree if they look OK ? Regards, Abhilash -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/2] dts: Documentation: Add documentation for Exynos7 SoC thermal bindings
Add documentation for exynos7 thermal bindings including compatible name and special clock properties. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- .../devicetree/bindings/thermal/exynos-thermal.txt |4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 0f44932..695150a 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -12,6 +12,7 @@ samsung,exynos5420-tmu-ext-triminfo for TMU channels 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) samsung,exynos5440-tmu + samsung,exynos7-tmu - interrupt-parent : The phandle for the interrupt controller - reg : Address range of the thermal registers. For soc's which has multiple instances of TMU and some registers are shared across all TMU's like @@ -32,10 +33,13 @@ - clocks : The main clocks for TMU device -- 1. operational clock for TMU channel -- 2. optional clock to access the shared registers of TMU channel + -- 3. optional special clock for functional operation - clock-names : Thermal system clock name -- tmu_apbif operational clock for current TMU channel -- tmu_triminfo_apbif clock to access the shared triminfo register for current TMU channel + -- tmu_sclk clock for functional operation of the current TMU + channel - vtmu-supply: This entry is optional and provides the regulator node supplying voltage to TMU. If needed this entry can be placed inside board/platform specific dts file. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/2] thermal: exynos: Add TMU support for Exynos7 SoC
Add registers, bit fields and compatible strings for Exynos7 TMU
(Thermal Management Unit). Following are a few of the differences
in the Exynos7 TMU from earlier SoCs:
- 8 trigger levels
- Different bit offsets and more registers for the rising
and falling thresholds.
- New power down detection bit in the TMU_CONTROL register
which does not update the CURRENT_TEMP0 when tmu power down
is detected.
- Change in bit offset for the NEXT_DATA field of EMUL_CON
register. EMUL_CON register address has also changed.
- INTSTAT and INTCLEAR registers present in earlier SoCs
have been combined into one INTPEND register. The register
address for INTCLEAR and INTPEND is also different.
- Since there are 8 rising/falling interrupts as against
at most 4 in earlier SoCs the INTEN bit offsets are different.
- Multiple probe support which is handled by a TMU_CONTROL1
register (No support for this in the current patch).
This patch adds special clock support required only for Exynos7. It
also updates the code_to_temp prototype as Exynos7 has 9 bit
code-temp mapping.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
This patch set has been tested on linux next-20150123 with Eduardo's
thermal-next branch merged along with the arch-side exynos7 related
dts changes applied.
Changes since v3:
Addressed comments from Lukasz Majewski:
- Added more comments in the code setting the thresholds.
- Split the documentation out into another patch.
Changes since v2:
- Rebased on top of Lukasz' latest exynos tmu series (v4).
- Added new exynos7 soc_type.
Changes since v1:
- Rebased on top of Lukasz' latest exynos tmu series (v2).
- Added sclk support to patch adding Exynos7 tmu support.
Previously, it was a separate patch.
- Used the SOC type to decide if sclk is present.
drivers/thermal/samsung/exynos_tmu.c | 204 --
drivers/thermal/samsung/exynos_tmu.h |1 +
2 files changed, 197 insertions(+), 8 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index 852e622..660ff69 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -119,6 +119,26 @@
#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
+/* Exynos7 specific registers */
+#define EXYNOS7_THD_TEMP_RISE7_6 0x50
+#define EXYNOS7_THD_TEMP_FALL7_6 0x60
+#define EXYNOS7_TMU_REG_INTEN 0x110
+#define EXYNOS7_TMU_REG_INTPEND0x118
+#define EXYNOS7_TMU_REG_EMUL_CON 0x160
+
+#define EXYNOS7_TMU_TEMP_MASK 0x1ff
+#define EXYNOS7_PD_DET_EN_SHIFT23
+#define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
+#define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1
+#define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2
+#define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3
+#define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4
+#define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5
+#define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6
+#define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7
+#define EXYNOS7_EMUL_DATA_SHIFT7
+#define EXYNOS7_EMUL_DATA_MASK 0x1ff
+
#define MCELSIUS 1000
/**
* struct exynos_tmu_data : A structure to hold the private data of the TMU
@@ -133,6 +153,7 @@
* @lock: lock to implement synchronization.
* @clk: pointer to the clock structure.
* @clk_sec: pointer to the clock structure for accessing the base_second.
+ * @sclk: pointer to the clock structure for accessing the tmu special clk.
* @temp_error1: fused value of the first point trim.
* @temp_error2: fused value of the second point trim.
* @regulator: pointer to the TMU regulator structure.
@@ -152,8 +173,8 @@ struct exynos_tmu_data {
enum soc_type soc;
struct work_struct irq_work;
struct mutex lock;
- struct clk *clk, *clk_sec;
- u8 temp_error1, temp_error2;
+ struct clk *clk, *clk_sec, *sclk;
+ u16 temp_error1, temp_error2;
struct regulator *regulator;
struct thermal_zone_device *tzd;
@@ -223,7 +244,7 @@ static int temp_to_code(struct exynos_tmu_data *data, u8
temp)
* Calculate a temperature value from a temperature code.
* The unit of the temperature is degree Celsius.
*/
-static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
+static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
{
struct exynos_tmu_platform_data *pdata = data-pdata;
int temp;
@@ -513,6 +534,84 @@ static int exynos5440_tmu_initialize(struct
platform_device *pdev)
return ret;
}
+static int exynos7_tmu_initialize(struct platform_device *pdev)
+{
+ struct exynos_tmu_data *data = platform_get_drvdata(pdev
Re: [PATCH 1/2] thermal: exynos: Reorder exynos_map_dt_data() function
Hi Lukasz,
On Thu, Jan 22, 2015 at 2:31 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Abhilash,
Hi Lukasz,
On Mon, Jan 19, 2015 at 5:14 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
The exynos_map_dt_data() function must be called before
thermal_zone_of_sensor_register(), and hence provide tmu_read()
function, before it is needed.
This change is driven by adding support for enabling thermal_zoneX
when it is properly initialized.
One can read the mode of operation
at /sys/class/thermal/thermal_zone0/mode Such functionality was
missing in the of-thermal.c code.
Reported-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c index 9d2d685..5d946ab 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -975,15 +975,16 @@ static int exynos_tmu_probe(struct
platform_device *pdev) platform_set_drvdata(pdev, data);
mutex_init(data-lock);
+ ret = exynos_map_dt_data(pdev);
+ if (ret)
+ goto err_sensor;
+
data-tzd = thermal_zone_of_sensor_register(pdev-dev, 0,
data, exynos_sensor_ops);
if (IS_ERR(data-tzd)) {
pr_err(thermal: tz: %p ERROR\n, data-tzd);
return PTR_ERR(data-tzd);
}
- ret = exynos_map_dt_data(pdev);
- if (ret)
- goto err_sensor;
pdata = data-pdata;
I have been testing this along with your v5 patch set and am seeing
incorrect temperature being reported at boot-up on exynos7.
Does it show a maximal temperature value (0x1FF)?
I did not print the current temperature register, but I remember the
message showing ~105C. Will give you the register value when I test
with more debug prints tomorrow.
It looks
like exynos_tmu_read gets called from thermal_zone_of_device_update
during boot-up, now that we have it populated early. However, as the
tmu initialization function has not been called yet it returns a wrong
value. Does that sound correct ?
No, this is a mistake. However, I'm wondering why on Exynos4/5 this
error didn't show up...
I have been lowering the software trip point temperature in the
exynos7 dts file (to 55C) for testing purposes. Hence, when the
temperature is read incorrectly as ~105C the board trips at boot-up
itself. Maybe for exynos4/5 the incorrect value read during boot-up is
in the non-tripping range and once the tmu is initialized later it
continues to function properly thereafter ?
The reordering is needed to be able to call set_mode callback at
of-thermal.c to set the mode.
If this change causes problems, then another solution (probably not so
neat) must be found.
Please let me know if you need any further details.
Thanks,
Abhilash
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Re: [PATCH 1/2] thermal: exynos: Reorder exynos_map_dt_data() function
Hi Lukasz,
On Mon, Jan 19, 2015 at 5:14 PM, Lukasz Majewski l.majew...@samsung.com wrote:
The exynos_map_dt_data() function must be called before
thermal_zone_of_sensor_register(), and hence provide tmu_read() function,
before it is needed.
This change is driven by adding support for enabling thermal_zoneX when
it is properly initialized.
One can read the mode of operation at /sys/class/thermal/thermal_zone0/mode
Such functionality was missing in the of-thermal.c code.
Reported-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
drivers/thermal/samsung/exynos_tmu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index 9d2d685..5d946ab 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -975,15 +975,16 @@ static int exynos_tmu_probe(struct platform_device
*pdev)
platform_set_drvdata(pdev, data);
mutex_init(data-lock);
+ ret = exynos_map_dt_data(pdev);
+ if (ret)
+ goto err_sensor;
+
data-tzd = thermal_zone_of_sensor_register(pdev-dev, 0, data,
exynos_sensor_ops);
if (IS_ERR(data-tzd)) {
pr_err(thermal: tz: %p ERROR\n, data-tzd);
return PTR_ERR(data-tzd);
}
- ret = exynos_map_dt_data(pdev);
- if (ret)
- goto err_sensor;
pdata = data-pdata;
I have been testing this along with your v5 patch set and am seeing
incorrect temperature being reported at boot-up on exynos7. It looks
like exynos_tmu_read gets called from thermal_zone_of_device_update
during boot-up, now that we have it populated early. However, as the
tmu initialization function has not been called yet it returns a wrong
value. Does that sound correct ?
Regards,
Abhilash
--
2.0.0.rc2
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Re: [PATCH v3] thermal: exynos: Add TMU support for Exynos7 SoC
Hi Lukasz, On Mon, Jan 19, 2015 at 6:34 PM, Lukasz Majewski l.majew...@samsung.com wrote: Hi Abhilash, Add registers, bit fields and compatible strings for Exynos7 TMU (Thermal Management Unit). Following are a few of the differences in the Exynos7 TMU from earlier SoCs: - 8 trigger levels - Different bit offsets and more registers for the rising and falling thresholds. - New power down detection bit in the TMU_CONTROL register which does not update the CURRENT_TEMP0 when tmu power down is detected. - Change in bit offset for the NEXT_DATA field of EMUL_CON register. EMUL_CON register address has also changed. - INTSTAT and INTCLEAR registers present in earlier SoCs have been combined into one INTPEND register. The register address for INTCLEAR and INTPEND is also different. - Since there are 8 rising/falling interrupts as against at most 4 in earlier SoCs the INTEN bit offsets are different. - Multiple probe support which is handled by a TMU_CONTROL1 register (No support for this in the current patch). This patch adds special clock support required only for Exynos7 and updates the bindings documentation appropriately. It also updates the code_to_temp prototype as Exynos7 has 9 bit code-temp mapping. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- This patch is based on Lukasz Majewski's Exynos TMU v4 patchset: http://www.spinics.net/lists/linux-samsung-soc/msg41183.html Changes since v2: - Rebased on top of Lukasz' latest exynos tmu series (v4). - Added new exynos7 soc_type. Changes since v1: - Rebased on top of Lukasz' latest exynos tmu series (v2). - Added sclk support to patch adding Exynos7 tmu support. Previously, it was a separate patch. - Used the SOC type to decide if sclk is present. .../devicetree/bindings/thermal/exynos-thermal.txt |4 + drivers/thermal/samsung/exynos_tmu.c | 203 +++- drivers/thermal/samsung/exynos_tmu.h |1 + 3 files changed, 199 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 0f44932..695150a 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -12,6 +12,7 @@ samsung,exynos5420-tmu-ext-triminfo for TMU channels 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) samsung,exynos5440-tmu +samsung,exynos7-tmu - interrupt-parent : The phandle for the interrupt controller - reg : Address range of the thermal registers. For soc's which has multiple instances of TMU and some registers are shared across all TMU's like @@ -32,10 +33,13 @@ - clocks : The main clocks for TMU device -- 1. operational clock for TMU channel -- 2. optional clock to access the shared registers of TMU channel + -- 3. optional special clock for functional operation - clock-names : Thermal system clock name -- tmu_apbif operational clock for current TMU channel -- tmu_triminfo_apbif clock to access the shared triminfo register for current TMU channel + -- tmu_sclk clock for functional operation of the current TMU + channel - vtmu-supply: This entry is optional and provides the regulator node supplying voltage to TMU. If needed this entry can be placed inside board/platform specific dts file. I would recommend splitting the documentation from the code. IMHO it would be more readable. I will split the documentation out into a separate patch. diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 633a9e2..8b26acb 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -119,6 +119,26 @@ #define EXYNOS5440_TMU_TH_RISE4_SHIFT24 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 +/* Exynos7 specific registers */ +#define EXYNOS7_THD_TEMP_RISE7_6 0x50 +#define EXYNOS7_THD_TEMP_FALL7_6 0x60 +#define EXYNOS7_TMU_REG_INTEN0x110 +#define EXYNOS7_TMU_REG_INTPEND 0x118 ^ I suppose that this misalignment is only done by my mail client and checkpatch is not complaining. I re-ran checkpatch and it did not report any warnings, so perhaps it is your e-mail client. +#define EXYNOS7_TMU_REG_EMUL_CON 0x160 + +#define EXYNOS7_TMU_TEMP_MASK0x1ff +#define EXYNOS7_PD_DET_EN_SHIFT
[PATCH v3] thermal: exynos: Add TMU support for Exynos7 SoC
Add registers, bit fields and compatible strings for Exynos7 TMU (Thermal Management Unit). Following are a few of the differences in the Exynos7 TMU from earlier SoCs: - 8 trigger levels - Different bit offsets and more registers for the rising and falling thresholds. - New power down detection bit in the TMU_CONTROL register which does not update the CURRENT_TEMP0 when tmu power down is detected. - Change in bit offset for the NEXT_DATA field of EMUL_CON register. EMUL_CON register address has also changed. - INTSTAT and INTCLEAR registers present in earlier SoCs have been combined into one INTPEND register. The register address for INTCLEAR and INTPEND is also different. - Since there are 8 rising/falling interrupts as against at most 4 in earlier SoCs the INTEN bit offsets are different. - Multiple probe support which is handled by a TMU_CONTROL1 register (No support for this in the current patch). This patch adds special clock support required only for Exynos7 and updates the bindings documentation appropriately. It also updates the code_to_temp prototype as Exynos7 has 9 bit code-temp mapping. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- This patch is based on Lukasz Majewski's Exynos TMU v4 patchset: http://www.spinics.net/lists/linux-samsung-soc/msg41183.html Changes since v2: - Rebased on top of Lukasz' latest exynos tmu series (v4). - Added new exynos7 soc_type. Changes since v1: - Rebased on top of Lukasz' latest exynos tmu series (v2). - Added sclk support to patch adding Exynos7 tmu support. Previously, it was a separate patch. - Used the SOC type to decide if sclk is present. .../devicetree/bindings/thermal/exynos-thermal.txt |4 + drivers/thermal/samsung/exynos_tmu.c | 203 +++- drivers/thermal/samsung/exynos_tmu.h |1 + 3 files changed, 199 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 0f44932..695150a 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -12,6 +12,7 @@ samsung,exynos5420-tmu-ext-triminfo for TMU channels 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) samsung,exynos5440-tmu + samsung,exynos7-tmu - interrupt-parent : The phandle for the interrupt controller - reg : Address range of the thermal registers. For soc's which has multiple instances of TMU and some registers are shared across all TMU's like @@ -32,10 +33,13 @@ - clocks : The main clocks for TMU device -- 1. operational clock for TMU channel -- 2. optional clock to access the shared registers of TMU channel + -- 3. optional special clock for functional operation - clock-names : Thermal system clock name -- tmu_apbif operational clock for current TMU channel -- tmu_triminfo_apbif clock to access the shared triminfo register for current TMU channel + -- tmu_sclk clock for functional operation of the current TMU + channel - vtmu-supply: This entry is optional and provides the regulator node supplying voltage to TMU. If needed this entry can be placed inside board/platform specific dts file. diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 633a9e2..8b26acb 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -119,6 +119,26 @@ #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 +/* Exynos7 specific registers */ +#define EXYNOS7_THD_TEMP_RISE7_6 0x50 +#define EXYNOS7_THD_TEMP_FALL7_6 0x60 +#define EXYNOS7_TMU_REG_INTEN 0x110 +#define EXYNOS7_TMU_REG_INTPEND0x118 +#define EXYNOS7_TMU_REG_EMUL_CON 0x160 + +#define EXYNOS7_TMU_TEMP_MASK 0x1ff +#define EXYNOS7_PD_DET_EN_SHIFT23 +#define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 +#define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 +#define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 +#define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 +#define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 +#define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 +#define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 +#define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 +#define EXYNOS7_EMUL_DATA_SHIFT7 +#define EXYNOS7_EMUL_DATA_MASK 0x1ff + #define MCELSIUS 1000 /** * struct exynos_tmu_data : A structure to hold the private data of the TMU @@ -133,6 +153,7
[PATCH 2/2] arm: dts: disable CCI on exynos420 based arndale-octa
The arndale-octa board was giving imprecise external aborts during
boot-up with MCPM enabled. CCI enablement of the boot cluster was found
to be the cause of these aborts (possibly because the secure f/w was not
allowing it). Hence, disable CCI for the arndale-octa board.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Tested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Tested-by: Kevin Hilman khil...@linaro.org
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index aa7a7d7..db2c1c4 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -372,3 +372,7 @@
usbdrd_dwc3_1 {
dr_mode = host;
};
+
+cci {
+ status = disabled;
+};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..0a82ae7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -120,7 +120,7 @@
};
};
- cci@10d2 {
+ cci: cci@10d2 {
compatible = arm,cci-400;
#address-cells = 1;
#size-cells = 1;
--
2.2.0
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[PATCH 1/2] drivers: bus: check cci device tree node status
The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Acked-by: Sudeep Holla sudeep.ho...@arm.com Acked-by: Nicolas Pitre n...@linaro.org Tested-by: Sudeep Holla sudeep.ho...@arm.com Tested-by: Kevin Hilman khil...@linaro.org --- Changes: - Re-sending without the RFT tags drivers/bus/arm-cci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 860da40..0ce5e2d 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1312,6 +1312,9 @@ static int cci_probe(void) if (!np) return -ENODEV; + if (!of_device_is_available(np)) + return -ENODEV; + cci_config = of_match_node(arm_cci_matches, np)-data; if (!cci_config) return -ENODEV; -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Hi Kevin, On Sat, Jan 10, 2015 at 2:39 AM, Kevin Hilman khil...@kernel.org wrote: Abhilash Kesavan kesavan.abhil...@gmail.com writes: Hi Arnd/Olof, On Fri, Jan 9, 2015 at 10:40 AM, Sudeep Holla sudeep.ho...@arm.com wrote: On Thursday 08 January 2015 08:57 PM, Abhilash Kesavan wrote: Hi Sudeep, On Thu, Jan 8, 2015 at 12:15 PM, Sudeep Holla sudeep.ho...@arm.com wrote: Hi Abhilash, [...] What's the status of this patch. It was useful for me on vexpress for some testing. Please feel free to add Tested-by: Sudeep Holla sudeep.ho...@arm.com if this is not yet queued. Thanks for the tested-by. This patch has not been merged yet; I am not quite sure who is supposed to pick this up. So far, most of the CCI patches are merged through arm-soc. Would you be OK picking this up as is or do you want me to re-send this with the RFT tag dropped ? Please resend without the RFT, and collect the Tested-by tags you can add mine: Tested-by: Kevin Hilman khil...@linaro.org Please send to a...@kernel.org where patches targeted for the arm-soc tree are collected. I have done as suggested. Kindly check. Regards, Abhilash Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Hi Arnd/Olof, On Fri, Jan 9, 2015 at 10:40 AM, Sudeep Holla sudeep.ho...@arm.com wrote: On Thursday 08 January 2015 08:57 PM, Abhilash Kesavan wrote: Hi Sudeep, On Thu, Jan 8, 2015 at 12:15 PM, Sudeep Holla sudeep.ho...@arm.com wrote: Hi Abhilash, [...] What's the status of this patch. It was useful for me on vexpress for some testing. Please feel free to add Tested-by: Sudeep Holla sudeep.ho...@arm.com if this is not yet queued. Thanks for the tested-by. This patch has not been merged yet; I am not quite sure who is supposed to pick this up. So far, most of the CCI patches are merged through arm-soc. Would you be OK picking this up as is or do you want me to re-send this with the RFT tag dropped ? Regards, Abhilash Regards, Sudeep -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/17] thermal: exynos: Thermal code rework to use device tree
Hi Lukasz, On Mon, Dec 22, 2014 at 9:51 PM, Lukasz Majewski l.majew...@samsung.com wrote: Hi Abhilash, Hi Lukasz and Eduardo, [...] Although, this shouldn't be a problem. That is why we had the cycle with cpufreq folks, remember? (I will have a look in your patches) It would be great if those patches could find their way to therma -next. Then also Abhilash could benefit from them. I have a couple of 5420/5800 based chromebooks that I will test this series on. Is it OK for me to start basing my Exynos7 TMU support on this series ? Please let me know if I can help in any other way with this. I'm fine if you rebase on top of my patches. However, it is up to Eduardo when he decides to pull them to -next branch. I hope that it will happen soon. I tested a Peach Pit (5420 based chromebook) with your patches and they work well (temperatures and software tripping). However, my earlier comments with regards to duplicate exynos_tmu_initialize() and the thermal zone showing as disabled in sysfs . Also, I think the documentation for the dt properties are missing ? I will post my exynos7 work based on your patches soon. Please take a look. Regards, Abhilash Regards, Abhilash -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/17] thermal: exynos: Thermal code rework to use device tree
Hi Lukasz and Eduardo, [...] Although, this shouldn't be a problem. That is why we had the cycle with cpufreq folks, remember? (I will have a look in your patches) It would be great if those patches could find their way to therma -next. Then also Abhilash could benefit from them. I have a couple of 5420/5800 based chromebooks that I will test this series on. Is it OK for me to start basing my Exynos7 TMU support on this series ? Please let me know if I can help in any other way with this. Regards, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Hi, On Fri, Nov 28, 2014 at 8:20 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com This patch helps disable CCI on the Arndale Octa board thus resolving some imprecise aborts seen on that board. Kindly review. Regards, Abhilash --- drivers/bus/arm-cci.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 860da40..0ce5e2d 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1312,6 +1312,9 @@ static int cci_probe(void) if (!np) return -ENODEV; + if (!of_device_is_available(np)) + return -ENODEV; + cci_config = of_match_node(arm_cci_matches, np)-data; if (!cci_config) return -ENODEV; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFT 1/2] drivers: bus: check cci device tree node status
Hi Sudeep, On Wed, Dec 10, 2014 at 9:44 AM, Sudeep Holla sudeep.ho...@arm.com wrote: Hi Abhilash, On Wednesday 10 December 2014 09:31 AM, Abhilash Kesavan wrote: Hi, On Fri, Nov 28, 2014 at 8:20 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com This patch helps disable CCI on the Arndale Octa board thus resolving some imprecise aborts seen on that board. Kindly review. Regards, Abhilash --- drivers/bus/arm-cci.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 860da40..0ce5e2d 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1312,6 +1312,9 @@ static int cci_probe(void) if (!np) return -ENODEV; + if (!of_device_is_available(np)) + return -ENODEV; + IIUC, by this change you are disabling the MCPM boot protocol here. Is there any alternative boot protocol that works on this platform to boot all 8 cores ? Sorry by quick grep couldn't find one, hence so I am asking. Thanks for the reply. On disabling MCPM, we will default to platsmp.c/firmware.c which boots 4 cores as per Kevin's comment here[1]. This was the original behavior before MCPM was enabled for all 5420 based SoCs. Regards, Abhilash [1] http://www.spinics.net/lists/arm-kernel/msg381191.html Regards, Sudeep -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFT 1/2] drivers: bus: check cci device tree node status
The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- drivers/bus/arm-cci.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 860da40..0ce5e2d 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1312,6 +1312,9 @@ static int cci_probe(void) if (!np) return -ENODEV; + if (!of_device_is_available(np)) + return -ENODEV; + cci_config = of_match_node(arm_cci_matches, np)-data; if (!cci_config) return -ENODEV; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFT 2/2] arm: dts: disable CCI on exynos420 based arndale-octa
The arndale-octa board was giving imprecise external aborts during
boot-up with MCPM enabled. CCI enablement of the boot cluster was found
to be the cause of these aborts (possibly because the secure f/w was not
allowing it). Hence, disable CCI for the arndale-octa board.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts |4
arch/arm/boot/dts/exynos5420.dtsi |2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index aa7a7d7..db2c1c4 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -372,3 +372,7 @@
usbdrd_dwc3_1 {
dr_mode = host;
};
+
+cci {
+ status = disabled;
+};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..0a82ae7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -120,7 +120,7 @@
};
};
- cci@10d2 {
+ cci: cci@10d2 {
compatible = arm,cci-400;
#address-cells = 1;
#size-cells = 1;
--
1.7.9.5
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Re: [PATCH RFT 2/2] arm: dts: disable CCI on exynos420 based arndale-octa
Hello Krzysztof, On Fri, Nov 28, 2014 at 8:49 PM, Krzysztof Kozlowski k.kozlow...@samsung.com wrote: On pią, 2014-11-28 at 20:20 +0530, Abhilash Kesavan wrote: The arndale-octa board was giving imprecise external aborts during boot-up with MCPM enabled. CCI enablement of the boot cluster was found to be the cause of these aborts (possibly because the secure f/w was not allowing it). Hence, disable CCI for the arndale-octa board. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- arch/arm/boot/dts/exynos5420-arndale-octa.dts |4 arch/arm/boot/dts/exynos5420.dtsi |2 +- 2 files changed, 5 insertions(+), 1 deletion(-) I tested these 2 patches on Arndale Octa but there are no improvements. I still got imprecise aborts (some not fatal and sometimes killing init with full backtrace). Thanks for testing. Are you testing this with exynos_defconfig with no other changes ? Can you please confirm from the bootlog that MCPM and CCI are not being initialized. Can you remove these 2 patches and on linux-next check if you are getting aborts even with 5420_MCPM disabled. Regards, Abhilash Tested on next-20141128. System booted from microSD (bootloader from Linaro Ubuntu Saucy server image): == U-Boot 2012.07 (Feb 15 2014 - 17:29:55) for ARNDALE OCTA CPU: Exynos5420 Rev2.0 [Samsung SOC on SMP Platform Base on ARM CortexA15] APLL = 800MHz, KPLL = 600MHz MPLL = 532MHz, BPLL = 800MHz Board: ARNDALE OCTA DRAM: 2 GiB WARNING: Caches not enabled TrustZone Enabled BSP BL1 version: Checking Boot Mode ... SDMMC MMC: S5P_MSHC2: 0, S5P_MSHC0: 1 MMC Device 0: 29.3 GiB MMC Device 1: 7.3 GiB MMC Device 2: MMC Device 2 not found there are pending interrupts 0x0001 In:serial Out: serial Err: serial Net: No ethernet found. (Re)start USB... USB: Register 1313 NbrPorts 3 USB EHCI 1.00 scanning bus for devices... The request port(2) is not configured The request port(2) is not configured 3 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 1 Ethernet Device(s) found Hit any key to stop autoboot: 0 ARNDALE # uTTY Unknown command 'uTTY' - try 'help' ARNDALE # run nn reading uImage 3674704 bytes read reading uInitrd 2330480 bytes read reading board.dtb 33680 bytes read ## Booting kernel from Legacy Image at 20007000 ... Image Name: Linux-exynos5420-arndale-octa Image Type: ARM Linux Kernel Image (uncompressed) Data Size:3674640 Bytes = 3.5 MiB Load Address: 41008000 Entry Point: 41008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 2200 ... Image Name: initramfs Image Type: ARM Linux RAMDisk Image (uncompressed) Data Size:2330416 Bytes = 2.2 MiB Load Address: Entry Point: Verifying Checksum ... OK ## Flattened Device Tree blob at 21f0 Booting using the fdt blob at 0x21f0 Loading Kernel Image ... OK OK Using Device Tree in place at 21f0, end 21f0b38f Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 3.18.0-rc6-next-20141128-7-g33b7bf7da133 (k.kozlowski@AMDC1943) (gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1) ) #24 SMP PREEMPT Fri Nov 28 16:13:43 CET 2014 [0.00] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d ... [ 12.874514] VFS: Mounted root (ext4 filesystem) readonly on device 179:67. [ 12.887392] devtmpfs: mounted [ 12.889321] Freeing unused kernel memory: 324K (c0669000 - c06ba000) [ 12.951241] Unhandled fault: imprecise external abort (0x406) at 0x [ 12.966312] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0007 [ 12.966312] [ 12.973980] CPU: 0 PID: 1 Comm: bash Tainted: GW 3.18.0-rc6-next-20141128-7-g33b7bf7da133 #24 [ 12.983938] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 12.990014] [c0014d44] (unwind_backtrace) from [c0011c88] (show_stack+0x10/0x14) [ 12.997723] [c0011c88] (show_stack) from [c048e82c] (dump_stack+0x70/0xbc) [ 13.004911] [c048e82c] (dump_stack) from [c048a8c0] (panic+0x94/0x20c) [ 13.011753] [c048a8c0] (panic) from [c0026500] (do_exit+0x944/0x988) [ 13.018424] [c0026500] (do_exit) from [c00265f4] (do_group_exit+0x3c/0xbc) [ 13.025621] [c00265f4] (do_group_exit) from [c0030d60] (get_signal+0x218/0x8c4) [ 13.033247] [c0030d60] (get_signal) from [c048a39c] (do_signal+0x84/0x350) [ 13.040438] [c048a39c] (do_signal) from [c00115ec] (do_work_pending+0xbc/0xcc) [ 13.047979] [c00115ec] (do_work_pending) from [c000f1f8] (work_pending+0xc/0x20) [ 13.055693] CPU1: stopping [ 13.058385] CPU: 1 PID: 0 Comm: swapper/1 Tainted: GW 3.18.0-rc6-next-20141128-7-g33b7bf7da133 #24 [ 13.068790] Hardware name: SAMSUNG EXYNOS
Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
Hi Kevin,
On Thu, Nov 27, 2014 at 12:11 AM, Nicolas Pitre
nicolas.pi...@linaro.org wrote:
On Wed, 26 Nov 2014, Kevin Hilman wrote:
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
[...]
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts go away.
I can't see how enabling snoops for the boot cluster is causing these
aborts. Perhaps as Krzysztof commented it has something to do with the
secure firmware/tz software on these boards ? Other than there does
not appear to be any difference between the working/non-working
setups.
Perhaps the secure firmware is preventing the CCI to be enabled by the
kernel, and that is causing the imprecise abort?
That is well possible.
Now.. if the bootloader/firmware does not let Linux deal with both
the CCI and caches then MCPM simply has no more purpose for this board.
The whole point of MCPM is actually to handle the CCI properly and the
most efficient way despite all the possible races and opportunities for
memory corruptions. And yes, this is a complex task.
So there is actually two choices: the firmware let Linux take care of it
via the MCPM layer (easy), or the firmware has to implement it all
_properly_ (hard) behind an interface such as PSCI, at which point MCPM
should be configured out.
If the firmware does not let Linux interact with the CCI _and_ does not
implement full MCPM-like services then the platform is broken and only a
firmware upgrade could fix that. It might still be possible to boot all
CPUs through other means, but power management would then be severely
limited.
How about restricting the mcpm initialization to only known working
boards like chromebooks and smdk. This would be better than disabling
the config altogether from exynos_defconfig. The non-working boards
would then default to platsmp. Assuming that the firmware handles all
CCI/cache activities then platsmp may work for secondary core boot-up
?
Can you please apply the below diff and test the non-working boards
with CONFIG_EXYNOS5420_MCPM enabled.
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index b0d3c2e..34d77bb 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -316,8 +316,9 @@ static void __init exynos_cache_off(void)
}
static const struct of_device_id exynos_dt_mcpm_match[] = {
- { .compatible = samsung,exynos5420 },
- { .compatible = samsung,exynos5800 },
+ { .compatible = samsung,smdk5420 },
+ { .compatible = google,pi },
+ { .compatible = google,pit },
{},
};
On a different note, I did not see any mainline support for Odroid
Xu3, are you testing this board with a non-mainline kernel ?
Regards,
Abhilash
Nicolas
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[PATCH 3/4] clk: samsung: add cpu clock support for Exynos7
The divider and mux register offsets and bits are different on
Exynos7 from the older SoCs. Add new pre/post rate change callbacks
for Exynos7 to handle these differences. To do this:
- Add a new exynos_cpuclk_soc_data structure that will hold
the SoC-specific pre/post rate change call-backs
- Modify exynos_register_cpu_clock() prototype to include a
node pointer
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.c| 130 +-
drivers/clk/samsung/clk-cpu.h| 33 -
drivers/clk/samsung/clk-exynos4.c|2 +-
drivers/clk/samsung/clk-exynos5250.c |2 +-
drivers/clk/samsung/clk-exynos5420.c |4 +-
5 files changed, 163 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 009a21b..6c00802 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -51,6 +51,13 @@
#define DIV_MASK_ALL 0x
#define MUX_MASK 7
+#define EXYNOS7_SRC_CPU0x208
+#define EXYNOS7_STAT_CPU 0x408
+#define EXYNOS7_DIV_CPU0 0x600
+#define EXYNOS7_DIV_CPU1 0x604
+#define EXYNOS7_DIV_STAT_CPU0 0x700
+#define EXYNOS7_DIV_STAT_CPU1 0x704
+
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
@@ -128,6 +135,88 @@ static void exynos_set_safe_div(void __iomem *base,
unsigned long div,
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
}
+static void exynos7_set_safe_div(void __iomem *base, unsigned long div,
+ unsigned long mask)
+{
+ unsigned long div0;
+
+ div0 = readl(base + EXYNOS7_DIV_CPU0);
+ div0 = (div0 ~mask) | (div mask);
+ writel(div0, base + EXYNOS7_DIV_CPU0);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, mask);
+}
+
+/* Exynos7 handler for pre-rate change notification from parent clock */
+static int exynos7_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk-cfg;
+ unsigned long alt_prate = clk_get_rate(cpuclk-alt_parent);
+ unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
+ unsigned long div0, div1 = 0, mux_reg;
+
+ /* find out the divider values to use for clock data */
+ while ((cfg_data-prate * 1000) != ndata-new_rate) {
+ if (cfg_data-prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+
+ spin_lock(cpuclk-lock);
+
+ /*
+* If the new and old parent clock speed is less than the clock speed
+* of the alternate parent, then it should be ensured that at no point
+* the armclk speed is more than the old_prate until the dividers are
+* set.
+*/
+ div0 = cfg_data-div0;
+ if (alt_prate ndata-old_rate) {
+ alt_div = DIV_ROUND_UP(alt_prate, ndata-old_rate) - 1;
+ WARN_ON(alt_div = MAX_DIV);
+
+ exynos7_set_safe_div(base, alt_div, alt_div_mask);
+ div0 |= alt_div;
+ }
+
+ /* select mout_bus0_pll_atlas as the alternate parent */
+ mux_reg = readl(base + EXYNOS7_SRC_CPU);
+ writel(mux_reg | (1 0), base + EXYNOS7_SRC_CPU);
+ wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 1);
+
+ /* alternate parent is active now. set the dividers */
+ writel(div0, base + EXYNOS7_DIV_CPU0);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, DIV_MASK_ALL);
+
+ if (test_bit(CLK_CPU_HAS_DIV1, cpuclk-flags)) {
+ writel(div1, base + EXYNOS7_DIV_CPU1);
+ wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU1,
+ DIV_MASK_ALL);
+ }
+
+ spin_unlock(cpuclk-lock);
+ return 0;
+}
+
+/* Exynos7 handler for post-rate change notification from parent clock */
+static int exynos7_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ unsigned long div = 0, div_mask = DIV_MASK;
+ unsigned long mux_reg;
+
+ spin_lock(cpuclk-lock);
+
+ /* select mout_atlas_pll as the alternate parent */
+ mux_reg = readl(base + EXYNOS7_SRC_CPU);
+ writel(mux_reg ~(1 0), base + EXYNOS7_SRC_CPU);
+ wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 0);
+
+ exynos7_set_safe_div(base, div, div_mask);
+ spin_unlock(cpuclk-lock);
+ return 0;
+}
+
/* handler for pre-rate change notification from parent clock */
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
@@ -248,25 +337,58 @@ static int exynos_cpuclk_notifier_cb(struct
notifier_block *nb
[PATCH 1/4] clk: samsung: exynos7: add clocks for CPU block
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h| 20 +++-
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f8..0b4ba7f 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-atlas
- samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
@@ -61,6 +62,11 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for atlas clock controller:
+ - fin_pll
+ - fout_atlas_pll
+ - mout_sclk_bus0_pll_atlas
+
Input clocks for ccore clock controller:
- fin_pll
- dout_aclk_ccore_133
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index a79bf23..78f66b4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -35,6 +35,34 @@
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
+static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = {
+ /* rate, m, p, s */
+ PLL_35XX_RATE(249600, 208, 2, 0),
+ PLL_35XX_RATE(24, 200, 2, 0),
+ PLL_35XX_RATE(230400, 288, 3, 0),
+ PLL_35XX_RATE(22, 275, 3, 0),
+ PLL_35XX_RATE(21, 175, 2, 0),
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(189600, 158, 2, 0),
+ PLL_35XX_RATE(18, 150, 2, 0),
+ PLL_35XX_RATE(170400, 142, 2, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 2, 1),
+ PLL_35XX_RATE(14, 350, 3, 1),
+ PLL_35XX_RATE(13, 325, 3, 1),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 350, 3, 2),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -50,6 +78,8 @@ PNAME(mout_bus1_pll_ctrl_p) = { fin_pll, fout_bus1_pll
};
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
PNAME(mout_mfc_pll_ctrl_p) = { fin_pll, fout_mfc_pll };
+PNAME(mout_topc_group1)= { mout_bus0_pll_ctrl,
ffac_topc_bus0_pll_div2,
+mout_bus1_pll_ctrl, mout_cci_pll };
PNAME(mout_topc_group2) = { mout_sclk_bus0_pll_cmuc,
mout_sclk_bus1_pll_cmuc, mout_sclk_cc_pll_cmuc,
mout_sclk_mfc_pll_cmuc };
@@ -104,6 +134,8 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(MOUT_SCLK_BUS0_PLL_ATLAS, mout_sclk_bus0_pll_atlas,
+ mout_topc_group1, MUX_SEL_TOPC1, 4, 2),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -402,6 +434,95 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_ATLAS (0x1180) */
+#defineATLAS_PLL_LOCK 0x
+#defineATLAS_PLL_CON0 0x0100
+#defineMUX_SEL_ATLAS0 0x0200
+#defineMUX_SEL_ATLAS1 0x0204
+#defineMUX_SEL_ATLAS2 0x0208
+#defineDIV_ATLAS0 0x0600
+#defineDIV_ATLAS1 0x0604
+#defineENABLE_IP_ATLAS00x0B00
+
+/* List of parent clocks for Muxes in CMU_ATLAS */
+PNAME(mout_atlas_pll_ctrl_p) = { fin_pll, fout_atlas_pll };
+PNAME(mout_bus_pll_atlas_p) = { fin_pll, mout_sclk_bus0_pll_atlas };
+PNAME(mout_atlas_p) = { mout_atlas_pll_ctrl, mout_bus_pll_atlas };
+
+static unsigned long atlas_clk_regs[] __initdata = {
+ ATLAS_PLL_LOCK,
+ ATLAS_PLL_CON0,
+ MUX_SEL_ATLAS0,
+ MUX_SEL_ATLAS1,
+ MUX_SEL_ATLAS2
[PATCH 0/4] Add CPU clock support for Exynos7
These patches add the atlas clocks on Exynos7. It also modifies the existing cpu clock infrastructure to handle exynos7 differences. These patches are a pre-requisite for enabling CPUFreq on Exynos7. Following are the dependencies: 1) arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg38734.html 2) cpufreq: use generic cpufreq drivers for exynos platforms http://www.spinics.net/lists/linux-samsung-soc/msg39332.html For testing I have applied the following: 1) mfd: sec: add S2MPS15 PMIC support https://lkml.org/lkml/2014/10/14/50 2) regulator: s2mps11: add support for S2MPS15 regulators https://lkml.org/lkml/2014/10/14/52 3) Regulators dt nodes were added in the espresso dts file and I2C channel 4 which has the PMIC on it was tested. Abhilash Kesavan (4): clk: samsung: exynos7: add clocks for CPU block clk: samsung: retrieve the clock provider information from samsung_cmu_register_one clk: samsung: add cpu clock support for Exynos7 clk: samsung: add cpu clock configuration data and instantiate cpu clock .../devicetree/bindings/clock/exynos7-clock.txt|6 + drivers/clk/samsung/clk-cpu.c | 130 - drivers/clk/samsung/clk-cpu.h | 38 - drivers/clk/samsung/clk-exynos4.c |2 +- drivers/clk/samsung/clk-exynos5250.c |2 +- drivers/clk/samsung/clk-exynos5420.c |4 +- drivers/clk/samsung/clk-exynos7.c | 147 drivers/clk/samsung/clk.c |6 +- drivers/clk/samsung/clk.h |4 +- include/dt-bindings/clock/exynos7-clk.h| 21 ++- 10 files changed, 347 insertions(+), 13 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] clk: samsung: retrieve the clock provider information from samsung_cmu_register_one
In case of SoCs with multiple CMUs like Exynos7 and Exynos5260 we are
making use of a common samsung_cmu_register_one function for pll, div,
mux registration. To register the cpu domain clock (for cpufreq) we need
a reference to this clock provider information in the cpu cmu block. Make
this information accessible by returning it from samsung_cmu_register_one().
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk.c |6 --
drivers/clk/samsung/clk.h |4 ++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index dd1f7c9..4a653fe 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -374,8 +374,8 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
* Common function which registers plls, muxes, dividers and gates
* for each CMU. It also add CMU register list to register cache.
*/
-void __init samsung_cmu_register_one(struct device_node *np,
- struct samsung_cmu_info *cmu)
+struct samsung_clk_provider * __init samsung_cmu_register_one(
+ struct device_node *np, struct samsung_cmu_info *cmu)
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
@@ -410,4 +410,6 @@ void __init samsung_cmu_register_one(struct device_node *np,
cmu-nr_clk_regs);
samsung_clk_of_add_provider(np, ctx);
+
+ return ctx;
}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 3f471e9..24ae23c 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -396,8 +396,8 @@ extern void __init samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_list,
unsigned int nr_clk, void __iomem *base);
-extern void __init samsung_cmu_register_one(struct device_node *,
- struct samsung_cmu_info *);
+extern struct samsung_clk_provider * __init
+samsung_cmu_register_one(struct device_node *, struct samsung_cmu_info *);
extern unsigned long _get_rate(const char *clk_name);
--
1.7.9.5
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[PATCH 4/4] clk: samsung: add cpu clock configuration data and instantiate cpu clock
Add the Atlas CPU clock configuration data and instantiate the CPU clock
type for Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.h |5 +
drivers/clk/samsung/clk-exynos7.c | 28 +++-
include/dt-bindings/clock/exynos7-clk.h |3 ++-
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 24e844e..1fd7f51 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -31,6 +31,11 @@
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) 24) | ((pclk) 20) | ((aclk) 4)))
+#define EXYNOS7_ATL_DIV0(aclk, pclk, atclk, pclk_dbg) \
+ ((aclk 8) | (pclk 12) | (atclk 20) | (pclk_dbg 26))
+#define EXYNOS7_ATL_DIV1(pll, hpm, cntclk) \
+ ((pll 0) | (hpm 4) | (cntclk 8))
+
/**
* struct exynos_cpuclk_data: config data to setup cpu clocks.
* @prate: frequency of the primary parent clock (in KHz).
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 78f66b4..dc9b7fb 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -14,6 +14,7 @@
#include linux/of.h
#include clk.h
+#include clk-cpu.h
#include dt-bindings/clock/exynos7-clk.h
/* Register Offset definitions for CMU_TOPC (0x1057) */
@@ -63,6 +64,25 @@ static const struct samsung_pll_rate_table
pll1450x_24mhz_tbl[] = {
PLL_35XX_RATE(2, 200, 3, 3),
};
+static const struct exynos_cpuclk_cfg_data exynos7_atlclk_d[] __initconst = {
+ { 160, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 150, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 140, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 130, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 120, EXYNOS7_ATL_DIV0(1, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 110, EXYNOS7_ATL_DIV0(1, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), },
+ { 100, EXYNOS7_ATL_DIV0(1, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 2, 6), },
+ { 90, EXYNOS7_ATL_DIV0(1, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 2, 6), },
+ { 80, EXYNOS7_ATL_DIV0(1, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 2, 5), },
+ { 70, EXYNOS7_ATL_DIV0(1, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 2, 5), },
+ { 60, EXYNOS7_ATL_DIV0(1, 4, 4, 4), EXYNOS7_ATL_DIV1(1, 2, 4), },
+ { 50, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 40, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 30, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 20, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), },
+ { 0 },
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -518,7 +538,13 @@ static struct samsung_cmu_info atlas_cmu_info __initdata =
{
static void __init exynos7_clk_atlas_init(struct device_node *np)
{
- samsung_cmu_register_one(np, atlas_cmu_info);
+ struct samsung_clk_provider *ctx;
+
+ ctx = samsung_cmu_register_one(np, atlas_cmu_info);
+ exynos_register_cpu_clock(ctx, CLK_ATLAS_CLK, atlclk,
+ mout_atlas_p[0], mout_atlas_p[1], 0x0,
+ exynos7_atlclk_d, ARRAY_SIZE(exynos7_atlclk_d),
+ CLK_CPU_HAS_DIV1, np);
}
CLK_OF_DECLARE(exynos7_clk_atlas, samsung,exynos7-clock-atlas,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 93c78f9..33bc166 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -55,7 +55,8 @@
#define CLK_ATLAS 12
#define DOUT_SCLK_HPM_ATLAS13
#define DOUT_ATLAS_PLL 14
-#define ATLAS_NR_CLK 15
+#define CLK_ATLAS_CLK 15
+#define ATLAS_NR_CLK 16
/* CCORE */
#define PCLK_RTC 1
--
1.7.9.5
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Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test it...I'll try to make a
test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
Are you seeing this on Chromebook2 (Peach-Pi 5800) too ?
No, it seems that my exynos5800-peach-pi is not having this problem,
which suggests it's a bootloader setup issue.
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
The 3 boards I have access to (SMDK5420, Chromebook Peach-Pi and
Chromebook Peach-Pit) work fine with MCPM enabled.
Thanks for helping look into this.
I am not sure why
it is failing only on the above mentioned boards as there is nothing
specific to them in the MCPM back-end.
I assume that when you default to platsmp (on disabling MCPM), the
non-working boards boot all cores upto userspace without any issues ?
Nope. With MCPM disabled:
- 5420/arndale-octa: CPU0-3 come up (A15s)
- 5422/odroid-xu3: only CPU0 (A7)
- 5800/peach-pi: only CPU0 (A15)
Note that with MCPM enabled, the arndale-octa gets the same result.
Peach-pi on the other hand gets all 8 CPUs, and the odroid-xu3 only gets
6/8 CPUs (see other thread on that topic.)
Based on the timeline (problems started about 2.5 months back), there
have only been a couple of changes in the 5420 MCPM back-end. Could
you revert the following commits and check if things improve.
20fe6f9 ARM: EXYNOS: Support cluster power off on exynos5420/5800
fbb0499 ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster
using the MCPM loopback
These might not revert cleanly, so instead of the above you could also
comment the following 2 lines:
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index dc9a764..9a07188 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -152,7 +152,7 @@ static void exynos_power_down(void)
exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
- exynos_cluster_power_down(cluster);
+ //exynos_cluster_power_down(cluster);
last_man = true;
}
2 } else if (cpu_use_count[cpu][cluster] == 1) {
@@ -356,8 +356,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
- if (!ret)
- ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
+ //if (!ret)
+ //ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI
*/
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
If you still get aborts then I suspect that the problem is with the
bootloader configuration but am not sure.
Nice. With those lines commented out, the arndale-octa is not geting
imprecise aborts anymore, and this is the platform where those aborts
seem to prevent booting into a full userspace (as originally reported by
Tyler.)
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts go away.
I can't see how enabling snoops for the boot cluster is causing these
aborts. Perhaps as Krzysztof commented it has something to do with the
secure firmware/tz software on these boards ? Other than there does
not appear to be any difference between the working/non-working
setups.
Abhilash
The odroid-xu3 is still getting them, but these seem to happen whether
or not MCPM is enabled, so must a different issue related to the
bootloader setup.
I am OK with disabling
5420_MCPM in the default configuration in such a case. This would
however mean
Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
Hello Kevin, On Tue, Nov 25, 2014 at 8:50 AM, Kevin Hilman khil...@kernel.org wrote: On Mon, Nov 24, 2014 at 5:50 PM, Kukjin Kim kg...@kernel.org wrote: Olof Johansson wrote: On Mon, Nov 24, 2014 at 5:37 PM, Olof Johansson o...@lixom.net wrote: On Mon, Nov 24, 2014 at 5:35 PM, Kevin Hilman khil...@kernel.org wrote: On Mon, Nov 24, 2014 at 4:25 PM, Olof Johansson o...@lixom.net wrote: On Mon, Nov 24, 2014 at 11:51 AM, Kevin Hilman khil...@kernel.org wrote: Kukjin, On Mon, Nov 10, 2014 at 11:35 AM, Kevin Hilman khil...@kernel.org wrote: Kukjin Kim kg...@kernel.org writes: Kevin Hilman wrote: From: Kevin Hilman khil...@linaro.org The option CONFIG_EXYNOS5420_MCPM is causing imprecise external aborts during boot testing, causing various userspace startup failures. Disable until it has gotten more testing. Cc: Kukjin Kim kgene@samsung.com, Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk, Cc: Sachin Kamat sachin.ka...@samsung.com, Cc: Doug Anderson diand...@chromium.org, Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com, Cc: Krzysztof Kozlowski k.kozlow...@samsung.com, Cc: Tushar Behera tushar.beh...@linaro.org, Cc: sta...@vger.kernel.org # v3.17+ Signed-off-by: Kevin Hilman khil...@linaro.org --- This has been reported by a few people[1], but not investigated or fixed, so it's time to disable this feature until it can be fixed. Hi Kevin, Yeah I agree with your opinion. But as you can see my tree, I've queued regarding mcpm patches for 3.19 will be shown in -next in this weekend. Which of the recently queued patches are expected to address the imprecise abort issue? I'd be happy to test them out. Exynos5 MCPM is still broken in linux-next and still causing an imprecise abort. What is the status of $SUBJECT patch? Anyway let me apply this into -fixes and then let's enable after test its functionality in -next in a couple of days. Yes, I think this needs to be applied until these aborts are understood and fixed. Is anyone at Samsung actually looking into these MCPM issues? Hi Kevin, What hardware are you having problems with? 5420 or 5422/5800? Yes. :) exynos5420-arndale-octa: http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc6/arm-exynos_defconfig/boot-exynos5420- arndale-octa.html exynos5422-odroid-xu3: http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc6/arm-exynos_defconfig/boot-exynos5422- odroid-xu3.html My boot tests seem to pass fine because I have such a minimal userspace, but Tyler Baker reported that with a real userspace, he can't boot to a shell: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/286203.html Hmm...his report was in Sep...I think it should be fine with current -next? No, it is still broken in linux-next (as I stated above.) Moreover, earlier in this thread you mentioned you were merging some MCPM patches that should address this, but did not respond when I asked which patches you thing should address this issue To be honest, since I don't have the exynos5420 arndale, chromebook...but smdk which has different bootloader, I couldn't test it...I'll try to make a test farm like you guys... Do you have some colleagues with any other 542x hardware? I had assumed that linux-next was being better tested on the publicaly available, and widely available boards like odroid-xu3 and Chromebook2, but I've come to realize the hard way that that is not Are you seeing this on Chromebook2 (Peach-Pi 5800) too ? the case. You mention your board has a different bootloader. Do you suspect there's a bootloader issue on these other platforms? If so, could you elaborate on possible fixes? I'm more than willing to test any proposed fixes, but I'm not familiar enough yet with these SoCs to figure out the underlying issues alone. Until you have a working board farm, you could start having a closer look at the boot logs we're already producing. Admittedly linux-next broken in many ways besides this one for exynos currently, but it has been having these imprecise aborts well before the other recent issues. Also, It's very possible that this issue is not even MCPM related at all, and MCPM is just uncovering a previously hidden bug. It would be very helpful if people more familiar with this hardware and SoC would investigate bug reports like these. The 3 boards I have access to (SMDK5420, Chromebook Peach-Pi and Chromebook Peach-Pit) work fine with MCPM enabled. I am not sure why it is failing only on the above mentioned boards as there is nothing specific to them in the MCPM back-end. I assume that when you default to platsmp (on disabling MCPM), the non-working boards boot all cores upto userspace without any issues ? Based on the timeline (problems started about 2.5 months back), there have only been a couple of changes in the 5420 MCPM back-end.
Re: exynos5250/arndale: failed to set cpu voltage
Hi Tyler, On Sun, Nov 16, 2014 at 12:12 AM, Tyler Baker tyler.ba...@linaro.org wrote: Hi Abhilash, On 13 November 2014 18:50, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hello Tyler, On Fri, Nov 14, 2014 at 3:30 AM, Tyler Baker tyler.ba...@linaro.org wrote: In recent upstream kernels, exynos5420-based arndale boards have been Boot logs are only for 5250, typo ? Apologies, this is a typo. Should have been 5250 as you mentioned. producing boot-time errors due to the fact they failed to set the cpu voltage. These message flood the serial console even after userspace has been loaded, yielding the console unusable without forcing a lower log level. These errors are produced _only_ with the multi_v7_defconfig and they are _not_ present with exynos_defconfig. Here are some recent boot logs showing the boot errors: mainline/v3.18-rc4-65-g2c54396: multi_v7_defconfig: http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc4-65-g2c54396/arm-multi_v7_defconfig/boot-exynos5250-arndale.html exynos_defconfig: http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc4-65-g2c54396/arm-exynos_defconfig/boot-exynos5250-arndale.html From the boot logs it appears that the S5M8767 regulator does not get probed with multi_v7_defconfig and you get the following messages: [1.147412] deviceless supply vdd_arm not found, using dummy regulator [1.152669] exynos-cpufreq exynos-cpufreq: failed to set cpu voltage to 130 [1.159771] cpufreq: __target_index: Failed to change cpu frequency: -22 Both multi_v7_defconfig and exynos_defconfig have the S5M8767 regulator enabled. However multi_v7_defconfig does not have the S3C I2C controller enabled while exynos_defconfig does. Can you re-check after enabling CONFIG_I2C_S3C2410 ? I have retested my two arndale boards with multi_v7_defconfg+CONFIG_I2C_S3C2410=y on mainline, next, and arm-soc. Enabling S3C I2C controller does resolve the issue I have reported above. It seems reasonable to patch the multi_v7_defconfig to enable this option by default, thoughts? Yes, I2C_S3C2410 should be enabled in multi_v7_defconfig. There was some work going on related to updating the multi_v7_defconfig [1] and maybe this could be part of it. Regards, Abhilash [1] http://www.spinics.net/lists/arm-kernel/msg377544.html Regards, Abhilash next/next-20141113: multi_v7_defconfig: http://storage.armcloud.us/kernel-ci/next/next-20141113/arm-multi_v7_defconfig/boot-exynos5250-arndale.html exynos_defconfig: http://storage.armcloud.us/kernel-ci/next/next-20141113/arm-exynos_defconfig/boot-exynos5250-arndale.html arm-soc/v3.18-rc4-185-gbfcf8f9: multi_v7_defconfig: http://storage.armcloud.us/kernel-ci/arm-soc/v3.18-rc4-185-gbfcf8f9/arm-multi_v7_defconfig/boot-exynos5250-arndale.html exynos_defconfig: http://storage.armcloud.us/kernel-ci/arm-soc/v3.18-rc4-185-gbfcf8f9/arm-exynos_defconfig/boot-exynos5250-arndale.html Cheers, -- Tyler Baker Tech Lead, LAVA Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel Cheers, -- Tyler Baker Tech Lead, LAVA Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND] serial: samsung: Fix serial config dependencies for exynos7
Hi Kukjin, On Wed, Nov 19, 2014 at 12:58 PM, Kukjin Kim kgene@samsung.com wrote: On 11/18/14 03:59, Greg KH wrote: On Mon, Nov 17, 2014 at 10:14:51AM +0530, Abhilash Kesavan wrote: From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- Acked-by: Greg Kroah-Hartman gre...@linuxfoundation.org Greg, thanks for your ack on this. Abhilash, I can't find the original patch in my mailbox, can you please re-send to me with adding Greg's ack? Will send it you with Greg's Ack. Thanks, Abhilash Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] serial: samsung: Fix serial config dependencies for exynos7
From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org Acked-by: Greg Kroah-Hartman gre...@linuxfoundation.org --- Changes in v2: - Added Greg's ack and Kukjin Kim as a recepient drivers/tty/serial/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index e71a28b..d0ce88c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -249,14 +249,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] serial: samsung: Fix serial config dependencies for exynos7
Hello Greg, On Mon, Nov 17, 2014 at 2:40 AM, gre...@linuxfoundation.org gre...@linuxfoundation.org wrote: On Sun, Nov 16, 2014 at 07:47:02AM +0530, Abhilash Kesavan wrote: Hello Greg, On Tue, Nov 11, 2014 at 7:55 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Greg, On Tue, Sep 30, 2014 at 8:02 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Tomasz, On Tue, Sep 30, 2014 at 4:08 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Abhilash, The patch itself seems fine, but I wonder if those config options aren't really just leftovers from the past and couldn't be completely removed. On 29.09.2014 07:16, Abhilash Kesavan wrote: From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- Build tested with s3c6400_defconfig, exynos_defconfig and arm64's defconfig with and without the serial driver enabled. drivers/tty/serial/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 81f6ee7..e6c0bcb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -249,14 +249,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs The only place where this symbol is used is below. config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help With this symbol the situation isn't that easy, but still should be manageable. Looking at the serial-samsung driver, all occurrences of CONFIG_SERIAL_SAMSUNG_UARTS could be simply replaced with a locally defined number equal to the maximum value - in this case 4. There are also two places in arch/arm where this symbol is used: 1) In arch/arm/mach-s3c64xx/irq-pm.c it's used as the number of serial ports which need suspend/resume handling. Since on s3c64xx the number is always 4, it can be simply defined locally as a constant. 2) In arch/arm/plat-samsung/init.c it is used to determine size of a static array of UART ports and to check whether the UART driver is enabled. In former case I believe it should be safe to hardcode it to 4 as well, in latter CONFIG_SERIAL_SAMSUNG can be used. I will post patches removing these two symbols. I posted a couple of patches handling Tomasz' comments but Kukjin prefers the approach in this patch (Discussion here: http://www.spinics.net/lists/linux-samsung-soc/msg38742.html). Can you please review the patch. This is a gentle reminder. The patch is required for serial enablement on the new exynos7 SoC, kindly take a look. What patch? I fail to see anything in my inboxes that I can apply, only this long thread that makes no sense at all. Please resend anything that you want to have applied, in a format that I can apply it, _AND_ get everyone to agree that it is the correct solution. Asking me to go look up random web archives, of mailing list threads I was never copied on, is a sure way to get your email ignored, as again, there is nothing I can do with it. You know better than this. Apologies for the patch not reaching you. I will re-send it right now. Kukjin Kim has already approved the approach under discussion; however the patch needs to go via Kukjin's tree due to other patches that depend on it. Hence, I require your ack on it. Once again, sorry for the inconvenience. Thanks, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND] serial: samsung: Fix serial config dependencies for exynos7
From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- Re-sending as the previous version did not reach Greg KH. drivers/tty/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index e71a28b..d0ce88c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -249,14 +249,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] serial: samsung: Fix serial config dependencies for exynos7
Hello Greg, On Tue, Nov 11, 2014 at 7:55 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Greg, On Tue, Sep 30, 2014 at 8:02 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Tomasz, On Tue, Sep 30, 2014 at 4:08 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Abhilash, The patch itself seems fine, but I wonder if those config options aren't really just leftovers from the past and couldn't be completely removed. On 29.09.2014 07:16, Abhilash Kesavan wrote: From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- Build tested with s3c6400_defconfig, exynos_defconfig and arm64's defconfig with and without the serial driver enabled. drivers/tty/serial/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 81f6ee7..e6c0bcb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -249,14 +249,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs The only place where this symbol is used is below. config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help With this symbol the situation isn't that easy, but still should be manageable. Looking at the serial-samsung driver, all occurrences of CONFIG_SERIAL_SAMSUNG_UARTS could be simply replaced with a locally defined number equal to the maximum value - in this case 4. There are also two places in arch/arm where this symbol is used: 1) In arch/arm/mach-s3c64xx/irq-pm.c it's used as the number of serial ports which need suspend/resume handling. Since on s3c64xx the number is always 4, it can be simply defined locally as a constant. 2) In arch/arm/plat-samsung/init.c it is used to determine size of a static array of UART ports and to check whether the UART driver is enabled. In former case I believe it should be safe to hardcode it to 4 as well, in latter CONFIG_SERIAL_SAMSUNG can be used. I will post patches removing these two symbols. I posted a couple of patches handling Tomasz' comments but Kukjin prefers the approach in this patch (Discussion here: http://www.spinics.net/lists/linux-samsung-soc/msg38742.html). Can you please review the patch. This is a gentle reminder. The patch is required for serial enablement on the new exynos7 SoC, kindly take a look. Thanks, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
Hi Olof and Arnd On Tue, Nov 11, 2014 at 7:59 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hello Olof and Arnd, On Sun, Nov 9, 2014 at 9:50 AM, Abhilash Kesavan a.kesa...@samsung.com wrote: These were originally part of 2 patchsets[1][2] adding support for Exynos7. The clock and pinctrl patches are going through the respective maintainer's tree; hence the remaining dt related patches have been consolidated and are being posted here as a separate series. This patchset has build dependencies on the following patches: a] [GIT PULL] Samsung clock changes for 3.19 - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 b] tty: serial: samsung: Clean-up selection of number of available UARTs http://www.spinics.net/lists/linux-samsung-soc/msg37418.html c] dts, kbuild: Implement support for dtb vendor subdirs(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 [1] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html [2] Add clock and DT support for a few IPs on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37973.html Changes since v6: - Fixed the platform ordering (exynos before thunder) in Kconfig file. - Fixed the ordering of reg and enable-method properties in cpu node as per Lorenzo Pieralisi's comment. Do you have any comments on this patchset ? A gentle reminder regarding this patch set. Kindly review. Abhilash Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for EXYNOS7 arm64: dts: Add initial pinctrl support to EXYNOS7 Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/arm/samsung/pmu.txt| 1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 + arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ arch/arm64/boot/dts/include/dt-bindings| 1 + arch/arm64/configs/defconfig | 4 + 9 files changed, 1231 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5250/arndale: failed to set cpu voltage
Hello Tyler, On Fri, Nov 14, 2014 at 3:30 AM, Tyler Baker tyler.ba...@linaro.org wrote: In recent upstream kernels, exynos5420-based arndale boards have been Boot logs are only for 5250, typo ? producing boot-time errors due to the fact they failed to set the cpu voltage. These message flood the serial console even after userspace has been loaded, yielding the console unusable without forcing a lower log level. These errors are produced _only_ with the multi_v7_defconfig and they are _not_ present with exynos_defconfig. Here are some recent boot logs showing the boot errors: mainline/v3.18-rc4-65-g2c54396: multi_v7_defconfig: http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc4-65-g2c54396/arm-multi_v7_defconfig/boot-exynos5250-arndale.html exynos_defconfig: http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc4-65-g2c54396/arm-exynos_defconfig/boot-exynos5250-arndale.html From the boot logs it appears that the S5M8767 regulator does not get probed with multi_v7_defconfig and you get the following messages: [1.147412] deviceless supply vdd_arm not found, using dummy regulator [1.152669] exynos-cpufreq exynos-cpufreq: failed to set cpu voltage to 130 [1.159771] cpufreq: __target_index: Failed to change cpu frequency: -22 Both multi_v7_defconfig and exynos_defconfig have the S5M8767 regulator enabled. However multi_v7_defconfig does not have the S3C I2C controller enabled while exynos_defconfig does. Can you re-check after enabling CONFIG_I2C_S3C2410 ? Regards, Abhilash next/next-20141113: multi_v7_defconfig: http://storage.armcloud.us/kernel-ci/next/next-20141113/arm-multi_v7_defconfig/boot-exynos5250-arndale.html exynos_defconfig: http://storage.armcloud.us/kernel-ci/next/next-20141113/arm-exynos_defconfig/boot-exynos5250-arndale.html arm-soc/v3.18-rc4-185-gbfcf8f9: multi_v7_defconfig: http://storage.armcloud.us/kernel-ci/arm-soc/v3.18-rc4-185-gbfcf8f9/arm-multi_v7_defconfig/boot-exynos5250-arndale.html exynos_defconfig: http://storage.armcloud.us/kernel-ci/arm-soc/v3.18-rc4-185-gbfcf8f9/arm-exynos_defconfig/boot-exynos5250-arndale.html Cheers, -- Tyler Baker Tech Lead, LAVA Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] serial: samsung: Fix serial config dependencies for exynos7
Hi Greg, On Tue, Sep 30, 2014 at 8:02 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Tomasz, On Tue, Sep 30, 2014 at 4:08 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Abhilash, The patch itself seems fine, but I wonder if those config options aren't really just leftovers from the past and couldn't be completely removed. On 29.09.2014 07:16, Abhilash Kesavan wrote: From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- Build tested with s3c6400_defconfig, exynos_defconfig and arm64's defconfig with and without the serial driver enabled. drivers/tty/serial/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 81f6ee7..e6c0bcb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -249,14 +249,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs The only place where this symbol is used is below. config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help With this symbol the situation isn't that easy, but still should be manageable. Looking at the serial-samsung driver, all occurrences of CONFIG_SERIAL_SAMSUNG_UARTS could be simply replaced with a locally defined number equal to the maximum value - in this case 4. There are also two places in arch/arm where this symbol is used: 1) In arch/arm/mach-s3c64xx/irq-pm.c it's used as the number of serial ports which need suspend/resume handling. Since on s3c64xx the number is always 4, it can be simply defined locally as a constant. 2) In arch/arm/plat-samsung/init.c it is used to determine size of a static array of UART ports and to check whether the UART driver is enabled. In former case I believe it should be safe to hardcode it to 4 as well, in latter CONFIG_SERIAL_SAMSUNG can be used. I will post patches removing these two symbols. I posted a couple of patches handling Tomasz' comments but Kukjin prefers the approach in this patch (Discussion here: http://www.spinics.net/lists/linux-samsung-soc/msg38742.html). Can you please review the patch. Regards, Abhilash Regards, Abhilash Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
Hello Olof and Arnd, On Sun, Nov 9, 2014 at 9:50 AM, Abhilash Kesavan a.kesa...@samsung.com wrote: These were originally part of 2 patchsets[1][2] adding support for Exynos7. The clock and pinctrl patches are going through the respective maintainer's tree; hence the remaining dt related patches have been consolidated and are being posted here as a separate series. This patchset has build dependencies on the following patches: a] [GIT PULL] Samsung clock changes for 3.19 - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 b] tty: serial: samsung: Clean-up selection of number of available UARTs http://www.spinics.net/lists/linux-samsung-soc/msg37418.html c] dts, kbuild: Implement support for dtb vendor subdirs(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 [1] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html [2] Add clock and DT support for a few IPs on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37973.html Changes since v6: - Fixed the platform ordering (exynos before thunder) in Kconfig file. - Fixed the ordering of reg and enable-method properties in cpu node as per Lorenzo Pieralisi's comment. Do you have any comments on this patchset ? Regards, Abhilash Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for EXYNOS7 arm64: dts: Add initial pinctrl support to EXYNOS7 Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/arm/samsung/pmu.txt| 1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 + arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ arch/arm64/boot/dts/include/dt-bindings| 1 + arch/arm64/configs/defconfig | 4 + 9 files changed, 1231 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] tty: serial: samsung: Clean-up selection of number of available UARTs
Hi Kukjin, On Sun, Nov 9, 2014 at 10:09 AM, Kukjin Kim kg...@kernel.org wrote: Abhilash Kesavan wrote: On Mon, Nov 3, 2014 at 1:51 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hello Kukjin, On Fri, Oct 31, 2014 at 8:06 AM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Kukjin, On Tue, Oct 28, 2014 at 5:56 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Kukjin On Tue, Oct 28, 2014 at 4:01 PM, Kukjin Kim kg...@kernel.org wrote: Abhilash Kesavan wrote: Hi, Sorry for late response. Remove symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS which select the number of UART ports available on the SoC. Replace the usage of SERIAL_SAMSUNG_UARTS in the serial driver with the maximum number of Well, as you know the number of uart ports are different on each Samsung SoCs so I don't think just using maximum number of uart ports are possible for new exynos7 SoC at this moment. Thanks for the review. The main reason for me sending this patch was so that we may be able to re-use the serial driver on arm64 based Exynos7 too. The two symbols mentioned above which depend on PLAT_SAMSUNG prevent this. I initially sent a patch which changed the dependency to SERIAL_SAMSUNG for these 2 symbols. However, Tomasz suggested that a clean-up of these two symbols would be a better option. Please see the discussion of the previous version here: https://lkml.org/lkml/2014/9/29/702 Can you please let me know if the previous version is acceptable ? Kukjin, can you please indicate the approach you would like me to take. Without this serial support is blocked on Exynos7. Gentle reminder on this. Hi Kukjin, Hi Abhilash, I don't mean to nag, but this another reminder to review this. Yeah, it's no problem for me ;) Please let me know if you are too busy to have a look at this or require some more inputs from me. Since I'm still having some objection on 2nd version, how about keeping current config options for serial for now and changing the dependency to SERIAL_SAMSUNG? And if required later, we can look into removal these config options later. OK, thanks. My earlier patch [1] which does this still applies cleanly on linux-next. I will request Greg to review the patch. I had a question regarding the merging of pending exynos7 patches. The clock exynos7 support will go through your tree (according to [2]) and so must the exynos7 arch/dts support [3] due to the related dependencies. As part of the arch/dts support we are enabling the samsung serial driver in arm64 defconfig. This will cause build breakages without [1] being applied. So, I assume all 3 patch-sets will go through your tree once they have been ack'ed or is there some other way ? [1] serial: samsung: Fix serial config dependencies for exynos7 https://patchwork.kernel.org/patch/4993521/ [2] GIT PULL] Samsung clock changes for 3.19 http://www.spinics.net/lists/arm-kernel/msg373962.html [3] [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/arm-kernel/msg375961.html Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] tty: serial: samsung: Clean-up selection of number of available UARTs
On Mon, Nov 3, 2014 at 1:51 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hello Kukjin,
On Fri, Oct 31, 2014 at 8:06 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Kukjin,
On Tue, Oct 28, 2014 at 5:56 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Kukjin
On Tue, Oct 28, 2014 at 4:01 PM, Kukjin Kim kg...@kernel.org wrote:
Abhilash Kesavan wrote:
Hi,
Sorry for late response.
Remove symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS which
select the number of UART ports available on the SoC. Replace the usage
of SERIAL_SAMSUNG_UARTS in the serial driver with the maximum number of
Well, as you know the number of uart ports are different on each Samsung
SoCs
so I don't think just using maximum number of uart ports are possible for
new
exynos7 SoC at this moment.
Thanks for the review.
The main reason for me sending this patch was so that we may be able
to re-use the serial driver on arm64 based Exynos7 too. The two
symbols mentioned above which depend on PLAT_SAMSUNG prevent this. I
initially sent a patch which changed the dependency to SERIAL_SAMSUNG
for these 2 symbols. However, Tomasz suggested that a clean-up of
these two symbols would be a better option.
Please see the discussion of the previous version here:
https://lkml.org/lkml/2014/9/29/702
Can you please let me know if the previous version is acceptable ?
Kukjin, can you please indicate the approach you would like me to
take. Without this serial support is blocked on Exynos7.
Gentle reminder on this.
Hi Kukjin,
I don't mean to nag, but this another reminder to review this.
Please let me know if you are too busy to have a look at this or
require some more inputs from me.
Regards,
Abhilash
Abhilash
Thanks,
Abhilash
UART ports possible. Removal of these symbols also helps in Exynos7
serial enablement.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig | 16
drivers/tty/serial/samsung.c | 11 +++
drivers/tty/serial/samsung.h |5 -
3 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 81f6ee7..9fc9092 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -247,22 +247,6 @@ config SERIAL_SAMSUNG
provide all of these ports, depending on how the serial port
pins are configured.
-config SERIAL_SAMSUNG_UARTS_4
- bool
- depends on PLAT_SAMSUNG
- default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 ||
CPU_S3C2442)
- help
- Internal node for the common case of 4 Samsung compatible UARTs
-
-config SERIAL_SAMSUNG_UARTS
- int
- depends on PLAT_SAMSUNG
- default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416
- default 3
- help
- Select the number of available UART ports for the Samsung S3C
- serial driver
-
config SERIAL_SAMSUNG_DEBUG
bool Samsung SoC serial debug
depends on SERIAL_SAMSUNG DEBUG_LL
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index c78f43a..ba04c6d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -962,14 +962,14 @@ static struct uart_ops s3c24xx_serial_ops = {
static struct uart_driver s3c24xx_uart_drv = {
.owner = THIS_MODULE,
.driver_name= s3c2410_serial,
- .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
+ .nr = MAX_SAMSUNG_UARTS,
.cons = S3C24XX_SERIAL_CONSOLE,
.dev_name = S3C24XX_SERIAL_NAME,
.major = S3C24XX_SERIAL_MAJOR,
.minor = S3C24XX_SERIAL_MINOR,
};
-static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
+static struct s3c24xx_uart_port s3c24xx_serial_ports[MAX_SAMSUNG_UARTS]
= {
[0] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
@@ -992,8 +992,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 1,
}
},
-#if CONFIG_SERIAL_SAMSUNG_UARTS 2
-
[2] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
@@ -1005,8 +1003,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 2,
}
},
-#endif
-#if CONFIG_SERIAL_SAMSUNG_UARTS 3
[3] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
@@ -1018,7 +1014,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line
[PATCH v7 1/7] arm64: dts: add dt-bindings/ symlink
From: Pankaj Dubey pankaj.du...@samsung.com Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299aa8754 (kbuild: create an include chroot for DT bindings) merged in v3.10-rc1 for details. Cc: Catalin Marinas catalin.mari...@arm.com Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com --- arch/arm64/boot/dts/include/dt-bindings | 1 + 1 file changed, 1 insertion(+) create mode 12 arch/arm64/boot/dts/include/dt-bindings diff --git a/arch/arm64/boot/dts/include/dt-bindings b/arch/arm64/boot/dts/include/dt-bindings new file mode 12 index 000..08c00e4 --- /dev/null +++ b/arch/arm64/boot/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../../include/dt-bindings \ No newline at end of file -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
These were originally part of 2 patchsets[1][2] adding support for Exynos7. The clock and pinctrl patches are going through the respective maintainer's tree; hence the remaining dt related patches have been consolidated and are being posted here as a separate series. This patchset has build dependencies on the following patches: a] [GIT PULL] Samsung clock changes for 3.19 - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 b] tty: serial: samsung: Clean-up selection of number of available UARTs http://www.spinics.net/lists/linux-samsung-soc/msg37418.html c] dts, kbuild: Implement support for dtb vendor subdirs(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 [1] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html [2] Add clock and DT support for a few IPs on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37973.html Changes since v6: - Fixed the platform ordering (exynos before thunder) in Kconfig file. - Fixed the ordering of reg and enable-method properties in cpu node as per Lorenzo Pieralisi's comment. Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for EXYNOS7 arm64: dts: Add initial pinctrl support to EXYNOS7 Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/arm/samsung/pmu.txt| 1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 + arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ arch/arm64/boot/dts/include/dt-bindings| 1 + arch/arm64/configs/defconfig | 4 + 9 files changed, 1231 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 4/7] arm64: dts: Add PMU DT node for exynos7 SoC
Adds PMU DT node for exynos7 SoC.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- samsung,exynos5260-pmu - for Exynos5260 SoC.
- samsung,exynos5410-pmu - for Exynos5410 SoC,
- samsung,exynos5420-pmu - for Exynos5420 SoC.
+ - samsung,exynos7-pmu - for Exynos7 SoC.
second value must be always syscon.
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 22fb71c..8aab9f9 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
1 11 0xff01,
1 10 0xff01;
};
+
+ pmu_system_controller: system-controller@105c {
+ compatible = samsung,exynos7-pmu, syscon;
+ reg = 0x105c 0x5000;
+ };
};
};
--
2.1.0
--
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[PATCH v7 2/7] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/exynos/Makefile | 5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8f..fdda246 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..6d6a4c2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x0;
+ enable-method = psci;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x1;
+ enable-method = psci;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x2;
+ enable-method = psci;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x3;
+ enable-method = psci;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti
[PATCH v7 5/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, watchdog and adc
on Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45
arch/arm64/boot/dts/exynos/exynos7.dtsi | 276
2 files changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..5424cc4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = serial_2;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
};
chosen {
@@ -37,3 +39,46 @@
serial_2 {
status = okay;
};
+
+rtc {
+ status = okay;
+};
+
+watchdog {
+ status = okay;
+};
+
+adc {
+ status = okay;
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_qrdy sd0_bus1 sd0_bus4 sd0_bus8;
+ bus-width = 8;
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ cap-sd-highspeed;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+ disable-wp;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8aab9f9..d7a37c3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
dout_sclk_mfc_pll;
};
+ clock_top1: clock-controller@105e {
+ compatible = samsung,exynos7-clock-top1;
+ reg = 0x105e 0xb000;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_SCLK_BUS0_PLL,
+clock_topc DOUT_SCLK_BUS1_PLL,
+clock_topc DOUT_SCLK_CC_PLL,
+clock_topc DOUT_SCLK_MFC_PLL;
+ clock-names = fin_pll, dout_sclk_bus0_pll,
+ dout_sclk_bus1_pll, dout_sclk_cc_pll,
+ dout_sclk_mfc_pll;
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = samsung,exynos7-clock-ccore;
+ reg = 0x105b 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_ACLK_CCORE_133;
+ clock-names = fin_pll, dout_aclk_ccore_133;
+ };
+
clock_peric0: clock-controller@1361 {
compatible = samsung,exynos7-clock-peric0;
reg = 0x1361 0xd00;
@@ -143,6 +164,27 @@
clock-names = fin_pll, dout_aclk_peris_66;
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = samsung,exynos7-clock-fsys0;
+ reg = 0x10e9 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS0_200,
+clock_top1 DOUT_SCLK_MMC2;
+ clock-names = fin_pll, dout_aclk_fsys0_200,
+ dout_sclk_mmc2;
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = samsung,exynos7-clock-fsys1;
+ reg = 0x156e 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS1_200,
+clock_top1 DOUT_SCLK_MMC0,
+clock_top1 DOUT_SCLK_MMC1;
+ clock-names = fin_pll, dout_aclk_fsys1_200,
+ dout_sclk_mmc0, dout_sclk_mmc1;
+ };
+
serial_0: serial@1363 {
compatible = samsung,exynos4210-uart;
reg = 0x1363 0x100;
@@ -236,6 +278,162 @@
interrupts = 0 203 0;
};
+ hsi2c_0: hsi2c@1364 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1364 0x1000;
+ interrupts = 0 441 0
[PATCH v7 6/7] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. It also enables RTC, WDT and Pinctrl for Exynos7. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 66b0b51..2b5e0b0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -143,6 +143,23 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos7 SoC family + config ARCH_THUNDER bool Cavium Inc. Thunder SoC Family help -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 3/7] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Linus Walleij linus.wall...@linaro.org
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 588
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 654 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..2eef4a2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,588 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ #interrupt-cells = 2;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ #interrupt-cells = 2;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2
[PATCH v7 7/7] arm64: Enable Exynos7 SOC in the defconfig
From: Alim Akhtar alim.akh...@samsung.com Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- arch/arm64/configs/defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ce602c..cc2aa19 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y @@ -84,6 +86,8 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 2/7] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/Makefile |5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183 +++
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8f..fdda246 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..c4cabc6
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti
[PATCH v6 1/7] arm64: dts: add dt-bindings/ symlink
From: Pankaj Dubey pankaj.du...@samsung.com Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299aa8754 (kbuild: create an include chroot for DT bindings) merged in v3.10-rc1 for details. Cc: Catalin Marinas catalin.mari...@arm.com Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com --- arch/arm64/boot/dts/include/dt-bindings |1 + 1 file changed, 1 insertion(+) create mode 12 arch/arm64/boot/dts/include/dt-bindings diff --git a/arch/arm64/boot/dts/include/dt-bindings b/arch/arm64/boot/dts/include/dt-bindings new file mode 12 index 000..08c00e4 --- /dev/null +++ b/arch/arm64/boot/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../../include/dt-bindings \ No newline at end of file -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 0/7] Enable support for Samsung Exynos7 SoC
Exynos7 is a System-On-Chip that is based on 64-bit ARMv8 RISC processor (Cortex-A57). This patchset adds arch/device tree support for Exynos7. These were originally part of 2 patchsets[1][2] adding support for Exynos7. The clock and pinctrl patches are going through the respective maintainer's tree; hence the remaining dt related patches have been consolidated and are being posted here as a separate series. This patchset has build dependencies on the following patches: a] [GIT PULL] Samsung clock changes for 3.19 - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 b] tty: serial: samsung: Clean-up selection of number of available UARTs http://www.spinics.net/lists/linux-samsung-soc/msg37418.html c] dts, kbuild: Implement support for dtb vendor subdirs(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 [1] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html [2] Add clock and DT support for a few IPs on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37973.html Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for EXYNOS7 arm64: dts: Add initial pinctrl support to EXYNOS7 Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/arm/samsung/pmu.txt|1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/Makefile|5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 ++ arch/arm64/boot/dts/include/dt-bindings|1 + arch/arm64/configs/defconfig |4 + 9 files changed, 1231 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 3/7] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Linus Walleij linus.wall...@linaro.org
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 588 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 654 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..2eef4a2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,588 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ #interrupt-cells = 2;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ #interrupt-cells = 2;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2
[PATCH v6 4/7] arm64: dts: Add PMU DT node for exynos7 SoC
Adds PMU DT node for exynos7 SoC.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/arm/samsung/pmu.txt|1 +
arch/arm64/boot/dts/exynos/exynos7.dtsi|5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- samsung,exynos5260-pmu - for Exynos5260 SoC.
- samsung,exynos5410-pmu - for Exynos5410 SoC,
- samsung,exynos5420-pmu - for Exynos5420 SoC.
+ - samsung,exynos7-pmu - for Exynos7 SoC.
second value must be always syscon.
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index c38567a..2bce3f3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
1 11 0xff01,
1 10 0xff01;
};
+
+ pmu_system_controller: system-controller@105c {
+ compatible = samsung,exynos7-pmu, syscon;
+ reg = 0x105c 0x5000;
+ };
};
};
--
1.7.9.5
--
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[PATCH v6 6/7] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. It also enables RTC, WDT and Pinctrl for Exynos7. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 66b0b51..8196889 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -148,6 +148,23 @@ config ARCH_THUNDER help This enables support for Cavium's Thunder Family of SoCs. +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 5/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, watchdog and adc
on Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45
arch/arm64/boot/dts/exynos/exynos7.dtsi | 276 +++
2 files changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..5424cc4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = serial_2;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
};
chosen {
@@ -37,3 +39,46 @@
serial_2 {
status = okay;
};
+
+rtc {
+ status = okay;
+};
+
+watchdog {
+ status = okay;
+};
+
+adc {
+ status = okay;
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_qrdy sd0_bus1 sd0_bus4 sd0_bus8;
+ bus-width = 8;
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ cap-sd-highspeed;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+ disable-wp;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 2bce3f3..cff0256 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
dout_sclk_mfc_pll;
};
+ clock_top1: clock-controller@105e {
+ compatible = samsung,exynos7-clock-top1;
+ reg = 0x105e 0xb000;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_SCLK_BUS0_PLL,
+clock_topc DOUT_SCLK_BUS1_PLL,
+clock_topc DOUT_SCLK_CC_PLL,
+clock_topc DOUT_SCLK_MFC_PLL;
+ clock-names = fin_pll, dout_sclk_bus0_pll,
+ dout_sclk_bus1_pll, dout_sclk_cc_pll,
+ dout_sclk_mfc_pll;
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = samsung,exynos7-clock-ccore;
+ reg = 0x105b 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_ACLK_CCORE_133;
+ clock-names = fin_pll, dout_aclk_ccore_133;
+ };
+
clock_peric0: clock-controller@1361 {
compatible = samsung,exynos7-clock-peric0;
reg = 0x1361 0xd00;
@@ -143,6 +164,27 @@
clock-names = fin_pll, dout_aclk_peris_66;
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = samsung,exynos7-clock-fsys0;
+ reg = 0x10e9 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS0_200,
+clock_top1 DOUT_SCLK_MMC2;
+ clock-names = fin_pll, dout_aclk_fsys0_200,
+ dout_sclk_mmc2;
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = samsung,exynos7-clock-fsys1;
+ reg = 0x156e 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS1_200,
+clock_top1 DOUT_SCLK_MMC0,
+clock_top1 DOUT_SCLK_MMC1;
+ clock-names = fin_pll, dout_aclk_fsys1_200,
+ dout_sclk_mmc0, dout_sclk_mmc1;
+ };
+
serial_0: serial@1363 {
compatible = samsung,exynos4210-uart;
reg = 0x1363 0x100;
@@ -236,6 +278,162 @@
interrupts = 0 203 0;
};
+ hsi2c_0: hsi2c@1364 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1364 0x1000;
+ interrupts = 0 441 0
[PATCH v6 7/7] arm64: Enable Exynos7 SOC in the defconfig
From: Alim Akhtar alim.akh...@samsung.com Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- arch/arm64/configs/defconfig |4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ce602c..cc2aa19 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y @@ -84,6 +86,8 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] tty: serial: samsung: Clean-up selection of number of available UARTs
Hello Kukjin,
On Fri, Oct 31, 2014 at 8:06 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Kukjin,
On Tue, Oct 28, 2014 at 5:56 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Kukjin
On Tue, Oct 28, 2014 at 4:01 PM, Kukjin Kim kg...@kernel.org wrote:
Abhilash Kesavan wrote:
Hi,
Sorry for late response.
Remove symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS which
select the number of UART ports available on the SoC. Replace the usage
of SERIAL_SAMSUNG_UARTS in the serial driver with the maximum number of
Well, as you know the number of uart ports are different on each Samsung
SoCs
so I don't think just using maximum number of uart ports are possible for
new
exynos7 SoC at this moment.
Thanks for the review.
The main reason for me sending this patch was so that we may be able
to re-use the serial driver on arm64 based Exynos7 too. The two
symbols mentioned above which depend on PLAT_SAMSUNG prevent this. I
initially sent a patch which changed the dependency to SERIAL_SAMSUNG
for these 2 symbols. However, Tomasz suggested that a clean-up of
these two symbols would be a better option.
Please see the discussion of the previous version here:
https://lkml.org/lkml/2014/9/29/702
Can you please let me know if the previous version is acceptable ?
Kukjin, can you please indicate the approach you would like me to
take. Without this serial support is blocked on Exynos7.
Gentle reminder on this.
Abhilash
Thanks,
Abhilash
UART ports possible. Removal of these symbols also helps in Exynos7
serial enablement.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig | 16
drivers/tty/serial/samsung.c | 11 +++
drivers/tty/serial/samsung.h |5 -
3 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 81f6ee7..9fc9092 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -247,22 +247,6 @@ config SERIAL_SAMSUNG
provide all of these ports, depending on how the serial port
pins are configured.
-config SERIAL_SAMSUNG_UARTS_4
- bool
- depends on PLAT_SAMSUNG
- default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 ||
CPU_S3C2442)
- help
- Internal node for the common case of 4 Samsung compatible UARTs
-
-config SERIAL_SAMSUNG_UARTS
- int
- depends on PLAT_SAMSUNG
- default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416
- default 3
- help
- Select the number of available UART ports for the Samsung S3C
- serial driver
-
config SERIAL_SAMSUNG_DEBUG
bool Samsung SoC serial debug
depends on SERIAL_SAMSUNG DEBUG_LL
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index c78f43a..ba04c6d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -962,14 +962,14 @@ static struct uart_ops s3c24xx_serial_ops = {
static struct uart_driver s3c24xx_uart_drv = {
.owner = THIS_MODULE,
.driver_name= s3c2410_serial,
- .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
+ .nr = MAX_SAMSUNG_UARTS,
.cons = S3C24XX_SERIAL_CONSOLE,
.dev_name = S3C24XX_SERIAL_NAME,
.major = S3C24XX_SERIAL_MAJOR,
.minor = S3C24XX_SERIAL_MINOR,
};
-static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
+static struct s3c24xx_uart_port s3c24xx_serial_ports[MAX_SAMSUNG_UARTS] =
{
[0] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
@@ -992,8 +992,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 1,
}
},
-#if CONFIG_SERIAL_SAMSUNG_UARTS 2
-
[2] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
@@ -1005,8 +1003,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 2,
}
},
-#endif
-#if CONFIG_SERIAL_SAMSUNG_UARTS 3
[3] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
@@ -1018,7 +1014,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 3,
}
}
-#endif
};
/* s3c24xx_serial_resetport
@@ -1590,7 +1585,7 @@ s3c24xx_serial_console_setup(struct console *co,
char *options)
/* is this a valid port */
- if (co-index == -1 || co-index = CONFIG_SERIAL_SAMSUNG_UARTS
Re: [PATCH v2 2/2] tty: serial: samsung: Clean-up selection of number of available UARTs
Hi Kukjin,
On Tue, Oct 28, 2014 at 5:56 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Kukjin
On Tue, Oct 28, 2014 at 4:01 PM, Kukjin Kim kg...@kernel.org wrote:
Abhilash Kesavan wrote:
Hi,
Sorry for late response.
Remove symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS which
select the number of UART ports available on the SoC. Replace the usage
of SERIAL_SAMSUNG_UARTS in the serial driver with the maximum number of
Well, as you know the number of uart ports are different on each Samsung SoCs
so I don't think just using maximum number of uart ports are possible for new
exynos7 SoC at this moment.
Thanks for the review.
The main reason for me sending this patch was so that we may be able
to re-use the serial driver on arm64 based Exynos7 too. The two
symbols mentioned above which depend on PLAT_SAMSUNG prevent this. I
initially sent a patch which changed the dependency to SERIAL_SAMSUNG
for these 2 symbols. However, Tomasz suggested that a clean-up of
these two symbols would be a better option.
Please see the discussion of the previous version here:
https://lkml.org/lkml/2014/9/29/702
Can you please let me know if the previous version is acceptable ?
Kukjin, can you please indicate the approach you would like me to
take. Without this serial support is blocked on Exynos7.
Thanks,
Abhilash
UART ports possible. Removal of these symbols also helps in Exynos7
serial enablement.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig | 16
drivers/tty/serial/samsung.c | 11 +++
drivers/tty/serial/samsung.h |5 -
3 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 81f6ee7..9fc9092 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -247,22 +247,6 @@ config SERIAL_SAMSUNG
provide all of these ports, depending on how the serial port
pins are configured.
-config SERIAL_SAMSUNG_UARTS_4
- bool
- depends on PLAT_SAMSUNG
- default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 ||
CPU_S3C2442)
- help
- Internal node for the common case of 4 Samsung compatible UARTs
-
-config SERIAL_SAMSUNG_UARTS
- int
- depends on PLAT_SAMSUNG
- default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416
- default 3
- help
- Select the number of available UART ports for the Samsung S3C
- serial driver
-
config SERIAL_SAMSUNG_DEBUG
bool Samsung SoC serial debug
depends on SERIAL_SAMSUNG DEBUG_LL
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index c78f43a..ba04c6d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -962,14 +962,14 @@ static struct uart_ops s3c24xx_serial_ops = {
static struct uart_driver s3c24xx_uart_drv = {
.owner = THIS_MODULE,
.driver_name= s3c2410_serial,
- .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
+ .nr = MAX_SAMSUNG_UARTS,
.cons = S3C24XX_SERIAL_CONSOLE,
.dev_name = S3C24XX_SERIAL_NAME,
.major = S3C24XX_SERIAL_MAJOR,
.minor = S3C24XX_SERIAL_MINOR,
};
-static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
+static struct s3c24xx_uart_port s3c24xx_serial_ports[MAX_SAMSUNG_UARTS] = {
[0] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
@@ -992,8 +992,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 1,
}
},
-#if CONFIG_SERIAL_SAMSUNG_UARTS 2
-
[2] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
@@ -1005,8 +1003,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 2,
}
},
-#endif
-#if CONFIG_SERIAL_SAMSUNG_UARTS 3
[3] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
@@ -1018,7 +1014,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 3,
}
}
-#endif
};
/* s3c24xx_serial_resetport
@@ -1590,7 +1585,7 @@ s3c24xx_serial_console_setup(struct console *co, char
*options)
/* is this a valid port */
- if (co-index == -1 || co-index = CONFIG_SERIAL_SAMSUNG_UARTS)
+ if (co-index == -1 || co-index = MAX_SAMSUNG_UARTS)
If we use max number, second condition is not required...
co-index = 0
Re: [PATCH v2 1/2] arch: arm: samsung: Clean-up usage of CONFIG_SERIAL_SAMSUNG_UARTS symbol
Hi Kukjin,
On Mon, Oct 20, 2014 at 7:11 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Kukjin,
On Wed, Oct 1, 2014 at 10:12 PM, Abhilash Kesavan a.kesa...@samsung.com
wrote:
Remove usage of CONFIG_SERIAL_SAMSUNG_UARTS symbol from platform
specific code.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Can you please pick this up if it looks OK ?
A gentle reminder on these 2 patches.
Abhilash
Abhilash
---
Changes in v2:
- Re-ordered the patches
- Added a define for number of uart ports in
arch/arm/plat-samsung/init.c
- Removed CONFIG_SERIAL_SAMSUNG #ifdef in
arch/arm/plat-samsung/init.c
Build tested using s3c2410_defconfig, s3c6400_defconfig, exynos_defconfig
and arm64's defconfig with and without the serial driver enabled. Boot tested
on Exynos5420 and Exynos7.
arch/arm/mach-s3c64xx/irq-pm.c |6 +++---
arch/arm/plat-samsung/init.c |7 ++-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index ae4ea76..b20024e 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -55,10 +55,10 @@ static struct irq_grp_save {
u32 mask;
} eint_grp_save[5];
-#ifndef CONFIG_SERIAL_SAMSUNG_UARTS
-#define SERIAL_SAMSUNG_UARTS 0
+#ifndef CONFIG_SERIAL_SAMSUNG
+#define SERIAL_SAMSUNG_UARTS 0
#else
-#defineSERIAL_SAMSUNG_UARTS CONFIG_SERIAL_SAMSUNG_UARTS
+#define SERIAL_SAMSUNG_UARTS 4
#endif
static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS];
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 11fbbc2..6114942 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -92,10 +92,9 @@ void __init s3c24xx_init_clocks(int xtal)
/* uart management */
#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
static int nr_uarts __initdata = 0;
+#define MAX_UART_PORTS 4
-#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
-static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
-#endif
+static struct s3c2410_uartcfg uart_cfgs[MAX_UART_PORTS];
/* s3c24xx_init_uartdevs
*
@@ -110,7 +109,6 @@ void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no)
{
-#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
struct platform_device *platdev;
struct s3c2410_uartcfg *cfgptr = uart_cfgs;
struct s3c24xx_uart_resources *resp;
@@ -133,7 +131,6 @@ void __init s3c24xx_init_uartdevs(char *name,
}
nr_uarts = no;
-#endif
}
void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
--
1.7.9.5
--
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Re: [PATCH v2 3/7] clk: samsung: exynos7: add clocks for RTC block
Hello Sylwester, On Mon, Oct 27, 2014 at 10:01 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: Hi, On 21/10/14 07:43, Abhilash Kesavan wrote: From: Naveen Krishna Ch naveenkrishna...@gmail.com Add clock support for the RTC block in Exynos7. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- .../devicetree/bindings/clock/exynos7-clock.txt|5 ++ drivers/clk/samsung/clk-exynos7.c | 54 include/dt-bindings/clock/exynos7-clk.h| 17 +++--- 3 files changed, 70 insertions(+), 6 deletions(-) [...] diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index ff63c4e..3227679 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -11,12 +11,13 @@ #define _DT_BINDINGS_CLOCK_EXYNOS7_H /* TOPC */ -#define DOUT_ACLK_PERIS 1 -#define DOUT_SCLK_BUS0_PLL 2 -#define DOUT_SCLK_BUS1_PLL 3 -#define DOUT_SCLK_CC_PLL 4 -#define DOUT_SCLK_MFC_PLL5 -#define TOPC_NR_CLK 6 +#define DOUT_ACLK_CCORE_133 1 +#define DOUT_ACLK_PERIS 2 +#define DOUT_SCLK_BUS0_PLL 3 +#define DOUT_SCLK_BUS1_PLL 4 +#define DOUT_SCLK_CC_PLL 5 +#define DOUT_SCLK_MFC_PLL6 +#define TOPC_NR_CLK 7 Please don't do that, don't change the meaning of already defined clock identifiers. We should carefully assign the clock identifiers based on the SoC documentation beforehand, not at will when we see fit for development of the Linux driver. Please either add DOUT_ACLK_CCORE_133 at the end of list or move this change to the first patch in your series adding initial support for Exynos7 SoC. Thanks for reviewing this series and picking up the initial patchset. I will re-post this patchset with the ccore clock at the end of the list. All the future clock id entries will be added at the bottom of the list. Regards, Abhilash -- Thanks, Sylwester ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/5] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt| 21 ++
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 265 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..b29cb50 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -50,6 +53,13 @@ Input clocks for top0 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for top1 clock controller:
+ - fin_pll
+ - dout_sclk_bus0_pll
+ - dout_sclk_bus1_pll
+ - dout_sclk_cc_pll
+ - dout_sclk_mfc_pll
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
@@ -65,3 +75,14 @@ Input clocks for peric1 clock controller:
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+ - fin_pll
+ - dout_aclk_fsys0_200
+ - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+ - fin_pll
+ - dout_aclk_fsys1_200
+ - dout_sclk_mmc0
+ - dout_sclk_mmc1
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0
[PATCH v3 3/5] clk: samsung: exynos7: add clocks for RTC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the RTC block in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|5 ++
drivers/clk/samsung/clk-exynos7.c | 54
include/dt-bindings/clock/exynos7-clk.h|7 ++-
3 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index b29cb50..6d3d5f8 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
@@ -60,6 +61,10 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for ccore clock controller:
+ - fin_pll
+ - dout_aclk_ccore_133
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index f5e43fa..3a30f43 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -29,7 +29,9 @@
#define AUD_PLL_CON0 0x0140
#define MUX_SEL_TOPC0 0x0200
#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC2 0x0208
#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
AUD_PLL_CON0,
MUX_SEL_TOPC0,
MUX_SEL_TOPC1,
+ MUX_SEL_TOPC2,
MUX_SEL_TOPC3,
+ DIV_TOPC0,
DIV_TOPC1,
DIV_TOPC3,
};
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[]
__initdata = {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
MUX(0, mout_aclk_peris_66, mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
};
static struct samsung_div_clock topc_div_clks[] __initdata = {
+ DIV(DOUT_ACLK_CCORE_133, dout_aclk_ccore_133, mout_aclk_ccore_133,
+ DIV_TOPC0, 4, 4),
+
DIV(DOUT_ACLK_PERIS, dout_aclk_peris_66, mout_aclk_peris_66,
DIV_TOPC1, 24, 4),
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_CCORE (0x105B) */
+#define MUX_SEL_CCORE 0x0200
+#define DIV_CCORE 0x0600
+#define ENABLE_ACLK_CCORE0 0x0800
+#define ENABLE_ACLK_CCORE1 0x0804
+#define ENABLE_PCLK_CCORE 0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p) = { fin_pll, dout_aclk_ccore_133 };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+ MUX_SEL_CCORE,
+ ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+ MUX(0, mout_aclk_ccore_133_user, mout_aclk_ccore_133_p,
+ MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+ GATE(PCLK_RTC, pclk_rtc, mout_aclk_ccore_133_user,
+ ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+ .mux_clks = ccore_mux_clks,
+ .nr_mux_clks= ARRAY_SIZE(ccore_mux_clks),
+ .gate_clks = ccore_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
+ .nr_clk_ids = CCORE_NR_CLK,
+ .clk_regs = ccore_clk_regs,
+ .nr_clk_regs= ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, samsung,exynos7-clock-ccore,
+ exynos7_clk_ccore_init);
+
/* Register Offset definitions for CMU_PERIC0 (0x1361) */
#define MUX_SEL_PERIC0 0x0200
#define ENABLE_PCLK_PERIC0 0x0900
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index ff63c4e..dd89aa0 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -16,7 +16,8 @@
#define DOUT_SCLK_BUS1_PLL 3
#define
[PATCH v3 1/5] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, pclk_hsi2c0, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, pclk_hsi2c1, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, pclk_hsi2c4, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, pclk_hsi2c5, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, pclk_hsi2c9, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, pclk_hsi2c10, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, pclk_hsi2c11, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, pclk_hsi2c2, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, pclk_hsi2c3, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, pclk_hsi2c6, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, pclk_hsi2c7, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, pclk_hsi2c8, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, pclk_uart1, mout_aclk_peric1_66_user,
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, pclk_uart2, mout_aclk_peric1_66_user,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
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[PATCH v3 4/5] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, pclk_pwm, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, sclk_uart0_user, mout_sclk_uart0_user,
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, sclk_pwm, fin_pll, ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
samsung,exynos7-clock-peric1,
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { fin_pll,
dout_aclk_peris_66 };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, pclk_wdt, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, pclk_tmu_apbif, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, pclk_chipid, mout_aclk_peris_66_user,
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, sclk_chipid, fin_pll,
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, sclk_tmu, fin_pll, ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index dd89aa0..f255bb7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
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[PATCH v3 5/5] clk: samsung: exynos7: add gate clock for ADC block
Add clock support for the ADC interface in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c |2 ++
include/dt-bindings/clock/exynos7-clk.h |3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 17e5cf4..ea4483b 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,6 +486,8 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_ADCIF, pclk_adcif, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 20, 0, 0),
GATE(PCLK_PWM, pclk_pwm, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 21, 0, 0),
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index f255bb7..8e4681b0 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -55,7 +55,8 @@
#define PCLK_HSI2C11 9
#define PCLK_PWM 10
#define SCLK_PWM 11
-#define PERIC0_NR_CLK 12
+#define PCLK_ADCIF 12
+#define PERIC0_NR_CLK 13
/* PERIC1 */
#define PCLK_UART1 1
--
1.7.9.5
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Re: [PATCH v2 2/2] tty: serial: samsung: Clean-up selection of number of available UARTs
Hi Kukjin
On Tue, Oct 28, 2014 at 4:01 PM, Kukjin Kim kg...@kernel.org wrote:
Abhilash Kesavan wrote:
Hi,
Sorry for late response.
Remove symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS which
select the number of UART ports available on the SoC. Replace the usage
of SERIAL_SAMSUNG_UARTS in the serial driver with the maximum number of
Well, as you know the number of uart ports are different on each Samsung SoCs
so I don't think just using maximum number of uart ports are possible for new
exynos7 SoC at this moment.
Thanks for the review.
The main reason for me sending this patch was so that we may be able
to re-use the serial driver on arm64 based Exynos7 too. The two
symbols mentioned above which depend on PLAT_SAMSUNG prevent this. I
initially sent a patch which changed the dependency to SERIAL_SAMSUNG
for these 2 symbols. However, Tomasz suggested that a clean-up of
these two symbols would be a better option.
Please see the discussion of the previous version here:
https://lkml.org/lkml/2014/9/29/702
Can you please let me know if the previous version is acceptable ?
UART ports possible. Removal of these symbols also helps in Exynos7
serial enablement.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig | 16
drivers/tty/serial/samsung.c | 11 +++
drivers/tty/serial/samsung.h |5 -
3 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 81f6ee7..9fc9092 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -247,22 +247,6 @@ config SERIAL_SAMSUNG
provide all of these ports, depending on how the serial port
pins are configured.
-config SERIAL_SAMSUNG_UARTS_4
- bool
- depends on PLAT_SAMSUNG
- default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 ||
CPU_S3C2442)
- help
- Internal node for the common case of 4 Samsung compatible UARTs
-
-config SERIAL_SAMSUNG_UARTS
- int
- depends on PLAT_SAMSUNG
- default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416
- default 3
- help
- Select the number of available UART ports for the Samsung S3C
- serial driver
-
config SERIAL_SAMSUNG_DEBUG
bool Samsung SoC serial debug
depends on SERIAL_SAMSUNG DEBUG_LL
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index c78f43a..ba04c6d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -962,14 +962,14 @@ static struct uart_ops s3c24xx_serial_ops = {
static struct uart_driver s3c24xx_uart_drv = {
.owner = THIS_MODULE,
.driver_name= s3c2410_serial,
- .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
+ .nr = MAX_SAMSUNG_UARTS,
.cons = S3C24XX_SERIAL_CONSOLE,
.dev_name = S3C24XX_SERIAL_NAME,
.major = S3C24XX_SERIAL_MAJOR,
.minor = S3C24XX_SERIAL_MINOR,
};
-static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
+static struct s3c24xx_uart_port s3c24xx_serial_ports[MAX_SAMSUNG_UARTS] = {
[0] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
@@ -992,8 +992,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 1,
}
},
-#if CONFIG_SERIAL_SAMSUNG_UARTS 2
-
[2] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
@@ -1005,8 +1003,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 2,
}
},
-#endif
-#if CONFIG_SERIAL_SAMSUNG_UARTS 3
[3] = {
.port = {
.lock =
__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
@@ -1018,7 +1014,6 @@ static struct s3c24xx_uart_port
s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS
.line = 3,
}
}
-#endif
};
/* s3c24xx_serial_resetport
@@ -1590,7 +1585,7 @@ s3c24xx_serial_console_setup(struct console *co, char
*options)
/* is this a valid port */
- if (co-index == -1 || co-index = CONFIG_SERIAL_SAMSUNG_UARTS)
+ if (co-index == -1 || co-index = MAX_SAMSUNG_UARTS)
If we use max number, second condition is not required...
co-index = 0;
port = s3c24xx_serial_ports[co-index].port;
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index eb071dd..484b49e 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -1,6 +1,9
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
+Sylwester On Wed, Oct 8, 2014 at 11:18 AM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Hi Tomasz, On Tue, Oct 7, 2014 at 9:46 AM, Kukjin Kim kg...@kernel.org wrote: Tomasz Figa wrote: On 30.09.2014 17:12, Abhilash Kesavan wrote: Hi Tomasz, On Mon, Sep 22, 2014 at 2:22 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Abhilash, On 22.09.2014 06:47, Abhilash Kesavan wrote: Changes since v4: - Fixed comments from Tomasz Figa: - Changed the namespace prefix from exynos to samsung - Defined bindings to take all input clocks - Sorted the Kconfig entries alphabetically in clock Makefile - Used consistent 1 tab line breaks across the clock file - Statically initialized the samsung_cmu_info struct - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags. The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds. Will you be picking up the clock changes soon ? I'd like to do so. Kukjin, since clock changes are a part of this series, might I have your Ack for them to be applied separately? Sure, I'm fine so please go ahead with my ack on the changes. Acked-by: Kukjin Kim kgene@samsung.com Thanks for your asking. Can you please pick up the clock changes now that Kukjin has ack'ed it. Sylwester, you mentioned in another thread that Tomasz might not be available for the next few days. Could you please consider applying the clock changes in this series to samsung clk-next if they look OK ? Please take a look at clock changes at http://www.spinics.net/lists/arm-kernel/msg370673.html too. Regards, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Fri, Oct 24, 2014 at 5:31 PM, Linus Walleij linus.wall...@linaro.org wrote: On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan kesavan.abhil...@gmail.com wrote: Can you please pick this series up. Yes, sorry for the delay. I've applied patches 1,2,3,4. The patches to the DTS files should be taken through whatever tree funnels arm64 dts files. Thank you for applying my patches. However, this version (v5) was based on Tomasz's clean-up series and makes use of structures such as samsung_pin_bank_data introduced by his series. It also marks the samsung_pin_ctrl instance as __initconst. Thus, patch 4 would cause compilation issues if Tomasz's clean-up patches have not been applied before it. My v4 version was independent of Tomasz's patch series and could be applied directly. Regards, Abhilash I hope Tomasz can rebase his nice clean-up patches on top of this now. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5422-odroid-xu3: MCPM: only 6 of 8 CPUs coming online
Hello Kevin, On Thu, Oct 23, 2014 at 9:26 PM, Kevin Hilman khil...@kernel.org wrote: Abhilash Kesavan a.kesa...@samsung.com writes: The change was based on my reading of the platsmp file of the Odroid-xu3 3.10 kernel and issues experienced previously. From what I understand, the platsmp code in 3.10 kernel is trying to reset the A7s and my change just bypasses the check (no magic here ). The change was only suggested as a workaround to get 8 cores up using MCPM and not an actual fix. I had explained this in my mail to Kevin. So, if this were to be mainlined we would probably need to use something like exynos_core_restart in mcpm along with the workaround. But, this is all guesswork on my part and someone with knowledge of the 3.10 kernel/bootloader needs to comment. Unfortunately, the harkernel tree git repo doesn't help understand where the change came from because an entire v3.10.y based Samsung BSP is checked into the tree on top of a v3.8.y kernel in a single commit !!! Abhilash, in the absence of the original author, could write up a patch with your change? Or, if you can help me with a detailed changelog, I can work on the patch. I don't have any exynos docs, so it would be good to have a description of what reading/writing to that register are actually doing. I could post a patch with an explanation of how I think the workaround works, but there are a few issues: - I am not completely confident that this is the best/right change. - We are adding code to the exynos mcpm back-end to work-around a bootloader setting for Odroid-xu3. We would have to make it specific to odroid somehow as we do not require it for 5420/5800 chromebooks. - This might solve the 8 core boot-up issue but other scenarios might still fail like the one Joonyoung has already reported. Also, can you explain what you meant by using exynos_core_restart? I don't see that function in mainline. It is present in linux-next and kgene's for-next branch as part of this commit ARM: EXYNOS: SWRESET is needed to boot secondary CPU on exynos3250. Regards, Abhilash -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
Hi Alim and Tomasz,
Thanks for the review.
On Wed, Oct 22, 2014 at 3:05 AM, Alim Akhtar alim.akh...@gmail.com wrote:
Hi Tomasz,
On Tue, Oct 21, 2014 at 7:30 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 21.10.2014 15:52, Alim Akhtar wrote:
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
Please use mmc_hs200-1_8v instead.
I guess you mean mmc-hs200-1_8v (with a hyphen between mmc and hs200).
Yes, right, that was a typo. Thanks.
Will modify it to mmc-hs200-1_8v.
+ supports-highspeed;
As per synopsys-dw-mshc DT binding documentation, supports-highspeed
property is deprecated, so please use common DT binding for this,
which is cap-mmc-highspeed.
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_qrdy sd0_bus1 sd0_bus4
sd0_bus8;
+ bus-width = 8;
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
Here also common DT binding please cap-sd-highspeed
Above you suggest cap-mmc-highspeed to replace the same deprecated
property, but here cap-sd-highspeed. What is the rationale behind
using only one particular new property and not both for both controllers?
Well, on this particular board dw_mmc channels are dedicated to use
only one kind of card. e.g. mmc_0 is for eMMC and which is
non-removable and mmc_2 is for SD cards. Although controller supports
both the properties on all channel on this SoC.
Will use cap-sd/mmc-highspeed instead of supports-highspeed.
Regards,
Abhilash
Best regards,
Tomasz
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Alim
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Re: [PATCH v2 1/2] arch: arm: samsung: Clean-up usage of CONFIG_SERIAL_SAMSUNG_UARTS symbol
Hi Kukjin,
On Wed, Oct 1, 2014 at 10:12 PM, Abhilash Kesavan a.kesa...@samsung.com wrote:
Remove usage of CONFIG_SERIAL_SAMSUNG_UARTS symbol from platform
specific code.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Can you please pick this up if it looks OK ?
Abhilash
---
Changes in v2:
- Re-ordered the patches
- Added a define for number of uart ports in
arch/arm/plat-samsung/init.c
- Removed CONFIG_SERIAL_SAMSUNG #ifdef in arch/arm/plat-samsung/init.c
Build tested using s3c2410_defconfig, s3c6400_defconfig, exynos_defconfig
and arm64's defconfig with and without the serial driver enabled. Boot tested
on Exynos5420 and Exynos7.
arch/arm/mach-s3c64xx/irq-pm.c |6 +++---
arch/arm/plat-samsung/init.c |7 ++-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index ae4ea76..b20024e 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -55,10 +55,10 @@ static struct irq_grp_save {
u32 mask;
} eint_grp_save[5];
-#ifndef CONFIG_SERIAL_SAMSUNG_UARTS
-#define SERIAL_SAMSUNG_UARTS 0
+#ifndef CONFIG_SERIAL_SAMSUNG
+#define SERIAL_SAMSUNG_UARTS 0
#else
-#defineSERIAL_SAMSUNG_UARTS CONFIG_SERIAL_SAMSUNG_UARTS
+#define SERIAL_SAMSUNG_UARTS 4
#endif
static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS];
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 11fbbc2..6114942 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -92,10 +92,9 @@ void __init s3c24xx_init_clocks(int xtal)
/* uart management */
#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
static int nr_uarts __initdata = 0;
+#define MAX_UART_PORTS 4
-#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
-static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
-#endif
+static struct s3c2410_uartcfg uart_cfgs[MAX_UART_PORTS];
/* s3c24xx_init_uartdevs
*
@@ -110,7 +109,6 @@ void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no)
{
-#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
struct platform_device *platdev;
struct s3c2410_uartcfg *cfgptr = uart_cfgs;
struct s3c24xx_uart_resources *resp;
@@ -133,7 +131,6 @@ void __init s3c24xx_init_uartdevs(char *name,
}
nr_uarts = no;
-#endif
}
void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
--
1.7.9.5
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Re: [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
Hi Vivek,
On Mon, Oct 20, 2014 at 3:19 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
Hi Abhilash,
On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan a.kesa...@samsung.com
wrote:
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|3 +
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 247 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
same here, the input clocks for top1, fsys0 and fsys1 block need to be
mentioned in this doc.
Thanks for the review. I missed adding these, will fix in the next version.
Regards,
Abhilash
- reg: physical base address of the controller and the length of
memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4,
1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0, mout_aclk_fsys1_200, mout_top1_group1, MUX_SEL_TOP13, 24,
2),
+ MUX(0, mout_aclk_fsys0_200, mout_top1_group1, MUX_SEL_TOP13, 28,
2),
+
+ MUX(0, mout_sclk_mmc2, mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24,
2),
+
+ MUX(0, mout_sclk_mmc1, mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24,
2
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Sun, Oct 12, 2014 at 12:27 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Abhilash, Linus, On 09.10.2014 15:54, Abhilash Kesavan wrote: Changes since v4: - Rebased over Tomasz Figa's pinctrl clean-up patches[1] Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham This series has been tested on linux-next (20141008) https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ with the following dependencies and [1]. a) Samsung Serial symbol clean-up for exynos7 serial driver enablement (v2) http://www.spinics.net/lists/arm-kernel/msg366947.html http://www.spinics.net/lists/arm-kernel/msg366948.html b) dts, kbuild: Implement support for dtb vendor subdirs patchset - rebased http://comments.gmane.org/gmane.linux.kbuild.devel/12131 c) arch: arm64: enable support for Samsung Exynos7 SoC patchset (v5) - rebased http://www.spinics.net/lists/arm-kernel/msg364014.html [1] https://lkml.org/lkml/2014/10/2/476 Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 188 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 791 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi No further comments from me. Thanks Abhilash for addressing all of them. Linus, feel free to apply this series with my ACK (which seems to be already present in all patches). Can you please pick this series up. Thanks, Abhilash Best regards, Tomasz ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/7] Add clock and DT support for a few IPs on Exynos7
Changes since v1: - Added documentation for input clocks of the newly added CMUs Following are the dependencies: 1) dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 2) arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html 3) Serial clean-up patches for Exynos7 http://www.spinics.net/lists/arm-kernel/msg367348.html http://www.spinics.net/lists/arm-kernel/msg367349.html 4) Add initial support for pinctrl on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37708.html For testing I have applied the following: 1) mmc: dw_mmc: Add IDMAC 64-bit address mode support http://www.spinics.net/lists/kernel/msg1842300.html 2) mmc: dw_mmc: Reset DMA before enabling IDMAC http://www.gossamer-threads.com/lists/linux/kernel/2021576?page=last 3) drivers: rtc: fix s3c-rtc initialization failure without rtc source clock https://lkml.org/lkml/2014/10/15/210 4) mfd: sec: add S2MPS15 PMIC support https://lkml.org/lkml/2014/10/14/50 5) regulator: s2mps11: add support for S2MPS15 regulators https://lkml.org/lkml/2014/10/14/52 6) Regulators dt nodes were added in the espresso dts file and I2C channel 4 which has the PMIC on it was tested. 7) watchdog: s3c2410_wdt: Fix the mask bit offset for Exynos7 http://www.spinics.net/lists/linux-watchdog/msg05292.html Abhilash Kesavan (3): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7 arm64: exynos: Enable rtc and watchdog support for Exynos7 Naveen Krishna Ch (4): clk: samsung: exynos7: add clocks for I2C block clk: samsung: exynos7: add clocks for MMC block clk: samsung: exynos7: add clocks for RTC block clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks .../devicetree/bindings/arm/samsung/pmu.txt|1 + .../devicetree/bindings/clock/exynos7-clock.txt| 26 ++ arch/arm64/Kconfig |3 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 41 +++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 261 drivers/clk/samsung/clk-exynos7.c | 316 include/dt-bindings/clock/exynos7-clk.h| 60 +++- 7 files changed, 699 insertions(+), 9 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/7] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, pclk_hsi2c0, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, pclk_hsi2c1, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, pclk_hsi2c4, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, pclk_hsi2c5, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, pclk_hsi2c9, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, pclk_hsi2c10, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, pclk_hsi2c11, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, pclk_hsi2c2, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, pclk_hsi2c3, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, pclk_hsi2c6, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, pclk_hsi2c7, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, pclk_hsi2c8, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, pclk_uart1, mout_aclk_peric1_66_user,
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, pclk_uart2, mout_aclk_peric1_66_user,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
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[PATCH v2 2/7] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt| 21 ++
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 265 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..b29cb50 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -50,6 +53,13 @@ Input clocks for top0 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for top1 clock controller:
+ - fin_pll
+ - dout_sclk_bus0_pll
+ - dout_sclk_bus1_pll
+ - dout_sclk_cc_pll
+ - dout_sclk_mfc_pll
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
@@ -65,3 +75,14 @@ Input clocks for peric1 clock controller:
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+ - fin_pll
+ - dout_aclk_fsys0_200
+ - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+ - fin_pll
+ - dout_aclk_fsys1_200
+ - dout_sclk_mmc0
+ - dout_sclk_mmc1
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0
[PATCH v2 3/7] clk: samsung: exynos7: add clocks for RTC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the RTC block in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|5 ++
drivers/clk/samsung/clk-exynos7.c | 54
include/dt-bindings/clock/exynos7-clk.h| 17 +++---
3 files changed, 70 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index b29cb50..6d3d5f8 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
@@ -60,6 +61,10 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for ccore clock controller:
+ - fin_pll
+ - dout_aclk_ccore_133
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index f5e43fa..3a30f43 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -29,7 +29,9 @@
#define AUD_PLL_CON0 0x0140
#define MUX_SEL_TOPC0 0x0200
#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC2 0x0208
#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
AUD_PLL_CON0,
MUX_SEL_TOPC0,
MUX_SEL_TOPC1,
+ MUX_SEL_TOPC2,
MUX_SEL_TOPC3,
+ DIV_TOPC0,
DIV_TOPC1,
DIV_TOPC3,
};
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[]
__initdata = {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
MUX(0, mout_aclk_peris_66, mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
};
static struct samsung_div_clock topc_div_clks[] __initdata = {
+ DIV(DOUT_ACLK_CCORE_133, dout_aclk_ccore_133, mout_aclk_ccore_133,
+ DIV_TOPC0, 4, 4),
+
DIV(DOUT_ACLK_PERIS, dout_aclk_peris_66, mout_aclk_peris_66,
DIV_TOPC1, 24, 4),
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_CCORE (0x105B) */
+#define MUX_SEL_CCORE 0x0200
+#define DIV_CCORE 0x0600
+#define ENABLE_ACLK_CCORE0 0x0800
+#define ENABLE_ACLK_CCORE1 0x0804
+#define ENABLE_PCLK_CCORE 0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p) = { fin_pll, dout_aclk_ccore_133 };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+ MUX_SEL_CCORE,
+ ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+ MUX(0, mout_aclk_ccore_133_user, mout_aclk_ccore_133_p,
+ MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+ GATE(PCLK_RTC, pclk_rtc, mout_aclk_ccore_133_user,
+ ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+ .mux_clks = ccore_mux_clks,
+ .nr_mux_clks= ARRAY_SIZE(ccore_mux_clks),
+ .gate_clks = ccore_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
+ .nr_clk_ids = CCORE_NR_CLK,
+ .clk_regs = ccore_clk_regs,
+ .nr_clk_regs= ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, samsung,exynos7-clock-ccore,
+ exynos7_clk_ccore_init);
+
/* Register Offset definitions for CMU_PERIC0 (0x1361) */
#define MUX_SEL_PERIC0 0x0200
#define ENABLE_PCLK_PERIC0 0x0900
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index ff63c4e..3227679 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -11,12 +11,13 @@
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
/* TOPC
[PATCH v2 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, pclk_pwm, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, sclk_uart0_user, mout_sclk_uart0_user,
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, sclk_pwm, fin_pll, ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
samsung,exynos7-clock-peric1,
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { fin_pll,
dout_aclk_peris_66 };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, pclk_wdt, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, pclk_tmu_apbif, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, pclk_chipid, mout_aclk_peris_66_user,
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, sclk_chipid, fin_pll,
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, sclk_tmu, fin_pll, ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
--
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