Hello,
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk is not enough.
Signed-off-by: Vivek Gautam
Hi Vivek,
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
In case of the PHY the situation is pretty much the same as with
DWC3 core. Here we should control 6 clocks to make
Hi Vivek,
Some Exynos SoCs have a separate regulator controlling a
I guess you meant the Exynos based *boards* instead of SoCs,
since Exynos SoCs don't have any boost regulators.
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
Hi,
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To: linux
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators'
Hi,
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches
Hi Kamil,
...
+| 3. Supporting SoCs
++
+
+To support a new SoC a new file should be added to the drivers/phy
+directory. Each SoC's configuration is stored in an instance of the
+struct samsung_usb2_phy_config.
+
+struct samsung_usb2_phy_config {
+ const struct
Hello,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
On Thursday 06 March 2014 01:56 PM, Anton Tikhomirov wrote:
Hi Kamil,
...
+| 3. Supporting SoCs
++
+
+To support a new SoC a new file should be added to the drivers/phy
Hi,
Subject: RE: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
On Thursday 06 March 2014 02:22 PM, Anton Tikhomirov wrote:
Hello,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY
Hi,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
On Thursday 06 March 2014 02:49 PM, Anton Tikhomirov wrote:
Hi,
Subject: RE: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi Kamil,
Hi Anton,
From: Anton Tikhomirov [mailto:av.tikhomi...@samsung.com]
Sent: Tuesday, December 10, 2013 3:43 AM
Hi Kamil,
Same USB2.0 PHY may be used by several HCDs, for example EHCI and
OHCI.
Consider the situation, when EHCI stops using the PHY and calls
power_off
Hi Felipe,
On Fri, Dec 13, 2013 at 02:01:32PM +0900, Anton Tikhomirov wrote:
Hi Felipe,
-static int dwc3_exynos_suspend(struct device *dev)
+static int __dwc3_exynos_suspend(struct dwc3_exynos *exynos)
{
- struct dwc3_exynos *exynos = dev_get_drvdata(dev);
-
clk_disable
Hi Felipe,
On Fri, Dec 13, 2013 at 01:56:18PM -0600, Felipe Balbi wrote:
On Fri, Dec 13, 2013 at 02:01:32PM +0900, Anton Tikhomirov wrote:
Hi Felipe,
-static int dwc3_exynos_suspend(struct device *dev)
+static int __dwc3_exynos_suspend(struct dwc3_exynos *exynos
Hi Felipe,
-static int dwc3_exynos_suspend(struct device *dev)
+static int __dwc3_exynos_suspend(struct dwc3_exynos *exynos)
{
- struct dwc3_exynos *exynos = dev_get_drvdata(dev);
-
clk_disable(exynos-clk);
return 0;
}
+static int __dwc3_exynos_resume(struct
Hi Kamil,
Same USB2.0 PHY may be used by several HCDs, for example EHCI and OHCI.
Consider the situation, when EHCI stops using the PHY and calls power_off,
then OHCI becomes non-operational. In other words, PHY power_on and
power_off calls must be balanced.
Shall we handle it in your driver?
Hi Praveen,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Praveen Paneri
Sent: Wednesday, August 08, 2012 4:41 PM
To: linux-...@vger.kernel.org
Cc: devicetree-disc...@lists.ozlabs.org; linux-arm-
Cc: Kukjin Kim kgene.kim at samsung.com
Cc: Greg Kroah-Hartman gregkh at suse.de
Cc: Felipe Balbi balbi at ti.com
Adds DRD global register definitions and related platform data.
Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com
---
.../include/plat/regs-usb3-exynos-drd.h
Cc: Kukjin Kim kgene.kim at samsung.com
Cc: Greg Kroah-Hartman gregkh at suse.de
Cc: Felipe Balbi balbi at ti.com
Adds SET SEL standard request definition as defined by ch9
of the USB3.0 specification.
Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com
---
include/linux/usb/ch9.h |1
Hi Felipe,
I'm sorry for the misunderstanding from our side. We will implement the glue
layer for our Exynos SoC and reuse the dwc3 driver.
Thank you.
Felipe Balbi wrote:
Hi,
On Mon, Feb 06, 2012 at 05:13:28PM +0900, Anton Tikhomirov wrote:
Cc: Kukjin Kim kgene.kim at samsung.com
Cc
Hi,
Greg KH wrote:
On Mon, Feb 06, 2012 at 05:12:33PM +0900, Anton Tikhomirov wrote:
Cc: Kukjin Kim kgene.kim at samsung.com
Cc: Greg Kroah-Hartman gregkh at suse.de
Cc: Felipe Balbi balbi at ti.com
What is that mess? It belongs, with real email addresses, below your
signed-off
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