Re: [PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-10 Thread Chander Kashyap
On Fri, Nov 7, 2014 at 5:28 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Nov 05, 2014 at 01:15:31PM +, Chander Kashyap wrote:
 Exynos7 has core power down state where cores can be powered off 
 independently.

 ...has a core power down idle state...

 This patch adds support for this state.

 ...for this idle state.

 Entry latency for the core power down is calculated as follows:
 1. Time difference is measured between cpuidle entry and exit.
 2. WFI is skipped for measuring the time.
 3. Select the worst case time in the set of 10 cpuidle transactions,
with varying load.

 Exit latency and target residency are supplied as per HW team

 Exit latency and min residency values are supplied by the HW team.

 Target residency is a kernel naming scheme, non-existent in the idle state
 bindings.

 Please take time to write proper commit logs, thanks.

 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 This patch has following dependencies:
   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
 Changes in v2:
   - Moved the cpu-idle-state property after reg property
   - removed the status property.

 Changes in v3:
   - Added the Entry latency calculation in commit message.
 Changes in v4:
   - Corrected the commit message.
   - Corrected the entry latency value.

  arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
  1 file changed, 17 insertions(+)

 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
 b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 index 50ae936..444dde1 100644
 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
 +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 @@ -37,6 +37,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;

 enable-method should be after reg, it is not an ordering issues added
 by this patch but I still do not like that.

This is being taken care in new patch for Exynos7 support.


 Other than that, please take some time to rewrite the commit log and
 ask to fix the ordering above, you can add my:


Yes i will change as suggested.

Thanks for the review.

 Acked-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com

   reg = 0x0;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@1 {
 @@ -44,6 +45,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x1;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@2 {
 @@ -51,6 +53,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x2;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@3 {
 @@ -58,6 +61,20 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x3;
 + cpu-idle-states = CPU_SLEEP;
 + };
 +
 + idle-states {
 + entry-method = arm,psci;
 +
 + CPU_SLEEP: cpu-sleep {
 + compatible = arm,idle-state;
 + local-timer-stop;
 + arm,psci-suspend-param = 0x001;
 + entry-latency-us = 34;
 + exit-latency-us = 150;
 + min-residency-us = 2100;
 + };
   };
   };

 --
 1.7.9.5



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[PATCH v5] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-10 Thread Chander Kashyap
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.

This patch adds support for core power down idle state.

Entry latency for core power down idle state is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in a set of 10 cpuidle transactions,
   with varying load.

Exit latency and min residency values are supplied as per HW team.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
www.spinics.net/lists/arm-kernel/msg375961.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.
Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.
Changes in v5:
- Commit message modified

 arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..891eef4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x0;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x1;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x2;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x3;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 34;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.9.1

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Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Sorry for very late response. As i was on vacation so couldn’t reply.

On Tue, Oct 21, 2014 at 10:03 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Fri, Oct 17, 2014 at 10:43:59AM +0100, Chander Kashyap wrote:
 Hi Lorenzo,

 On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
 lorenzo.pieral...@arm.com wrote:
  On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
  Exynos7 has core power down state where cores can be powered off 
  independently.
  This patch adds support for this state.
 
  Please tell us more about the idle-state values you are adding, in 
  particular
  entry, exit latencies and min-residency values.

 Entry latency: This value is calculated as follows:

 On entry to arm64_enter_idle_state:
 timestamp1 = ktimeget();

 after returning from cpu_suspend()

 timestamp2 = ktimeget();

 latency = timestamp2-timestamp1;

 Cpu is not allowed to enter core powerdown by skipping wfi instruction at 
 end.
 This may not be the worst case (because the worst case depends on the state
 of the cache in the core unless the latency is power down command dominated,
 so at the cost of being pedantic, please make sure that's what you are
 measuring and document it in the commit log).


If i understood correctly you are referring to cache flush time.
The measured entry latency time is averaged time for 10
transactions with varying load.
I will document entry latency calculation in the commit message.

 Hence calculated time contains entry time + failure exit time.


 Regarding
 exit-latency and target-residency time, got these values from HW team.

 I am using these as initial values and I will be working on optimizing
 these values with further experiments.
 If you could suggest any formal method of deriving these values, i can
 try those methods as well.

 Well, you have to set the core/cluster in worst case scenario and
 compute the break-even residency against wfi (since you have two
 states); it certainly has a dependency on PSCI implementation too among
 other things.

 exit-latency should come from HW design even though there is a cache
 refill factor to be considered too and should be factored in.

Exit and target residency are provided by HW team.

I will post the V3 with changed commit message.

 Lorenzo


 
  Signed-off-by: Chander Kashyap k.chan...@samsung.com
  ---
  This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
- [PATCH v9 0/8] ARM generic idle states

  http://permalink.gmane.org/gmane.linux.power-management.general/49224
 
  Series above was merged, so dependency is stale.

 i will remove this

 
   arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
   1 file changed, 18 insertions(+)dont
 
  diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
  b/arch/arm64/boot/dts/exynos/exynos7.dtsi
  index ce221ac..8e0a034 100644
  --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
  +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
  @@ -36,6 +36,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
 
  I would add cpu-idle-states phandle after the reg property, as defined
  in the idle states bindings.

 i will move this after reg property.

 
reg = 0x0;
};
 
  @@ -43,6 +44,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
reg = 0x1;
};
 
  @@ -50,6 +52,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
reg = 0x2;
};
 
  @@ -57,8 +60,23 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
reg = 0x3;
};
  +
  + idle-states {
  + entry-method = arm,psci;
  +
  + CPU_SLEEP: cpu-sleep {
  + compatible = arm,idle-state;
  + local-timer-stop;
  + arm,psci-suspend-param = 0x001;
  + entry-latency-us = 20;
  + exit-latency-us = 150;
  + min-residency-us = 2100;
  + status = enabled;
 
  status ? This is not a documented property. If you need it please explain
  why, define its

[PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in the set of 10 cpuidle transactions,
   with varying load.

Exit latency and target residency are supplied as per HW team

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x0;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x1;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x2;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x3;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 34;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.7.9.5

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[PATCH v2] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-20 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x0;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x1;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x2;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x3;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 20;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.7.9.5

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Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-17 Thread Chander Kashyap
Hi Lorenzo,

On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
 Exynos7 has core power down state where cores can be powered off 
 independently.
 This patch adds support for this state.

 Please tell us more about the idle-state values you are adding, in particular
 entry, exit latencies and min-residency values.

Entry latency: This value is calculated as follows:

On entry to arm64_enter_idle_state:
timestamp1 = ktimeget();

after returning from cpu_suspend()

timestamp2 = ktimeget();

latency = timestamp2-timestamp1;

Cpu is not allowed to enter core powerdown by skipping wfi instruction at end.
Hence calculated time contains entry time + failure exit time.


Regarding
exit-latency and target-residency time, got these values from HW team.

I am using these as initial values and I will be working on optimizing
these values with further experiments.
If you could suggest any formal method of deriving these values, i can
try those methods as well.


 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 This patch has following dependencies:
   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
   - [PATCH v9 0/8] ARM generic idle states
   
 http://permalink.gmane.org/gmane.linux.power-management.general/49224

 Series above was merged, so dependency is stale.

i will remove this


  arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
  1 file changed, 18 insertions(+)dont

 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
 b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 index ce221ac..8e0a034 100644
 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
 +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 @@ -36,6 +36,7 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;

 I would add cpu-idle-states phandle after the reg property, as defined
 in the idle states bindings.

i will move this after reg property.


   reg = 0x0;
   };

 @@ -43,6 +44,7 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;
   reg = 0x1;
   };

 @@ -50,6 +52,7 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;
   reg = 0x2;
   };

 @@ -57,8 +60,23 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;
   reg = 0x3;
   };
 +
 + idle-states {
 + entry-method = arm,psci;
 +
 + CPU_SLEEP: cpu-sleep {
 + compatible = arm,idle-state;
 + local-timer-stop;
 + arm,psci-suspend-param = 0x001;
 + entry-latency-us = 20;
 + exit-latency-us = 150;
 + min-residency-us = 2100;
 + status = enabled;

 status ? This is not a documented property. If you need it please explain
 why, define its bindings and we can see how to accommodate it.

I will add okay for status property. As per the bindings posted by you.

regards,

 Thank you,
 Lorenzo

 + };
 + };
   };

   psci {
 --
 1.7.9.5




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[PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-15 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
- [PATCH v9 0/8] ARM generic idle states

http://permalink.gmane.org/gmane.linux.power-management.general/49224

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..8e0a034 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -36,6 +36,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x0;
};
 
@@ -43,6 +44,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x1;
};
 
@@ -50,6 +52,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x2;
};
 
@@ -57,8 +60,23 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x3;
};
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 20;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   status = enabled;
+   };
+   };
};
 
psci {
-- 
1.7.9.5

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Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

2014-08-25 Thread Chander Kashyap
Hi Kevin, Tomasz,

On Sat, Aug 23, 2014 at 5:32 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Kevin,

 Thanks for taking a look at this.

 On 23.08.2014 01:54, Kevin Hilman wrote:
 Tomasz Figa tomasz.f...@gmail.com writes:

 Kukjin,

 On 31.07.2014 20:32, Kukjin Kim wrote:
 On 07/30/14 17:07, Thomas Abraham wrote:
 The new CPU clock type allows the use of generic CPUfreq drivers. So for
 Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
 which did not have CPUfreq driver support, enable the use of generic
 CPUfreq driver.

 Suggested-by: Tomasz Figat.f...@samsung.com
 Cc: Kukjin Kimkgene@samsung.com

 Looks good to me,

 Acked-by: Kukjin Kim kgene@samsung.com

 BTW, who will handle this series? I hope see this series in 3.17.

 This series consists mostly of clock changes and it likely depends on
 patches already in my for-next, so I would be inclined toward taking it
 through samsung-clk tree.

 So has this series been picked up anywhere?  I don't see it in your
 samsung-clk tree, nor in Kukjin's for-next.

 No, it has not. In general it was already too late in the release cycle
 when the last version was posted.

 I had a plan to take it through clock tree with Kukjin's and Viresh's
 cooperation, but now as you say it...


 Also, I'm curious whether or how this is has been tested on big.LITTLE
 SoCs.

 I'm trying it on the 5800/Chromebook2 and it's not terribly stable.  I'm
 testing along with CPUidle, so there may be some untested interactions
 there as it seems a bit more stable without CPUidle enabled.

 I'd love to hear from anyone else that's testing CPUidle and CPUfreq
 together big.LITTLE 5420/5800, with or without the switcher.

I have tested this patch series on SMDK5420 with cpuidle (with and
without b.L switcher enabled).

As of now voltage scaling support is not there in generic big-little
cpufreq driver (arm_big_little.c).
Hence need to tie arm and kfc voltages to highest level for testing.

Without this change stability issues are there, but with this change
everything is stable.


 I'd definitely like to see a clarification on this issues, before this
 series hits mainline or at least its parts related to affected SoCs.
 Also I'd like to hear some confirmation from Samsung Poland RD Center
 guys (on CC), whether this code works stable on their target boards
 (Universal C210, Trats, Trats2).


 Also, the patch below[2] is needed for 5800.

 FWIW, I have a temporary branch[1] based on the v3.17-rc branch of the
 exynos-reference tree where I've added the DT patch needed for CPUidle,
 this series (and it's dependencies) which is what I'm using for testing.

 The patch looks fine to me (well, it's trivial :)), thanks.

 Best regards,
 Tomasz

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Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

2014-08-25 Thread Chander Kashyap
Hi Kevin,

On Mon, Aug 25, 2014 at 9:02 PM, Kevin Hilman khil...@linaro.org wrote:
 Hi Chander,

 Chander Kashyap k.chan...@samsung.com writes:

 [...]

 I'm trying it on the 5800/Chromebook2 and it's not terribly stable.  I'm
 testing along with CPUidle, so there may be some untested interactions
 there as it seems a bit more stable without CPUidle enabled.

 I'd love to hear from anyone else that's testing CPUidle and CPUfreq
 together big.LITTLE 5420/5800, with or without the switcher.

 I have tested this patch series on SMDK5420 with cpuidle (with and
 without b.L switcher enabled).

 As of now voltage scaling support is not there in generic big-little
 cpufreq driver (arm_big_little.c).
 Hence need to tie arm and kfc voltages to highest level for testing.

 Without this change stability issues are there, but with this change
 everything is stable.

 Can you clarify how you're setting the voltages to ensure stability?

below is the diff :  wip/exynos/integ

--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -225,7 +225,7 @@

buck2_reg: BUCK2 {
regulator-name = vdd_arm;
-   regulator-min-microvolt = 80;
+   regulator-min-microvolt = 150;
regulator-max-microvolt = 150;
regulator-always-on;
regulator-boot-on;
@@ -260,7 +260,7 @@

buck6_reg: BUCK6 {
regulator-name = vdd_kfc;
-   regulator-min-microvolt = 80;
+   regulator-min-microvolt = 150;
regulator-max-microvolt = 150;
regulator-always-on;
regulator-boot-on;


 Tomasz, I didn't mean to suggest this isn't ready for mainline.  For the
 5420/5800 it seems cpufreq support is a new feature, so this isn't a
 regression against previous (mainline) behavior.  Maybe the big.LITTLE
 cpufreq support should've been separated out from the cleanup since it's
 more of a new feature, but that's up to you.

 Kevin

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Re: [PATCH] ARM: Exynos: remove arm diagnostic and power register save/restore code

2014-08-19 Thread Chander Kashyap
On Mon, Aug 11, 2014 at 11:52 AM, Chander Kashyap k.chan...@samsung.com wrote:
 As save/restore of arm diagnostic and power registers is handled by
 generic code, so remove the same.

 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
  arch/arm/mach-exynos/pm.c |   54 
 ++---
  1 file changed, 2 insertions(+), 52 deletions(-)

 diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
 index 18646b7..af99c55 100644
 --- a/arch/arm/mach-exynos/pm.c
 +++ b/arch/arm/mach-exynos/pm.c
 @@ -134,45 +134,6 @@ void exynos_enter_aftr(void)
 exynos_sys_powerdown_conf(SYS_AFTR);
  }

 -/* For Cortex-A9 Diagnostic and Power control register */
 -static unsigned int save_arm_register[2];
 -
 -static void exynos_cpu_save_register(void)
 -{
 -   unsigned long tmp;
 -
 -   /* Save Power control register */
 -   asm (mrc p15, 0, %0, c15, c0, 0
 -: =r (tmp) : : cc);
 -
 -   save_arm_register[0] = tmp;
 -
 -   /* Save Diagnostic register */
 -   asm (mrc p15, 0, %0, c15, c0, 1
 -: =r (tmp) : : cc);
 -
 -   save_arm_register[1] = tmp;
 -}
 -
 -static void exynos_cpu_restore_register(void)
 -{
 -   unsigned long tmp;
 -
 -   /* Restore Power control register */
 -   tmp = save_arm_register[0];
 -
 -   asm volatile (mcr p15, 0, %0, c15, c0, 0
 - : : r (tmp)
 - : cc);
 -
 -   /* Restore Diagnostic register */
 -   tmp = save_arm_register[1];
 -
 -   asm volatile (mcr p15, 0, %0, c15, c0, 1
 - : : r (tmp)
 - : cc);
 -}
 -
  static int exynos_cpu_suspend(unsigned long arg)
  {
  #ifdef CONFIG_CACHE_L2X0
 @@ -238,9 +199,6 @@ static int exynos_pm_suspend(void)
 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);

 -   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 -   exynos_cpu_save_register();
 -
 return 0;
  }

 @@ -272,9 +230,6 @@ static void exynos_pm_resume(void)
 if (exynos_pm_central_resume())
 goto early_wakeup;

 -   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 -   exynos_cpu_restore_register();
 -
 /* For release retention */

 pmu_raw_writel((1  28), S5P_PAD_RET_MAUDIO_OPTION);
 @@ -376,19 +331,14 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
 *self,

 switch (cmd) {
 case CPU_PM_ENTER:
 -   if (cpu == 0) {
 +   if (cpu == 0)
 exynos_pm_central_suspend();
 -   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 -   exynos_cpu_save_register();
 -   }
 break;

 case CPU_PM_EXIT:
 if (cpu == 0) {
 -   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 +   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 scu_enable(S5P_VA_SCU);
 -   exynos_cpu_restore_register();
 -   }
 exynos_pm_central_resume();
 }
 break;

Hi Kukjin,
Can you take this patch?
 --
 1.7.9.5

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[PATCH] ARM: Exynos: remove arm diagnostic and power register save/restore code

2014-08-11 Thread Chander Kashyap
As save/restore of arm diagnostic and power registers is handled by
generic code, so remove the same.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/pm.c |   54 ++---
 1 file changed, 2 insertions(+), 52 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 18646b7..af99c55 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -134,45 +134,6 @@ void exynos_enter_aftr(void)
exynos_sys_powerdown_conf(SYS_AFTR);
 }
 
-/* For Cortex-A9 Diagnostic and Power control register */
-static unsigned int save_arm_register[2];
-
-static void exynos_cpu_save_register(void)
-{
-   unsigned long tmp;
-
-   /* Save Power control register */
-   asm (mrc p15, 0, %0, c15, c0, 0
-: =r (tmp) : : cc);
-
-   save_arm_register[0] = tmp;
-
-   /* Save Diagnostic register */
-   asm (mrc p15, 0, %0, c15, c0, 1
-: =r (tmp) : : cc);
-
-   save_arm_register[1] = tmp;
-}
-
-static void exynos_cpu_restore_register(void)
-{
-   unsigned long tmp;
-
-   /* Restore Power control register */
-   tmp = save_arm_register[0];
-
-   asm volatile (mcr p15, 0, %0, c15, c0, 0
- : : r (tmp)
- : cc);
-
-   /* Restore Diagnostic register */
-   tmp = save_arm_register[1];
-
-   asm volatile (mcr p15, 0, %0, c15, c0, 1
- : : r (tmp)
- : cc);
-}
-
 static int exynos_cpu_suspend(unsigned long arg)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -238,9 +199,6 @@ static int exynos_pm_suspend(void)
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 
-   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-   exynos_cpu_save_register();
-
return 0;
 }
 
@@ -272,9 +230,6 @@ static void exynos_pm_resume(void)
if (exynos_pm_central_resume())
goto early_wakeup;
 
-   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-   exynos_cpu_restore_register();
-
/* For release retention */
 
pmu_raw_writel((1  28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -376,19 +331,14 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
 
switch (cmd) {
case CPU_PM_ENTER:
-   if (cpu == 0) {
+   if (cpu == 0)
exynos_pm_central_suspend();
-   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-   exynos_cpu_save_register();
-   }
break;
 
case CPU_PM_EXIT:
if (cpu == 0) {
-   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
scu_enable(S5P_VA_SCU);
-   exynos_cpu_restore_register();
-   }
exynos_pm_central_resume();
}
break;
-- 
1.7.9.5

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Re: [PATCH v2 5/6] ARM: EXYNOS: Fix suspend/resume sequences

2014-07-15 Thread Chander Kashyap
On Tue, Jul 15, 2014 at 5:45 PM, Tomasz Figa t.f...@samsung.com wrote:
 On 15.07.2014 13:19, Bartlomiej Zolnierkiewicz wrote:

 Hi,

 On Monday, July 14, 2014 11:54:48 AM Tomasz Figa wrote:
 Hi Kukjin,

 On 25.06.2014 13:52, Tomasz Figa wrote:
 Due to recent consolidation of Exynos suspend and cpuidle code, some
 parts of suspend and resume sequences are executed two times, once from
 exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
 breaks suspend, at least on Exynos4-based boards.

 This patch fixes the issue by removing exynos_pm_syscore_ops completely
 and making the code rely only on CPU PM notifier.

 Tested on Exynos4210-based Trats board.

 Signed-off-by: Tomasz Figa t.f...@samsung.com
 ---
  arch/arm/mach-exynos/pm.c | 23 ---
  1 file changed, 4 insertions(+), 19 deletions(-)

 Changes since v1:
  - rebased onto Kukjin's fixes branch.

 diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
 index 202ca73..f23cc77 100644
 --- a/arch/arm/mach-exynos/pm.c
 +++ b/arch/arm/mach-exynos/pm.c
 @@ -364,11 +364,6 @@ early_wakeup:
 return;
  }

 -static struct syscore_ops exynos_pm_syscore_ops = {
 -   .suspend= exynos_pm_suspend,
 -   .resume = exynos_pm_resume,
 -};
 -
  /*
   * Suspend Ops
   */
 @@ -438,22 +433,13 @@ static int exynos_cpu_pm_notifier(struct 
 notifier_block *self,

 switch (cmd) {
 case CPU_PM_ENTER:
 -   if (cpu == 0) {
 -   exynos_pm_central_suspend();
 -   if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 -   exynos_cpu_save_register();
 -   }
 +   if (cpu == 0)
 +   exynos_pm_suspend();
 break;

 case CPU_PM_EXIT:
 -   if (cpu == 0) {
 -   if (read_cpuid_part_number() ==
 -   ARM_CPU_PART_CORTEX_A9) {
 -   scu_enable(S5P_VA_SCU);
 -   exynos_cpu_restore_register();
 -   }
 -   exynos_pm_central_resume();
 -   }
 +   if (cpu == 0)
 +   exynos_pm_resume();
 break;
 }

 @@ -478,6 +464,5 @@ void __init exynos_pm_init(void)
 tmp |= ((0xFF  8) | (0x1F  1));
 __raw_writel(tmp, S5P_WAKEUP_MASK);

 -   register_syscore_ops(exynos_pm_syscore_ops);
 suspend_set_ops(exynos_suspend_ops);
  }


 Please consider this patch for next fixes pull request. Without it
 suspend/resume is broken for Exynos4 and probably other SoCs. This patch
 just restores the sequence from before the patch moving things to PM
 notifier, so I don't think it should need any special treatment.

 Your patch fixes the regression and is a step in the good direction but it
 seems that it needs a bit more work:

 Your patch adds to cpuidle AFTR code path restoring of exynos_core_save and
 exynos5_sys_save registers without saving them first (restoring is done
 through exynos_pm_resume() which is used by both suspend and cpuidle while
 saving is done through exynos_pm_prepare() which is used only by suspend).

 That's right, unfortunately. Interestingly enough AFTR worked fine on
 Exynos4210 with this patch, but still this needs to be fixed.

 Now, in fact, I recall that Chander had some objections to this patch as
 well and we decided that he will send another patch to replace mine [1],
 but I haven't heard from him since that.

Patch for the same has been already posted.
Below is the link for the same
http://www.spinics.net/lists/arm-kernel/msg343402.html

This patch has conflict with Russel's patch, so i will rebase on his
tree and resend

This patch can be ignored in that case.


 Chander, do you have any progress with this? Keep in mind that we need
 this as an rc fix and we already have rc5, so not much time left. If you
 don't have time to work on this I can take care of this, proceeding as
 we discussed in [1].

 [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29085/focus=33975

 Best regards,
 Tomasz
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Re: [PATCH 2/2] cpuidle: Exynos: fix cpuidle for all states

2014-07-15 Thread Chander Kashyap
Hi Tomasz,

On Tue, Jul 15, 2014 at 11:11 PM, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander,

 Please see my comments inline.

 On 01.07.2014 16:32, Chander Kashyap wrote:
 Pre/post platform specific cpuidle operations are handled by pm_notifier.
 But these operations are not same for all cpuidle states. Handle this by
 moving cpuidle specific code from pm_notifier to cpuidle specific function.

 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
  arch/arm/mach-exynos/common.h|2 +-
  arch/arm/mach-exynos/pm.c|   45 
 ++
  drivers/cpuidle/cpuidle-exynos.c |7 --
  3 files changed, 17 insertions(+), 37 deletions(-)

 diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
 index 1ee9176..7769f58 100644
 --- a/arch/arm/mach-exynos/common.h
 +++ b/arch/arm/mach-exynos/common.h
 @@ -166,7 +166,7 @@ extern int  exynos_cpu_power_state(int cpu);
  extern void exynos_cluster_power_down(int cluster);
  extern void exynos_cluster_power_up(int cluster);
  extern int  exynos_cluster_power_state(int cluster);
 -extern void exynos_enter_aftr(void);
 +extern void exynos_enter_aftr(int entering_idle);

  extern void s5p_init_cpu(void __iomem *cpuid_addr);
  extern unsigned int samsung_rev(void);
 diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
 index a092cc3..328644f 100644
 --- a/arch/arm/mach-exynos/pm.c
 +++ b/arch/arm/mach-exynos/pm.c
 @@ -188,14 +188,6 @@ static void exynos_cpu_set_boot_vector(long flags)
   __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
  }

 -void exynos_enter_aftr(void)
 -{
 - exynos_set_wakeupmask(0xff3e);
 - exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 - /* Set value of power down register for aftr mode */
 - exynos_sys_powerdown_conf(SYS_AFTR);
 -}
 -
  static int exynos_cpu_suspend(unsigned long arg)
  {
  #ifdef CONFIG_CACHE_L2X0
 @@ -386,40 +378,25 @@ static const struct platform_suspend_ops 
 exynos_suspend_ops = {
   .valid  = suspend_valid_only_mem,
  };

 -static int exynos_cpu_pm_notifier(struct notifier_block *self,
 -   unsigned long cmd, void *v)
 +void exynos_enter_aftr(int entering_idle)
  {
 - int cpu = smp_processor_id();
 -
 - switch (cmd) {
 - case CPU_PM_ENTER:
 - if (cpu == 0)
 - exynos_pm_central_suspend();
 - break;
 -
 - case CPU_PM_EXIT:
 - if (cpu == 0) {
 - if (read_cpuid_part_number() ==
 - ARM_CPU_PART_CORTEX_A9)
 - scu_enable(S5P_VA_SCU);
 - exynos_pm_central_resume();
 - }
 - break;
 + if (entering_idle) {
 + exynos_set_wakeupmask(0xff3e);
 + exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 + /* Set value of power down register for aftr mode */
 + exynos_sys_powerdown_conf(SYS_AFTR);
 + exynos_pm_central_suspend();
 + } else {
 + if (scu_a9_has_base())
 + scu_enable(S5P_VA_SCU);
 + exynos_pm_central_resume();

 Hmm. This is not very readable. Basically you have two functions that do
 completely different things packed into one function. I would suggest
 moving the calls to cpu_pm_enter/exit() and everything in between to
 this function then you wouldn't need anything like this and the whole
 low level logic would be in one place.

   }
 -
 - return NOTIFY_OK;
  }

 -static struct notifier_block exynos_cpu_pm_notifier_block = {
 - .notifier_call = exynos_cpu_pm_notifier,
 -};
 -
  void __init exynos_pm_init(void)
  {
   u32 tmp;

 - cpu_pm_register_notifier(exynos_cpu_pm_notifier_block);
 -
   /* Platform-specific GIC callback */
   gic_arch_extn.irq_set_wake = exynos_irq_set_wake;

 diff --git a/drivers/cpuidle/cpuidle-exynos.c 
 b/drivers/cpuidle/cpuidle-exynos.c
 index 7c01512..1196ca7 100644
 --- a/drivers/cpuidle/cpuidle-exynos.c
 +++ b/drivers/cpuidle/cpuidle-exynos.c
 @@ -18,11 +18,10 @@
  #include asm/suspend.h
  #include asm/cpuidle.h

 -static void (*exynos_enter_aftr)(void);
 +static void (*exynos_enter_aftr)(int);

  static int idle_finisher(unsigned long flags)
  {
 - exynos_enter_aftr();
   cpu_do_idle();

   return 1;
 @@ -32,8 +31,12 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
 *dev,
   struct cpuidle_driver *drv,
   int index)
  {
 + int entering_idle = true;
   cpu_pm_enter();
 + exynos_enter_aftr(entering_idle);
   cpu_suspend(0, idle_finisher);
 + entering_idle = false;
 + exynos_enter_aftr(entering_idle);

 This doesn't look good. Couldn't you just have called it with constant
 arguments? E.g.

 exynos_enter_aftr(true);
 [...]
 exynos_enter_aftr(false);

 Well, sorry for late comments, I have missed this series

Re: [PATCH 0/2] cpuidle fixes and cleanup

2014-07-09 Thread Chander Kashyap
On Tue, Jul 8, 2014 at 7:47 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
 On Tue, Jul 08, 2014 at 03:56:48PM +0200, Tomasz Figa wrote:
 On 02.07.2014 05:11, Chander Kashyap wrote:
  On Tue, Jul 1, 2014 at 8:22 PM, Russell King - ARM Linux
  li...@arm.linux.org.uk wrote:
  On Tue, Jul 01, 2014 at 08:02:36PM +0530, Chander Kashyap wrote:
  This patch series fixes the cpuidle for different states. Also removes 
  arm
  diagnostic and power register save/restore code as it is made generic.
 
  Based on:
  ARM: save/restore diagnostic register on Cortex-A9 suspend/resume
   http://www.spinics.net/lists/arm-kernel/msg340506.html

 [Ccing people who participated in discussion in that thread]

 
  As there is an outstanding issue with this patch, we can't proceed with
  this set of changes until we know what's going on there.
 
  Sure, I will wait for the conclusion.

 So I believe the conclusion was that this can't be handled in generic
 way, because on systems running in non-secure mode writing to those
 registers faults.

 That is, unfortunately, correct.

 There is a way around this, but people aren't going to like it.  That
 is - we move it to the suspend and resume paths anyway.

 In the resume path, we read the register, compare it with the value
 which we would update it to, and if it's identical, we avoid the write.

 This gets secure-mode platforms working.

 For non-secure mode platforms, we have to require them to insert some
 assembly code into the early resume path which calls their secure
 monitor to restore these registers before continuing on to cpu_resume,
 thereby ensuring that the CPU specific code sees that the value in the
 register is identical with the saved value, and omitting the write.

 This isn't really a new principle - we already have this requirement
 for non-secure mode platforms when they're booting a kernel with
 various errata enabled.

 I can't see any other alternative which satisfies everyone (by
 everyone, I'm including the requirements from the hardware folk who
 expect these registers to be static once the MMU is enabled.)

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 improving, and getting towards what was expected from it.

In that case i will re-post this after Russell post changes which
conflict with that patch.

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[PATCH 0/2] cpuidle fixes and cleanup

2014-07-01 Thread Chander Kashyap
This patch series fixes the cpuidle for different states. Also removes arm
diagnostic and power register save/restore code as it is made generic.

Based on:
ARM: save/restore diagnostic register on Cortex-A9 suspend/resume
 http://www.spinics.net/lists/arm-kernel/msg340506.html

ARM: save/restore power control register on Cortex-A9 suspend/resume
 http://www.spinics.net/lists/arm-kernel/msg343320.html

Chander Kashyap (2):
  ARM: Exynos: remove arm diagnostic and power register save/restore
code
  cpuidle: Exynos: fix cpuidle for all states

 arch/arm/mach-exynos/common.h|2 +-
 arch/arm/mach-exynos/pm.c|   95 +-
 drivers/cpuidle/cpuidle-exynos.c |7 ++-
 3 files changed, 17 insertions(+), 87 deletions(-)

-- 
1.7.9.5

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[PATCH 2/2] cpuidle: Exynos: fix cpuidle for all states

2014-07-01 Thread Chander Kashyap
Pre/post platform specific cpuidle operations are handled by pm_notifier.
But these operations are not same for all cpuidle states. Handle this by
moving cpuidle specific code from pm_notifier to cpuidle specific function.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/common.h|2 +-
 arch/arm/mach-exynos/pm.c|   45 ++
 drivers/cpuidle/cpuidle-exynos.c |7 --
 3 files changed, 17 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ee9176..7769f58 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -166,7 +166,7 @@ extern int  exynos_cpu_power_state(int cpu);
 extern void exynos_cluster_power_down(int cluster);
 extern void exynos_cluster_power_up(int cluster);
 extern int  exynos_cluster_power_state(int cluster);
-extern void exynos_enter_aftr(void);
+extern void exynos_enter_aftr(int entering_idle);
 
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
 extern unsigned int samsung_rev(void);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a092cc3..328644f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -188,14 +188,6 @@ static void exynos_cpu_set_boot_vector(long flags)
__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
 }
 
-void exynos_enter_aftr(void)
-{
-   exynos_set_wakeupmask(0xff3e);
-   exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
-   /* Set value of power down register for aftr mode */
-   exynos_sys_powerdown_conf(SYS_AFTR);
-}
-
 static int exynos_cpu_suspend(unsigned long arg)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -386,40 +378,25 @@ static const struct platform_suspend_ops 
exynos_suspend_ops = {
.valid  = suspend_valid_only_mem,
 };
 
-static int exynos_cpu_pm_notifier(struct notifier_block *self,
- unsigned long cmd, void *v)
+void exynos_enter_aftr(int entering_idle)
 {
-   int cpu = smp_processor_id();
-
-   switch (cmd) {
-   case CPU_PM_ENTER:
-   if (cpu == 0)
-   exynos_pm_central_suspend();
-   break;
-
-   case CPU_PM_EXIT:
-   if (cpu == 0) {
-   if (read_cpuid_part_number() ==
-   ARM_CPU_PART_CORTEX_A9)
-   scu_enable(S5P_VA_SCU);
-   exynos_pm_central_resume();
-   }
-   break;
+   if (entering_idle) {
+   exynos_set_wakeupmask(0xff3e);
+   exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+   /* Set value of power down register for aftr mode */
+   exynos_sys_powerdown_conf(SYS_AFTR);
+   exynos_pm_central_suspend();
+   } else {
+   if (scu_a9_has_base())
+   scu_enable(S5P_VA_SCU);
+   exynos_pm_central_resume();
}
-
-   return NOTIFY_OK;
 }
 
-static struct notifier_block exynos_cpu_pm_notifier_block = {
-   .notifier_call = exynos_cpu_pm_notifier,
-};
-
 void __init exynos_pm_init(void)
 {
u32 tmp;
 
-   cpu_pm_register_notifier(exynos_cpu_pm_notifier_block);
-
/* Platform-specific GIC callback */
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 
diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c
index 7c01512..1196ca7 100644
--- a/drivers/cpuidle/cpuidle-exynos.c
+++ b/drivers/cpuidle/cpuidle-exynos.c
@@ -18,11 +18,10 @@
 #include asm/suspend.h
 #include asm/cpuidle.h
 
-static void (*exynos_enter_aftr)(void);
+static void (*exynos_enter_aftr)(int);
 
 static int idle_finisher(unsigned long flags)
 {
-   exynos_enter_aftr();
cpu_do_idle();
 
return 1;
@@ -32,8 +31,12 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
struct cpuidle_driver *drv,
int index)
 {
+   int entering_idle = true;
cpu_pm_enter();
+   exynos_enter_aftr(entering_idle);
cpu_suspend(0, idle_finisher);
+   entering_idle = false;
+   exynos_enter_aftr(entering_idle);
cpu_pm_exit();
 
return index;
-- 
1.7.9.5

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Re: [PATCH 0/2] cpuidle fixes and cleanup

2014-07-01 Thread Chander Kashyap
On Tue, Jul 1, 2014 at 8:22 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
 On Tue, Jul 01, 2014 at 08:02:36PM +0530, Chander Kashyap wrote:
 This patch series fixes the cpuidle for different states. Also removes arm
 diagnostic and power register save/restore code as it is made generic.

 Based on:
 ARM: save/restore diagnostic register on Cortex-A9 suspend/resume
  http://www.spinics.net/lists/arm-kernel/msg340506.html

 As there is an outstanding issue with this patch, we can't proceed with
 this set of changes until we know what's going on there.

Sure, I will wait for the conclusion.


 Also, bear in mind that I have changes which conflict with this in my
 tree (which I've just updated.)

I will resend after your changes are posted.

Thanks

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Re: [PATCH V5 16/20] ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm notifier

2014-06-26 Thread Chander Kashyap
On Fri, Apr 11, 2014 at 4:10 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
 The code to initiate and exit the powerdown sequence is the same in pm.c and
 cpuidle.c.

 Let's split the common part in the pm.c and reuse it from the cpu_pm notifier.

 That is one more step forward to make the cpuidle driver arch indenpendant.

 Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
 Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
 Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
 ---
  arch/arm/mach-exynos/cpuidle.c |   22 --
  arch/arm/mach-exynos/pm.c  |   24 
  2 files changed, 20 insertions(+), 26 deletions(-)

 diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
 index e6d813d..02609ac 100644
 --- a/arch/arm/mach-exynos/cpuidle.c
 +++ b/arch/arm/mach-exynos/cpuidle.c
 @@ -28,7 +28,6 @@
  #include mach/map.h

  #include common.h
 -#include regs-pmu.h

  static int idle_finisher(unsigned long flags)
  {
 @@ -42,31 +41,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
 *dev,
 struct cpuidle_driver *drv,
 int index)
  {
 -   unsigned long tmp;
 -
 -   /* Setting Central Sequence Register for power down mode */
 -   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 -   tmp = ~S5P_CENTRAL_LOWPWR_CFG;
 -   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 -
 cpu_pm_enter();
 cpu_suspend(0, idle_finisher);
 cpu_pm_exit();

 -   /*
 -* If PMU failed while entering sleep mode, WFI will be
 -* ignored by PMU and then exiting cpu_do_idle().
 -* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 -* in this situation.
 -*/
 -   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 -   if (!(tmp  S5P_CENTRAL_LOWPWR_CFG)) {
 -   tmp |= S5P_CENTRAL_LOWPWR_CFG;
 -   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 -   /* Clear wakeup state register */
 -   __raw_writel(0x0, S5P_WAKEUP_STAT);
 -   }
 -
 return index;
  }

 diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
 index 50b6b4d..6d9ef69 100644
 --- a/arch/arm/mach-exynos/pm.c
 +++ b/arch/arm/mach-exynos/pm.c
 @@ -213,15 +213,21 @@ static void exynos_pm_prepare(void)
 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
  }

 -static int exynos_pm_suspend(void)
 +static void exynos_pm_central_suspend(void)
  {
 unsigned long tmp;

 /* Setting Central Sequence Register for power down mode */
 -
 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 tmp = ~S5P_CENTRAL_LOWPWR_CFG;
 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 +}
 +
 +static int exynos_pm_suspend(void)
 +{
 +   unsigned long tmp;
 +
 +   exynos_pm_central_suspend();

 /* Setting SEQ_OPTION register */

 @@ -234,7 +240,7 @@ static int exynos_pm_suspend(void)
 return 0;
  }

 -static void exynos_pm_resume(void)
 +static int exynos_pm_central_resume(void)
  {
 unsigned long tmp;

 @@ -251,9 +257,17 @@ static void exynos_pm_resume(void)
 /* clear the wakeup state register */
 __raw_writel(0x0, S5P_WAKEUP_STAT);
 /* No need to perform below restore code */
 -   goto early_wakeup;
 +   return -1;
 }

 +   return 0;
 +}
 +
 +static void exynos_pm_resume(void)
 +{
 +   if (exynos_pm_central_resume())
 +   goto early_wakeup;
 +
 if (!soc_is_exynos5250())
 exynos_cpu_restore_register();

 @@ -359,6 +373,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
 *self,
 switch (cmd) {
 case CPU_PM_ENTER:
 if (cpu == 0) {
 +   exynos_pm_central_suspend();
 exynos_cpu_save_register();
 }
 break;
 @@ -368,6 +383,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
 *self,
 if (!soc_is_exynos5250())
 scu_enable(S5P_VA_SCU);
 exynos_cpu_restore_register();
 +   exynos_pm_central_resume();

This notifier is called for system wide suspend and cpuidle.

In case of Exynos cpuidle only AFTR and LPA state need to program
central_sequencer and store/restore the registers.

But in 5420 (core-power-down), this is not required, and causing the regression.

Hence need to remove this notifier, or need to find a way to
differentiate the cpuidle state.


 }
 break;
 }
 --
 1.7.9.5

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Re: [PATCH V5 16/20] ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm notifier

2014-06-26 Thread Chander Kashyap
On Thu, Jun 26, 2014 at 3:18 PM, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander,

 On 26.06.2014 11:07, Chander Kashyap wrote:
 On Fri, Apr 11, 2014 at 4:10 PM, Daniel Lezcano
 daniel.lezc...@linaro.org wrote:

 [snip]

 @@ -359,6 +373,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
 *self,
 switch (cmd) {
 case CPU_PM_ENTER:
 if (cpu == 0) {
 +   exynos_pm_central_suspend();
 exynos_cpu_save_register();
 }
 break;
 @@ -368,6 +383,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
 *self,
 if (!soc_is_exynos5250())
 scu_enable(S5P_VA_SCU);
 exynos_cpu_restore_register();
 +   exynos_pm_central_resume();

 This notifier is called for system wide suspend and cpuidle.

 In case of Exynos cpuidle only AFTR and LPA state need to program
 central_sequencer and store/restore the registers.

 But in 5420 (core-power-down), this is not required, and causing the 
 regression.

 Hence need to remove this notifier, or need to find a way to
 differentiate the cpuidle state.

 This patch is already present in v3.16. Moreover, Exynos5420 cpuidle has
 not been merged yet. This means that this issue is not a regression and
 I believe any further work on this should be carried out as further
 patches on top of this change.

 Anyway, this change has introduced a regression, though, but in another
 area - it broke suspend, at least on Exynos4-based devices, because now
 certain steps are performed twice. I've sent a patch for 3.16-rc3 to fix
 this by dropping custom suspend-specific syscore ops, effectively moving
 most of the handling to CPU PM notifier, which also matches requirements
 of AFTR and lower power states. See [1].

 [1]
 http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32935.html

 However, in this case, moving back to suspend-specific syscore_ops and
 simply duplicating some code for lower cpuidle states might be a better
 option. Care to send a patch (fix for 3.16, replacing mine) or I should
 do it?

Yes need to move the common code to lower cpuildle implementation and
removing the notifier all together.
I will do it and send the patch.



 Best regards,
 Tomasz
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-16 Thread Chander Kashyap
Hi Doug,

On 13 June 2014 20:40, Doug Anderson diand...@chromium.org wrote:
 Chander,

 On Fri, Jun 13, 2014 at 4:54 AM, Chander Kashyap k.chan...@samsung.com 
 wrote:
 This patch is effectively changing the mcpm_entry_point address from
 nsbase + 0x1c to nsbase + 0x8

 Hence while integrating with mainline u-boot we need to take care for
 new mcpm_entry_point address.

 With Chromebook it works straightforward.

 Can you explain more and point to the code that is using the nsbase +
 0x1c?  Specifically the only code I see that uses the nsbase + 0x1c is
 the code that is located at nsbase, which is the code we're
 overwriting here.  I'd imagine you're using U-Boot code that looks
 something like the bits that start at code_base here:

 https://chromium.googlesource.com/chromiumos/third_party/u-boot/+/ce358daf5069f1dc145b0f9d403cfbb028271807/arch/arm/cpu/armv7/exynos/lowlevel.S

 With my kernel change you can completely eliminate U-Boot's
 installation of this code (or keep it, it makes no difference).

Yes i agree with your point.
What i am saying is when there is full support for Exynos5420 in
mainline u-boot we need to take care for the mcpm_entry_point address.


 -Doug



-- 
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[Patch v7 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Changes in v6: None
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index 0498d0b..fc47e68 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -258,10 +258,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register.
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.wait_for_powerdown = exynos_wait_for_powerdown,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[Patch v7 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e8..2f6b33e 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -9,7 +9,7 @@ config ARM_ARMADA_370_XP_CPUIDLE
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[Patch v7 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v6:
1. Move cpuidle registration check to exynos.c from cpuidle.c and
   use samsung,exynos5420 compatible string to avvoid registration
 arch/arm/mach-exynos/exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 90aab4d..f4c08d6 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -271,7 +271,9 @@ static void __init exynos_dt_machine_init(void)
}
}
 
-   exynos_cpuidle_init();
+   if (!of_machine_is_compatible(samsung,exynos5420))
+   exynos_cpuidle_init();
+
exynos_cpufreq_init();
 
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5

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[Patch v7 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v5: None
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[Patch v7 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[Patch v7 2/6] arm: exynos: add generic function to calculate cpu number

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d13b08..aff23bd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -323,4 +323,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[Patch v7 0/6] add cpuidle support for Exynos5420

2014-06-16 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.
Rebased on 3.16-rc1

Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/exynos.c|4 +++-
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-13 Thread Chander Kashyap
On Wed, Jun 11, 2014 at 8:58 PM, Kukjin Kim kgene@samsung.com wrote:
 On 06/12/14 00:19, Doug Anderson wrote:

 Chander,

 On Tue, Jun 10, 2014 at 9:52 PM, Chander Kashyapk.chan...@samsung.com
 wrote:

 Hi Doug,

 On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitrenicolas.pi...@linaro.org
 wrote:

 On Tue, 10 Jun 2014, Doug Anderson wrote:

 My S-state knowledge is not strong, but I believe that Lorenzo's
 questions matter if we're using S2 for CPUidle (where we actually turn
 off power and hot unplug CPUs) but not when we're using S1 for CPUidle
 (where we just enter WFI/WFE).


 No Its not plain WFI.

 All cores in Exynos5420 can be powered off independently.
 This functionality has been tested.

 Below is the link for the posted patches.

 https://lkml.org/lkml/2014/6/10/194

 And as Nicolas wrote, these patches need MCPM for that.


 Most excellent!  I should have been more clear that I only knew about
 how CPUidle worked in our local production kernel.  There I'm pretty
 sure CPUidle is just WFI/WFE.  If you've got patches to do better then
 that's great!

 ...can you confirm that my patch doesn't interfere with your improved
 CPUidle?  It's been Acked by Nicolas (thanks!) so I'd imagine it will
 land shortly.  Kukjin: I assume you'll be taking this?


This patch is effectively changing the mcpm_entry_point address from
nsbase + 0x1c to nsbase + 0x8

Hence while integrating with mainline u-boot we need to take care for
new mcpm_entry_point address.

With Chromebook it works straightforward.


 Sure, I will ;-)

 Thanks,
 Kukjin

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-11 Thread Chander Kashyap
On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
 Hi Doug,

 On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org 
 wrote:
  On Tue, 10 Jun 2014, Doug Anderson wrote:
 
  My S-state knowledge is not strong, but I believe that Lorenzo's
  questions matter if we're using S2 for CPUidle (where we actually turn
  off power and hot unplug CPUs) but not when we're using S1 for CPUidle
  (where we just enter WFI/WFE).
 

 No Its not plain WFI.

 All cores in Exynos5420 can be powered off independently.
 This functionality has been tested.

 Below is the link for the posted patches.

 https://lkml.org/lkml/2014/6/10/194

 And as Nicolas wrote, these patches need MCPM for that.

 Chander, I cast a look into the code and I have a question
 (you also told me on CPUidle review that only core off
 is supported in CPUidle).

 When you say all cores can be powered off independently, do
 you also mean that clusters can be powered off (in CPUidle) ?

 I am pointing this out since in the MCPM backend I noticed:

 /* TODO: Turn off the cluster here to save power. */

 I do not see any cluster power down request in the down path.

 If I am wrong, ignore my message, I am just writing to help.

 If you can only power down cores, but not the clusters on idle,
 please keep in mind that you are currently cleaning and invalidating
 the L2 when last man is running and this must not be taken
 lightly since, if L2 stays on, that's a massive energy waste
 for nothing.

 So, if clusters stay up, you _have_ to tweak the MCPM backend slightly
 to avoid cleaning L2, that's pivotal.

Hi Lorenzo,
Cluster shutdown is in progress. Abhilash will add support for that.

https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31104.html



 Lorenzo


  I believe that in ChromeOS we use S1 CPUidle and that it works fine.
  We've never implemented S2 that I'm aware of.
 
  You'll have to rely on MCPM for that.  That's probably why it hasn't
  been implemented before.
 
 
  Nicolas
 
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-11 Thread Chander Kashyap
On 11 June 2014 18:45, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Wed, Jun 11, 2014 at 01:14:21PM +0100, Chander Kashyap wrote:
 On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
 lorenzo.pieral...@arm.com wrote:
  On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
  Hi Doug,
 
  On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org 
  wrote:
   On Tue, 10 Jun 2014, Doug Anderson wrote:
  
   My S-state knowledge is not strong, but I believe that Lorenzo's
   questions matter if we're using S2 for CPUidle (where we actually turn
   off power and hot unplug CPUs) but not when we're using S1 for CPUidle
   (where we just enter WFI/WFE).
  
 
  No Its not plain WFI.
 
  All cores in Exynos5420 can be powered off independently.
  This functionality has been tested.
 
  Below is the link for the posted patches.
 
  https://lkml.org/lkml/2014/6/10/194
 
  And as Nicolas wrote, these patches need MCPM for that.
 
  Chander, I cast a look into the code and I have a question
  (you also told me on CPUidle review that only core off
  is supported in CPUidle).
 
  When you say all cores can be powered off independently, do
  you also mean that clusters can be powered off (in CPUidle) ?
 
  I am pointing this out since in the MCPM backend I noticed:
 
  /* TODO: Turn off the cluster here to save power. */
 
  I do not see any cluster power down request in the down path.
 
  If I am wrong, ignore my message, I am just writing to help.
 
  If you can only power down cores, but not the clusters on idle,
  please keep in mind that you are currently cleaning and invalidating
  the L2 when last man is running and this must not be taken
  lightly since, if L2 stays on, that's a massive energy waste
  for nothing.
 
  So, if clusters stay up, you _have_ to tweak the MCPM backend slightly
  to avoid cleaning L2, that's pivotal.

 Hi Lorenzo,
 Cluster shutdown is in progress. Abhilash will add support for that.

 https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31104.html


Hi Lorenzo,

 Hi Chander,

 thanks. So, as a heads-up:

 1) if you merge CPUidle support now, as it is it is at least suboptimal, may
even burn more energy than it saves. Latencies in the bL idle driver
are likely to be wrong, since they are for cluster shutdown and for
TC2, not core power gating that should require shorter target_residencies.
On top of that, L2 is cleaned and invalidated for nothing.

Yes true.

 2) when cluster support is merged, you might want to extend the CPUidle
driver to add an additional state (ie C1 core gating, C2 cluster
gating) and to do that you should extend the driver and the MCPM
back-end accordingly, I discussed that with Nico already some time ago
and actually it should be fairly easy to do but we have got to talk
about that.


Yes thats the final goal to add two states (C1 core gating, C2 cluster gating).
But that will be done in combination with yours patches(to pass
cpuidle data thru DT).

So finally the mcpm backend will take care for c1 and c2 cpuidle state
implementation.

 Thank you,
 Lorenzo



 
  Lorenzo
 
 
   I believe that in ChromeOS we use S1 CPUidle and that it works fine.
   We've never implemented S2 that I'm aware of.
  
   You'll have to rely on MCPM for that.  That's probably why it hasn't
   been implemented before.
  
  
   Nicolas
  
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-10 Thread Chander Kashyap
On 10 June 2014 04:08, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:

 [...]

 Cold boot and resume from suspend are detected via various special
 flags in various special locations.  Resume from suspend looks at
 INFORM1 (0x10048004) for flags.  This register is 0 during a cold boot
 and has special values set by the kernel at resume time.

 It also looks as if some code looks at 0x10040900 (PMU_SPARE0) to help
 tell initial cold boot and secondary CPU bringup.

 Ok, thanks a lot. It looks like firmware paths should be ready to
 detect cold vs warm boot, and hopefully do not rely on a specific
 MPIDR to come up first out of power states.

  I am asking to check if on this platform CPUidle (where the notion of
  primary CPU disappears) has a chance to run properly.

 I believe it should be possible, but we don't have CPUidle implemented
 in our current system.  Abhilash may be able to comment more.


Cpuidle is implemented for exynos5420, and is tested on chromebook.


 I am interested in more insights, that's very helpful thanks.

  Probably CPUidle won't attain idle states where IRAM content is lost, but I
  am still worried about the primary vs secondaries firmware boot behaviour.

 I don't think iRAM can be turned off for CPUidle.

Yes thats true.

 It might be added a system state but I doubt that too and if you are
 relying on registers for jump addresses that's not even a problem in
 the first place.

  What happens on reboot from suspend to RAM (or to put it differently,
  what does secure firmware do on reboot from suspend to RAM - in
  particular how is the jump address to bootloader/kernel set ?)

 Should be described above now.

 Thank you very much.

 Lorenzo

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-10 Thread Chander Kashyap
Hi Doug,

On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org wrote:
 On Tue, 10 Jun 2014, Doug Anderson wrote:

 My S-state knowledge is not strong, but I believe that Lorenzo's
 questions matter if we're using S2 for CPUidle (where we actually turn
 off power and hot unplug CPUs) but not when we're using S1 for CPUidle
 (where we just enter WFI/WFE).


No Its not plain WFI.

All cores in Exynos5420 can be powered off independently.
This functionality has been tested.

Below is the link for the posted patches.

https://lkml.org/lkml/2014/6/10/194

And as Nicolas wrote, these patches need MCPM for that.

 I believe that in ChromeOS we use S1 CPUidle and that it works fine.
 We've never implemented S2 that I'm aware of.

 You'll have to rely on MCPM for that.  That's probably why it hasn't
 been implemented before.


 Nicolas

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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-28 Thread Chander Kashyap
On 28 May 2014 14:32, Daniel Lezcano daniel.lezc...@linaro.org wrote:
 On 05/28/2014 06:35 AM, Kukjin Kim wrote:

 Chander Kashyap wrote:


 On 26 May 2014 15:59, Tomasz Figa tomasz.f...@gmail.com wrote:

 Hi Chander,

 On 16.05.2014 10:03, Chander Kashyap wrote:

 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7

 cores.


 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
driver: cpuidle-big-little: add of_device_id structure
arm: exynos: add generic function to calculate cpu number
cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
  driver
driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
exynos: cpuidle: do not allow cpuidle registration for Exynos5420
mcpm: exynos: populate suspend and powered_up callbacks

   arch/arm/mach-exynos/exynos.c|4 +++-
   arch/arm/mach-exynos/mcpm-exynos.c   |   36

 ++

   arch/arm/mach-exynos/regs-pmu.h  |9 +
   drivers/cpuidle/Kconfig.arm  |2 +-
   drivers/cpuidle/cpuidle-big_little.c |   12 +++-
   5 files changed, 60 insertions(+), 3 deletions(-)


 For the whole series,

 Reviewed-by: Tomasz Figa t.f...@samsung.com


 Thanks Tomasz.

 Dear Kukjin,
 Can you take these patches.


 When I looked at this series quickly, looks good to me but I need to get
 ack from cpuidle maintainer Rafael or Daniel.


 Acked the different cpuidle bits.

Hi Kukjin,
Can you take it now?



 Thanks
   -- Daniel


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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-27 Thread Chander Kashyap
On 26 May 2014 15:59, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Chander,

 On 16.05.2014 10:03, Chander Kashyap wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
   1. [PATCH 0/5] MCPM backend for Exynos5420
  http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)


 For the whole series,

 Reviewed-by: Tomasz Figa t.f...@samsung.com

Thanks Tomasz.

Dear Kukjin,
Can you take these patches.

 Best regards,
 Tomasz



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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-25 Thread Chander Kashyap
On 19 May 2014 11:10, Chander Kashyap chander.kash...@linaro.org wrote:
 Hi Daniel/Kgene,

 On 16 May 2014 13:33, Chander Kashyap chander.kash...@linaro.org wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
 1. [PATCH 0/5] MCPM backend for Exynos5420
http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)

 --
 1.7.9.5


 As dependency patches are merged. If their are no further comment, can
 these patches be taken?


ping

 --
 with warm regards,
 Chander Kashyap



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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-18 Thread Chander Kashyap
Hi Daniel/Kgene,

On 16 May 2014 13:33, Chander Kashyap chander.kash...@linaro.org wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
 1. [PATCH 0/5] MCPM backend for Exynos5420
http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)

 --
 1.7.9.5


As dependency patches are merged. If their are no further comment, can
these patches be taken?

-- 
with warm regards,
Chander Kashyap
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[PATCH v6 2/6] arm: exynos: add generic function to calculate cpu number

2014-05-16 Thread Chander Kashyap
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4179f6a..485aefd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -325,4 +325,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-16 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/exynos.c|4 +++-
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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[PATCH v6 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-16 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v6:
1. Move cpuidle registration check to exynos.c from cpuidle.c and
   use samsung,exynos5420 compatible string to avvoid registration
 arch/arm/mach-exynos/exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 4df3452..ef24edf 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -286,7 +286,9 @@ static void __init exynos_dt_machine_init(void)
}
}
 
-   exynos_cpuidle_init();
+   if (!of_machine_is_compatible(samsung,exynos5420))
+   exynos_cpuidle_init();
+
exynos_cpufreq_init();
 
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5

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[PATCH v6 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-16 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v6: None
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index c6bb3a4..623dfa7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -253,10 +253,46 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register.
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[PATCH v6 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-16 Thread Chander Kashyap
Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[PATCH v6 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-05-16 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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Re: [PATCH v5 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-15 Thread Chander Kashyap
Hi Tomasz,

On 16 May 2014 02:56, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Chander,

 On 14.05.2014 10:03, Chander Kashyap wrote:
 Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle 
 driver.
 Hence do not allow exynos cpuidle driver registration for Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
 ---
  arch/arm/mach-exynos/cpuidle.c |3 +++
  1 file changed, 3 insertions(+)

 diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
 index 3dd385e..807a386 100644
 --- a/arch/arm/mach-exynos/cpuidle.c
 +++ b/arch/arm/mach-exynos/cpuidle.c
 @@ -218,6 +218,9 @@ static int exynos_cpuidle_probe(struct platform_device 
 *pdev)
   int cpu_id, ret;
   struct cpuidle_device *device;

 + if (soc_is_exynos5420())
 + return -ENODEV;
 +
   if (soc_is_exynos5250())
   exynos5_core_down_clk();



 Why not put this in exynos.c in exynos_dt_machine_init(), so
 exynos_cpuidle_init() is called only if not running on Exynos5420?


That makes more sense.
I will update this

Thanks
 Best regards,
 Tomasz



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Re: [PATCH] arm: exynos: add generic function to calculate cpu number

2014-05-14 Thread Chander Kashyap
On 9 May 2014 14:04, Chander Kashyap chander.kash...@linaro.org wrote:
 On 9 May 2014 13:47, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander,

 On 09.05.2014 09:50, Chander Kashyap wrote:
 On 5 May 2014 09:37, Chander Kashyap chander.kash...@linaro.org wrote:
 On 25 April 2014 11:14, Chander Kashyap chander.kash...@linaro.org wrote:
 The address of cpu power registers in pmu is based on cpu number
 offsets. This function calculate the same. This is essentially
 required in case of multicluster SoC's e.g Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
  arch/arm/mach-exynos/regs-pmu.h |9 +
  1 file changed, 9 insertions(+)

 diff --git a/arch/arm/mach-exynos/regs-pmu.h 
 b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..217da2e 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -313,4 +313,13 @@

  #define EXYNOS5_OPTION_USE_RETENTION   (1  4)

 +#include asm/cputype.h
 +#define MAX_CPUS_IN_CLUSTER4
 +
 +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 +{
 +   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
 ++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
 +}
 +
  #endif /* __ASM_ARCH_REGS_PMU_H */
 --
 1.7.9.5


 Kukjin, Can you please have a look.



 --
 with warm regards,
 Chander Kashyap
 Hi Kgene,
 Can you take this patch if no issues with it.

 Is there any user for this function right now? Shouldn't this patch
 rather be included as a part of some series that adds actual users of it?

 Hi Tomasz,
 Exynos5420 patches have dependency on this.
 Those patches already posted.


Please ignore. Sending this with cpuidle patches



 Best regards,
 Tomasz




 --
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 Chander Kashyap



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[PATCH v5 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-14 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index c6bb3a4..623dfa7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -253,10 +253,46 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register.
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[PATCH v5 2/6] arm: exynos: add generic function to calculate cpu number

2014-05-14 Thread Chander Kashyap
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4179f6a..485aefd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -325,4 +325,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[PATCH v5 0/6] add cpuidle support for Exynos5420

2014-05-14 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 +++
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH v5 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-14 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 3dd385e..807a386 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -218,6 +218,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;
 
+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();
 
-- 
1.7.9.5

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[PATCH v5 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-14 Thread Chander Kashyap
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[PATCH v5 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-05-14 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[PATCH v5 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-14 Thread Chander Kashyap
Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-little SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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Re: [PATCH v5 0/6] add cpuidle support for Exynos5420

2014-05-14 Thread Chander Kashyap
Hi Daniel,

On 14 May 2014 15:26, Daniel Lezcano daniel.lezc...@linaro.org wrote:
 On 05/14/2014 10:03 AM, Chander Kashyap wrote:

 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.


 Hi Chander,

 just a side question. I am not succeeding to have both cluster A7/A15 with
 the upstream kernel.

 How can I test your driver ?

Hmm on octa can be tested only for 4 cores. as cci is disabled.


 Did I miss something ?

 Thanks
   -- Daniel


 Tested on SMDK5420.

 This patch set depends on:
 1. [PATCH 0/5] MCPM backend for Exynos5420
http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
driver: cpuidle-big-little: add of_device_id structure
arm: exynos: add generic function to calculate cpu number
cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
  driver
driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
exynos: cpuidle: do not allow cpuidle registration for Exynos5420
mcpm: exynos: populate suspend and powered_up callbacks

   arch/arm/mach-exynos/cpuidle.c   |3 +++
   arch/arm/mach-exynos/mcpm-exynos.c   |   36
 ++
   arch/arm/mach-exynos/regs-pmu.h  |9 +
   drivers/cpuidle/Kconfig.arm  |2 +-
   drivers/cpuidle/cpuidle-big_little.c |   12 +++-
   5 files changed, 60 insertions(+), 2 deletions(-)



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Re: [Patch v4 5/5] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-13 Thread Chander Kashyap
Hi Lorenzo

On 9 May 2014 21:02, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Mon, May 05, 2014 at 10:27:20AM +0100, Chander Kashyap wrote:
 In order to support cpuidle through mcpm, suspend and powered-up
 callbacks are required in mcpm platform code.
 Hence populate the same callbacks.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 Changes in v4: None
 Changes in v3:
   1. Removed coherancy enablement after suspend failure.

 coherency

   2. Use generic function to poweron cpu.
 changes in v2:
   1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
  arch/arm/mach-exynos/mcpm-exynos.c |   34 ++
  1 file changed, 34 insertions(+)

 diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
 b/arch/arm/mach-exynos/mcpm-exynos.c
 index d0f7461..6d4a907 100644
 --- a/arch/arm/mach-exynos/mcpm-exynos.c
 +++ b/arch/arm/mach-exynos/mcpm-exynos.c
 @@ -256,10 +256,44 @@ static int exynos_power_down_finish(unsigned int cpu, 
 unsigned int cluster)
   return -ETIMEDOUT; /* timeout */
  }

 +void exynos_powered_up(void)

 static ?

Ok, done


 +{
 + unsigned int mpidr, cpu, cluster;
 +
 + mpidr = read_cpuid_mpidr();
 + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 +
 + arch_spin_lock(exynos_mcpm_lock);
 + if (cpu_use_count[cpu][cluster] == 0)
 + cpu_use_count[cpu][cluster] = 1;
 + arch_spin_unlock(exynos_mcpm_lock);
 +}
 +
 +static void exynos_suspend(u64 residency)
 +{
 + unsigned int mpidr, cpunr;
 +
 + mpidr = read_cpuid_mpidr();
 + cpunr = exynos_pmu_cpunr(mpidr);

 If I were to be picky, I would compute these values only if they
 are needed, ie move the computation after exynos_power_down().

Yes thats make sense. I will realign it.


 There is another quite horrible issue here. We know this code works
 because the processors A15/A7 hit the caches with C bit in SCTLR cleared.

 On processors where this is not true, this sequence would explode
 if power down fails (in case core is gated but L2 is still powered on,
 the stack is stuck in L2) since it is going to read stack data that is
 in L2 but can't be read.

 It is not related to this sequence only, but it is an issue in general
 and wanted to mention that on the lists for public awareness.


Can you please elaborate. I didn't understand.

 The gist of what I am saying is, please add a comment to that extent,
 here and it should be added in exynos_power_down() too.

 + __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 0x1c);

 No magic numbers please (0x1c). You can add a macro/wrapper, as TC2 does.

Yes i will remove it.


 + exynos_power_down();
 +
 + /*
 +  * Execution reaches here only if cpu did not power down.
 +  * Hence roll back the changes done in exynos_power_down function.
 + */
 + exynos_cpu_powerup(cpunr);

 Please be aware that if this function returns MCPM will soft reboot, and
 the CPUidle driver will have no way to detect a state entry failure.

 I am just flagging this up, since fixing this behaviour is not easy, and
 honestly, since power down failure should be the exception not the rule,
 the idle stats should not be affected much.

 I think this is the proper way of implementing the sequence but please
 all keep in mind what I wrote above.

 Lorenzo

 +}
 +
  static const struct mcpm_platform_ops exynos_power_ops = {
   .power_up   = exynos_power_up,
   .power_down = exynos_power_down,
   .power_down_finish  = exynos_power_down_finish,
 + .suspend= exynos_suspend,
 + .powered_up = exynos_powered_up,
  };

  static void __init exynos_mcpm_usage_count_init(void)
 --
 1.7.9.5






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Re: [Patch v4 5/5] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-13 Thread Chander Kashyap
Hi Lorenzo,

On 13 May 2014 22:44, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Tue, May 13, 2014 at 12:43:31PM +0100, Chander Kashyap wrote:

 [...]

  +static void exynos_suspend(u64 residency)
  +{
  + unsigned int mpidr, cpunr;
  +
  + mpidr = read_cpuid_mpidr();
  + cpunr = exynos_pmu_cpunr(mpidr);
 
  If I were to be picky, I would compute these values only if they
  are needed, ie move the computation after exynos_power_down().

 Yes thats make sense. I will realign it.

 
  There is another quite horrible issue here. We know this code works
  because the processors A15/A7 hit the caches with C bit in SCTLR cleared.
 
  On processors where this is not true, this sequence would explode
  if power down fails (in case core is gated but L2 is still powered on,
  the stack is stuck in L2) since it is going to read stack data that is
  in L2 but can't be read.
 
  It is not related to this sequence only, but it is an issue in general
  and wanted to mention that on the lists for public awareness.
 

 Can you please elaborate. I didn't understand.

 It is not related to this patch only. This function carries out writes to the
 stack (which might end up in eg L2) and then disables the C bit in SCTLR
 through MCPM.

 A15 and A7 processors hit the cache with the C bit clear in the SCTLR
 so the processor still hits the stack values if the power down fails.
 On processors where caches are not hit with the C bit clear (eg A9) this code
 would fail since the stack values that sit in the caches cannot be read with
 the C bit clear in SCTLR until the SCTLR is restored, so it will have to
 be implemented in assembly with no stack usage (or better, no cacheable data
 usage).

 So, all I am saying is, to avoid copy'n'paste havoc and to avoid running
 this code on Exynos platforms where it must not be run as-is, please add
 a comment along the line:

 This function requires the stack data to be visible through power down
 and can only be executed on processors like A15 and A7 that hit the cache
 with the C bit clear in the SCTLR register.

 Please let me know if that's clear.

It all clear now.
Thanks a lot.


 Lorenzo


  The gist of what I am saying is, please add a comment to that extent,
  here and it should be added in exynos_power_down() too.
 
  + __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 
  0x1c);
 
  No magic numbers please (0x1c). You can add a macro/wrapper, as TC2 does.

 Yes i will remove it.

 
  + exynos_power_down();
  +
  + /*
  +  * Execution reaches here only if cpu did not power down.
  +  * Hence roll back the changes done in exynos_power_down function.
  + */
  + exynos_cpu_powerup(cpunr);
 
  Please be aware that if this function returns MCPM will soft reboot, and
  the CPUidle driver will have no way to detect a state entry failure.
 
  I am just flagging this up, since fixing this behaviour is not easy, and
  honestly, since power down failure should be the exception not the rule,
  the idle stats should not be affected much.
 
  I think this is the proper way of implementing the sequence but please
  all keep in mind what I wrote above.
 
  Lorenzo
 
  +}
  +
   static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
  + .suspend= exynos_suspend,
  + .powered_up = exynos_powered_up,
   };
 
   static void __init exynos_mcpm_usage_count_init(void)
  --
  1.7.9.5
 
 
 



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 Chander Kashyap





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Re: [PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

2014-05-13 Thread Chander Kashyap
On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
 Hi Lorenzo,

 On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
 lorenzo.pieral...@arm.com wrote:
 On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:

 [...]

 +static int __init exynos_mcpm_init(void)
 +{
 +   struct device_node *node;
 +   int ret = 0;

 There is no point in initializing it to 0.
 OK.

 +
 +   node = of_find_compatible_node(NULL, NULL, samsung,exynos5420);
 +   if (!node)
 +   return -ENODEV;
 +   of_node_put(node);
 +
 +   if (!cci_probed())
 +   return -ENODEV;
 +
 +   node = of_find_compatible_node(NULL, NULL,
 +   samsung,exynos4210-sysram-ns);
 +   if (!node)
 +   return -ENODEV;
 +
 +   ns_sram_base_addr = of_iomap(node, 0);
 +   of_node_put(node);
 +   if (!ns_sram_base_addr) {
 +   pr_err(failed to map non-secure iRAM base address\n);
 +   return -ENOMEM;
 +   }
 +
 +   /*
 +* To increase the stability of KFC reset we need to program
 +* the PMU SPARE3 register
 +*/
 +   __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
 +
 +   exynos_mcpm_usage_count_init();
 +
 +   ret = mcpm_platform_register(exynos_power_ops);
 +   if (!ret)
 +   ret = mcpm_sync_init(exynos_pm_power_up_setup);
 +   if (ret) {
 +   iounmap(ns_sram_base_addr);
 +   return ret;
 +   }
 +
 +   mcpm_smp_set_ops();
 +
 +   pr_info(Exynos MCPM support installed\n);
 +
 +   /*
 +* Future entries into the kernel can now go
 +* through the cluster entry vectors.
 +*/
 +   __raw_writel(virt_to_phys(mcpm_entry_point),
 +   ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
 +

 ns_sram_base_addr must be unmapped, since it is unused after the write.
 Will unmap.

This mapping is required in for cpuilde (suspend) to program
mcpm_entry before going to suspend.


 Regards,
 Abhilash
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Re: [PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

2014-05-13 Thread Chander Kashyap
On 14 May 2014 08:32, Nicolas Pitre nicolas.pi...@linaro.org wrote:
 On Wed, 14 May 2014, Chander Kashyap wrote:

 On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
  Hi Lorenzo,
 
  On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
  lorenzo.pieral...@arm.com wrote:
  On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
 
  [...]
 
  +static int __init exynos_mcpm_init(void)
  +{
  +   struct device_node *node;
  +   int ret = 0;
 
  There is no point in initializing it to 0.
  OK.
 
  +
  +   node = of_find_compatible_node(NULL, NULL, samsung,exynos5420);
  +   if (!node)
  +   return -ENODEV;
  +   of_node_put(node);
  +
  +   if (!cci_probed())
  +   return -ENODEV;
  +
  +   node = of_find_compatible_node(NULL, NULL,
  +   samsung,exynos4210-sysram-ns);
  +   if (!node)
  +   return -ENODEV;
  +
  +   ns_sram_base_addr = of_iomap(node, 0);
  +   of_node_put(node);
  +   if (!ns_sram_base_addr) {
  +   pr_err(failed to map non-secure iRAM base address\n);
  +   return -ENOMEM;
  +   }
  +
  +   /*
  +* To increase the stability of KFC reset we need to program
  +* the PMU SPARE3 register
  +*/
  +   __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
  +
  +   exynos_mcpm_usage_count_init();
  +
  +   ret = mcpm_platform_register(exynos_power_ops);
  +   if (!ret)
  +   ret = mcpm_sync_init(exynos_pm_power_up_setup);
  +   if (ret) {
  +   iounmap(ns_sram_base_addr);
  +   return ret;
  +   }
  +
  +   mcpm_smp_set_ops();
  +
  +   pr_info(Exynos MCPM support installed\n);
  +
  +   /*
  +* Future entries into the kernel can now go
  +* through the cluster entry vectors.
  +*/
  +   __raw_writel(virt_to_phys(mcpm_entry_point),
  +   ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
  +
 
  ns_sram_base_addr must be unmapped, since it is unused after the write.
  Will unmap.

 This mapping is required in for cpuilde (suspend) to program
 mcpm_entry before going to suspend.

 Why?

This is required to program the mcpm_entry point address (resume
address) after cpuidle exit/fail.

Abhilash, as i am not clearing it, it can be unmapped.

Thanks Nicolas.




 Nicolas




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Re: [PATCH] arm: exynos: add generic function to calculate cpu number

2014-05-09 Thread Chander Kashyap
On 5 May 2014 09:37, Chander Kashyap chander.kash...@linaro.org wrote:
 On 25 April 2014 11:14, Chander Kashyap chander.kash...@linaro.org wrote:
 The address of cpu power registers in pmu is based on cpu number
 offsets. This function calculate the same. This is essentially
 required in case of multicluster SoC's e.g Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
  arch/arm/mach-exynos/regs-pmu.h |9 +
  1 file changed, 9 insertions(+)

 diff --git a/arch/arm/mach-exynos/regs-pmu.h 
 b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..217da2e 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -313,4 +313,13 @@

  #define EXYNOS5_OPTION_USE_RETENTION   (1  4)

 +#include asm/cputype.h
 +#define MAX_CPUS_IN_CLUSTER4
 +
 +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 +{
 +   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
 ++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
 +}
 +
  #endif /* __ASM_ARCH_REGS_PMU_H */
 --
 1.7.9.5


 Kukjin, Can you please have a look.



 --
 with warm regards,
 Chander Kashyap
Hi Kgene,
Can you take this patch if no issues with it.


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Re: [PATCH] arm: exynos: add generic function to calculate cpu number

2014-05-09 Thread Chander Kashyap
On 9 May 2014 13:47, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander,

 On 09.05.2014 09:50, Chander Kashyap wrote:
 On 5 May 2014 09:37, Chander Kashyap chander.kash...@linaro.org wrote:
 On 25 April 2014 11:14, Chander Kashyap chander.kash...@linaro.org wrote:
 The address of cpu power registers in pmu is based on cpu number
 offsets. This function calculate the same. This is essentially
 required in case of multicluster SoC's e.g Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
  arch/arm/mach-exynos/regs-pmu.h |9 +
  1 file changed, 9 insertions(+)

 diff --git a/arch/arm/mach-exynos/regs-pmu.h 
 b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..217da2e 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -313,4 +313,13 @@

  #define EXYNOS5_OPTION_USE_RETENTION   (1  4)

 +#include asm/cputype.h
 +#define MAX_CPUS_IN_CLUSTER4
 +
 +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 +{
 +   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
 ++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
 +}
 +
  #endif /* __ASM_ARCH_REGS_PMU_H */
 --
 1.7.9.5


 Kukjin, Can you please have a look.



 --
 with warm regards,
 Chander Kashyap
 Hi Kgene,
 Can you take this patch if no issues with it.

 Is there any user for this function right now? Shouldn't this patch
 rather be included as a part of some series that adds actual users of it?

Hi Tomasz,
Exynos5420 patches have dependency on this.
Those patches already posted.



 Best regards,
 Tomasz




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[PATCH v3 0/5] add cpuidle support for Exynos5420

2014-05-05 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg327923.html

2. [PATCH] arm: exynos: add generic function to calculate cpu number
   http://www.spinics.net/lists/linux-samsung-soc/msg29446.html
   http://www.spinics.net/lists/arm-kernel/msg324024.html

Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 +++
 arch/arm/mach-exynos/mcpm-exynos.c   |   34 ++
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 4 files changed, 49 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[Patch v3 4/5] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-05 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index c57cae0..242f75d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -219,6 +219,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;
 
+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();
 
-- 
1.7.9.5

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[Patch v3 5/5] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-05 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v3:
1. Removed coherance enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index d0f7461..6d4a907 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -256,10 +256,44 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 0x1c);
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+   */
+   exynos_cpu_powerup(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[Patch v3 3/5] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-05 Thread Chander Kashyap
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[Patch v3 2/5] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-05 Thread Chander Kashyap
Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
In order to use generic cpuidle-big-little driver, this patch adds Exynos5420
specific check to initialize generic cpuidle driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to SOC_EXYNOS5420
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[Patch v3 1/5] driver: cpuidle-big-little: add of_device_id structure

2014-05-05 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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Re: [Patch v3 2/5] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-05 Thread Chander Kashyap
Hi Andreas,

On 5 May 2014 14:29, Andreas Färber afaer...@suse.de wrote:
 Hi,

 Am 05.05.2014 10:27, schrieb Chander Kashyap:
 Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
 In order to use generic cpuidle-big-little driver, this patch adds Exynos5420
 specific check to initialize generic cpuidle driver.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 Changes in v3: None
 Changes in v2:
   1. Changed config macro from SOC_EXYNOS5420 to SOC_EXYNOS5420

 This is probably a copypasto? Anyway, the commit message needs an
 update since no Exynos5420 specific check is done below afaics. That
 went into 3/5.

Oops that's write,
Copy paste mistake, and commit message change is required. I will fix it .

Thanks



 Cheers,
 Andreas

  drivers/cpuidle/Kconfig.arm |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
 index 97ccc31..d9596e7 100644
 --- a/drivers/cpuidle/Kconfig.arm
 +++ b/drivers/cpuidle/Kconfig.arm
 @@ -4,7 +4,7 @@

  config ARM_BIG_LITTLE_CPUIDLE
   bool Support for ARM big.LITTLE processors
 - depends on ARCH_VEXPRESS_TC2_PM
 + depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
   select ARM_CPU_SUSPEND
   select CPU_IDLE_MULTIPLE_DRIVERS
   help



 --
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 GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg



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[PATCH v4 0/5] add cpuidle support for Exynos5420

2014-05-05 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg327923.html

2. [PATCH] arm: exynos: add generic function to calculate cpu number
   http://www.spinics.net/lists/linux-samsung-soc/msg29446.html
   http://www.spinics.net/lists/arm-kernel/msg324024.html

Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 +++
 arch/arm/mach-exynos/mcpm-exynos.c   |   34 ++
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 4 files changed, 49 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[Patch v4 1/5] driver: cpuidle-big-little: add of_device_id structure

2014-05-05 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[Patch v4 2/5] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-05 Thread Chander Kashyap
Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[Patch v4 3/5] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-05 Thread Chander Kashyap
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[Patch v4 4/5] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-05 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index c57cae0..242f75d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -219,6 +219,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;
 
+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();
 
-- 
1.7.9.5

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[Patch v4 5/5] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-05 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v4: None
Changes in v3:
1. Removed coherancy enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index d0f7461..6d4a907 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -256,10 +256,44 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 0x1c);
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+   */
+   exynos_cpu_powerup(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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Re: [PATCH] arm: exynos: add generic function to calculate cpu number

2014-05-04 Thread Chander Kashyap
On 25 April 2014 11:14, Chander Kashyap chander.kash...@linaro.org wrote:
 The address of cpu power registers in pmu is based on cpu number
 offsets. This function calculate the same. This is essentially
 required in case of multicluster SoC's e.g Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
  arch/arm/mach-exynos/regs-pmu.h |9 +
  1 file changed, 9 insertions(+)

 diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..217da2e 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -313,4 +313,13 @@

  #define EXYNOS5_OPTION_USE_RETENTION   (1  4)

 +#include asm/cputype.h
 +#define MAX_CPUS_IN_CLUSTER4
 +
 +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 +{
 +   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
 ++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
 +}
 +
  #endif /* __ASM_ARCH_REGS_PMU_H */
 --
 1.7.9.5


Kukjin, Can you please have a look.



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Re: [PATCH v5] arm: exynos: generalize power register address calculation

2014-04-24 Thread Chander Kashyap
On 24 April 2014 13:18, Chander Kashyap chander.kash...@linaro.org wrote:
 On 22 April 2014 17:55, Chander Kashyap chander.kash...@linaro.org wrote:
 Currently status/configuration power register values are hard-coded for cpu1.

 Make it generic so that it is useful for SoC's with more than two cpus.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 changes in v5:
 1. Fix typo: enynos_pmu_cpunr - exynos_pmu_cpunr
 changes in v4:
 1: Dropped changes in platsmp.c and hotplug.c as those are taken 
 care by
Tomasz Patches.
 2. Converted ENYNOS_PMU_CPUNR macro to static inline function
 changes in v3:
 1. Move cpunr calculation to a macro
 2. Changed printk format specifier from unsigned hex to unsigned 
 decimal
 Changes in v2:
 1. Used existing macros for clusterid and cpuid calculation

  arch/arm/mach-exynos/regs-pmu.h |   18 --
  1 file changed, 16 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/mach-exynos/regs-pmu.h 
 b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..f39e78c 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -105,8 +105,13 @@
  #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
  #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)

 -#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
 -#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
 +#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
 +#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
 +
 +#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
 +   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
 +#define S5P_ARM_CORE_STATUS(_cpunr) \
 +   (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr))

  #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
  #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
 @@ -313,4 +318,13 @@

  #define EXYNOS5_OPTION_USE_RETENTION   (1  4)

 +#include asm/cputype.h
 +#define MAX_CPUS_IN_CLUSTER4
 +
 +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 +{
 +   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
 ++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
 +}
 +
  #endif /* __ASM_ARCH_REGS_PMU_H */
 --
 1.7.9.5


 Any other comment on this. If not can this be merged?

Please reject this patch as some of changes also done by Tomasz in his patches.


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 with warm regards,
 Chander Kashyap



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[PATCH] arm: exynos: add generic function to calculate cpu number

2014-04-24 Thread Chander Kashyap
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multicluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..217da2e 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -313,4 +313,13 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION   (1  4)
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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Re: [Patch v2 4/4] mcpm: exynos: populate suspend and powered_up callbacks

2014-04-24 Thread Chander Kashyap
On 23 April 2014 21:32, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 [added Nico in CC]

 On Wed, Apr 23, 2014 at 10:25:54AM +0100, Chander Kashyap wrote:
 In order to support cpuidle through mcpm, suspend and powered-up
 callbacks are required in mcpm platform code.
 Hence populate the same callbacks.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 changes in v2:
   1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr

  arch/arm/mach-exynos/mcpm-exynos.c |   53 
 
  1 file changed, 53 insertions(+)

 diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
 b/arch/arm/mach-exynos/mcpm-exynos.c
 index 6c74c82..d53f597 100644
 --- a/arch/arm/mach-exynos/mcpm-exynos.c
 +++ b/arch/arm/mach-exynos/mcpm-exynos.c
 @@ -272,10 +272,63 @@ static int exynos_power_down_finish(unsigned int cpu, 
 unsigned int cluster)
   return 0; /* success: the CPU is halted */
  }

 +static void enable_coherency(void)
 +{
 + unsigned long v, u;
 +
 + asm volatile(
 + mrcp15, 0, %0, c1, c0, 1\n
 + orr%0, %0, %2\n
 + ldr%1, [%3]\n
 + and%1, %1, #0\n
 + orr%0, %0, %1\n
 + mcrp15, 0, %0, c1, c0, 1\n
 + : =r (v), =r (u)
 + : Ir (0x40), Ir (S5P_INFORM0)
 + : cc);
 +}
 +
 +void exynos_powered_up(void)
 +{
 + unsigned int mpidr, cpu, cluster;
 +
 + mpidr = read_cpuid_mpidr();
 + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 +
 + arch_spin_lock(exynos_mcpm_lock);
 + if (cpu_use_count[cpu][cluster] == 0)
 + cpu_use_count[cpu][cluster] = 1;
 + arch_spin_unlock(exynos_mcpm_lock);
 +}
 +
 +static void exynos_suspend(u64 residency)
 +{
 + unsigned int mpidr, cpunr;
 +
 + mpidr = read_cpuid_mpidr();
 + cpunr = exynos_pmu_cpunr(mpidr);
 +
 + __raw_writel(virt_to_phys(mcpm_entry_point), REG_ENTRY_ADDR);
 +
 + exynos_power_down();
 +
 + /*
 +  * Execution reaches here only if cpu did not power down.
 +  * Hence roll back the changes done in exynos_power_down function.
 + */
 + __raw_writel(EXYNOS_CORE_LOCAL_PWR_EN,
 + EXYNOS_ARM_CORE_CONFIGURATION(cpunr));
 + set_cr(get_cr() | CR_C);
 + enable_coherency();

 This is wrong:

 1) MCPM would eventually reboot the CPU in question if the suspend call
returns (and restore SCTLR and ACTLR in cpu_resume), so there is 0 point
in doing that here.

Yes i missed that. I will correct it.

 2) The core would have executed out of coherency for a while so the
tlbs could be stale and you do not invalidate them. But given (1), (2)
becomes just informational. The register write must be executed
though (I guess...). Now, on restoring the SMP bit in cpu_resume
(errata 799270) I need to verify this is safe and get back to you.

Ok

Thanks Lorenzo.



 Cheers,
 Lorenzo




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Re: [Patch v2 2/4] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-04-24 Thread Chander Kashyap
On 23 April 2014 22:02, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Wed, Apr 23, 2014 at 10:25:52AM +0100, Chander Kashyap wrote:
 Add samsung,exynos5420 compatible string to initialize generic
 big-little cpuidle driver for Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
 ---
  drivers/cpuidle/cpuidle-big_little.c |3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

 diff --git a/drivers/cpuidle/cpuidle-big_little.c 
 b/drivers/cpuidle/cpuidle-big_little.c
 index b45fc62..d0fac53 100644
 --- a/drivers/cpuidle/cpuidle-big_little.c
 +++ b/drivers/cpuidle/cpuidle-big_little.c
 @@ -170,7 +170,8 @@ static int __init bl_idle_init(void)
   /*
* Initialize the driver just for a compliant set of machines
*/
 - if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
 + if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7) 
 + (!of_machine_is_compatible(samsung,exynos5420)))
   return -ENODEV;

 We should handle the string matching differently, we can't keep adding
 comparisons.

yes, that's true.



 Daniel raised the point already: what about the idle tables (data and
 number of states ?). TC2 has just a cluster state, and specific
 latencies, which are highly unlikely to be correct for this platform.


As of now only support for one state i.e. core power down.

As latencies are  concerned, need to fine tune.

Thanks again for the review.

 Lorenzo




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Re: [PATCH v5] arm: exynos: generalize power register address calculation

2014-04-24 Thread Chander Kashyap
On 22 April 2014 17:55, Chander Kashyap chander.kash...@linaro.org wrote:
 Currently status/configuration power register values are hard-coded for cpu1.

 Make it generic so that it is useful for SoC's with more than two cpus.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 changes in v5:
 1. Fix typo: enynos_pmu_cpunr - exynos_pmu_cpunr
 changes in v4:
 1: Dropped changes in platsmp.c and hotplug.c as those are taken care 
 by
Tomasz Patches.
 2. Converted ENYNOS_PMU_CPUNR macro to static inline function
 changes in v3:
 1. Move cpunr calculation to a macro
 2. Changed printk format specifier from unsigned hex to unsigned 
 decimal
 Changes in v2:
 1. Used existing macros for clusterid and cpuid calculation

  arch/arm/mach-exynos/regs-pmu.h |   18 --
  1 file changed, 16 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..f39e78c 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -105,8 +105,13 @@
  #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
  #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)

 -#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
 -#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
 +#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
 +#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
 +
 +#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
 +   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
 +#define S5P_ARM_CORE_STATUS(_cpunr) \
 +   (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr))

  #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
  #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
 @@ -313,4 +318,13 @@

  #define EXYNOS5_OPTION_USE_RETENTION   (1  4)

 +#include asm/cputype.h
 +#define MAX_CPUS_IN_CLUSTER4
 +
 +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 +{
 +   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
 ++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
 +}
 +
  #endif /* __ASM_ARCH_REGS_PMU_H */
 --
 1.7.9.5


Any other comment on this. If not can this be merged?


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Re: [PATCH 1/4] cpuidle: config: Add SOC_EXYNOS5420 entry to select cpuidle-big-little driver

2014-04-23 Thread Chander Kashyap
Hi Daniel,

On 22 April 2014 16:12, Daniel Lezcano daniel.lezc...@linaro.org wrote:
 On 04/21/2014 01:49 PM, Chander Kashyap wrote:

 Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
 In order to use generic cpuidle-big-little driver, this patch adds
 Exynos5420
 specific check to initialize generic cpuidle driver.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
   drivers/cpuidle/Kconfig.arm |2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
 index 97ccc31..5244d87 100644
 --- a/drivers/cpuidle/Kconfig.arm
 +++ b/drivers/cpuidle/Kconfig.arm
 @@ -4,7 +4,7 @@

   config ARM_BIG_LITTLE_CPUIDLE
 bool Support for ARM big.LITTLE processors
 -   depends on ARCH_VEXPRESS_TC2_PM
 +   depends on ARCH_VEXPRESS_TC2_PM || SOC_EXYNOS5420


 For the sake of consistency, I would prefer:

 depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS

Yes i will change it.

Thanks

 and let the current code (and future platform driver) to handle the loading
 of the driver.


 select ARM_CPU_SUSPEND
 select CPU_IDLE_MULTIPLE_DRIVERS
 help



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Re: [PATCH 4/4] mcpm: exynos: populate suspend and powered_up callbacks

2014-04-23 Thread Chander Kashyap
On 22 April 2014 16:21, Daniel Lezcano daniel.lezc...@linaro.org wrote:
 On 04/21/2014 01:49 PM, Chander Kashyap wrote:

 In order to support cpuidle through mcpm, suspend and powered-up
 callbacks are required in mcpm platform code.
 Hence populate the same callbacks.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
   arch/arm/mach-exynos/mcpm-exynos.c |   53
 
   1 file changed, 53 insertions(+)

 diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
 b/arch/arm/mach-exynos/mcpm-exynos.c
 index 46d4968..16af0bd 100644
 --- a/arch/arm/mach-exynos/mcpm-exynos.c
 +++ b/arch/arm/mach-exynos/mcpm-exynos.c
 @@ -318,10 +318,63 @@ static int exynos_power_down_finish(unsigned int
 cpu, unsigned int cluster)
 return 0; /* success: the CPU is halted */
   }

 +static void enable_coherency(void)
 +{
 +   unsigned long v, u;
 +
 +   asm volatile(
 +   mrcp15, 0, %0, c1, c0, 1\n
 +   orr%0, %0, %2\n
 +   ldr%1, [%3]\n
 +   and%1, %1, #0\n
 +   orr%0, %0, %1\n
 +   mcrp15, 0, %0, c1, c0, 1\n
 +   : =r (v), =r (u)
 +   : Ir (0x40), Ir (S5P_INFORM0)
 +   : cc);
 +}


 Shouldn't this function to be used from hotplug.c also ?

Hotplug.c already taking care for this. And anyhow that will go away
for mcpm dependent SoCs



 +
 +void exynos_powered_up(void)
 +{
 +   unsigned int mpidr, cpu, cluster;
 +
 +   mpidr = read_cpuid_mpidr();
 +   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 +   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 +
 +   arch_spin_lock(bl_lock);
 +   if (cpu_use_count[cpu][cluster] == 0)
 +   cpu_use_count[cpu][cluster] = 1;
 +   arch_spin_unlock(bl_lock);
 +}
 +
 +static void exynos_suspend(u64 residency)
 +{
 +   unsigned int mpidr, cpunr;
 +
 +   mpidr = read_cpuid_mpidr();
 +   cpunr = enynos_pmu_cpunr(mpidr);


 *enynos*_pmu_cpunr ?

oops, I will fix typo



 +
 +   __raw_writel(virt_to_phys(mcpm_entry_point), REG_ENTRY_ADDR);
 +
 +   exynos_power_down();
 +
 +   /*
 +* Execution reaches here only if cpu did not power down.
 +* Hence roll back the changes done in exynos_power_down function.
 +   */
 +   __raw_writel(EXYNOS_CORE_LOCAL_PWR_EN,
 +   EXYNOS_ARM_CORE_CONFIGURATION(cpunr));


 Why don't you use the functions defined in the

 patch 5/5 arm: exynos: Add MCPM call-back functions

In exynos_core_power_control it powerup the alreay powered down core.
But here i need to simply set this value as core never powered down.


 exynos_core_power_control() ?


 +   set_cr(get_cr() | CR_C);
 +   enable_coherency();
 +}
 +
   static const struct mcpm_platform_ops exynos_power_ops = {
 .power_up   = exynos_power_up,
 .power_down = exynos_power_down,
 .power_down_finish  = exynos_power_down_finish,
 +   .suspend= exynos_suspend,
 +   .powered_up = exynos_powered_up,
   };

   static void __init exynos_mcpm_usage_count_init(void)



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[Patch v2 1/4] cpuidle: config: Add SOC_EXYNOS5420 entry to select cpuidle-big-little driver

2014-04-23 Thread Chander Kashyap
Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
In order to use generic cpuidle-big-little driver, this patch adds Exynos5420
specific check to initialize generic cpuidle driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to SOC_EXYNOS5420
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[Patch v2 0/4] add cpuidle support for Exynos5420

2014-04-23 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg321666.html

2. [PATCH v4] arm: exynos: generalize power register address calculation
   http://www.spinics.net/lists/arm-kernel/msg324024.html

Changelog is in respective patches.
Chander Kashyap (4):
  cpuidle: config: Add SOC_EXYNOS5420 entry to select
cpuidle-big-little driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 ++
 arch/arm/mach-exynos/mcpm-exynos.c   |   53 ++
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |3 +-
 4 files changed, 59 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH v5] arm: exynos: generalize power register address calculation

2014-04-22 Thread Chander Kashyap
Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
changes in v5:
1. Fix typo: enynos_pmu_cpunr - exynos_pmu_cpunr
changes in v4:
1: Dropped changes in platsmp.c and hotplug.c as those are taken care by
   Tomasz Patches.
2. Converted ENYNOS_PMU_CPUNR macro to static inline function
changes in v3:
1. Move cpunr calculation to a macro
2. Changed printk format specifier from unsigned hex to unsigned decimal
Changes in v2:
1. Used existing macros for clusterid and cpuid calculation

 arch/arm/mach-exynos/regs-pmu.h |   18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..f39e78c 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,8 +105,13 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
+#define S5P_ARM_CORE_STATUS(_cpunr) \
+   (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr))
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
@@ -313,4 +318,13 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION   (1  4)
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[PATCH v4] arm: exynos: generalize power register address calculation

2014-04-21 Thread Chander Kashyap
Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.org
---
changes in v4:
1: Dropped changes in platsmp.c and hotplug.c as those are taken care by
   Tomasz Patches.
2. Converted ENYNOS_PMU_CPUNR macro to static inline function
changes in v3:
1. Move cpunr calculation to a macro
2. Changed printk format specifier from unsigned hex to unsigned decimal
Changes in v2:
1. Used existing macros for clusterid and cpuid calculation

 arch/arm/mach-exynos/regs-pmu.h |   18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..f39e78c 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,8 +105,13 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
+#define S5P_ARM_CORE_STATUS(_cpunr) \
+   (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr))
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
@@ -313,4 +318,13 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION   (1  4)
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int enynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[PATCH 2/4] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-04-21 Thread Chander Kashyap
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.org
---
 drivers/cpuidle/cpuidle-big_little.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..d0fac53 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -170,7 +170,8 @@ static int __init bl_idle_init(void)
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7) 
+   (!of_machine_is_compatible(samsung,exynos5420)))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[PATCH 0/4] add cpuidle support for Exynos5420

2014-04-21 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg321666.html

2. [PATCH v4] arm: exynos: generalize power register address calculation
   http://www.spinics.net/lists/arm-kernel/msg324024.html

Chander Kashyap (4):
  cpuidle: config: Add SOC_EXYNOS5420 entry to select
cpuidle-big-little driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 ++
 arch/arm/mach-exynos/mcpm-exynos.c   |   53 ++
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |3 +-
 4 files changed, 59 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH 3/4] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-04-21 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/cpuidle.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index c57cae0..242f75d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -219,6 +219,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;
 
+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();
 
-- 
1.7.9.5

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[PATCH 4/4] mcpm: exynos: populate suspend and powered_up callbacks

2014-04-21 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/mcpm-exynos.c |   53 
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index 46d4968..16af0bd 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -318,10 +318,63 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return 0; /* success: the CPU is halted */
 }
 
+static void enable_coherency(void)
+{
+   unsigned long v, u;
+
+   asm volatile(
+   mrcp15, 0, %0, c1, c0, 1\n
+   orr%0, %0, %2\n
+   ldr%1, [%3]\n
+   and%1, %1, #0\n
+   orr%0, %0, %1\n
+   mcrp15, 0, %0, c1, c0, 1\n
+   : =r (v), =r (u)
+   : Ir (0x40), Ir (S5P_INFORM0)
+   : cc);
+}
+
+void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(bl_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(bl_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   mpidr = read_cpuid_mpidr();
+   cpunr = enynos_pmu_cpunr(mpidr);
+
+   __raw_writel(virt_to_phys(mcpm_entry_point), REG_ENTRY_ADDR);
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+   */
+   __raw_writel(EXYNOS_CORE_LOCAL_PWR_EN,
+   EXYNOS_ARM_CORE_CONFIGURATION(cpunr));
+   set_cr(get_cr() | CR_C);
+   enable_coherency();
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[PATCH 1/4] cpuidle: config: Add SOC_EXYNOS5420 entry to select cpuidle-big-little driver

2014-04-21 Thread Chander Kashyap
Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
In order to use generic cpuidle-big-little driver, this patch adds Exynos5420
specific check to initialize generic cpuidle driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..5244d87 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || SOC_EXYNOS5420
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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Re: [PATCH] arm: exynos: generalize power register address calculation

2014-04-20 Thread Chander Kashyap
Hi Tomasz,

On 18 April 2014 19:42, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander,


 On 15.04.2014 09:38, Chander Kashyap wrote:

 Currently status/configuration power register values are hard-coded for
 cpu1.

 Make it generic so that it is useful for SoC's with more than two cpus.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 ---
 changes in v3:
 1. Move cpunr calculation to a macro
 2. Changed printk format specifier from unsigned hex to unsigned
 decimal
 Changes in v2:
 1. Used existing macros for clusterid and cpuid calculation

   arch/arm/mach-exynos/hotplug.c  |7 ---
   arch/arm/mach-exynos/platsmp.c  |   13 +++--
   arch/arm/mach-exynos/regs-pmu.h |   15 +--
   3 files changed, 24 insertions(+), 11 deletions(-)


 Now as I think of it, the code that is touched by this patch is not supposed
 to be used on multi-cluster systems. Instead a separate MCPM driver should.
 As far as I know, somebody is said to be already working on this.

 This means that we don't need to consider multi-cluster support in this
 patch and simplify any calculations to just account for core ID. This would
 also eliminate any need to handle non-zero cluster ID on single-cluster
 SoCs.

 Please correct me if I'm wrong.

Yes thats true.
As mcpm code is in review process, so i will remove platsmp.c and
hotplug.c changes and respin the patch.
The  patch will add support for cpunr calculation and offset calculation.



 diff --git a/arch/arm/mach-exynos/hotplug.c
 b/arch/arm/mach-exynos/hotplug.c
 index 5eead53..9f74be2 100644
 --- a/arch/arm/mach-exynos/hotplug.c
 +++ b/arch/arm/mach-exynos/hotplug.c
 @@ -92,11 +92,12 @@ static inline void cpu_leave_lowpower(void)

   static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
   {
 +   unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu));
 for (;;) {

 -   /* make cpu1 to be turned off at next WFI command */
 -   if (cpu == 1)
 -   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
 +   /* make cpu to be turned off at next WFI command */
 +   if (cpu)


 As I mentioned in my previous reply, I don't see what could go wrong if this
 check is omitted. What happens if CPU0 is being hot-unplugged?

 If hardware doesn't support this (but I don't see any mention about this in
 the documentation), such hotplug attempt should either simply fail on
 .cpu_kill() operation for CPU0 or even have CPU0 marked as non-hotpluggable.

That makes more sense, but i need to cross verify.



 +   __raw_writel(0,
 S5P_ARM_CORE_CONFIGURATION(cpunr));

 /*
  * here's the WFI
 diff --git a/arch/arm/mach-exynos/platsmp.c
 b/arch/arm/mach-exynos/platsmp.c
 index 03e5e9f..d9c182f 100644
 --- a/arch/arm/mach-exynos/platsmp.c
 +++ b/arch/arm/mach-exynos/platsmp.c
 @@ -90,7 +90,7 @@ static int exynos_boot_secondary(unsigned int cpu,
 struct task_struct *idle)
   {
 unsigned long timeout;
 unsigned long phys_cpu = cpu_logical_map(cpu);
 -
 +   unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu));
 /*
  * Set synchronisation state between this boot processor
  * and the secondary one
 @@ -107,14 +107,15 @@ static int exynos_boot_secondary(unsigned int cpu,
 struct task_struct *idle)
  */
 write_pen_release(phys_cpu);

 -   if (!(__raw_readl(S5P_ARM_CORE1_STATUS)  S5P_CORE_LOCAL_PWR_EN))
 {
 +   if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
 +S5P_CORE_LOCAL_PWR_EN)) {
 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
 -S5P_ARM_CORE1_CONFIGURATION);
 +S5P_ARM_CORE_CONFIGURATION(cpunr));

 timeout = 10;

 -   /* wait max 10 ms until cpu1 is on */
 -   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
 +   /* wait max 10 ms until secondary cpu is on */
 +   while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
  S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN)
 {
 if (timeout-- == 0)
 break;
 @@ -123,7 +124,7 @@ static int exynos_boot_secondary(unsigned int cpu,
 struct task_struct *idle)
 }

 if (timeout == 0) {
 -   printk(KERN_ERR cpu1 power enable failed);
 +   pr_err(cpu%u power enable failed, cpu);
 spin_unlock(boot_lock);
 return -ETIMEDOUT;
 }
 diff --git a/arch/arm/mach-exynos/regs-pmu.h
 b/arch/arm/mach-exynos/regs-pmu.h
 index 4f6a256..0de6df4 100644
 --- a/arch/arm/mach-exynos/regs-pmu.h
 +++ b/arch/arm/mach-exynos/regs-pmu.h
 @@ -105,8 +105,13 @@
   #define S5P_GPS_LOWPWRS5P_PMUREG(0x139C)
   #define S5P_GPS_ALIVE_LOWPWR

Re: [PATCH 2/4] ARM: EXYNOS: Fix core ID used by platsmp and hotplug code

2014-04-20 Thread Chander Kashyap
 = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 boot_addr = virt_to_phys(exynos4_secondary_startup);

 -   if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
 -   __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
 +   if (call_firmware_op(set_cpu_boot_addr, core_id, boot_addr))
 +   __raw_writel(boot_addr, cpu_boot_reg(core_id));
 }
  }

 --
 1.9.2

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Chander Kashyap
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[PATCH] arm: exynos: generalize power register address calculation

2014-04-15 Thread Chander Kashyap
Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
changes in v3:
1. Move cpunr calculation to a macro
2. Changed printk format specifier from unsigned hex to unsigned decimal
Changes in v2:
1. Used existing macros for clusterid and cpuid calculation

 arch/arm/mach-exynos/hotplug.c  |7 ---
 arch/arm/mach-exynos/platsmp.c  |   13 +++--
 arch/arm/mach-exynos/regs-pmu.h |   15 +--
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9f74be2 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -92,11 +92,12 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+   unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu));
for (;;) {
 
-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   /* make cpu to be turned off at next WFI command */
+   if (cpu)
+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr));
 
/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..d9c182f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -90,7 +90,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
-
+   unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu));
/*
 * Set synchronisation state between this boot processor
 * and the secondary one
@@ -107,14 +107,15 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS)  S5P_CORE_LOCAL_PWR_EN)) {
+   if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
+S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
+S5P_ARM_CORE_CONFIGURATION(cpunr));
 
timeout = 10;
 
-   /* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+   /* wait max 10 ms until secondary cpu is on */
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
 S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -123,7 +124,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
}
 
if (timeout == 0) {
-   printk(KERN_ERR cpu1 power enable failed);
+   pr_err(cpu%u power enable failed, cpu);
spin_unlock(boot_lock);
return -ETIMEDOUT;
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..0de6df4 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,8 +105,13 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
+#define S5P_ARM_CORE_STATUS(_cpunr)\
+   (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr))
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
@@ -313,4 +318,10 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION   (1  4)
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+#define ENYNOS_PMU_CPUNR(mpidr) \
+   ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) \
+ + MPIDR_AFFINITY_LEVEL(mpidr, 0));
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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Re: [PATCH] arm: exynos: generalize power register address calculation

2014-04-13 Thread Chander Kashyap
Hi,

On 10 April 2014 11:18, Chander Kashyap chander.kash...@linaro.org wrote:
 Hi Tomasz,

 On 9 April 2014 20:15, Tomasz Figa t.f...@samsung.com wrote:
 On 09.04.2014 15:49, Chander Kashyap wrote:

 Hi Tomasz,

 On 9 April 2014 17:19, Tomasz Figa t.f...@samsung.com wrote:

 Hi Chander,


 On 09.04.2014 13:09, Chander Kashyap wrote:


 Currently status/configuration power register values are hard-coded for
 cpu1.

 Make it generic so that it is useful for SoC's with more than two cpus.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 ---
 changes in v2 : Used existing macros for clusterid and cpuid calculation

arch/arm/mach-exynos/hotplug.c  |   15 ---
arch/arm/mach-exynos/platsmp.c  |   20 +++-
arch/arm/mach-exynos/regs-pmu.h |9 +++--
3 files changed, 34 insertions(+), 10 deletions(-)

 diff --git a/arch/arm/mach-exynos/hotplug.c
 b/arch/arm/mach-exynos/hotplug.c
 index 5eead53..eab6121 100644
 --- a/arch/arm/mach-exynos/hotplug.c
 +++ b/arch/arm/mach-exynos/hotplug.c
 @@ -17,6 +17,7 @@

#include asm/cacheflush.h
#include asm/cp15.h
 +#include asm/cputype.h
#include asm/smp_plat.h

#include plat/cpu.h
 @@ -92,11 +93,19 @@ static inline void cpu_leave_lowpower(void)

static inline void platform_do_lowpower(unsigned int cpu, int
 *spurious)
{
 +   unsigned int mpidr, cpunr, cluster;
 +
 +   mpidr = cpu_logical_map(cpu);
 +   cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 +   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 +
 +   /* Maximum possible cpus in a cluster can be 4 */
 +   cpunr += cluster * 4;



 I believe this is rather a weak assumption. First of all, the limit seems
 to
 be hardcoded only for the few existing SoCs. In addition, the value is
 not
 used as a maximum, but rather it is assumed that each cluster has always
 four cores.


 The MPIDR register contains 2 bits for cpu id. Hence maximum number of
 cpus can be 4 only (A15/A9/A7).


 This is not what I meant. Exynos5260 contains 2 big cores (not 4) and 4
 little cores. Are you sure that PMU register layout on Exynos5260 matches
 your equation?


 Yes the equation covers that as the PMU register layout takes care for that:
 Address offset are as follows:
 2 Big Cores:
 cpu0 : 2000
 cpu1: 2080

 4 Little cores:

 cpu0: 2200
 cpu1: 2280
 cpu2: 2300
 cpu3: 2380



 Moreover, it is assumed here that the mapping between core ID (calculated
 by
 the equation below) and PMU core numbers is 1:1, which is not true. On
 Exynos4210, the cluster ID is always 0x09 and on Exynos4x12 it is 0x0a,
 which will lead to completely wrong register offsets.


 Exynos4210 and Exynos4x12, cluster ids are not passed from DT as it
 breaks the gic_init_bases. Hence the Physical CpuID for Exynos4210
 will be 0,1 and Exynos4x12 will be 0,1,2,3.

 So it will not break.


 I already have patches ready fixing GIC driver, just waiting for 3.15-rc1 to
 be released. Anyway, CPU topology in DT is mandatory and Exynos4 device tree
 files need to be fixed to contain them. This needs to be accounted for in
 any changes touching CPU topology related code.


 That's great.





 I believe the proper way to deal with this is to provide per-CPU property
 in
 DT called samsung,pmu-offset that could be used be code like this to
 calculate register addresses properly.

 For now, I would recommend doing the above ignoring cluster ID completely
 to
 not break (and actually fix) single cluster systems and existing multi
 cluster ones on which only the first cluster is supported now.

 After that, per-CPU PMU offset should be implemented to support
 multi-cluster SoCs with proper support of multiple clusters.


 As of now the smp-boot (cores  2) is broken. This is required to fix it.


 SMP boot works fine on all four cores of Exynos 4412. Obiously hot-(un)plug
 doesn't, but this is another issue.


 It works as of now as at power on all the cores powered on. Hence the
 powerOn in platsmp.c doent make any difference,  It breaks in hotplug
 as we always poweron cpu1, not the correct cpu.

 Best regards,
 Tomasz



 --
 with warm regards,
 Chander Kashyap

Any other comments on this patch. If not then can it be merged?

-- 
with warm regards,
Chander Kashyap
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[PATCH] arm: exynos: generalize power register address calculation

2014-04-09 Thread Chander Kashyap
Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
changes in v2 : Used existing macros for clusterid and cpuid calculation

 arch/arm/mach-exynos/hotplug.c  |   15 ---
 arch/arm/mach-exynos/platsmp.c  |   20 +++-
 arch/arm/mach-exynos/regs-pmu.h |9 +++--
 3 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..eab6121 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -17,6 +17,7 @@
 
 #include asm/cacheflush.h
 #include asm/cp15.h
+#include asm/cputype.h
 #include asm/smp_plat.h
 
 #include plat/cpu.h
@@ -92,11 +93,19 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+   unsigned int mpidr, cpunr, cluster;
+
+   mpidr = cpu_logical_map(cpu);
+   cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   /* Maximum possible cpus in a cluster can be 4 */
+   cpunr += cluster * 4;
for (;;) {
 
-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   /* make cpu to be turned off at next WFI command */
+   if (cpu)
+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr));
 
/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..8d06b2c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -22,6 +22,7 @@
 #include linux/io.h
 
 #include asm/cacheflush.h
+#include asm/cputype.h
 #include asm/smp_plat.h
 #include asm/smp_scu.h
 #include asm/firmware.h
@@ -92,6 +93,14 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+   unsigned int mpidr, cpunr, cluster;
+
+   mpidr = cpu_logical_map(cpu);
+   cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   /* Maximum possible cpus in a cluster can be 4 */
+   cpunr += cluster * 4;
 
/*
 * Set synchronisation state between this boot processor
@@ -109,14 +118,15 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS)  S5P_CORE_LOCAL_PWR_EN)) {
+   if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
+S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
+S5P_ARM_CORE_CONFIGURATION(cpunr));
 
timeout = 10;
 
-   /* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+   /* wait max 10 ms until secondary cpu is on */
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
 S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -125,7 +135,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
}
 
if (timeout == 0) {
-   printk(KERN_ERR cpu1 power enable failed);
+   pr_err(cpu%x power enable failed, cpu);
spin_unlock(boot_lock);
return -ETIMEDOUT;
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce..16e17e4 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -104,8 +104,13 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * _cpunr)
+#define S5P_ARM_CORE_STATUS(_cpunr)\
+   (S5P_ARM_CORE0_STATUS + 0x80 * _cpunr)
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
-- 
1.7.9.5

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Re: [PATCH] arm: exynos: generalize power register address calculation

2014-04-09 Thread Chander Kashyap
Hi Tomasz,

On 9 April 2014 17:19, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander,


 On 09.04.2014 13:09, Chander Kashyap wrote:

 Currently status/configuration power register values are hard-coded for
 cpu1.

 Make it generic so that it is useful for SoC's with more than two cpus.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 ---
 changes in v2 : Used existing macros for clusterid and cpuid calculation

   arch/arm/mach-exynos/hotplug.c  |   15 ---
   arch/arm/mach-exynos/platsmp.c  |   20 +++-
   arch/arm/mach-exynos/regs-pmu.h |9 +++--
   3 files changed, 34 insertions(+), 10 deletions(-)

 diff --git a/arch/arm/mach-exynos/hotplug.c
 b/arch/arm/mach-exynos/hotplug.c
 index 5eead53..eab6121 100644
 --- a/arch/arm/mach-exynos/hotplug.c
 +++ b/arch/arm/mach-exynos/hotplug.c
 @@ -17,6 +17,7 @@

   #include asm/cacheflush.h
   #include asm/cp15.h
 +#include asm/cputype.h
   #include asm/smp_plat.h

   #include plat/cpu.h
 @@ -92,11 +93,19 @@ static inline void cpu_leave_lowpower(void)

   static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
   {
 +   unsigned int mpidr, cpunr, cluster;
 +
 +   mpidr = cpu_logical_map(cpu);
 +   cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 +   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 +
 +   /* Maximum possible cpus in a cluster can be 4 */
 +   cpunr += cluster * 4;


 I believe this is rather a weak assumption. First of all, the limit seems to
 be hardcoded only for the few existing SoCs. In addition, the value is not
 used as a maximum, but rather it is assumed that each cluster has always
 four cores.

The MPIDR register contains 2 bits for cpu id. Hence maximum number of
cpus can be 4 only (A15/A9/A7).


 Moreover, it is assumed here that the mapping between core ID (calculated by
 the equation below) and PMU core numbers is 1:1, which is not true. On
 Exynos4210, the cluster ID is always 0x09 and on Exynos4x12 it is 0x0a,
 which will lead to completely wrong register offsets.

Exynos4210 and Exynos4x12, cluster ids are not passed from DT as it
breaks the gic_init_bases. Hence the Physical CpuID for Exynos4210
will be 0,1 and Exynos4x12 will be 0,1,2,3.

So it will not break.



 I believe the proper way to deal with this is to provide per-CPU property in
 DT called samsung,pmu-offset that could be used be code like this to
 calculate register addresses properly.

 For now, I would recommend doing the above ignoring cluster ID completely to
 not break (and actually fix) single cluster systems and existing multi
 cluster ones on which only the first cluster is supported now.

 After that, per-CPU PMU offset should be implemented to support
 multi-cluster SoCs with proper support of multiple clusters.

As of now the smp-boot (cores  2) is broken. This is required to fix it.


 Best regards,
 Tomasz



-- 
with warm regards,
Chander Kashyap
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Re: [PATCH] arm: exynos: generalize power register address calculation

2014-04-09 Thread Chander Kashyap
Hi Tomasz,

On 9 April 2014 20:15, Tomasz Figa t.f...@samsung.com wrote:
 On 09.04.2014 15:49, Chander Kashyap wrote:

 Hi Tomasz,

 On 9 April 2014 17:19, Tomasz Figa t.f...@samsung.com wrote:

 Hi Chander,


 On 09.04.2014 13:09, Chander Kashyap wrote:


 Currently status/configuration power register values are hard-coded for
 cpu1.

 Make it generic so that it is useful for SoC's with more than two cpus.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 ---
 changes in v2 : Used existing macros for clusterid and cpuid calculation

arch/arm/mach-exynos/hotplug.c  |   15 ---
arch/arm/mach-exynos/platsmp.c  |   20 +++-
arch/arm/mach-exynos/regs-pmu.h |9 +++--
3 files changed, 34 insertions(+), 10 deletions(-)

 diff --git a/arch/arm/mach-exynos/hotplug.c
 b/arch/arm/mach-exynos/hotplug.c
 index 5eead53..eab6121 100644
 --- a/arch/arm/mach-exynos/hotplug.c
 +++ b/arch/arm/mach-exynos/hotplug.c
 @@ -17,6 +17,7 @@

#include asm/cacheflush.h
#include asm/cp15.h
 +#include asm/cputype.h
#include asm/smp_plat.h

#include plat/cpu.h
 @@ -92,11 +93,19 @@ static inline void cpu_leave_lowpower(void)

static inline void platform_do_lowpower(unsigned int cpu, int
 *spurious)
{
 +   unsigned int mpidr, cpunr, cluster;
 +
 +   mpidr = cpu_logical_map(cpu);
 +   cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 +   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 +
 +   /* Maximum possible cpus in a cluster can be 4 */
 +   cpunr += cluster * 4;



 I believe this is rather a weak assumption. First of all, the limit seems
 to
 be hardcoded only for the few existing SoCs. In addition, the value is
 not
 used as a maximum, but rather it is assumed that each cluster has always
 four cores.


 The MPIDR register contains 2 bits for cpu id. Hence maximum number of
 cpus can be 4 only (A15/A9/A7).


 This is not what I meant. Exynos5260 contains 2 big cores (not 4) and 4
 little cores. Are you sure that PMU register layout on Exynos5260 matches
 your equation?


Yes the equation covers that as the PMU register layout takes care for that:
Address offset are as follows:
2 Big Cores:
cpu0 : 2000
cpu1: 2080

4 Little cores:

cpu0: 2200
cpu1: 2280
cpu2: 2300
cpu3: 2380



 Moreover, it is assumed here that the mapping between core ID (calculated
 by
 the equation below) and PMU core numbers is 1:1, which is not true. On
 Exynos4210, the cluster ID is always 0x09 and on Exynos4x12 it is 0x0a,
 which will lead to completely wrong register offsets.


 Exynos4210 and Exynos4x12, cluster ids are not passed from DT as it
 breaks the gic_init_bases. Hence the Physical CpuID for Exynos4210
 will be 0,1 and Exynos4x12 will be 0,1,2,3.

 So it will not break.


 I already have patches ready fixing GIC driver, just waiting for 3.15-rc1 to
 be released. Anyway, CPU topology in DT is mandatory and Exynos4 device tree
 files need to be fixed to contain them. This needs to be accounted for in
 any changes touching CPU topology related code.


That's great.





 I believe the proper way to deal with this is to provide per-CPU property
 in
 DT called samsung,pmu-offset that could be used be code like this to
 calculate register addresses properly.

 For now, I would recommend doing the above ignoring cluster ID completely
 to
 not break (and actually fix) single cluster systems and existing multi
 cluster ones on which only the first cluster is supported now.

 After that, per-CPU PMU offset should be implemented to support
 multi-cluster SoCs with proper support of multiple clusters.


 As of now the smp-boot (cores  2) is broken. This is required to fix it.


 SMP boot works fine on all four cores of Exynos 4412. Obiously hot-(un)plug
 doesn't, but this is another issue.


It works as of now as at power on all the cores powered on. Hence the
powerOn in platsmp.c doent make any difference,  It breaks in hotplug
as we always poweron cpu1, not the correct cpu.

 Best regards,
 Tomasz



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Re: AFTR does not work on arndale 5250

2014-04-08 Thread Chander Kashyap
Hi Daniel,

I have tested on v3.14 Stable on arndale board.
I have tested wit cramfs.

Last commit on tree is:

01d5f3b598b18a5035426c30801adf65822dbd0c

Below are the logs from the console.
$ uname -a
Linux (none) 3.14.0-00604-g0c6d388 #28 SMP PREEMPT Tue Apr 8 19:19:09
IST 2014 armv7l unknown

$ mount -t sysfs sys sys
/ $ echo 0  /sys/devices/system/cpu/cpu1/online
[  152.439901] IRQ153 no longer affine to CPU1
[  152.440120] CPU1: shutdown

$ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
39
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
44
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
46
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
51
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
56
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
61
/ $


It is working perfectly fine.

If still issue is there, please feel free to ask.

On 4 April 2014 18:36, Daniel Lezcano daniel.lezc...@linaro.org wrote:

 Hi,

 I tried to make the idle AFTR state working on arndale 5250 but that leads
 to a kernel reboot and crash.

 How to reproduce ?

 echo 0  /sys/devices/system/cpu/cpu1/online

 Reproductible on v3.14 and samsung/for-next

 Any ideas ?

 Thanks

   -- Daniel

 --
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 http://twitter.com/#!/linaroorg Twitter |
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[PATCH] arm: exynos: generalize power register address calculation

2014-04-08 Thread Chander Kashyap
Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
 arch/arm/mach-exynos/hotplug.c  |   10 +++---
 arch/arm/mach-exynos/platsmp.c  |   13 -
 arch/arm/mach-exynos/regs-pmu.h |9 +++--
 3 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..460aec0 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -92,11 +92,15 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+   unsigned long phys_cpu = cpu_logical_map(cpu);
+   unsigned int cpunr;
+
+   cpunr = phys_cpu  0xF00 ? (4 + phys_cpu  0xFF) : phys_cpu  0xFF;
for (;;) {
 
-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   /* make cpu to be turned off at next WFI command */
+   if (cpu)
+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr));
 
/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..e694bdf 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -92,6 +92,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+   unsigned int cpunr;
 
/*
 * Set synchronisation state between this boot processor
@@ -109,14 +110,16 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS)  S5P_CORE_LOCAL_PWR_EN)) {
+   cpunr = phys_cpu  0xF00 ? (4 + phys_cpu  0xFF) : phys_cpu  0xFF;
+   if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
+S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
+S5P_ARM_CORE_CONFIGURATION(cpunr));
 
timeout = 10;
 
-   /* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+   /* wait max 10 ms until secondary cpu is on */
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
 S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -125,7 +128,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
}
 
if (timeout == 0) {
-   printk(KERN_ERR cpu1 power enable failed);
+   pr_err(cpu%x power enable failed, cpu);
spin_unlock(boot_lock);
return -ETIMEDOUT;
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce..16e17e4 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -104,8 +104,13 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * _cpunr)
+#define S5P_ARM_CORE_STATUS(_cpunr)\
+   (S5P_ARM_CORE0_STATUS + 0x80 * _cpunr)
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
-- 
1.7.9.5

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Re: [PATCH v2] clk: exynos5420: fix cpll clock register offsets

2013-12-02 Thread Chander Kashyap
Ping

On 26 November 2013 13:37, Chander Kashyap chander.kash...@linaro.org wrote:
 Hi Mike,

 On 22 October 2013 11:20, Chander Kashyap chander.kash...@linaro.org wrote:
 On 16 October 2013 11:10, Chander Kashyap chander.kash...@linaro.org wrote:
 On 26 September 2013 14:36, Chander Kashyap chander.kash...@linaro.org 
 wrote:
 Fixes cpll control and lock register offset values for Exynos5420 SoC.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Acked-by: Kukjin Kim kgene@samsung.com
 ---
 Changes Since v1:
 - Fixed patch subject as per Kukgin suggestion.

  drivers/clk/samsung/clk-exynos5420.c |4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos5420.c 
 b/drivers/clk/samsung/clk-exynos5420.c
 index 86dfc64..892aac0 100644
 --- a/drivers/clk/samsung/clk-exynos5420.c
 +++ b/drivers/clk/samsung/clk-exynos5420.c
 @@ -730,8 +730,8 @@ struct samsung_gate_clock exynos5420_gate_clks[] 
 __initdata = {
  struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
 [apll] = PLL(pll_2550, fout_apll, fout_apll, fin_pll, 
 APLL_LOCK,
 APLL_CON0, NULL),
 -   [cpll] = PLL(pll_2550, fout_mpll, fout_mpll, fin_pll, 
 MPLL_LOCK,
 -   MPLL_CON0, NULL),
 +   [cpll] = PLL(pll_2550, fout_cpll, fout_cpll, fin_pll, 
 CPLL_LOCK,
 +   CPLL_CON0, NULL),
 [dpll] = PLL(pll_2550, fout_dpll, fout_dpll, fin_pll, 
 DPLL_LOCK,
 DPLL_CON0, NULL),
 [epll] = PLL(pll_2650, fout_epll, fout_epll, fin_pll, 
 EPLL_LOCK,
 --
 1.7.9.5



 Mike, can you please take this patch.

 Can this patch be merged?

 Any update on this patch ?



 --
 with warm regards,
 Chander Kashyap



 --
 with warm regards,
 Chander Kashyap



 --
 with warm regards,
 Chander Kashyap



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Re: [Patch v4 0/2] Enable all cpus in Exynos5420

2013-12-02 Thread Chander Kashyap
Hi Kukjin,

On 25 November 2013 12:08, Chander Kashyap chander.kash...@linaro.org wrote:
 Hi Kukjin,

 On 12 November 2013 17:12, Kukjin Kim kg...@kernel.org wrote:
 Chander Kashyap wrote:

 Hi Kukjin,

 On 7 October 2013 09:47, Chander Kashyap chander.kash...@linaro.org
 wrote:
  Exynos5420 is an octa-core SoC. This patch series enables the remaining
 4 cores.
 
  Changes in v2:
  - Changed the cpu node @unit-address value to reg property
 value.
  Changes in v3:
  - Removed leading 0x from @unit-address value.
  Changes in v4:
  - Fixed typo and patch subject from arm: dt to ARM: dt.
 
  Chander Kashyap (2):
clocksource: mct: extend mct to support 8 local interrupts for
  Exynos5420
arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
 
   arch/arm/boot/dts/exynos5420.dtsi |   37
 +++--
   drivers/clocksource/exynos_mct.c  |4 
   2 files changed, 39 insertions(+), 2 deletions(-)
 
  --
  1.7.9.5

 Looks OK to me, applied.

 I cant find these patches in yours tree.

Any update on these patches?



 Thanks,
 Kukjin




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 Chander Kashyap



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Re: [PATCH v2] clk: exynos5420: fix cpll clock register offsets

2013-11-26 Thread Chander Kashyap
Hi Mike,

On 22 October 2013 11:20, Chander Kashyap chander.kash...@linaro.org wrote:
 On 16 October 2013 11:10, Chander Kashyap chander.kash...@linaro.org wrote:
 On 26 September 2013 14:36, Chander Kashyap chander.kash...@linaro.org 
 wrote:
 Fixes cpll control and lock register offset values for Exynos5420 SoC.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Acked-by: Kukjin Kim kgene@samsung.com
 ---
 Changes Since v1:
 - Fixed patch subject as per Kukgin suggestion.

  drivers/clk/samsung/clk-exynos5420.c |4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos5420.c 
 b/drivers/clk/samsung/clk-exynos5420.c
 index 86dfc64..892aac0 100644
 --- a/drivers/clk/samsung/clk-exynos5420.c
 +++ b/drivers/clk/samsung/clk-exynos5420.c
 @@ -730,8 +730,8 @@ struct samsung_gate_clock exynos5420_gate_clks[] 
 __initdata = {
  struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
 [apll] = PLL(pll_2550, fout_apll, fout_apll, fin_pll, APLL_LOCK,
 APLL_CON0, NULL),
 -   [cpll] = PLL(pll_2550, fout_mpll, fout_mpll, fin_pll, MPLL_LOCK,
 -   MPLL_CON0, NULL),
 +   [cpll] = PLL(pll_2550, fout_cpll, fout_cpll, fin_pll, CPLL_LOCK,
 +   CPLL_CON0, NULL),
 [dpll] = PLL(pll_2550, fout_dpll, fout_dpll, fin_pll, DPLL_LOCK,
 DPLL_CON0, NULL),
 [epll] = PLL(pll_2650, fout_epll, fout_epll, fin_pll, EPLL_LOCK,
 --
 1.7.9.5



 Mike, can you please take this patch.

 Can this patch be merged?

Any update on this patch ?



 --
 with warm regards,
 Chander Kashyap



 --
 with warm regards,
 Chander Kashyap



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