Re: [PATCH 1/3] mfd: use to_i2c_client
Hi Geliang, On 2015년 12월 29일 00:00, Geliang Tang wrote: > Use to_i2c_client() instead of open-coding it. > > Signed-off-by: Geliang Tang <geliangt...@163.com> > --- > drivers/mfd/88pm80x.c | 4 ++-- > drivers/mfd/88pm860x-core.c | 4 ++-- > drivers/mfd/max14577.c | 4 ++-- > drivers/mfd/max77686.c | 4 ++-- > drivers/mfd/max77693.c | 4 ++-- > drivers/mfd/max77843.c | 4 ++-- > drivers/mfd/max8925-i2c.c | 4 ++-- > drivers/mfd/max8997.c | 8 > drivers/mfd/max8998.c | 8 > drivers/mfd/sec-core.c | 4 ++-- > 10 files changed, 24 insertions(+), 24 deletions(-) Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com> Thanks, Chanwoo Choi [snip] -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
Hi, On 2015년 12월 15일 12:41, Krzysztof Kozlowski wrote: > On 14.12.2015 15:38, Chanwoo Choi wrote: >> This patch adds the generic exynos bus frequency driver for AMBA AXI bus >> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC >> have the common architecture for bus between DRAM and sub-blocks in SoC. >> This driver can support the generic bus frequency driver for Exynos SoCs. >> >> In devicetree, Each bus block has a bus clock, regulator, operation-point >> and devfreq-event devices which measure the utilization of each bus block. >> >> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >> [linux.amoon: Tested on Odroid U3] >> Tested-by: Anand Moon <linux.am...@gmail.com> >> --- >> drivers/devfreq/Kconfig | 15 ++ >> drivers/devfreq/Makefile| 1 + >> drivers/devfreq/exynos/Makefile | 1 + >> drivers/devfreq/exynos/exynos-bus.c | 449 >> >> 4 files changed, 466 insertions(+) >> create mode 100644 drivers/devfreq/exynos/exynos-bus.c >> >> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig >> index 64281bb2f650..55ec774f794c 100644 >> --- a/drivers/devfreq/Kconfig >> +++ b/drivers/devfreq/Kconfig >> @@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE >> >> comment "DEVFREQ Drivers" >> >> +config ARM_EXYNOS_BUS_DEVFREQ >> +bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver" >> +depends on ARCH_EXYNOS >> +select DEVFREQ_GOV_SIMPLE_ONDEMAND >> +select DEVFREQ_EVENT_EXYNOS_PPMU >> +select PM_DEVFREQ_EVENT >> +select PM_OPP >> +help >> + This adds the common DEVFREQ driver for Exynos Memory bus. Exynos >> + Memory bus has one more group of memory bus (e.g, MIF and INT block). >> + Each memory bus group could contain many memoby bus block. It reads >> + PPMU counters of memory controllers by using DEVFREQ-event device >> + and adjusts the operating frequencies and voltages with OPP support. >> + This does not yet operate with optimal voltages. >> + >> config ARM_EXYNOS4_BUS_DEVFREQ >> bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver" >> depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && >> !ARCH_MULTIPLATFORM >> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile >> index 5134f9ee983d..375ebbb4fcfb 100644 >> --- a/drivers/devfreq/Makefile >> +++ b/drivers/devfreq/Makefile >> @@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o >> obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o >> >> # DEVFREQ Drivers >> +obj-$(CONFIG_ARCH_EXYNOS) += exynos/ > > Why limiting it to ARCH_EXYNOS? Are there real dependencies on exynos > mach code? Or on ARM code? There is no dependency. > > If not, then this probably should be obj-y to allow compile testing. > Particular objects would be selected by ARM_EXYNOS_BUS_DEVFREQ. OK. I'll alter it as obj-y. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
On 2015년 12월 18일 09:34, Chanwoo Choi wrote: > Hi, > > On 2015년 12월 15일 12:41, Krzysztof Kozlowski wrote: >> On 14.12.2015 15:38, Chanwoo Choi wrote: >>> This patch adds the generic exynos bus frequency driver for AMBA AXI bus >>> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC >>> have the common architecture for bus between DRAM and sub-blocks in SoC. >>> This driver can support the generic bus frequency driver for Exynos SoCs. >>> >>> In devicetree, Each bus block has a bus clock, regulator, operation-point >>> and devfreq-event devices which measure the utilization of each bus block. >>> >>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >>> [linux.amoon: Tested on Odroid U3] >>> Tested-by: Anand Moon <linux.am...@gmail.com> >>> --- >>> drivers/devfreq/Kconfig | 15 ++ >>> drivers/devfreq/Makefile| 1 + >>> drivers/devfreq/exynos/Makefile | 1 + >>> drivers/devfreq/exynos/exynos-bus.c | 449 >>> >>> 4 files changed, 466 insertions(+) >>> create mode 100644 drivers/devfreq/exynos/exynos-bus.c >>> >>> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig >>> index 64281bb2f650..55ec774f794c 100644 >>> --- a/drivers/devfreq/Kconfig >>> +++ b/drivers/devfreq/Kconfig >>> @@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE >>> >>> comment "DEVFREQ Drivers" >>> >>> +config ARM_EXYNOS_BUS_DEVFREQ >>> + bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver" >>> + depends on ARCH_EXYNOS >>> + select DEVFREQ_GOV_SIMPLE_ONDEMAND >>> + select DEVFREQ_EVENT_EXYNOS_PPMU >>> + select PM_DEVFREQ_EVENT >>> + select PM_OPP >>> + help >>> + This adds the common DEVFREQ driver for Exynos Memory bus. Exynos >>> + Memory bus has one more group of memory bus (e.g, MIF and INT block). >>> + Each memory bus group could contain many memoby bus block. It reads >>> + PPMU counters of memory controllers by using DEVFREQ-event device >>> + and adjusts the operating frequencies and voltages with OPP support. >>> + This does not yet operate with optimal voltages. >>> + >>> config ARM_EXYNOS4_BUS_DEVFREQ >>> bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver" >>> depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && >>> !ARCH_MULTIPLATFORM >>> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile >>> index 5134f9ee983d..375ebbb4fcfb 100644 >>> --- a/drivers/devfreq/Makefile >>> +++ b/drivers/devfreq/Makefile >>> @@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o >>> obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o >>> >>> # DEVFREQ Drivers >>> +obj-$(CONFIG_ARCH_EXYNOS) += exynos/ >> >> Why limiting it to ARCH_EXYNOS? Are there real dependencies on exynos >> mach code? Or on ARM code? > > There is no dependency. > >> >> If not, then this probably should be obj-y to allow compile testing. >> Particular objects would be selected by ARM_EXYNOS_BUS_DEVFREQ. > > OK. I'll alter it as obj-y. As you commented, CONFIG_ARM_EXYNOS_BUS_DEVFREQ is more appropriate without exynos/ directory as following: +obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 05/20] PM / devfreq: Add new passive governor
On 2015년 12월 14일 18:04, MyungJoo Ham wrote:
>>
>> This patch adds the new passive governor for DEVFREQ framework. The
>> following
>> governors are already present and used for DVFS (Dynamic Voltage and
>> Frequency
>> Scaling) drivers. The following governors are independently used for one
>> device
>> driver which don't give the influence to other device drviers and also don't
>> receive the effect from other device drivers.
>> - ondemand / performance / powersave / userspace
>>
>> The passive governor depends on operation of parent driver with specific
>> governos extremely and is not able to decide the new frequency by oneself.
>> According to the decided new frequency of parent driver with governor,
>> the passive governor uses it to decide the appropriate frequency for own
>> device driver. The passive governor must need the following information
>> from device tree:
>> - the source clock and OPP tables
>> - the instance of parent device
>>
>> For exameple,
>> there are one more devfreq device drivers which need to change their source
>> clock according to their utilization on runtime. But, they share the same
>> power line (e.g., regulator). So, specific device driver is operated as
>> parent
>> with ondemand governor and then the rest device driver with passive governor
>> is influenced by parent device.
>>
>> Suggested-by: Myungjoo Ham <myungjoo@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> [linux.amoon: Tested on Odroid U3]
>> Tested-by: Anand Moon <linux.am...@gmail.com>
>> ---
>> drivers/devfreq/Kconfig| 9
>> drivers/devfreq/Makefile | 1 +
>> drivers/devfreq/devfreq.c | 47
>> drivers/devfreq/governor_passive.c | 108
>> +
>> include/linux/devfreq.h| 15 ++
>> 5 files changed, 180 insertions(+)
>> create mode 100644 drivers/devfreq/governor_passive.c
>>
>> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
>> index 55ec774f794c..d03f635a93e1 100644
>> --- a/drivers/devfreq/Kconfig
>> +++ b/drivers/devfreq/Kconfig
>> @@ -64,6 +64,15 @@ config DEVFREQ_GOV_USERSPACE
>>Otherwise, the governor does not change the frequnecy
>>given at the initialization.
>>
>> +config DEVFREQ_GOV_PASSIVE
>> +tristate "Passive"
>> +help
>> + Sets the frequency by other governors (simple_ondemand, performance,
>> + powersave, usersapce) of a parent devfreq device. This governor
>> + always has the dependency on the chosen frequency from paired
>> + governor. This governor does not change the frequency by oneself
>> + through sysfs entry.
>
> Sets the frequency based on the frequency of its parent devfreq
> device. This governor does not change the frequency by itself
> through sysfs entries.
OK. I'll modify it.
>
>> +
>> comment "DEVFREQ Drivers"
>>
>> config ARM_EXYNOS_BUS_DEVFREQ
>> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
>> index 375ebbb4fcfb..f81c313b4b79 100644
>> --- a/drivers/devfreq/Makefile
>> +++ b/drivers/devfreq/Makefile
> []
>> diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
>> index 984c5e9e7bdd..15e58779e4c0 100644
>> --- a/drivers/devfreq/devfreq.c
>> +++ b/drivers/devfreq/devfreq.c
>> @@ -190,6 +190,31 @@ static struct devfreq_governor
>> *find_devfreq_governor(const char *name)
>>
>> /* Load monitoring helper functions for governors use */
>>
>> +static int update_devfreq_passive(struct devfreq *devfreq, unsigned long
>> freq)
>> +{
>> +struct devfreq *passive;
>> +unsigned long rate;
>> +int ret;
>> +
>> +list_for_each_entry(passive, >passive_dev_list, passive_node) {
>> +if (!passive->governor)
>> +continue;
>> +rate = freq;
>> +
>> +ret = passive->governor->get_target_freq(passive, );
>> +if (ret)
>> +return ret;
>> +
>> +ret = passive->profile->target(passive->dev.parent, , 0);
>> +if (ret)
>> +return ret;
>> +
>> +passive->previous_freq = rate;
>> +}
>> +
>> +return 0;
>> +}
>> +
>> /**
>> * update_devfreq() - Reevaluate the device and configure frequency
Re: [PATCH v4 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
On 2015년 12월 14일 17:28, MyungJoo Ham wrote:
>>
>> This patch adds the generic exynos bus frequency driver for AMBA AXI bus
>> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
>> have the common architecture for bus between DRAM and sub-blocks in SoC.
>> This driver can support the generic bus frequency driver for Exynos SoCs.
>>
>> In devicetree, Each bus block has a bus clock, regulator, operation-point
>> and devfreq-event devices which measure the utilization of each bus block.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> [linux.amoon: Tested on Odroid U3]
>> Tested-by: Anand Moon <linux.am...@gmail.com>
>>
>
> Chanwoo, could you please show me testing this set of patches in your site?
> Please let me know when is ok to visit you.
> (I do not have exynos machines right now.)
>
>> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
>> index 5134f9ee983d..375ebbb4fcfb 100644
>> --- a/drivers/devfreq/Makefile
>> +++ b/drivers/devfreq/Makefile
>> @@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
>> obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
>>
>> # DEVFREQ Drivers
>> +obj-$(CONFIG_ARCH_EXYNOS) += exynos/
>> obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
>> obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
>
> CONFIG_ARCH_EXYNOS is true if
> CONFIG_ARM_EXYNOS4_BUS_DEVFREQ is true
> or
> CONFIG_ARM_EXYNOS5_BUS_DEVFREQ is true
> Thus, the two lines after you've added have become useless. (dead code)
>
> Please delete them.
In this series, patch11 deletes all of both exynos4_bus.c and exynos5_bus.c.
>
> []
>> --- /dev/null
>> +++ b/drivers/devfreq/exynos/exynos-bus.c
> []
>> +static int exynos_bus_target(struct device *dev, unsigned long *freq, u32
>> flags)
>> +{
>> +struct exynos_bus *bus = dev_get_drvdata(dev);
>> +struct dev_pm_opp *new_opp;
>> +unsigned long old_freq, new_freq, old_volt, new_volt;
>> +int ret = 0;
>> +
>> +/* Get new opp-bus instance according to new bus clock */
>> +rcu_read_lock();
>> +new_opp = devfreq_recommended_opp(dev, freq, flags);
>> +if (IS_ERR_OR_NULL(new_opp)) {
>> +dev_err(dev, "failed to get recommed opp instance\n");
>> +rcu_read_unlock();
>> +return PTR_ERR(new_opp);
>> +}
>> +
>> +new_freq = dev_pm_opp_get_freq(new_opp);
>> +new_volt = dev_pm_opp_get_voltage(new_opp);
>> +old_freq = dev_pm_opp_get_freq(bus->curr_opp);
>> +old_volt = dev_pm_opp_get_voltage(bus->curr_opp);
>> +rcu_read_unlock();
>> +
>> +if (old_freq == new_freq)
>> +return 0;
>> +
>> +/* Change voltage and frequency according to new OPP level */
>> +mutex_lock(>lock);
>> +
>> +if (old_freq < new_freq) {
>> +ret = regulator_set_voltage(bus->regulator, new_volt, new_volt);
>
> Setting the maximum volt same as the minimum volt is not recommended.
> Especially for any DVFS mechanisms, I recommend to set values as:
> min_volt = minimum voltage that does not harm the stability
> max_volt = maximum voltage that does not break the circuit
>
> Please refer to /include/linux/regulator/driver.h
> "@set_voltage" comments.
>
> For the rest of regulator_set_voltage usages, I'd say the same.
OK.
I'll add the 'voltage-tolerance' property as cpufreq-dt.c driver.
The cpufreq-dt.c get the percentage value by using 'voltage-tolerance'
devicetree property.
For example,
if (of_property_read_u32(np, "exynos,voltage-tolerance",
>voltage_tolerance))
bus->voltage_tolerance = DEFAULT_VOLTAGE_TOLERANCE;
tol = new_volt * bus->voltage_tolerance / 100;
regulator_set_voltage_tol(regulator, new_volt, tol);
>
> []
>> +static int exynos_bus_get_dev_status(struct device *dev,
>> + struct devfreq_dev_status *stat)
>> +{
>> +struct exynos_bus *bus = dev_get_drvdata(dev);
>> +struct devfreq_event_data edata;
>> +int ret;
>> +
>> +rcu_read_lock();
>> +stat->current_frequency = dev_pm_opp_get_freq(bus->curr_opp);
>> +rcu_read_unlock();
>> +
>> +ret = exynos_bus_get_event(bus, );
>> +if (ret < 0) {
>> +stat->total_time = stat->busy_time = 0;
>> +goto err;
>> +}
>> +
>> +stat->busy
Re: [PATCH v4 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
On 2015년 12월 14일 17:28, MyungJoo Ham wrote:
>>
>> This patch adds the generic exynos bus frequency driver for AMBA AXI bus
>> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
>> have the common architecture for bus between DRAM and sub-blocks in SoC.
>> This driver can support the generic bus frequency driver for Exynos SoCs.
>>
>> In devicetree, Each bus block has a bus clock, regulator, operation-point
>> and devfreq-event devices which measure the utilization of each bus block.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> [linux.amoon: Tested on Odroid U3]
>> Tested-by: Anand Moon <linux.am...@gmail.com>
>>
>
> Chanwoo, could you please show me testing this set of patches in your site?
> Please let me know when is ok to visit you.
> (I do not have exynos machines right now.)
Sure. I can show it tomorrow whenever you want.
Before visiting to me, just let me know. I'll prepare the demonstartion.
Regards,
Chanwo oChoi
>
>> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
>> index 5134f9ee983d..375ebbb4fcfb 100644
>> --- a/drivers/devfreq/Makefile
>> +++ b/drivers/devfreq/Makefile
>> @@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
>> obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
>>
>> # DEVFREQ Drivers
>> +obj-$(CONFIG_ARCH_EXYNOS) += exynos/
>> obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
>> obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
>
> CONFIG_ARCH_EXYNOS is true if
> CONFIG_ARM_EXYNOS4_BUS_DEVFREQ is true
> or
> CONFIG_ARM_EXYNOS5_BUS_DEVFREQ is true
> Thus, the two lines after you've added have become useless. (dead code)
>
> Please delete them.
>
> []
>> --- /dev/null
>> +++ b/drivers/devfreq/exynos/exynos-bus.c
> []
>> +static int exynos_bus_target(struct device *dev, unsigned long *freq, u32
>> flags)
>> +{
>> +struct exynos_bus *bus = dev_get_drvdata(dev);
>> +struct dev_pm_opp *new_opp;
>> +unsigned long old_freq, new_freq, old_volt, new_volt;
>> +int ret = 0;
>> +
>> +/* Get new opp-bus instance according to new bus clock */
>> +rcu_read_lock();
>> +new_opp = devfreq_recommended_opp(dev, freq, flags);
>> +if (IS_ERR_OR_NULL(new_opp)) {
>> +dev_err(dev, "failed to get recommed opp instance\n");
>> +rcu_read_unlock();
>> +return PTR_ERR(new_opp);
>> +}
>> +
>> +new_freq = dev_pm_opp_get_freq(new_opp);
>> +new_volt = dev_pm_opp_get_voltage(new_opp);
>> +old_freq = dev_pm_opp_get_freq(bus->curr_opp);
>> +old_volt = dev_pm_opp_get_voltage(bus->curr_opp);
>> +rcu_read_unlock();
>> +
>> +if (old_freq == new_freq)
>> +return 0;
>> +
>> +/* Change voltage and frequency according to new OPP level */
>> +mutex_lock(>lock);
>> +
>> +if (old_freq < new_freq) {
>> +ret = regulator_set_voltage(bus->regulator, new_volt, new_volt);
>
> Setting the maximum volt same as the minimum volt is not recommended.
> Especially for any DVFS mechanisms, I recommend to set values as:
> min_volt = minimum voltage that does not harm the stability
> max_volt = maximum voltage that does not break the circuit
>
> Please refer to /include/linux/regulator/driver.h
> "@set_voltage" comments.
>
> For the rest of regulator_set_voltage usages, I'd say the same.
>
> []
>> +static int exynos_bus_get_dev_status(struct device *dev,
>> + struct devfreq_dev_status *stat)
>> +{
>> +struct exynos_bus *bus = dev_get_drvdata(dev);
>> +struct devfreq_event_data edata;
>> +int ret;
>> +
>> +rcu_read_lock();
>> +stat->current_frequency = dev_pm_opp_get_freq(bus->curr_opp);
>> +rcu_read_unlock();
>> +
>> +ret = exynos_bus_get_event(bus, );
>> +if (ret < 0) {
>> +stat->total_time = stat->busy_time = 0;
>> +goto err;
>> +}
>> +
>> +stat->busy_time = (edata.load_count * 100) / bus->ratio;
>> +stat->total_time = edata.total_count;
>> +
>> +dev_dbg(dev, "Usage of devfreq-event : %ld/%ld\n", stat->busy_time,
>> +stat->total_time);
>
> These two values are unsigned long.
>
> []
>> +static int exynos_bus_parse_of(struct device_node *np,
>> +
Re: [PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
On 2015년 12월 14일 17:40, MyungJoo Ham wrote: >> >> This patch adds the documentation for generic exynos bus frequency >> driver. >> >> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >> Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> > > A little changes following: > >> --- >> .../devicetree/bindings/devfreq/exynos-bus.txt | 93 >> ++ >> 1 file changed, 93 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> >> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> new file mode 100644 >> index ..e32daef328da >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> @@ -0,0 +1,93 @@ >> +* Generic Exynos Bus frequency device >> + >> +The Samsung Exynos SoC have many buses for data transfer between DRAM > > +The Samsung Exynos SoC has many buses for data transfer between DRAM > > or > > +The Samsung Exynos SoCs have many buses for data transfer between DRAM > (because you intend to support mulitple Exynos SoCs) > >> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture > > +and sub-blocks in SoC. Most Exynos SoCs share the common architecture > >> +for buses. Generally, the each bus of Exynos SoC includes the source clock > > +for buses. Generally, each bus of Exynos SoC includes a source clock > >> +and power line and then is able to change the clock according to the usage > > +and a power line, which are able to change the clock frequency > >> +of each buses on runtime. When gathering the usage of each buses on runtime, > > +of the bus in runtime. To monitor the usage of each bus in runtime, > >> +the driver uses the PPMU (Platform Performance Monitoring Unit) which > > +the driver uses the PPMU (Platform Performance Monitoring Unit), which > >> +is able to measure the current load of sub-blocks. >> + >> +There are a little different composition among Exynos SoC because each >> Exynos >> +SoC has the different sub-blocks. So, this difference should be specified > > +SoC has different sub-blocks. Therefore, such difference should be specified > >> +in devicetree file instead of each device driver. In result, this driver >> +is able to support the bus frequency for all Exynos SoCs. >> + Okay. I'll modify it. Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 18/20] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
This patch adds the bus device-tree nodes of INT (internal) block
to enable the bus frequency scaling. The following sub-blocks share
the VDD_INT power source:
- LEFTBUS (parent device)
- RIGHTBUS
- PERIL
- LCD0
- FSYS
- MCUISP / ISP
- MFC
The LEFTBUS is parent device with devfreq ondemand governor
and the rest of devices depend on the LEFTBUS device.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos3250-rinato.dts | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 2a1c22598fdc..c29d5533ec1f 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -154,6 +154,47 @@
status = "okay";
};
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_lcd0 {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mcuisp {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_isp {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peril {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
--
1.9.1
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[PATCH v4 19/20] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
This patch expands the voltage range of buck1/3 regulator due to as following:
- MIF (Memory Interface) bus frequency needs the range of '900 - 1050 mV'.
- INT (Internal) bus frequency needs the range of '900 - 1000 mV'.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index cda1ec86dfba..7bd65026761e 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -356,8 +356,8 @@
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
- regulator-min-microvolt = <100>;
- regulator-max-microvolt = <100>;
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <105>;
regulator-always-on;
regulator-boot-on;
};
@@ -372,7 +372,7 @@
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
- regulator-min-microvolt = <100>;
+ regulator-min-microvolt = <90>;
regulator-max-microvolt = <100>;
regulator-always-on;
regulator-boot-on;
--
1.9.1
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[PATCH v4 20/20] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
THis patch adds the bus device tree nodes for both MIF (Memory) and INT
(Internal) block to enable the bus frequency.
The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
bus is parent device in INT block using VDD_INT.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47 +
arch/arm/boot/dts/exynos4412-trats2.dts | 47 +
2 files changed, 94 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 7bd65026761e..cb7e54df6a23 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -109,6 +109,53 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_acp {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_c2c {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_display {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peri {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 92438eb6eec6..9f33c651e37a 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -289,6 +289,53 @@
status = "okay";
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_acp {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_c2c {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_display {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peri {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
--
1.9.1
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[PATCH v4 07/20] PM / devfreq: Show the related information according to governor type
This patch modifies the following sysfs entry of DEVFREQ framework
because the devfreq device using passive governor don't need the same
information of the devfreq device using rest governor.
- polling_interval: passive gov don't use the sampling rate.
- available_governors : passive gov don't be changed on runtime in this version.
- trans_stat : passive governor don't support trans_stat in this
version.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/devfreq.c | 31 +--
drivers/devfreq/governor.h| 7 +++
drivers/devfreq/governor_passive.c| 1 +
drivers/devfreq/governor_performance.c| 1 +
drivers/devfreq/governor_powersave.c | 1 +
drivers/devfreq/governor_simpleondemand.c | 1 +
drivers/devfreq/governor_userspace.c | 1 +
include/linux/devfreq.h | 2 ++
8 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 78ea4cdaa82c..18ad956fec93 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -597,7 +597,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
goto err_init;
}
- if (!strncmp(devfreq->governor_name, "passive", 7)) {
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
struct devfreq *parent_devfreq =
((struct devfreq_passive_data *)data)->parent;
@@ -963,13 +963,23 @@ static ssize_t available_governors_show(struct device *d,
struct device_attribute *attr,
char *buf)
{
- struct devfreq_governor *tmp_governor;
+ struct devfreq *devfreq = to_devfreq(d);
ssize_t count = 0;
mutex_lock(_list_lock);
- list_for_each_entry(tmp_governor, _governor_list, node)
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
count += scnprintf([count], (PAGE_SIZE - count - 2),
- "%s ", tmp_governor->name);
+ "%s ", devfreq->governor->name);
+ } else {
+ struct devfreq_governor *tmp_governor;
+
+ list_for_each_entry(tmp_governor, _governor_list, node)
{
+ if (tmp_governor->type == DEVFREQ_GOV_PASSIVE)
+ continue;
+ count += scnprintf([count], (PAGE_SIZE - count - 2),
+ "%s ", tmp_governor->name);
+ }
+ }
mutex_unlock(_list_lock);
/* Truncate the trailing space */
@@ -1006,6 +1016,11 @@ static DEVICE_ATTR_RO(target_freq);
static ssize_t polling_interval_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
+ struct devfreq *df = to_devfreq(dev);
+
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
return sprintf(buf, "%d\n", to_devfreq(dev)->profile->polling_ms);
}
@@ -1020,6 +1035,9 @@ static ssize_t polling_interval_store(struct device *dev,
if (!df->governor)
return -EINVAL;
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return -EINVAL;
+
ret = sscanf(buf, "%u", );
if (ret != 1)
return -EINVAL;
@@ -1137,11 +1155,12 @@ static ssize_t trans_stat_show(struct device *dev,
int i, j;
unsigned int max_state = devfreq->profile->max_state;
+ if (max_state == 0 || devfreq->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
if (!devfreq->stop_polling &&
devfreq_update_status(devfreq, devfreq->previous_freq))
return 0;
- if (max_state == 0)
- return sprintf(buf, "Not Supported.\n");
len = sprintf(buf, " From : To\n");
len += sprintf(buf + len, " :");
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index fad7d6321978..43513a58f5bf 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -18,6 +18,13 @@
#define to_devfreq(DEV)container_of((DEV), struct devfreq, dev)
+/* Devfreq governor type */
+#define DEVFREQ_GOV_ONDEMAND 0x1
+#define DEVFREQ_GOV_PERFORMANCE0x2
+#define DEVFREQ_GOV_POWERSAVE 0x3
+#define DEVFREQ_GOV_USERSPACE 0x4
+#define DEVFREQ_GOV_PASSIVE0x4
+
/* Devfreq events */
#define DEVFREQ_GOV
[PATCH v4 08/20] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the source clock and
regulator at the same time. So, this patch uses the passive governor to support
the bus frequency for all buses which sharing the one power line.
For example,
Exynos3250 include the two power line for AXI buses as following:
: VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller)
with the power (regulator).
: VDD_INT : INT (Internal) provide the various sub-blocks with the power
(regulator).
Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus
use the power line. So, there is no any depencency between buese. But, in the
case of VDD_INT, various buses share the one power line of VDD_INT. We need to
make the depenency between buses. When using passive governor, there is no
problem to support the bus frequency as DVFS for all buses. One bus should be
operated as the parent bus device which gathering the current load of INT block
and then decides the new frequency with some governors except of passive
governor. After deciding the new frequency by the parent bus device, the rest
bus devices will change the each source clock according to new frequency of the
parent bus device.
- MIF (Memory Interface) block
: VDD_MIF |--- DMC
- INT (Internal) block
: VDD_INT |--- LEFTBUS (parent)
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAM
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/Kconfig | 1 +
drivers/devfreq/exynos/exynos-bus.c | 179
2 files changed, 144 insertions(+), 36 deletions(-)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index d03f635a93e1..88f7cc4539b8 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -79,6 +79,7 @@ config ARM_EXYNOS_BUS_DEVFREQ
bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
depends on ARCH_EXYNOS
select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_GOV_PASSIVE
select DEVFREQ_EVENT_EXYNOS_PPMU
select PM_DEVFREQ_EVENT
select PM_OPP
diff --git a/drivers/devfreq/exynos/exynos-bus.c
b/drivers/devfreq/exynos/exynos-bus.c
index f1bc20839650..d1c137ea22ca 100644
--- a/drivers/devfreq/exynos/exynos-bus.c
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -91,7 +91,7 @@ static int exynos_bus_get_event(struct exynos_bus *bus,
}
/*
- * Must necessary function for devfreq governor
+ * Must necessary function for devfreq simple-ondemand governor
*/
static int exynos_bus_target(struct device *dev, unsigned long *freq, u32
flags)
{
@@ -205,57 +205,74 @@ static void exynos_bus_exit(struct device *dev)
dev_pm_opp_of_remove_table(dev);
}
-static int exynos_bus_parse_of(struct device_node *np,
- struct exynos_bus *bus)
+/*
+ * Must necessary function for devfreq passive governor
+ */
+static int exynos_bus_passive_target(struct device *dev, unsigned long *freq,
+ u32 flags)
{
- struct device *dev = bus->dev;
- unsigned long rate;
- int i, ret, count, size;
+ struct exynos_bus *bus = dev_get_drvdata(dev);
+ struct dev_pm_opp *new_opp;
+ unsigned long old_freq, new_freq;
+ int ret = 0;
- /* Get the clock to provide each bus with source clock */
- bus->clk = devm_clk_get(dev, "bus");
- if (IS_ERR(bus->clk)) {
- dev_err(dev, "failed to get bus clock\n");
- return PTR_ERR(bus->clk);
+ /* Get new opp-bus instance according to new bus clock */
+ rcu_read_lock();
+ new_opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR_OR_NULL(new_opp)) {
+ dev_err(dev, "failed to get recommed opp instance\n");
+ rcu_read_unlock();
+ return PTR_ERR(new_opp);
}
- ret = clk_prepare_enable(bus->clk);
- if (ret < 0) {
- dev_err(dev, "failed to get enable clock\n");
- return ret;
- }
+ new_freq = dev_pm_opp_get_freq(new_opp);
+ old_freq = dev_pm_opp_get_freq(bus->curr_opp);
+ rcu_read_unlock();
- /* Get the freq/voltage OPP table to scale the bus frequency */
- rcu_read_lock();
- ret = dev_pm_opp_of_add_table(dev);
+ if (old_freq == new_freq)
+ return 0;
+
+ /* Change the frequency according to new OPP level */
+ mutex
[PATCH v4 09/20] PM / devfreq: exynos: Update documentation for bus devices using passive governor
This patch updates the documentation for passive bus devices and adds the detailed example of Exynos3250. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- .../devicetree/bindings/devfreq/exynos-bus.txt | 250 - 1 file changed, 247 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index e32daef328da..a251f9120561 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -8,22 +8,46 @@ of each buses on runtime. When gathering the usage of each buses on runtime, the driver uses the PPMU (Platform Performance Monitoring Unit) which is able to measure the current load of sub-blocks. +The Exynos SoC includes the various sub-blocks which have the each AXI bus. +The each AXI bus has the owned source clock but, has not the only owned +power line. The power line might be shared among one more sub-blocks. +So, we can divide into two type of device as the role of each sub-block. +There are two type of bus devices as following: +- parent bus device +- passive bus device + +Basically, parent and passive bus device share the same power line. +The parent bus device can only change the voltage of shared power line +and the rest bus devices (passive bus device) depend on the decision of +the parent bus device. If there are three blocks which share the VDD_xxx +power line, Only one block should be parent device and then the rest blocks +should depend on the parent device as passive device. + + VDD_xxx |--- A block (parent) + |--- B block (passive) + |--- C block (passive) + There are a little different composition among Exynos SoC because each Exynos SoC has the different sub-blocks. So, this difference should be specified in devicetree file instead of each device driver. In result, this driver is able to support the bus frequency for all Exynos SoCs. -Required properties for bus device: +Required properties for all bus devices: - compatible: Should be "samsung,exynos-bus". - clock-names : the name of clock used by the bus, "bus". - clocks : phandles for clock specified in "clock-names" property. - operating-points-v2: the OPP table including frequency/voltage information to support DVFS (Dynamic Voltage/Frequency Scaling) feature. + +Required properties only for parent bus device: - vdd-supply: the regulator to provide the buses with the voltage. - devfreq-events: the devfreq-event device to monitor the current utilization of buses. -Optional properties for bus device: +Required properties only for passive bus device: +- devfreq: the parent bus device. + +Optional properties only for parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count against total cycle count. @@ -32,7 +56,20 @@ Example1: power line (regulator). The MIF (Memory Interface) AXI bus is used to transfer data between DRAM and CPU and uses the VDD_MIF regualtor. - - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block + - MIF (Memory Interface) block + : VDD_MIF |--- DMC (Dynamic Memory Controller) + + - INT (Internal) block + : VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM - MIF bus's frequency/voltage table --- @@ -45,6 +82,24 @@ Example1: |L5| 40 |875000 | --- + - INT bus's frequency/voltage table + -- + |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP|PERIL ||VDD_INT | + | name| |LCD0| | | ||| + | | |FSYS| | | ||| + | | |MFC | | | ||| + -- + |Mode |*parent|passive |passive|passive|passive||| + -- + |Lv |Frequency ||Voltage | + -- + |L1 |5 |5 |5 |5 |5 ||90 | + |L2 |8 |8 |8 |8 |8 ||90 | + |L3 |10 |10 |10 |10 |10 ||100 | + |L4 |134000 |134000 |20 |20 | ||100 | + |L5 |20 |20 |40 |30 | ||100 | + -- + Example2 :
[PATCH v4 10/20] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
This patch adds the detailed corrleation between sub-blocks and power line for Exynos3250, Exynos4210 and Exynos4x12. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- .../devicetree/bindings/devfreq/exynos-bus.txt | 51 ++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index a251f9120561..f3a32b310dc7 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -51,6 +51,57 @@ Optional properties only for parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count against total cycle count. +Detailed correlation between sub-blocks and power line according to Exynos SoC: +- In case of Exynos3250, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- PERIR + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM + +- In case of Exynos4210, there is one power line as following: + VDD_INT |--- DMC (parent device) + |--- LEFTBUS + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- LCD0 + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- LCD1 + +- In case of Exynos4x12, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- IMAGE + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- ISP + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 00/20] PM / devferq: Add generic exynos bus frequency driver and new passive governor
its/ 64 <4>;
opp-microvolt = <875000>;
};
};
- Usage case to handle the frequency and voltage of bus on runtime
in exynos3250-rinato.dts are listed below:
_dmc {
devfreq-events = <_dmc0_3>, <_dmc1_3>;
vdd-supply = <_reg>; /* VDD_MIF */
status = "okay";
};
2. Add new passive governor of DEVFREQ framework (patch5-patch7)
: This patch-set add the new passive governor for DEVFREQ framework.
The existing governors (ondemand, performance and so on) are used for DVFS
(Dynamic Voltage and Frequency Scaling) drivers. The existing governors
are independently used for specific device driver which don't give the
influence to other device drviers and also don't receive the effect from
other device drivers.
The passive governor depends on operation of parent driver with existing
governors(ondemand, performance and so on) extremely and is not able to
decide the new frequency by oneself. According to the decided new frequency
of parent driver with governor, the passive governor uses it to decide
the appropriate frequency for own device driver. The passive governor
must need the following information from device tree:
For exameple,
There are one more bus device drivers in Exynos3250 which need to
change their source clock according to their utilization on runtime.
But, they share the same power line (e.g., regulator). So, LEFTBUS bus
driver is operated as parent with ondemand governor and then the rest
device driver with passive governor.
The buses of Internal block in exynos3250.dtsi are listed below:
When LEFTBUS bus driver (parent) changes the bus frequency with
ondemand governor on runtime, the rest bus devices which sharing
the same power line (VDD_INT) will change the each bus frequency
according to the decision of LEFTBUS bus driver (parent).
- INT (Internal) block
: VDD_INT |--- LEFTBUS
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAM
- The buss of INT block in exynos3250.dtsi are listed below:
bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDL>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
bus_rightbus: bus_rightbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDR>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
(Omit the rest bus dt node)
- Usage case to handle the frequency and voltage of bus on runtime
in exynos3250-rinato.dts are listed below:
/* Parent bus device of VDD_INT */
_leftbus {
devfreq-events = <_leftbus_3>, <_rightbus_3>;
vdd-supply = <_reg>;
status = "okay";
};
/* Passive bus device depend on LEFTBUS bus. */
_rightbus {
devfreq = <_leftbus>; /* 'devfreq' property indicates
the phandle of parent device. */
status = "okay";
};
(Omit the rest bus dt node)
Chanwoo Choi (20):
PM / devfreq: exynos: Add generic exynos bus frequency driver
PM / devfreq: exynos: Add documentation for generic exynos bus frequency
driver
ARM: dts: Add DMC bus node for Exynos3250
ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
PM / devfreq: Add new passive governor
PM / devfreq: Add devfreq_get_devfreq_by_phandle()
PM / devfreq: Show the related information according to governor type
PM / devfreq: exynos: Add support of bus frequency of sub-blocks using
passive governor
PM / devfreq: exynos: Update documentation for bus devices using passive
governor
PM / devfreq: exynos: Add the detailed correlation between sub-blocks and
power line
PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
MAINTAINERS: Add samsung bus frequency driver entry
ARM: dts: Add bus nodes using VDD_INT for Exynos3250
ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
ARM: dts: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes
ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
ARM: dts: Expand the voltage range of buck1/3 regulator for
exynos4412-odroidu3
ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
.../devi
[PATCH v4 04/20] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
This patch adds the DMC (Dynamic Memory Controller) bus frequency node
which includes the devfreq-events and regulator properties. The bus
frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
with ondemand governor.
The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
the DMC block.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos3250-monk.dts | 6 ++
arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 443a35085846..456844a81189 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -156,6 +156,12 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 3e64d5dcdd60..d6bb990ce931 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -147,6 +147,12 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
--
1.9.1
--
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[PATCH v4 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
This patch adds the generic exynos bus frequency driver for AMBA AXI bus
of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
have the common architecture for bus between DRAM and sub-blocks in SoC.
This driver can support the generic bus frequency driver for Exynos SoCs.
In devicetree, Each bus block has a bus clock, regulator, operation-point
and devfreq-event devices which measure the utilization of each bus block.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/Kconfig | 15 ++
drivers/devfreq/Makefile| 1 +
drivers/devfreq/exynos/Makefile | 1 +
drivers/devfreq/exynos/exynos-bus.c | 449
4 files changed, 466 insertions(+)
create mode 100644 drivers/devfreq/exynos/exynos-bus.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 64281bb2f650..55ec774f794c 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE
comment "DEVFREQ Drivers"
+config ARM_EXYNOS_BUS_DEVFREQ
+ bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
+ depends on ARCH_EXYNOS
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_EVENT_EXYNOS_PPMU
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+ Memory bus has one more group of memory bus (e.g, MIF and INT block).
+ Each memory bus group could contain many memoby bus block. It reads
+ PPMU counters of memory controllers by using DEVFREQ-event device
+ and adjusts the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
config ARM_EXYNOS4_BUS_DEVFREQ
bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
!ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 5134f9ee983d..375ebbb4fcfb 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
# DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS) += exynos/
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_TEGRA_DEVFREQ)+= tegra-devfreq.o
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 49bc9175f923..4ec06d322996 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,3 +1,4 @@
# Exynos DEVFREQ Drivers
+obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos-bus.c
b/drivers/devfreq/exynos/exynos-bus.c
new file mode 100644
index ..f1bc20839650
--- /dev/null
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -0,0 +1,449 @@
+/*
+ * Generic Exynos Bus frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi <cw00.c...@samsung.com>
+ *
+ * This driver support Exynos Bus frequency feature by using
+ * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DEFAULT_SATURATION_RATIO 40
+
+struct exynos_bus {
+ struct device *dev;
+
+ struct devfreq *devfreq;
+ struct devfreq_event_dev **edev;
+ unsigned int edev_count;
+ struct mutex lock;
+
+ struct dev_pm_opp *curr_opp;
+
+ struct regulator *regulator;
+ struct clk *clk;
+ int ratio;
+};
+
+/*
+ * Control the devfreq-event device to get the current state of bus
+ */
+#define exynos_bus_ops_edev(ops) \
+static int exynos_bus_##ops(struct exynos_bus *bus)\
+{ \
+ int i, ret; \
+ \
+ for (i = 0; i < bus->edev_count; i++) { \
+ if (!bus->edev[i]) \
+ continue; \
+ ret = devfre
[PATCH v4 12/20] MAINTAINERS: Add samsung bus frequency driver entry
This patch adds the 'SAMSUNG BUS FREQUENCY DRIVER' entry to review the patches as supporter. Patches will be picked up by DEVFREQ maintainer on devfreq git repository. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ff2d20173d98..89e645688a3c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3434,6 +3434,15 @@ F: drivers/devfreq/devfreq-event.c F: include/linux/devfreq-event.h F: Documentation/devicetree/bindings/devfreq/event/ +SAMSUNG BUS FREQUENCY DRIVER +M: Chanwoo Choi <cw00.c...@samsung.com> +L: linux...@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git +S: Supported +F: drivers/devfreq/exynos/exynos-bus.c +F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt + DEVICE NUMBER REGISTRY M: Torben Mathiasen <dev...@lanana.org> W: http://lanana.org/docs/device-list/index.html -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 11/20] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
This patch removes the unused exynos4/5 busfreq driver. Instead,
generic exynos-bus frequency driver support the all Exynos SoCs.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/Kconfig | 22 -
drivers/devfreq/exynos/Makefile |2 -
drivers/devfreq/exynos/exynos4_bus.c | 1055 --
drivers/devfreq/exynos/exynos4_bus.h | 110
drivers/devfreq/exynos/exynos5_bus.c | 431 --
drivers/devfreq/exynos/exynos_ppmu.c | 119
drivers/devfreq/exynos/exynos_ppmu.h | 86 ---
7 files changed, 1825 deletions(-)
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 88f7cc4539b8..e82b1d8cd200 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -91,28 +91,6 @@ config ARM_EXYNOS_BUS_DEVFREQ
and adjusts the operating frequencies and voltages with OPP support.
This does not yet operate with optimal voltages.
-config ARM_EXYNOS4_BUS_DEVFREQ
- bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
- depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
!ARCH_MULTIPLATFORM
- select DEVFREQ_GOV_SIMPLE_ONDEMAND
- select PM_OPP
- help
- This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
- and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
- It reads PPMU counters of memory controllers and adjusts
- the operating frequencies and voltages with OPP support.
- This does not yet operate with optimal voltages.
-
-config ARM_EXYNOS5_BUS_DEVFREQ
- tristate "ARM Exynos5250 Bus DEVFREQ Driver"
- depends on SOC_EXYNOS5250
- select DEVFREQ_GOV_SIMPLE_ONDEMAND
- select PM_OPP
- help
- This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).
- It reads PPMU counters of memory controllers and adjusts the
- operating frequencies and voltages with OPP support.
-
config ARM_TEGRA_DEVFREQ
tristate "Tegra DEVFREQ Driver"
depends on ARCH_TEGRA_124_SOC
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 4ec06d322996..bc695ad81c7d 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,4 +1,2 @@
# Exynos DEVFREQ Drivers
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
-obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
-obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos4_bus.c
b/drivers/devfreq/exynos/exynos4_bus.c
deleted file mode 100644
index da9509205169..
--- a/drivers/devfreq/exynos/exynos4_bus.c
+++ /dev/null
@@ -1,1055 +0,0 @@
-/* drivers/devfreq/exynos4210_memorybus.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- * MyungJoo Ham <myungjoo@samsung.com>
- *
- * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
- * This version supports EXYNOS4210 only. This changes bus frequencies
- * and vddint voltages. Exynos4412/4212 should be able to be supported
- * with minor modifications.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include "exynos_ppmu.h"
-#include "exynos4_bus.h"
-
-#define MAX_SAFEVOLT 120 /* 1.2V */
-
-enum exynos4_busf_type {
- TYPE_BUSF_EXYNOS4210,
- TYPE_BUSF_EXYNOS4x12,
-};
-
-/* Assume that the bus is saturated if the utilization is 40% */
-#define BUS_SATURATION_RATIO 40
-
-enum busclk_level_idx {
- LV_0 = 0,
- LV_1,
- LV_2,
- LV_3,
- LV_4,
- _LV_END
-};
-
-enum exynos_ppmu_idx {
- PPMU_DMC0,
- PPMU_DMC1,
- PPMU_END,
-};
-
-#define EX4210_LV_MAX LV_2
-#define EX4x12_LV_MAX LV_4
-#define EX4210_LV_NUM (LV_2 + 1)
-#define EX4x12_LV_NUM (LV_4 + 1)
-
-/**
- * struct busfreq_opp_info - opp information for bus
- * @rate: Frequency in hertz
- * @volt: Voltage in microvolts corresponding to this OPP
- */
-struct busfreq_opp_info {
- unsigned long rate;
- unsigned long volt;
-};
-
-struct busfreq_data {
- enum exynos4_busf_type type;
- struct device *dev;
- struct devfreq *devfreq;
- bool disabled;
- struct regulator *vdd_int;
- struct regulator *vdd_mif; /* Exynos4412/421
[PATCH v4 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 147 ++
1 file changed, 147 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 262b3b1995fd..5cc98cf13173 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -735,6 +735,153 @@
opp-microvolt = <875000>;
};
};
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_160>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_200>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mcuisp: bus_mcuisp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "bus";
+ operating-points-v2 = <_mcuisp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_isp: bus_isp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_266>;
+ clock-names = "bus";
+ operating-points-v2 = <_isp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peril: bus_peril {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peril_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <90>;
+ };
+ opp@8000 {
+ opp-hz = /bits/ 64 <8000>;
+ opp-microvolt = <90>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <100>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <100>;
+ };
+ opp@2 {
+
[PATCH v4 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
one power line for all buses to translate data between DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- DMC/ACP clock for DMC (Dynamic Memory Controller)
- ACLK200 clock for LCD0
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD0/LCD1
- ACLK133 clock for FSYS/GPS
- GDL/GDR clock for LEFTBUS/RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 159 ++
1 file changed, 159 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index c1cb8df6da07..2d9b02967105 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,165 @@
power-domains = <_lcd1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK200>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <1025000>;
+ };
+ opp@26700 {
+ opp-hz = /bits/ 64 <26700>;
+ opp-microvolt = <105>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <115>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ };
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ };
+ };
+
+ bus_peri_opp_
[PATCH v4 14/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
This patch adds the bus nodes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 68 +++
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 84a23f962946..99a0f4ca3d47 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -281,6 +281,74 @@
clocks = < CLK_SMMU_LITE1>, < CLK_FIMC_LITE1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_c2c: bus_c2c {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_C2C>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <90>;
+ };
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <90>;
+ };
+ opp@26700 {
+ opp-hz = /bits/ 64 <26700>;
+ opp-microvolt = <95>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <105>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ };
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ };
+ opp@26700 {
+ opp-hz = /bits/ 64 <26700>;
+ };
+ };
};
{
--
1.9.1
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[PATCH v4 15/20] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD
: The minimum clock of ACLK160 should be over 160MHz.
When drop the clock under 160MHz, show the broken image.
- ACLK133 clock for FSYS
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 106 ++
1 file changed, 106 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 99a0f4ca3d47..e5173107ed44 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -349,6 +349,112 @@
opp-hz = /bits/ 64 <26700>;
};
};
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <925000>;
+ };
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ };
+
+ bus_display_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ };
+ };
+
+ bus_fsys_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ };
+ };
};
{
--
1.9.1
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[PATCH v4 03/20] ARM: dts: Add DMC bus node for Exynos3250
This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
SDRAM devices. The bus includes the OPP tables and the source clock for DMC
block.
Following list specifies the detailed relation between the clock and DMC block:
- The source clock of DMC block : div_dmc
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 18e3deffbf48..262b3b1995fd 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -701,6 +701,40 @@
clock-names = "ppmu";
status = "disabled";
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <80>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <825000>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
};
};
--
1.9.1
--
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[PATCH v4 06/20] PM / devfreq: Add devfreq_get_devfreq_by_phandle()
This patch adds the new devfreq_get_devfreq_by_phandle() OF helper function
which can find the instance of devfreq device by using phandle ("devfreq").
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/devfreq.c | 44
include/linux/devfreq.h | 9 +
2 files changed, 53 insertions(+)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 15e58779e4c0..78ea4cdaa82c 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "governor.h"
static struct class *devfreq_class;
@@ -686,6 +687,49 @@ struct devfreq *devm_devfreq_add_device(struct device *dev,
}
EXPORT_SYMBOL(devm_devfreq_add_device);
+#ifdef CONFIG_OF
+/*
+ * devfreq_get_devfreq_by_phandle - Get the devfreq device from devicetree
+ * @dev - instance to the given device
+ * @index - index into list of devfreq
+ *
+ * return the instance of devfreq device
+ */
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+ struct device_node *node;
+ struct devfreq *devfreq;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ if (!dev->of_node)
+ return ERR_PTR(-EINVAL);
+
+ node = of_parse_phandle(dev->of_node, "devfreq", index);
+ if (!node)
+ return ERR_PTR(-ENODEV);
+
+ mutex_lock(_list_lock);
+ list_for_each_entry(devfreq, _list, node) {
+ if (devfreq->dev.parent
+ && devfreq->dev.parent->of_node == node) {
+ mutex_unlock(_list_lock);
+ return devfreq;
+ }
+ }
+ mutex_unlock(_list_lock);
+
+ return ERR_PTR(-EPROBE_DEFER);
+}
+#else
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+ return ERR_PTR(-ENODEV);
+}
+#endif /* CONFIG_OF */
+EXPORT_SYMBOL_GPL(devfreq_get_devfreq_by_phandle);
+
/**
* devm_devfreq_remove_device() - Resource-managed devfreq_remove_device()
* @dev: the device to add devfreq feature.
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 95c54578a1b4..cf972befca2b 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -211,6 +211,9 @@ extern int devm_devfreq_register_opp_notifier(struct device
*dev,
extern void devm_devfreq_unregister_opp_notifier(struct device *dev,
struct devfreq *devfreq);
+extern struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev,
+ int index);
+
/**
* devfreq_update_stats() - update the last_status pointer in struct devfreq
* @df:the devfreq instance whose status needs updating
@@ -322,6 +325,12 @@ static inline void
devm_devfreq_unregister_opp_notifier(struct device *dev,
{
}
+static inline struct devfreq *devfreq_get_devfreq_by_phandle(struct device
*dev,
+ int index)
+{
+ return ERR_PTR(-ENODEV);
+}
+
static inline int devfreq_update_stats(struct devfreq *df)
{
return -EINVAL;
--
1.9.1
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[PATCH v4 05/20] PM / devfreq: Add new passive governor
This patch adds the new passive governor for DEVFREQ framework. The following
governors are already present and used for DVFS (Dynamic Voltage and Frequency
Scaling) drivers. The following governors are independently used for one device
driver which don't give the influence to other device drviers and also don't
receive the effect from other device drivers.
- ondemand / performance / powersave / userspace
The passive governor depends on operation of parent driver with specific
governos extremely and is not able to decide the new frequency by oneself.
According to the decided new frequency of parent driver with governor,
the passive governor uses it to decide the appropriate frequency for own
device driver. The passive governor must need the following information
from device tree:
- the source clock and OPP tables
- the instance of parent device
For exameple,
there are one more devfreq device drivers which need to change their source
clock according to their utilization on runtime. But, they share the same
power line (e.g., regulator). So, specific device driver is operated as parent
with ondemand governor and then the rest device driver with passive governor
is influenced by parent device.
Suggested-by: Myungjoo Ham <myungjoo@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/Kconfig| 9
drivers/devfreq/Makefile | 1 +
drivers/devfreq/devfreq.c | 47
drivers/devfreq/governor_passive.c | 108 +
include/linux/devfreq.h| 15 ++
5 files changed, 180 insertions(+)
create mode 100644 drivers/devfreq/governor_passive.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 55ec774f794c..d03f635a93e1 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -64,6 +64,15 @@ config DEVFREQ_GOV_USERSPACE
Otherwise, the governor does not change the frequnecy
given at the initialization.
+config DEVFREQ_GOV_PASSIVE
+ tristate "Passive"
+ help
+ Sets the frequency by other governors (simple_ondemand, performance,
+ powersave, usersapce) of a parent devfreq device. This governor
+ always has the dependency on the chosen frequency from paired
+ governor. This governor does not change the frequency by oneself
+ through sysfs entry.
+
comment "DEVFREQ Drivers"
config ARM_EXYNOS_BUS_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 375ebbb4fcfb..f81c313b4b79 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +=
governor_simpleondemand.o
obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)+= governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
+obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
# DEVFREQ Drivers
obj-$(CONFIG_ARCH_EXYNOS) += exynos/
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 984c5e9e7bdd..15e58779e4c0 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -190,6 +190,31 @@ static struct devfreq_governor
*find_devfreq_governor(const char *name)
/* Load monitoring helper functions for governors use */
+static int update_devfreq_passive(struct devfreq *devfreq, unsigned long freq)
+{
+ struct devfreq *passive;
+ unsigned long rate;
+ int ret;
+
+ list_for_each_entry(passive, >passive_dev_list, passive_node) {
+ if (!passive->governor)
+ continue;
+ rate = freq;
+
+ ret = passive->governor->get_target_freq(passive, );
+ if (ret)
+ return ret;
+
+ ret = passive->profile->target(passive->dev.parent, , 0);
+ if (ret)
+ return ret;
+
+ passive->previous_freq = rate;
+ }
+
+ return 0;
+}
+
/**
* update_devfreq() - Reevaluate the device and configure frequency.
* @devfreq: the devfreq instance.
@@ -233,10 +258,18 @@ int update_devfreq(struct devfreq *devfreq)
flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */
}
+ if (!list_empty(>passive_dev_list)
+ && devfreq->previous_freq > freq)
+ update_devfreq_passive(devfreq, freq);
+
err = devfreq->profile->target(devfreq->dev.parent, , flags);
if (err)
return err;
+ if (!list_empty(>passive_dev_list)
+ && devfreq->previous_freq < freq)
+ update_devfreq_passive(devfreq, freq);
+
if (devfreq->profile->freq_table)
[PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
This patch adds the documentation for generic exynos bus frequency
driver.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 93 ++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
new file mode 100644
index ..e32daef328da
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,93 @@
+* Generic Exynos Bus frequency device
+
+The Samsung Exynos SoC have many buses for data transfer between DRAM
+and sub-blocks in SoC. Almost Exynos SoC have the common architecture
+for buses. Generally, the each bus of Exynos SoC includes the source clock
+and power line and then is able to change the clock according to the usage
+of each buses on runtime. When gathering the usage of each buses on runtime,
+the driver uses the PPMU (Platform Performance Monitoring Unit) which
+is able to measure the current load of sub-blocks.
+
+There are a little different composition among Exynos SoC because each Exynos
+SoC has the different sub-blocks. So, this difference should be specified
+in devicetree file instead of each device driver. In result, this driver
+is able to support the bus frequency for all Exynos SoCs.
+
+Required properties for bus device:
+- compatible: Should be "samsung,exynos-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- operating-points-v2: the OPP table including frequency/voltage information
+ to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- vdd-supply: the regulator to provide the buses with the voltage.
+- devfreq-events: the devfreq-event device to monitor the current utilization
+ of buses.
+
+Optional properties for bus device:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+ the performance count against total cycle count.
+
+Example1:
+ Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
+ power line (regulator). The MIF (Memory Interface) AXI bus is used to
+ transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
+
+ - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+
+ - MIF bus's frequency/voltage table
+ ---
+ |Lv| Freq | Voltage |
+ ---
+ |L1| 5 |80 |
+ |L2| 10 |80 |
+ |L3| 134000 |80 |
+ |L4| 20 |825000 |
+ |L5| 40 |875000 |
+ ---
+
+Example2 :
+ The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
+ is listed below:
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <80>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <825000>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
+
+ Usage case to handle the frequency and voltage of bus on runtime
+ in exynos3250-rinato.dts is listed below:
+
+ _dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>; /* VDD_MIF */
+ status = "okay";
+ };
--
1.9.1
--
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Re: [PATCH v3 20/20] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
On 2015년 12월 11일 16:20, Krzysztof Kozlowski wrote:
> On 11.12.2015 14:07, Chanwoo Choi wrote:
>> THis patch adds the bus device tree nodes for both MIF (Memory) and INT
>> (Internal) block to enable the bus frequency.
>>
>> The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
>> bus is parent device in INT block using VDD_INT.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> [linux.amoon: Tested on Odroid U3]
>> Tested-by: Anand Moon <linux.am...@gmail.com>
>> ---
>> arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47
>>
>> arch/arm/boot/dts/exynos4412-trats2.dts | 48
>> +
>> 2 files changed, 95 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> index 7bd65026761e..b6818aec7cf9 100644
>> --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> @@ -501,3 +501,50 @@
>> {
>> status = "okay";
>> };
>> +
>> +_acp {
>> +devfreq = <_dmc>;
>> +status = "okay";
>> +};
>
> I meant put them in proper place, respecting alphabetical order. The 'b'
> comes before 'w'.
>
> As for the new nodes (bus_XXX) your previous sorting (first parent, then
> passive) was also okay - it had sense. This is up to you. Just put
> everything not at the end of file.
OK. I'll reorder them. Thanks for review.
[snip]
Best Regards,
Chanwoo Choi
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Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
On 2015년 12월 11일 12:24, Rob Herring wrote: > On Fri, Dec 11, 2015 at 12:10:13AM +0900, Chanwoo Choi wrote: >> On Thu, Dec 10, 2015 at 11:21 PM, Rob Herring <r...@kernel.org> wrote: >>> On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote: >>>> This patch updates the documentation for passive bus devices and adds the >>>> detailed example of Exynos3250. >>>> >>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >>>> --- >>>> .../devicetree/bindings/devfreq/exynos-bus.txt | 244 >>>> - >>>> 1 file changed, 241 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >>>> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >>>> index 54a1f9c46c88..c4fdc70f8eac 100644 >>>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >>>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >>>> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference >>>> should be specified >>>> in devicetree file instead of each device driver. In result, this driver >>>> is able to support the bus frequency for all Exynos SoCs. >>>> >>>> -Required properties for bus device: >>>> +Required properties for all bus devices: >>>> - compatible: Should be "samsung,exynos-bus". >>>> - clock-names : the name of clock used by the bus, "bus". >>>> - clocks : phandles for clock specified in "clock-names" property. >>>> - #clock-cells: should be 1. >>>> - operating-points-v2: the OPP table including frequency/voltage >>>> information >>>>to support DVFS (Dynamic Voltage/Frequency Scaling) feature. >>>> + >>>> +Required properties for only parent bus device: >>>> - vdd-supply: the regulator to provide the buses with the voltage. >>>> - devfreq-events: the devfreq-event device to monitor the curret >>>> utilization >>>>of buses. >>>> >>>> -Optional properties for bus device: >>>> +Required properties for only passive bus device: >>>> +- devfreq: the parent bus device. >>>> + >>>> +Optional properties for only parent bus device: >>>> - exynos,saturation-ratio: the percentage value which is used to calibrate >>>> the performance count againt total cycle count. >>>> >>>> @@ -33,7 +38,20 @@ Example1: >>>> power line (regulator). The MIF (Memory Interface) AXI bus is used to >>>> transfer data between DRAM and CPU and uses the VDD_MIF regualtor. >>>> >>>> - - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) >>>> block >>>> + - MIF (Memory Interface) block >>>> + : VDD_MIF |--- DMC (Dynamic Memory Controller) >>>> + >>>> + - INT (Internal) block >>>> + : VDD_INT |--- LEFTBUS (parent device) >>>> + |--- PERIL >>>> + |--- MFC >>>> + |--- G3D >>>> + |--- RIGHTBUS >>>> + |--- FSYS >>>> + |--- LCD0 >>>> + |--- PERIR >>>> + |--- ISP >>>> + |--- CAM >>> >>> This still has the same problem as before. I would expect that the bus >>> hierarchy in the dts match the hierarchy here. You just have flat nodes >>> in the example below. So all IP blocks affected by frequency scaling >>> should be under the bus node defining the OPPs. Something like this: >> >> The each bus of sub-block has not h/w dependency among sub-blocks >> and has the owned source clock / OPP table. Just they share the same >> power line. So, I think that flat nodes in the example below is not problem. > > I'm talking about the peripherals not described here. Is the ISP block > not a child of the bus_isp node? Same for the display controller block > and bus_lcd0. And so on. >From the H/W point of view, ISP block is really not included in ISP's AXI bus >(bus_isp). Just, the bus_isp connect to between ISP block and DRAM. Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3
On 2015년 12월 10일 15:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
>> exynos4412-odroidu3 board. Each PPMU dt node includes one event of
>> 'PPMU Count3'.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40
>> +
>> 1 file changed, 40 insertions(+)
>>
>
> The patch itself is good but now I see that it is duplicated with
> Rinato, Monk and Trats2. Probably for all other Exynos4 and
> one-cluster-Exynos5 boards this would be exactly the same as well.
>
> How about making a DTSI file with common PPMU events configuration?
OK. I'll make the exynos4412-ppmu-common.dtsi.
The Exynos4 series used the PPMU firstly. That is why deciding the filename
of exynos4412-ppmu-common.dtsi.
Best Regards,
Chanwoo Choi
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Re: [PATCH v3 17/20] ARM: dts: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU node
On 2015년 12월 11일 16:15, Krzysztof Kozlowski wrote: > On 11.12.2015 14:07, Chanwoo Choi wrote: >> This patch adds the exynos4412-ppmu-common.dtsi to duplicate PPMU node > > I think the goal of the patch was to remove duplication of nodes, not to > duplicate them. :) OK. I'll modify both subject and description of this patch. > > Except of that patch is okay: > > Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> [snip] Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 18/20] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
On 2015년 12월 11일 16:18, Krzysztof Kozlowski wrote: > On 11.12.2015 14:07, Chanwoo Choi wrote: >> This patch adds the bus device-tree node of INT (internal) block >> to enable the bus frequency scaling. The following sub-blocks share >> the VDD_INT power source: >> - LEFTBUS (parent device) >> - RIGHTBUS >> - PERIL >> - LCD0 >> - FSYS >> - MCUISP / ISP >> - MFC >> >> The LEFTBUS is parent device with devfreq ondemand governor >> and the rest devices has the dependency on LEFTBUS bus. > > I pointed this previously. If you wish to leave the sentence in such > form then "rest of" and "have" not "has". It is my mistake. I'll modify it as following your comment: - "and the rest of devices depend on the LEFTBUS device." Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
Dear MyungJoo,
Almost device tree patches in this series are reviewed by Exynos maintainer.
Could you please review this series?
Best Regards,
Chanwoo Choi
On 2015년 12월 11일 14:07, Chanwoo Choi wrote:
> This patch adds the generic exynos bus frequency driver for AMBA AXI bus
> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
> have the common architecture for bus between DRAM and sub-blocks in SoC.
> This driver can support the generic bus frequency driver for Exynos SoCs.
>
> In devicetree, Each bus block has a bus clock, regulator, operation-point
> and devfreq-event devices which measure the utilization of each bus block.
>
> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
> [linux.amoon: Tested on Odroid U3]
> Tested-by: Anand Moon <linux.am...@gmail.com>
> ---
> drivers/devfreq/Kconfig | 15 ++
> drivers/devfreq/Makefile| 1 +
> drivers/devfreq/exynos/Makefile | 1 +
> drivers/devfreq/exynos/exynos-bus.c | 449
>
> 4 files changed, 466 insertions(+)
> create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 64281bb2f650..55ec774f794c 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE
>
> comment "DEVFREQ Drivers"
>
> +config ARM_EXYNOS_BUS_DEVFREQ
> + bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
> + depends on ARCH_EXYNOS
> + select DEVFREQ_GOV_SIMPLE_ONDEMAND
> + select DEVFREQ_EVENT_EXYNOS_PPMU
> + select PM_DEVFREQ_EVENT
> + select PM_OPP
> + help
> + This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
> + Memory bus has one more group of memory bus (e.g, MIF and INT block).
> + Each memory bus group could contain many memoby bus block. It reads
> + PPMU counters of memory controllers by using DEVFREQ-event device
> + and adjusts the operating frequencies and voltages with OPP support.
> + This does not yet operate with optimal voltages.
> +
> config ARM_EXYNOS4_BUS_DEVFREQ
> bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
> depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
> !ARCH_MULTIPLATFORM
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 5134f9ee983d..375ebbb4fcfb 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
> obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
>
> # DEVFREQ Drivers
> +obj-$(CONFIG_ARCH_EXYNOS)+= exynos/
> obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)+= exynos/
> obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)+= exynos/
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o
> diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
> index 49bc9175f923..4ec06d322996 100644
> --- a/drivers/devfreq/exynos/Makefile
> +++ b/drivers/devfreq/exynos/Makefile
> @@ -1,3 +1,4 @@
> # Exynos DEVFREQ Drivers
> +obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)+= exynos_ppmu.o exynos4_bus.o
> obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)+= exynos_ppmu.o exynos5_bus.o
> diff --git a/drivers/devfreq/exynos/exynos-bus.c
> b/drivers/devfreq/exynos/exynos-bus.c
> new file mode 100644
> index ..f1bc20839650
> --- /dev/null
> +++ b/drivers/devfreq/exynos/exynos-bus.c
> @@ -0,0 +1,449 @@
> +/*
> + * Generic Exynos Bus frequency driver with DEVFREQ Framework
> + *
> + * Copyright (c) 2015 Samsung Electronics Co., Ltd.
> + * Author : Chanwoo Choi <cw00.c...@samsung.com>
> + *
> + * This driver support Exynos Bus frequency feature by using
> + * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define DEFAULT_SATURATION_RATIO 40
> +
> +struct exynos_bus {
> + struct device *dev;
> +
> + struct devfreq *devfreq;
> + struct devfreq_event_dev **edev;
> + unsigned int edev_count;
> + struct mutex lock;
> +
> + struct dev_pm_opp *curr_opp;
>
[PATCH v3 04/20] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
This patch adds the DMC (Dynamic Memory Controller) bus frequency node
which includes the devfreq-events and regulator properties. The bus
frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
with ondemand governor.
The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
the DMC block.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
arch/arm/boot/dts/exynos3250-monk.dts | 6 ++
arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 443a35085846..456844a81189 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -156,6 +156,12 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 3e64d5dcdd60..d6bb990ce931 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -147,6 +147,12 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
{
cpu0-supply = <_reg>;
};
--
1.9.1
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[PATCH v3 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver
This patch adds the generic exynos bus frequency driver for AMBA AXI bus
of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
have the common architecture for bus between DRAM and sub-blocks in SoC.
This driver can support the generic bus frequency driver for Exynos SoCs.
In devicetree, Each bus block has a bus clock, regulator, operation-point
and devfreq-event devices which measure the utilization of each bus block.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/Kconfig | 15 ++
drivers/devfreq/Makefile| 1 +
drivers/devfreq/exynos/Makefile | 1 +
drivers/devfreq/exynos/exynos-bus.c | 449
4 files changed, 466 insertions(+)
create mode 100644 drivers/devfreq/exynos/exynos-bus.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 64281bb2f650..55ec774f794c 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE
comment "DEVFREQ Drivers"
+config ARM_EXYNOS_BUS_DEVFREQ
+ bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
+ depends on ARCH_EXYNOS
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_EVENT_EXYNOS_PPMU
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+ Memory bus has one more group of memory bus (e.g, MIF and INT block).
+ Each memory bus group could contain many memoby bus block. It reads
+ PPMU counters of memory controllers by using DEVFREQ-event device
+ and adjusts the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
config ARM_EXYNOS4_BUS_DEVFREQ
bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
!ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 5134f9ee983d..375ebbb4fcfb 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
# DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS) += exynos/
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_TEGRA_DEVFREQ)+= tegra-devfreq.o
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 49bc9175f923..4ec06d322996 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,3 +1,4 @@
# Exynos DEVFREQ Drivers
+obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos-bus.c
b/drivers/devfreq/exynos/exynos-bus.c
new file mode 100644
index ..f1bc20839650
--- /dev/null
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -0,0 +1,449 @@
+/*
+ * Generic Exynos Bus frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi <cw00.c...@samsung.com>
+ *
+ * This driver support Exynos Bus frequency feature by using
+ * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DEFAULT_SATURATION_RATIO 40
+
+struct exynos_bus {
+ struct device *dev;
+
+ struct devfreq *devfreq;
+ struct devfreq_event_dev **edev;
+ unsigned int edev_count;
+ struct mutex lock;
+
+ struct dev_pm_opp *curr_opp;
+
+ struct regulator *regulator;
+ struct clk *clk;
+ int ratio;
+};
+
+/*
+ * Control the devfreq-event device to get the current state of bus
+ */
+#define exynos_bus_ops_edev(ops) \
+static int exynos_bus_##ops(struct exynos_bus *bus)\
+{ \
+ int i, ret; \
+ \
+ for (i = 0; i < bus->edev_count; i++) { \
+ if (!bus->edev[i]) \
+ continue; \
+ ret = devfre
[PATCH v3 03/20] ARM: dts: Add DMC bus node for Exynos3250
This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
SDRAM devices. The bus includes the OPP tables and the source clock for DMC
block.
Following list specifies the detailed relation between the clock and DMC block:
- The source clock of DMC block : div_dmc
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 18e3deffbf48..262b3b1995fd 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -701,6 +701,40 @@
clock-names = "ppmu";
status = "disabled";
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <80>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <825000>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
};
};
--
1.9.1
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[PATCH v3 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
one power line for all buses to translate data between DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- DMC/ACP clock for DMC (Dynamic Memory Controller)
- ACLK200 clock for LCD0
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD0/LCD1
- ACLK133 clock for FSYS/GPS
- GDL/GDR clock for LEFTBUS/RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 159 ++
1 file changed, 159 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index c1cb8df6da07..2d9b02967105 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,165 @@
power-domains = <_lcd1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK200>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <1025000>;
+ };
+ opp@26700 {
+ opp-hz = /bits/ 64 <26700>;
+ opp-microvolt = <105>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <115>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ };
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table3 {
+ compatible = "operat
[PATCH v3 11/20] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
This patch removes the unused exynos4/5 busfreq driver. Instead,
generic exynos-bus frequency driver support the all Exynos SoCs.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/Kconfig | 22 -
drivers/devfreq/exynos/Makefile |2 -
drivers/devfreq/exynos/exynos4_bus.c | 1055 --
drivers/devfreq/exynos/exynos4_bus.h | 110
drivers/devfreq/exynos/exynos5_bus.c | 431 --
drivers/devfreq/exynos/exynos_ppmu.c | 119
drivers/devfreq/exynos/exynos_ppmu.h | 86 ---
7 files changed, 1825 deletions(-)
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 88f7cc4539b8..e82b1d8cd200 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -91,28 +91,6 @@ config ARM_EXYNOS_BUS_DEVFREQ
and adjusts the operating frequencies and voltages with OPP support.
This does not yet operate with optimal voltages.
-config ARM_EXYNOS4_BUS_DEVFREQ
- bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
- depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
!ARCH_MULTIPLATFORM
- select DEVFREQ_GOV_SIMPLE_ONDEMAND
- select PM_OPP
- help
- This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
- and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
- It reads PPMU counters of memory controllers and adjusts
- the operating frequencies and voltages with OPP support.
- This does not yet operate with optimal voltages.
-
-config ARM_EXYNOS5_BUS_DEVFREQ
- tristate "ARM Exynos5250 Bus DEVFREQ Driver"
- depends on SOC_EXYNOS5250
- select DEVFREQ_GOV_SIMPLE_ONDEMAND
- select PM_OPP
- help
- This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).
- It reads PPMU counters of memory controllers and adjusts the
- operating frequencies and voltages with OPP support.
-
config ARM_TEGRA_DEVFREQ
tristate "Tegra DEVFREQ Driver"
depends on ARCH_TEGRA_124_SOC
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 4ec06d322996..bc695ad81c7d 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,4 +1,2 @@
# Exynos DEVFREQ Drivers
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
-obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
-obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos4_bus.c
b/drivers/devfreq/exynos/exynos4_bus.c
deleted file mode 100644
index da9509205169..
--- a/drivers/devfreq/exynos/exynos4_bus.c
+++ /dev/null
@@ -1,1055 +0,0 @@
-/* drivers/devfreq/exynos4210_memorybus.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- * MyungJoo Ham <myungjoo@samsung.com>
- *
- * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
- * This version supports EXYNOS4210 only. This changes bus frequencies
- * and vddint voltages. Exynos4412/4212 should be able to be supported
- * with minor modifications.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include "exynos_ppmu.h"
-#include "exynos4_bus.h"
-
-#define MAX_SAFEVOLT 120 /* 1.2V */
-
-enum exynos4_busf_type {
- TYPE_BUSF_EXYNOS4210,
- TYPE_BUSF_EXYNOS4x12,
-};
-
-/* Assume that the bus is saturated if the utilization is 40% */
-#define BUS_SATURATION_RATIO 40
-
-enum busclk_level_idx {
- LV_0 = 0,
- LV_1,
- LV_2,
- LV_3,
- LV_4,
- _LV_END
-};
-
-enum exynos_ppmu_idx {
- PPMU_DMC0,
- PPMU_DMC1,
- PPMU_END,
-};
-
-#define EX4210_LV_MAX LV_2
-#define EX4x12_LV_MAX LV_4
-#define EX4210_LV_NUM (LV_2 + 1)
-#define EX4x12_LV_NUM (LV_4 + 1)
-
-/**
- * struct busfreq_opp_info - opp information for bus
- * @rate: Frequency in hertz
- * @volt: Voltage in microvolts corresponding to this OPP
- */
-struct busfreq_opp_info {
- unsigned long rate;
- unsigned long volt;
-};
-
-struct busfreq_data {
- enum exynos4_busf_type type;
- struct device *dev;
- struct devfreq *devfreq;
- bool disabled;
- struct regulator *vdd_int;
- struct regulator *vdd_mif; /* Exynos4412/421
[PATCH v3 09/20] PM / devfreq: exynos: Update documentation for bus devices using passive governor
This patch updates the documentation for passive bus devices and adds the detailed example of Exynos3250. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- .../devicetree/bindings/devfreq/exynos-bus.txt | 250 - 1 file changed, 247 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index e32daef328da..a251f9120561 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -8,22 +8,46 @@ of each buses on runtime. When gathering the usage of each buses on runtime, the driver uses the PPMU (Platform Performance Monitoring Unit) which is able to measure the current load of sub-blocks. +The Exynos SoC includes the various sub-blocks which have the each AXI bus. +The each AXI bus has the owned source clock but, has not the only owned +power line. The power line might be shared among one more sub-blocks. +So, we can divide into two type of device as the role of each sub-block. +There are two type of bus devices as following: +- parent bus device +- passive bus device + +Basically, parent and passive bus device share the same power line. +The parent bus device can only change the voltage of shared power line +and the rest bus devices (passive bus device) depend on the decision of +the parent bus device. If there are three blocks which share the VDD_xxx +power line, Only one block should be parent device and then the rest blocks +should depend on the parent device as passive device. + + VDD_xxx |--- A block (parent) + |--- B block (passive) + |--- C block (passive) + There are a little different composition among Exynos SoC because each Exynos SoC has the different sub-blocks. So, this difference should be specified in devicetree file instead of each device driver. In result, this driver is able to support the bus frequency for all Exynos SoCs. -Required properties for bus device: +Required properties for all bus devices: - compatible: Should be "samsung,exynos-bus". - clock-names : the name of clock used by the bus, "bus". - clocks : phandles for clock specified in "clock-names" property. - operating-points-v2: the OPP table including frequency/voltage information to support DVFS (Dynamic Voltage/Frequency Scaling) feature. + +Required properties only for parent bus device: - vdd-supply: the regulator to provide the buses with the voltage. - devfreq-events: the devfreq-event device to monitor the current utilization of buses. -Optional properties for bus device: +Required properties only for passive bus device: +- devfreq: the parent bus device. + +Optional properties only for parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count against total cycle count. @@ -32,7 +56,20 @@ Example1: power line (regulator). The MIF (Memory Interface) AXI bus is used to transfer data between DRAM and CPU and uses the VDD_MIF regualtor. - - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block + - MIF (Memory Interface) block + : VDD_MIF |--- DMC (Dynamic Memory Controller) + + - INT (Internal) block + : VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM - MIF bus's frequency/voltage table --- @@ -45,6 +82,24 @@ Example1: |L5| 40 |875000 | --- + - INT bus's frequency/voltage table + -- + |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP|PERIL ||VDD_INT | + | name| |LCD0| | | ||| + | | |FSYS| | | ||| + | | |MFC | | | ||| + -- + |Mode |*parent|passive |passive|passive|passive||| + -- + |Lv |Frequency ||Voltage | + -- + |L1 |5 |5 |5 |5 |5 ||90 | + |L2 |8 |8 |8 |8 |8 ||90 | + |L3 |10 |10 |10 |10 |10 ||100 | + |L4 |134000 |134000 |20 |20 | ||100 | + |L5 |20 |20 |40 |30 | ||100 | + -- + Example2 :
[PATCH v3 08/20] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the source clock and
regulator at the same time. So, this patch uses the passive governor to support
the bus frequency for all buses which sharing the one power line.
For example,
Exynos3250 include the two power line for AXI buses as following:
: VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller)
with the power (regulator).
: VDD_INT : INT (Internal) provide the various sub-blocks with the power
(regulator).
Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus
use the power line. So, there is no any depencency between buese. But, in the
case of VDD_INT, various buses share the one power line of VDD_INT. We need to
make the depenency between buses. When using passive governor, there is no
problem to support the bus frequency as DVFS for all buses. One bus should be
operated as the parent bus device which gathering the current load of INT block
and then decides the new frequency with some governors except of passive
governor. After deciding the new frequency by the parent bus device, the rest
bus devices will change the each source clock according to new frequency of the
parent bus device.
- MIF (Memory Interface) block
: VDD_MIF |--- DMC
- INT (Internal) block
: VDD_INT |--- LEFTBUS (parent)
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAM
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/Kconfig | 1 +
drivers/devfreq/exynos/exynos-bus.c | 179
2 files changed, 144 insertions(+), 36 deletions(-)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index d03f635a93e1..88f7cc4539b8 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -79,6 +79,7 @@ config ARM_EXYNOS_BUS_DEVFREQ
bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
depends on ARCH_EXYNOS
select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_GOV_PASSIVE
select DEVFREQ_EVENT_EXYNOS_PPMU
select PM_DEVFREQ_EVENT
select PM_OPP
diff --git a/drivers/devfreq/exynos/exynos-bus.c
b/drivers/devfreq/exynos/exynos-bus.c
index f1bc20839650..d1c137ea22ca 100644
--- a/drivers/devfreq/exynos/exynos-bus.c
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -91,7 +91,7 @@ static int exynos_bus_get_event(struct exynos_bus *bus,
}
/*
- * Must necessary function for devfreq governor
+ * Must necessary function for devfreq simple-ondemand governor
*/
static int exynos_bus_target(struct device *dev, unsigned long *freq, u32
flags)
{
@@ -205,57 +205,74 @@ static void exynos_bus_exit(struct device *dev)
dev_pm_opp_of_remove_table(dev);
}
-static int exynos_bus_parse_of(struct device_node *np,
- struct exynos_bus *bus)
+/*
+ * Must necessary function for devfreq passive governor
+ */
+static int exynos_bus_passive_target(struct device *dev, unsigned long *freq,
+ u32 flags)
{
- struct device *dev = bus->dev;
- unsigned long rate;
- int i, ret, count, size;
+ struct exynos_bus *bus = dev_get_drvdata(dev);
+ struct dev_pm_opp *new_opp;
+ unsigned long old_freq, new_freq;
+ int ret = 0;
- /* Get the clock to provide each bus with source clock */
- bus->clk = devm_clk_get(dev, "bus");
- if (IS_ERR(bus->clk)) {
- dev_err(dev, "failed to get bus clock\n");
- return PTR_ERR(bus->clk);
+ /* Get new opp-bus instance according to new bus clock */
+ rcu_read_lock();
+ new_opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR_OR_NULL(new_opp)) {
+ dev_err(dev, "failed to get recommed opp instance\n");
+ rcu_read_unlock();
+ return PTR_ERR(new_opp);
}
- ret = clk_prepare_enable(bus->clk);
- if (ret < 0) {
- dev_err(dev, "failed to get enable clock\n");
- return ret;
- }
+ new_freq = dev_pm_opp_get_freq(new_opp);
+ old_freq = dev_pm_opp_get_freq(bus->curr_opp);
+ rcu_read_unlock();
- /* Get the freq/voltage OPP table to scale the bus frequency */
- rcu_read_lock();
- ret = dev_pm_opp_of_add_table(dev);
+ if (old_freq == new_freq)
+ return 0;
+
+ /* Change the frequency according to new OPP level */
+ mutex
[PATCH v3 10/20] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
This patch adds the detailed corrleation between sub-blocks and power line for Exynos3250, Exynos4210 and Exynos4x12. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- .../devicetree/bindings/devfreq/exynos-bus.txt | 51 ++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index a251f9120561..f3a32b310dc7 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -51,6 +51,57 @@ Optional properties only for parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count against total cycle count. +Detailed correlation between sub-blocks and power line according to Exynos SoC: +- In case of Exynos3250, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- PERIR + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM + +- In case of Exynos4210, there is one power line as following: + VDD_INT |--- DMC (parent device) + |--- LEFTBUS + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- LCD0 + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- LCD1 + +- In case of Exynos4x12, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- IMAGE + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- ISP + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 15/20] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD
: The minimum clock of ACLK160 should be over 160MHz.
When drop the clock under 160MHz, show the broken image.
- ACLK133 clock for FSYS
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 106 ++
1 file changed, 106 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 99a0f4ca3d47..e5173107ed44 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -349,6 +349,112 @@
opp-hz = /bits/ 64 <26700>;
};
};
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <925000>;
+ };
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ };
+
+ bus_display_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@16000 {
+ opp-hz = /bits/ 64 <16000>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ };
+ };
+
+ bus_fsys_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ };
+ };
};
{
--
1.9.1
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[PATCH v3 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 147 ++
1 file changed, 147 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 262b3b1995fd..5cc98cf13173 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -735,6 +735,153 @@
opp-microvolt = <875000>;
};
};
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_160>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_200>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mcuisp: bus_mcuisp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "bus";
+ operating-points-v2 = <_mcuisp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_isp: bus_isp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_266>;
+ clock-names = "bus";
+ operating-points-v2 = <_isp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peril: bus_peril {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peril_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <90>;
+ };
+ opp@8000 {
+ opp-hz = /bits/ 64 <8000>;
+ opp-microvolt = <90>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <100>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <100>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+
[PATCH v3 12/20] MAINTAINERS: Add samsung bus frequency driver entry
This patch adds the 'SAMSUNG BUS FREQUENCY DRIVER' entry to review the patches as supporter. Patches will be picked up by DEVFREQ maintainer on devfreq git repository. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ff2d20173d98..89e645688a3c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3434,6 +3434,15 @@ F: drivers/devfreq/devfreq-event.c F: include/linux/devfreq-event.h F: Documentation/devicetree/bindings/devfreq/event/ +SAMSUNG BUS FREQUENCY DRIVER +M: Chanwoo Choi <cw00.c...@samsung.com> +L: linux...@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git +S: Supported +F: drivers/devfreq/exynos/exynos-bus.c +F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt + DEVICE NUMBER REGISTRY M: Torben Mathiasen <dev...@lanana.org> W: http://lanana.org/docs/device-list/index.html -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 17/20] ARM: dts: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU node
This patch adds the exynos4412-ppmu-common.dtsi to duplicate PPMU node
because exynos3250-rinato/monk, exynos4412-trats2/odroidu3 has the same
PPMU device tree node.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250-monk.dts | 41 +
arch/arm/boot/dts/exynos3250-rinato.dts | 41 +
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 +
arch/arm/boot/dts/exynos4412-ppmu-common.dtsi | 49 +
arch/arm/boot/dts/exynos4412-trats2.dts | 41 +
5 files changed, 53 insertions(+), 120 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 456844a81189..a4e525e5e6e4 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -14,6 +14,7 @@
/dts-v1/;
#include "exynos3250.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
#include
#include
#include
@@ -464,46 +465,6 @@
status = "okay";
};
-_dmc0 {
- status = "okay";
-
- events {
- ppmu_dmc0_3: ppmu-event3-dmc0 {
- event-name = "ppmu-event3-dmc0";
- };
- };
-};
-
-_dmc1 {
- status = "okay";
-
- events {
- ppmu_dmc1_3: ppmu-event3-dmc1 {
- event-name = "ppmu-event3-dmc1";
- };
- };
-};
-
-_leftbus {
- status = "okay";
-
- events {
- ppmu_leftbus_3: ppmu-event3-leftbus {
- event-name = "ppmu-event3-leftbus";
- };
- };
-};
-
-_rightbus {
- status = "okay";
-
- events {
- ppmu_rightbus_3: ppmu-event3-rightbus {
- event-name = "ppmu-event3-rightbus";
- };
- };
-};
-
{
clock-frequency = <2400>;
};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index d6bb990ce931..2a1c22598fdc 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -14,6 +14,7 @@
/dts-v1/;
#include "exynos3250.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
#include
#include
#include
@@ -641,46 +642,6 @@
status = "okay";
};
-_dmc0 {
- status = "okay";
-
- events {
- ppmu_dmc0_3: ppmu-event3-dmc0 {
- event-name = "ppmu-event3-dmc0";
- };
- };
-};
-
-_dmc1 {
- status = "okay";
-
- events {
- ppmu_dmc1_3: ppmu-event3-dmc1 {
- event-name = "ppmu-event3-dmc1";
- };
- };
-};
-
-_leftbus {
- status = "okay";
-
- events {
- ppmu_leftbus_3: ppmu-event3-leftbus {
- event-name = "ppmu-event3-leftbus";
- };
- };
-};
-
-_rightbus {
- status = "okay";
-
- events {
- ppmu_rightbus_3: ppmu-event3-rightbus {
- event-name = "ppmu-event3-rightbus";
- };
- };
-};
-
{
clock-frequency = <2400>;
};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 395c3ca9601e..cda1ec86dfba 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -11,6 +11,7 @@
#include
#include
#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
#include
/ {
diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
new file mode 100644
index ..653904c5d479
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Device tree sources for Exynos4412 PPMU common device tree
+ *
+ * Copyright (c) 2015 Chanwoo Choi <cw00.c...@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+_dmc0 {
+ status = "okay";
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ };
+ };
+};
+
+_dmc1 {
+ status = "okay";
+
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = "ppmu-event3-dmc1";
+ };
+ };
+};
+
+_leftbus {
+ status = "okay";
+
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+
[PATCH v3 06/20] PM / devfreq: Add devfreq_get_devfreq_by_phandle()
This patch adds the new devfreq_get_devfreq_by_phandle() OF helper function
which can find the instance of devfreq device by using phandle ("devfreq").
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/devfreq.c | 44
include/linux/devfreq.h | 9 +
2 files changed, 53 insertions(+)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 15e58779e4c0..78ea4cdaa82c 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "governor.h"
static struct class *devfreq_class;
@@ -686,6 +687,49 @@ struct devfreq *devm_devfreq_add_device(struct device *dev,
}
EXPORT_SYMBOL(devm_devfreq_add_device);
+#ifdef CONFIG_OF
+/*
+ * devfreq_get_devfreq_by_phandle - Get the devfreq device from devicetree
+ * @dev - instance to the given device
+ * @index - index into list of devfreq
+ *
+ * return the instance of devfreq device
+ */
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+ struct device_node *node;
+ struct devfreq *devfreq;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ if (!dev->of_node)
+ return ERR_PTR(-EINVAL);
+
+ node = of_parse_phandle(dev->of_node, "devfreq", index);
+ if (!node)
+ return ERR_PTR(-ENODEV);
+
+ mutex_lock(_list_lock);
+ list_for_each_entry(devfreq, _list, node) {
+ if (devfreq->dev.parent
+ && devfreq->dev.parent->of_node == node) {
+ mutex_unlock(_list_lock);
+ return devfreq;
+ }
+ }
+ mutex_unlock(_list_lock);
+
+ return ERR_PTR(-EPROBE_DEFER);
+}
+#else
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+ return ERR_PTR(-ENODEV);
+}
+#endif /* CONFIG_OF */
+EXPORT_SYMBOL_GPL(devfreq_get_devfreq_by_phandle);
+
/**
* devm_devfreq_remove_device() - Resource-managed devfreq_remove_device()
* @dev: the device to add devfreq feature.
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 95c54578a1b4..cf972befca2b 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -211,6 +211,9 @@ extern int devm_devfreq_register_opp_notifier(struct device
*dev,
extern void devm_devfreq_unregister_opp_notifier(struct device *dev,
struct devfreq *devfreq);
+extern struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev,
+ int index);
+
/**
* devfreq_update_stats() - update the last_status pointer in struct devfreq
* @df:the devfreq instance whose status needs updating
@@ -322,6 +325,12 @@ static inline void
devm_devfreq_unregister_opp_notifier(struct device *dev,
{
}
+static inline struct devfreq *devfreq_get_devfreq_by_phandle(struct device
*dev,
+ int index)
+{
+ return ERR_PTR(-ENODEV);
+}
+
static inline int devfreq_update_stats(struct devfreq *df)
{
return -EINVAL;
--
1.9.1
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[PATCH v3 05/20] PM / devfreq: Add new passive governor
This patch adds the new passive governor for DEVFREQ framework. The following
governors are already present and used for DVFS (Dynamic Voltage and Frequency
Scaling) drivers. The following governors are independently used for one device
driver which don't give the influence to other device drviers and also don't
receive the effect from other device drivers.
- ondemand / performance / powersave / userspace
The passive governor depends on operation of parent driver with specific
governos extremely and is not able to decide the new frequency by oneself.
According to the decided new frequency of parent driver with governor,
the passive governor uses it to decide the appropriate frequency for own
device driver. The passive governor must need the following information
from device tree:
- the source clock and OPP tables
- the instance of parent device
For exameple,
there are one more devfreq device drivers which need to change their source
clock according to their utilization on runtime. But, they share the same
power line (e.g., regulator). So, specific device driver is operated as parent
with ondemand governor and then the rest device driver with passive governor
is influenced by parent device.
Suggested-by: Myungjoo Ham <myungjoo@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/Kconfig| 9
drivers/devfreq/Makefile | 1 +
drivers/devfreq/devfreq.c | 47
drivers/devfreq/governor_passive.c | 108 +
include/linux/devfreq.h| 15 ++
5 files changed, 180 insertions(+)
create mode 100644 drivers/devfreq/governor_passive.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 55ec774f794c..d03f635a93e1 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -64,6 +64,15 @@ config DEVFREQ_GOV_USERSPACE
Otherwise, the governor does not change the frequnecy
given at the initialization.
+config DEVFREQ_GOV_PASSIVE
+ tristate "Passive"
+ help
+ Sets the frequency by other governors (simple_ondemand, performance,
+ powersave, usersapce) of a parent devfreq device. This governor
+ always has the dependency on the chosen frequency from paired
+ governor. This governor does not change the frequency by oneself
+ through sysfs entry.
+
comment "DEVFREQ Drivers"
config ARM_EXYNOS_BUS_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 375ebbb4fcfb..f81c313b4b79 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +=
governor_simpleondemand.o
obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)+= governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
+obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
# DEVFREQ Drivers
obj-$(CONFIG_ARCH_EXYNOS) += exynos/
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 984c5e9e7bdd..15e58779e4c0 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -190,6 +190,31 @@ static struct devfreq_governor
*find_devfreq_governor(const char *name)
/* Load monitoring helper functions for governors use */
+static int update_devfreq_passive(struct devfreq *devfreq, unsigned long freq)
+{
+ struct devfreq *passive;
+ unsigned long rate;
+ int ret;
+
+ list_for_each_entry(passive, >passive_dev_list, passive_node) {
+ if (!passive->governor)
+ continue;
+ rate = freq;
+
+ ret = passive->governor->get_target_freq(passive, );
+ if (ret)
+ return ret;
+
+ ret = passive->profile->target(passive->dev.parent, , 0);
+ if (ret)
+ return ret;
+
+ passive->previous_freq = rate;
+ }
+
+ return 0;
+}
+
/**
* update_devfreq() - Reevaluate the device and configure frequency.
* @devfreq: the devfreq instance.
@@ -233,10 +258,18 @@ int update_devfreq(struct devfreq *devfreq)
flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */
}
+ if (!list_empty(>passive_dev_list)
+ && devfreq->previous_freq > freq)
+ update_devfreq_passive(devfreq, freq);
+
err = devfreq->profile->target(devfreq->dev.parent, , flags);
if (err)
return err;
+ if (!list_empty(>passive_dev_list)
+ && devfreq->previous_freq < freq)
+ update_devfreq_passive(devfreq, freq);
+
if (devfreq->profile->freq_table)
[PATCH v3 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
This patch adds the documentation for generic exynos bus frequency
driver.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 93 ++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
new file mode 100644
index ..e32daef328da
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,93 @@
+* Generic Exynos Bus frequency device
+
+The Samsung Exynos SoC have many buses for data transfer between DRAM
+and sub-blocks in SoC. Almost Exynos SoC have the common architecture
+for buses. Generally, the each bus of Exynos SoC includes the source clock
+and power line and then is able to change the clock according to the usage
+of each buses on runtime. When gathering the usage of each buses on runtime,
+the driver uses the PPMU (Platform Performance Monitoring Unit) which
+is able to measure the current load of sub-blocks.
+
+There are a little different composition among Exynos SoC because each Exynos
+SoC has the different sub-blocks. So, this difference should be specified
+in devicetree file instead of each device driver. In result, this driver
+is able to support the bus frequency for all Exynos SoCs.
+
+Required properties for bus device:
+- compatible: Should be "samsung,exynos-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- operating-points-v2: the OPP table including frequency/voltage information
+ to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- vdd-supply: the regulator to provide the buses with the voltage.
+- devfreq-events: the devfreq-event device to monitor the current utilization
+ of buses.
+
+Optional properties for bus device:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+ the performance count against total cycle count.
+
+Example1:
+ Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
+ power line (regulator). The MIF (Memory Interface) AXI bus is used to
+ transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
+
+ - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+
+ - MIF bus's frequency/voltage table
+ ---
+ |Lv| Freq | Voltage |
+ ---
+ |L1| 5 |80 |
+ |L2| 10 |80 |
+ |L3| 134000 |80 |
+ |L4| 20 |825000 |
+ |L5| 40 |875000 |
+ ---
+
+Example2 :
+ The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
+ is listed below:
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@5000 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp@13400 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <80>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <825000>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
+
+ Usage case to handle the frequency and voltage of bus on runtime
+ in exynos3250-rinato.dts is listed below:
+
+ _dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>; /* VDD_MIF */
+ status = "okay";
+ };
--
1.9.1
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[PATCH v3 07/20] PM / devfreq: Show the related information according to governor type
This patch modifies the following sysfs entry of DEVFREQ framework
because the devfreq device using passive governor don't need the same
information of the devfreq device using rest governor.
- polling_interval: passive gov don't use the sampling rate.
- available_governors : passive gov don't be changed on runtime in this version.
- trans_stat : passive governor don't support trans_stat in this
version.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
[linux.amoon: Tested on Odroid U3]
Tested-by: Anand Moon <linux.am...@gmail.com>
---
drivers/devfreq/devfreq.c | 31 +--
drivers/devfreq/governor.h| 7 +++
drivers/devfreq/governor_passive.c| 1 +
drivers/devfreq/governor_performance.c| 1 +
drivers/devfreq/governor_powersave.c | 1 +
drivers/devfreq/governor_simpleondemand.c | 1 +
drivers/devfreq/governor_userspace.c | 1 +
include/linux/devfreq.h | 2 ++
8 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 78ea4cdaa82c..18ad956fec93 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -597,7 +597,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
goto err_init;
}
- if (!strncmp(devfreq->governor_name, "passive", 7)) {
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
struct devfreq *parent_devfreq =
((struct devfreq_passive_data *)data)->parent;
@@ -963,13 +963,23 @@ static ssize_t available_governors_show(struct device *d,
struct device_attribute *attr,
char *buf)
{
- struct devfreq_governor *tmp_governor;
+ struct devfreq *devfreq = to_devfreq(d);
ssize_t count = 0;
mutex_lock(_list_lock);
- list_for_each_entry(tmp_governor, _governor_list, node)
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
count += scnprintf([count], (PAGE_SIZE - count - 2),
- "%s ", tmp_governor->name);
+ "%s ", devfreq->governor->name);
+ } else {
+ struct devfreq_governor *tmp_governor;
+
+ list_for_each_entry(tmp_governor, _governor_list, node)
{
+ if (tmp_governor->type == DEVFREQ_GOV_PASSIVE)
+ continue;
+ count += scnprintf([count], (PAGE_SIZE - count - 2),
+ "%s ", tmp_governor->name);
+ }
+ }
mutex_unlock(_list_lock);
/* Truncate the trailing space */
@@ -1006,6 +1016,11 @@ static DEVICE_ATTR_RO(target_freq);
static ssize_t polling_interval_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
+ struct devfreq *df = to_devfreq(dev);
+
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
return sprintf(buf, "%d\n", to_devfreq(dev)->profile->polling_ms);
}
@@ -1020,6 +1035,9 @@ static ssize_t polling_interval_store(struct device *dev,
if (!df->governor)
return -EINVAL;
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return -EINVAL;
+
ret = sscanf(buf, "%u", );
if (ret != 1)
return -EINVAL;
@@ -1137,11 +1155,12 @@ static ssize_t trans_stat_show(struct device *dev,
int i, j;
unsigned int max_state = devfreq->profile->max_state;
+ if (max_state == 0 || devfreq->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
if (!devfreq->stop_polling &&
devfreq_update_status(devfreq, devfreq->previous_freq))
return 0;
- if (max_state == 0)
- return sprintf(buf, "Not Supported.\n");
len = sprintf(buf, " From : To\n");
len += sprintf(buf + len, " :");
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index fad7d6321978..43513a58f5bf 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -18,6 +18,13 @@
#define to_devfreq(DEV)container_of((DEV), struct devfreq, dev)
+/* Devfreq governor type */
+#define DEVFREQ_GOV_ONDEMAND 0x1
+#define DEVFREQ_GOV_PERFORMANCE0x2
+#define DEVFREQ_GOV_POWERSAVE 0x3
+#define DEVFREQ_GOV_USERSPACE 0x4
+#define DEVFREQ_GOV_PASSIVE0x4
+
/* Devfreq events */
#define DEVFREQ_GOV
[PATCH v3 00/20] PM / devferq: Add generic exynos bus frequency driver and new passive governor
t;_reg>; /* VDD_MIF */
status = "okay";
};
2. Add new passive governor of DEVFREQ framework (patch5-patch7)
: This patch-set add the new passive governor for DEVFREQ framework.
The existing governors (ondemand, performance and so on) are used for DVFS
(Dynamic Voltage and Frequency Scaling) drivers. The existing governors
are independently used for specific device driver which don't give the
influence to other device drviers and also don't receive the effect from
other device drivers.
The passive governor depends on operation of parent driver with existing
governors(ondemand, performance and so on) extremely and is not able to
decide the new frequency by oneself. According to the decided new frequency
of parent driver with governor, the passive governor uses it to decide
the appropriate frequency for own device driver. The passive governor
must need the following information from device tree:
For exameple,
There are one more bus device drivers in Exynos3250 which need to
change their source clock according to their utilization on runtime.
But, they share the same power line (e.g., regulator). So, LEFTBUS bus
driver is operated as parent with ondemand governor and then the rest
device driver with passive governor.
The buses of Internal block in exynos3250.dtsi are listed below:
When LEFTBUS bus driver (parent) changes the bus frequency with
ondemand governor on runtime, the rest bus devices which sharing
the same power line (VDD_INT) will change the each bus frequency
according to the decision of LEFTBUS bus driver (parent).
- INT (Internal) block
: VDD_INT |--- LEFTBUS
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAM
- The buss of INT block in exynos3250.dtsi are listed below:
bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDL>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
bus_rightbus: bus_rightbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDR>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
(Omit the rest bus dt node)
- Usage case to handle the frequency and voltage of bus on runtime
in exynos3250-rinato.dts are listed below:
/* Parent bus device of VDD_INT */
_leftbus {
devfreq-events = <_leftbus_3>, <_rightbus_3>;
vdd-supply = <_reg>;
status = "okay";
};
/* Passive bus device depend on LEFTBUS bus. */
_rightbus {
devfreq = <_leftbus>; /* 'devfreq' property indicates
the phandle of parent device. */
status = "okay";
};
(Omit the rest bus dt node)
Chanwoo Choi (20):
PM / devfreq: exynos: Add generic exynos bus frequency driver
PM / devfreq: exynos: Add documentation for generic exynos bus frequency
driver
ARM: dts: Add DMC bus node for Exynos3250
ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
PM / devfreq: Add new passive governor
PM / devfreq: Add devfreq_get_devfreq_by_phandle()
PM / devfreq: Show the related information according to governor type
PM / devfreq: exynos: Add support of bus frequency of sub-blocks using
passive governor
PM / devfreq: exynos: Update documentation for bus devices using passive
governor
PM / devfreq: exynos: Add the detailed correlation between sub-blocks and
power line
PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
MAINTAINERS: Add samsung bus frequency driver entry
ARM: dts: Add bus nodes using VDD_INT for Exynos3250
ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
ARM: dts: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU node
ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
ARM: dts: Expand the voltage range of buck1/3 regulator for
exynos4412-odroidu3
ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
.../devicetree/bindings/devfreq/exynos-bus.txt | 388 +++
MAINTAINERS|9 +
arch/arm/boot/dts/exynos3250-monk.dts | 47 +-
arch/arm/boot/dts/exynos3250-rinato.dts| 88 +-
arch/arm/boot/dts/exynos3250.dtsi | 181
arch/arm/boot/dts/exynos4210.dtsi
Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
On Thu, Dec 10, 2015 at 11:21 PM, Rob Herring <r...@kernel.org> wrote:
> On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote:
>> This patch updates the documentation for passive bus devices and adds the
>> detailed example of Exynos3250.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> .../devicetree/bindings/devfreq/exynos-bus.txt | 244
>> -
>> 1 file changed, 241 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> index 54a1f9c46c88..c4fdc70f8eac 100644
>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference
>> should be specified
>> in devicetree file instead of each device driver. In result, this driver
>> is able to support the bus frequency for all Exynos SoCs.
>>
>> -Required properties for bus device:
>> +Required properties for all bus devices:
>> - compatible: Should be "samsung,exynos-bus".
>> - clock-names : the name of clock used by the bus, "bus".
>> - clocks : phandles for clock specified in "clock-names" property.
>> - #clock-cells: should be 1.
>> - operating-points-v2: the OPP table including frequency/voltage information
>>to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +
>> +Required properties for only parent bus device:
>> - vdd-supply: the regulator to provide the buses with the voltage.
>> - devfreq-events: the devfreq-event device to monitor the curret utilization
>>of buses.
>>
>> -Optional properties for bus device:
>> +Required properties for only passive bus device:
>> +- devfreq: the parent bus device.
>> +
>> +Optional properties for only parent bus device:
>> - exynos,saturation-ratio: the percentage value which is used to calibrate
>> the performance count againt total cycle count.
>>
>> @@ -33,7 +38,20 @@ Example1:
>> power line (regulator). The MIF (Memory Interface) AXI bus is used to
>> transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>>
>> - - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>> + - MIF (Memory Interface) block
>> + : VDD_MIF |--- DMC (Dynamic Memory Controller)
>> +
>> + - INT (Internal) block
>> + : VDD_INT |--- LEFTBUS (parent device)
>> + |--- PERIL
>> + |--- MFC
>> + |--- G3D
>> + |--- RIGHTBUS
>> + |--- FSYS
>> + |--- LCD0
>> + |--- PERIR
>> + |--- ISP
>> + |--- CAM
>
> This still has the same problem as before. I would expect that the bus
> hierarchy in the dts match the hierarchy here. You just have flat nodes
> in the example below. So all IP blocks affected by frequency scaling
> should be under the bus node defining the OPPs. Something like this:
The each bus of sub-block has not h/w dependency among sub-blocks
and has the owned source clock / OPP table. Just they share the same
power line. So, I think that flat nodes in the example below is not problem.
Because of using the same power line, the sub-blocks would be tied
by devfreq framework only for the behavior of bus frequency scaling .
>
> soc {
> compatible = "simple-bus";
> bus {
> compatible = "my-awesome-dvfs-bus"; /* simple-bus too if
> no setup needed first */
> reg = <0x0 0x0>; // Bus control registers
> clocks = < BUS_CLK>;
> operating-points-v2 = <>;
> device@0 {
> compatible = "my-awesome-device-1";
> };
> device@1 {
> compatible = "my-awesome-device-2";
> };
> };
> };
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Re: [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
On 2015년 12월 10일 09:53, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the DMC (Dynamic Memory Controller) bus frequency node
>> which includes the devfreq-events and regulator properties. The bus
>> frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
>> with ondemand governor.
>>
>> The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
>> on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
>> the DMC block.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos3250-monk.dts | 6 ++
>> arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++
>> 2 files changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
>> b/arch/arm/boot/dts/exynos3250-monk.dts
>> index 443a35085846..d982586a6533 100644
>> --- a/arch/arm/boot/dts/exynos3250-monk.dts
>> +++ b/arch/arm/boot/dts/exynos3250-monk.dts
>> @@ -498,6 +498,12 @@
>> };
>> };
>>
>> +_dmc {
>> +devfreq-events = <_dmc0_3>, <_dmc1_3>;
>> +vdd-supply = <_reg>;
>> +status = "okay";
>> +};
>> +
>> {
>> clock-frequency = <2400>;
>> };
>> diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
>> b/arch/arm/boot/dts/exynos3250-rinato.dts
>> index 3e64d5dcdd60..61477943015b 100644
>> --- a/arch/arm/boot/dts/exynos3250-rinato.dts
>> +++ b/arch/arm/boot/dts/exynos3250-rinato.dts
>> @@ -675,6 +675,12 @@
>> };
>> };
>>
>> +_dmc {
>> +devfreq-events = <_dmc0_3>, <_dmc1_3>;
>> +vdd-supply = <_reg>;
>> + status = "okay";
>> +};
>
> I would prefer to put this in alphabetical order... which could be
> tricky because the nodes are not entirely sorted. Maybe after the ""
> node?
OK. I'll move it.
>
> Anyway the change looks good:
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Thanks for your review.
Regards,
Chanwoo Choi
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Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250
>> SoC.
>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>> block.
>>
>> Following list specifies the detailed relation between the clock and DMC
>> block:
>> - The source clock of DMC block : div_dmc
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos3250.dtsi | 34 ++
>> 1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
>> b/arch/arm/boot/dts/exynos3250.dtsi
>> index 2f30d632f1cc..7214c5e42150 100644
>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -687,6 +687,40 @@
>> clock-names = "ppmu";
>> status = "disabled";
>> };
>> +
>> +bus_dmc: bus_dmc {
>> +compatible = "samsung,exynos-bus";
>> +clocks = <_dmc CLK_DIV_DMC>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_dmc_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_dmc_opp_table: opp_table1 {
>
> This is the firsy opp_table, right? So:
> s/opp_table1/opp_table0/
Right. It is first opp_table in exynos3250.dtsi.
But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.
>
>> +compatible = "operating-points-v2";
>> +opp-shared;
>> +
>> +opp00 {
>> +opp-hz = /bits/ 64 <5000>;
>> +opp-microvolt = <80>;
>> +};
>> +opp01 {
>> +opp-hz = /bits/ 64 <1>;
>> +opp-microvolt = <80>;
>> +};
>> +opp02 {
>> +opp-hz = /bits/ 64 <13400>;
>> +opp-microvolt = <80>;
>
> Why 134, not 133 MHz?
When I used the 13300, the source clock is changed to 100Mhz instead of
133MHz.
I add following test result on exynos3250-rinato board.
Case1.
When I use the 134 MHz, the source clock is changed to 133MHz
: exynos-bus soc:bus_dmc: old_freq(2) -> new_freq (13400) (real:
13334)
Case2.
When I use the 133 MHz, the source clock is changed to 100MHz
: exynos-bus soc:bus_dmc: old_freq(2) -> new_freq (13300) (real:
1)
>
>> +};
>> +opp03 {
>> +opp-hz = /bits/ 64 <2>;
>> +opp-microvolt = <80>;
>
> Shouldn't this be 825 mV, not 800? I think we used previously that value
> for our devices.
OK. I'll modify it.
Regards,
Chanwoo Choi
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Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
> On 10.12.2015 10:09, Chanwoo Choi wrote:
>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for
>>>> Exynos3250 SoC.
>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>>>> block.
>>>>
>>>> Following list specifies the detailed relation between the clock and DMC
>>>> block:
>>>> - The source clock of DMC block : div_dmc
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>>>> ---
>>>> arch/arm/boot/dts/exynos3250.dtsi | 34 ++
>>>> 1 file changed, 34 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
>>>> b/arch/arm/boot/dts/exynos3250.dtsi
>>>> index 2f30d632f1cc..7214c5e42150 100644
>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>>> @@ -687,6 +687,40 @@
>>>>clock-names = "ppmu";
>>>>status = "disabled";
>>>>};
>>>> +
>>>> + bus_dmc: bus_dmc {
>>>> + compatible = "samsung,exynos-bus";
>>>> + clocks = <_dmc CLK_DIV_DMC>;
>>>> + clock-names = "bus";
>>>> + operating-points-v2 = <_dmc_opp_table>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + bus_dmc_opp_table: opp_table1 {
>>>
>>> This is the firsy opp_table, right? So:
>>> s/opp_table1/opp_table0/
>>
>> Right. It is first opp_table in exynos3250.dtsi.
>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
>> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.
>
> Ok
>
>>
>>>
>>>> + compatible = "operating-points-v2";
>>>> + opp-shared;
>>>> +
>>>> + opp00 {
>>>> + opp-hz = /bits/ 64 <5000>;
>>>> + opp-microvolt = <80>;
>>>> + };
>>>> + opp01 {
>>>> + opp-hz = /bits/ 64 <1>;
>>>> + opp-microvolt = <80>;
>>>> + };
>>>> + opp02 {
>>>> + opp-hz = /bits/ 64 <13400>;
>>>> + opp-microvolt = <80>;
>>>
>>> Why 134, not 133 MHz?
>>
>> When I used the 13300, the source clock is changed to 100Mhz instead of
>> 133MHz.
>> I add following test result on exynos3250-rinato board.
>>
>> Case1.
>> When I use the 134 MHz, the source clock is changed to 133MHz
>> : exynos-bus soc:bus_dmc: old_freq(2) -> new_freq (13400) (real:
>> 13334)
>>
>> Case2.
>> When I use the 133 MHz, the source clock is changed to 100MHz
>> : exynos-bus soc:bus_dmc: old_freq(2) -> new_freq (13300) (real:
>> 1)
>
> Now I remember that issue. You could use here directly 13334 but
> that also would look a little bit weird... so 134 is ok for me. Could
> just add a comment that desired frequency is actually "133 MHz"?
Do you prefer among following example?
Example1.
opp02 {
/* The desired frequency is 133MHz because
* clock change has the dependency on clock driver.
* When set rate as 134MHz, the clock driver would
* change the 133MHz actually instead of 134MHz.
*/
opp-hz = /bits/ 64 <13400>;
opp-microvolt = <80>;
};
Example2.
opp02 {
opp-hz = /bits/ 64 <13334>;
opp-microvolt = <80>;
};
Best Regards,
Chanwoo Choi
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Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
On 2015년 12월 10일 11:04, Krzysztof Kozlowski wrote:
> On 10.12.2015 11:00, Chanwoo Choi wrote:
>> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 10:09, Chanwoo Choi wrote:
>>>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for
>>>>>> Exynos3250 SoC.
>>>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC
>>>>>> standard
>>>>>> SDRAM devices. The bus includes the OPP tables and the source clock for
>>>>>> DMC
>>>>>> block.
>>>>>>
>>>>>> Following list specifies the detailed relation between the clock and DMC
>>>>>> block:
>>>>>> - The source clock of DMC block : div_dmc
>>>>>>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>>>>>> ---
>>>>>> arch/arm/boot/dts/exynos3250.dtsi | 34
>>>>>> ++
>>>>>> 1 file changed, 34 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> b/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> index 2f30d632f1cc..7214c5e42150 100644
>>>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> @@ -687,6 +687,40 @@
>>>>>> clock-names = "ppmu";
>>>>>> status = "disabled";
>>>>>> };
>>>>>> +
>>>>>> +bus_dmc: bus_dmc {
>>>>>> +compatible = "samsung,exynos-bus";
>>>>>> +clocks = <_dmc CLK_DIV_DMC>;
>>>>>> +clock-names = "bus";
>>>>>> +operating-points-v2 = <_dmc_opp_table>;
>>>>>> +status = "disabled";
>>>>>> +};
>>>>>> +
>>>>>> +bus_dmc_opp_table: opp_table1 {
>>>>>
>>>>> This is the firsy opp_table, right? So:
>>>>> s/opp_table1/opp_table0/
>>>>
>>>> Right. It is first opp_table in exynos3250.dtsi.
>>>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
>>>> So, I have the plan that support the operation-points-v2 for Exynos3250
>>>> CPU.
>>>
>>> Ok
>>>
>>>>
>>>>>
>>>>>> +compatible = "operating-points-v2";
>>>>>> +opp-shared;
>>>>>> +
>>>>>> +opp00 {
>>>>>> +opp-hz = /bits/ 64 <5000>;
>>>>>> +opp-microvolt = <80>;
>>>>>> +};
>>>>>> +opp01 {
>>>>>> +opp-hz = /bits/ 64 <1>;
>>>>>> +opp-microvolt = <80>;
>>>>>> +};
>>>>>> +opp02 {
>>>>>> +opp-hz = /bits/ 64 <13400>;
>>>>>> +opp-microvolt = <80>;
>>>>>
>>>>> Why 134, not 133 MHz?
>>>>
>>>> When I used the 13300, the source clock is changed to 100Mhz instead
>>>> of 133MHz.
>>>> I add following test result on exynos3250-rinato board.
>>>>
>>>> Case1.
>>>> When I use the 134 MHz, the source clock is changed to 133MHz
>>>> : exynos-bus soc:bus_dmc: old_freq(2) -> new_freq (13400)
>>>> (real: 13334)
>>>>
>>>> Case2.
>>>> When I use the 133 MHz, the source clock is changed to 100MHz
>>>> : exynos-bus soc:bus_dmc: old_freq(2) -> new_freq (13300)
>>>> (real: 1)
>>>
>>> Now I remember that issue. You could use here directly 13334 but
>>> that also would look a little bit weird... so 134 is ok for me. Could
>>> just add a comment that desired frequency is actually "133 MHz"?
>>
>> Do you prefer among following example?
>>
>> Example1.
>> opp02 {
>> /* The desired frequency is 133MHz because
>> * clock change has the dependency on clock driver.
>> * When set rate as 134MHz, the clock driver would
>> * change the 133MHz actually instead of 134MHz.
>> */
>> opp-hz = /bits/ 64 <13400>;
>> opp-microvolt = <80>;
>> };
>>
>> Example2.
>> opp02 {
>> opp-hz = /bits/ 64 <13334>;
>> opp-microvolt = <80>;
>> };
>
> I would prefer the second one (13334) but I don't have strong
> feelings about it.
If you ok, I want to maintain the original approach as following:
opp02 {
opp-hz = /bits/ 64 <13400>;
opp-microvolt = <80>;
};
Best Regards,
Chanwoo Choi
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Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
On 2015년 12월 10일 10:22, Krzysztof Kozlowski wrote: > On 10.12.2015 09:57, Krzysztof Kozlowski wrote: >> On 09.12.2015 13:07, Chanwoo Choi wrote: >> >> (...) >> >>> .../devicetree/bindings/devfreq/exynos-bus.txt | 383 +++ >> >> How about adding this file to the MAINTAINERS to devfreq exynos entry? OK. I'll add new entry for 'devfreq exynos' as following: +SAMSUNG BUS DEVICE FREQUENCY SUPPORT +M: Chanwoo Choi <cw00.c...@samsung.com> +L: linux...@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git +S: Supported +F: drivers/devfreq/exynos/exynos-bus.c +F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> Unfortunately, in current linux-next, I can find the entry for devfreq > > D'oh! I meant:^ I cannot find the entry for... > > BR, > Krzysztof > >> exynos. However I saw patches adding such entries... aren't they merged >> to linux-next? Yes, it is not merged to linux-next because any git repository don't apply this patchset. To merge the devfreq patchset to linux-next, devfreq maintainer should send the request mail to Stephen Rothwell. [snip] Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
On 2015년 12월 10일 10:25, Krzysztof Kozlowski wrote:
> On 10.12.2015 09:49, Chanwoo Choi wrote:
>> Hi,
>>
> (...)
>
>>>
>>>> +
>>>> + bus_dmc: bus_dmc {
>>>> + compatible = "samsung,exynos-bus";
>>>> + clocks = <_dmc CLK_DIV_DMC>;
>>>> + clock-names = "bus";
>>>> + operating-points-v2 = <_dmc_opp_table>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + bus_dmc_opp_table: opp_table0 {
>>>> + compatible = "operating-points-v2";
>>>> + opp-shared;
>>>> +
>>>> + opp00 {
>>>
>>> Maybe use convention with frequency, like:
>>> opp@5000
>>> This also used in opp.txt examples.
>>
>> In the Documentations/devicetree/bindings/opp/opp.txt,
>> the example uses the 'opp@0x'. I check the opp.txt of Linux 4.4-rc4.
>
> Yes, it was changed by Viresh in "PM / OPP: Rename OPP nodes as
> opp@". You can find the most actual bindings in linux-next.
OK. I'll.
Best Regards,
Chanwoo Choi
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Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
On 2015년 12월 10일 10:31, Krzysztof Kozlowski wrote: > On 09.12.2015 13:08, Chanwoo Choi wrote: >> This patch updates the documentation for passive bus devices and adds the >> detailed example of Exynos3250. >> >> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >> --- >> .../devicetree/bindings/devfreq/exynos-bus.txt | 244 >> - >> 1 file changed, 241 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> index 54a1f9c46c88..c4fdc70f8eac 100644 >> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference >> should be specified >> in devicetree file instead of each device driver. In result, this driver >> is able to support the bus frequency for all Exynos SoCs. >> >> -Required properties for bus device: >> +Required properties for all bus devices: >> - compatible: Should be "samsung,exynos-bus". >> - clock-names : the name of clock used by the bus, "bus". >> - clocks : phandles for clock specified in "clock-names" property. >> - #clock-cells: should be 1. >> - operating-points-v2: the OPP table including frequency/voltage information >>to support DVFS (Dynamic Voltage/Frequency Scaling) feature. >> + >> +Required properties for only parent bus device: > > Maybe: > "Required properties only for parent bus devices:" OK. I'll modify it. > > In this binding documentation file the idea of "parent" is not > explained. I now it is related to passive devfreq governor but looking > at the binding itself it is a new idea, not covered here. OK. I'll add the detailed description of 'parent' and correlation between 'parent' and 'passive' device. > >> - vdd-supply: the regulator to provide the buses with the voltage. >> - devfreq-events: the devfreq-event device to monitor the curret utilization >>of buses. >> >> -Optional properties for bus device: >> +Required properties for only passive bus device: > > "Required properties only for passive bus devices:" OK. I'll modify it. > >> +- devfreq: the parent bus device. >> + >> +Optional properties for only parent bus device: >> - exynos,saturation-ratio: the percentage value which is used to calibrate >> the performance count againt total cycle count. >> >> @@ -33,7 +38,20 @@ Example1: >> power line (regulator). The MIF (Memory Interface) AXI bus is used to >> transfer data between DRAM and CPU and uses the VDD_MIF regualtor. >> >> -- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block >> +- MIF (Memory Interface) block >> +: VDD_MIF |--- DMC (Dynamic Memory Controller) >> + >> +- INT (Internal) block >> +: VDD_INT |--- LEFTBUS (parent device) >> + |--- PERIL >> + |--- MFC >> + |--- G3D >> + |--- RIGHTBUS >> + |--- FSYS >> + |--- LCD0 >> + |--- PERIR >> + |--- ISP >> + |--- CAM >> >> - MIF bus's frequency/voltage table >> --- >> @@ -46,6 +64,24 @@ Example1: >> |L5| 40 |875000 | >> --- >> >> +- INT bus's frequency/voltage table >> +-- >> +|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP|PERIL ||VDD_INT | >> +| name| |LCD0| | | ||| >> +| | |FSYS| | | ||| >> +| | |MFC | | | ||| >> +-- >> +|Mode |*parent|passive |passive|passive|passive||| >> +-- >> +|Lv |Frequency ||Voltage | >> +-- >> +|L1 |5 |5 |5 |5 |5 ||90 | >> +|L2 |8 |8 |8 |8 |8 ||90 | >> +|L3 |10 |10 |10 |10 |10 ||100 | >> +|L4 |134000 |134000 |20 |20 | ||100 | >> +|L5 |20 |20 |40
Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
Hi,
On 2015년 12월 10일 09:39, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the documentation for generic exynos bus frequency
>> driver.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> .../devicetree/bindings/devfreq/exynos-bus.txt | 94
>> ++
>> 1 file changed, 94 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> new file mode 100644
>> index ..54a1f9c46c88
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -0,0 +1,94 @@
>> +* Generic Exynos Bus frequency device
>> +
>> +The Samsung Exynos SoC have many buses for data transfer between DRAM
>> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture
>> +for buses. Generally, the each bus of Exynos SoC includes the source clock
>> +and power line and then is able to change the clock according to the usage
>> +of each buses on runtime. When gathering the usage of each buses on runtime,
>> +thie driver uses the PPMU (Platform Performance Monitoring Unit) which
>
> s/thie/the/
OK.
>
>> +is able to measure the current load of sub-blocks.
>> +
>> +There are a little different composition among Exynos SoC because each
>> Exynos
>> +SoC has the different sub-blocks. So, this difference should be specified
>> +in devicetree file instead of each device driver. In result, this driver
>> +is able to support the bus frequency for all Exynos SoCs.
>> +
>> +Required properties for bus device:
>> +- compatible: Should be "samsung,exynos-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- #clock-cells: should be 1.
>
> This is a clock consumer, right? So the clock-cells is not valid here.
You're right. I'll remove '#clock-cells'.
>
>> +- operating-points-v2: the OPP table including frequency/voltage information
>> + to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +- vdd-supply: the regulator to provide the buses with the voltage.
>> +- devfreq-events: the devfreq-event device to monitor the curret utilization
>
> s/curret/current/
>
>> + of buses.
>> +
>> +Optional properties for bus device:
>> +- exynos,saturation-ratio: the percentage value which is used to calibrate
>> + the performance count againt total cycle count.
>
> s/againt/against/
OK.
>
>> +
>> +Example1:
>> +Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
>> +power line (regulator). The MIF (Memory Interface) AXI bus is used to
>> +transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>> +
>> +- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>> +
>> +- MIF bus's frequency/voltage table
>> +---
>> +|Lv| Freq | Voltage |
>> +---
>> +|L1| 5 |80 |
>> +|L2| 10 |80 |
>> +|L3| 134000 |80 |
>> +|L4| 20 |80 |
>> +|L5| 40 |875000 |
>> +---
>> +
>> +Example2 :
>> +The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
>> +are listed below:
>
> s/are/is/ (one bus is listed)
OK.
>
>> +
>> +bus_dmc: bus_dmc {
>> +compatible = "samsung,exynos-bus";
>> +clocks = <_dmc CLK_DIV_DMC>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_dmc_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_dmc_opp_table: opp_table0 {
>> +compatible = "operating-points-v2";
>> +opp-shared;
>> +
>> +opp00 {
>
> Maybe use convention with frequency, like:
> opp@5000
> This also used in opp.txt examples.
In the Documentations/devicetree/bindings/opp/opp.txt,
the example uses the 'opp@0x'. I check the opp.txt of Linux 4.4-rc4.
>
>
>> +opp-hz = /bits/ 64 <5000>;
>> +opp-microvolt = <80>;
>> +};
>> +opp01 {
>> +opp-hz =
Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
Hi Anand,
First of all, thanks for trying to test this series.
On 2015년 12월 10일 04:05, Anand Moon wrote:
> Hi Chanwoo Choi,
>
> On 9 December 2015 at 09:37, Chanwoo Choi <cw00.c...@samsung.com> wrote:
>> This patch-set includes the two features as following. The generic exynos bus
>> frequency driver is able to support almost Exynos SoCs for bus frequency
>> scaling. And the new passive governor is able to make the dependency on
>> between devices for frequency/voltage scaling. I had posted the patch-set[1]
>> with the similiar concept. This is is revised version for exynos bus
>> frequency.
>> - Generic exynos bus frequency driver
>> - New passive governor of DEVFREQ framework
>>
>> Depends on:
>> - This patch-set is based on devfreq.git[2].
>> [1] https://lkml.org/lkml/2015/1/7/872
>>: [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
>> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch:
>> for-rafael)
>>
>> Changes from v1:
>> (https://lkml.org/lkml/2015/11/26/260)
>> - Check whether the instance of regulator is NULL or not
>> when executing regulator_disable() because of only parent
>> devfreq device has the regulator instance. After fixing it,
>> the wake-up from suspend state is well working. (patch1)
>> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>> after calling devm_clk_get() (on patch1)
>> - Update the documentation to remove the description about
>> DEVFREQ-EVENT subsystem (on patch2)
>> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
>> - Modify the detailed correlation of buses for Exynos3250
>> on documentation (patch2)
>> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
>> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
>> - Add the PPMU node for exynos4412-odroidu3
>> - Add the support of bus frequency for exynos4412-odroidu3
>>
>> Detailed descirption for patch-set:
>> 1. Add generic exynos bus frequency driver
>> : This patch-set adds the generic exynos bus frequency driver for AXI bus
>> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
>> architecture for bus between DRAM and sub-blocks in SoC.
>>
>> There are the different buses according to Exynos SoC because Exynos SoC
>> has the differnt sub-blocks and bus speed. In spite of this difference
>> among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
>> unique data of each bus in the devicetree file.
>>
>> In devicetree, each bus node has a bus clock, regulator, operation-point
>> and devfreq-event devices which measure the utilization of each bus block.
>>
>> For example,
>> - The bus of DMC block in exynos3250.dtsi are listed below:
>>
>> bus_dmc: bus_dmc {
>> compatible = "samsung,exynos-bus";
>> clocks = <_dmc CLK_DIV_DMC>;
>> clock-names = "bus";
>> operating-points-v2 = <_dmc_opp_table>;
>> status = "disabled";
>> };
>>
>> bus_dmc_opp_table: opp_table0 {
>> compatible = "operating-points-v2";
>> opp-shared;
>>
>> opp00 {
>> opp-hz = /bits/ 64 <5000>;
>> opp-microvolt = <80>;
>> };
>> opp01 {
>> opp-hz = /bits/ 64 <1>;
>> opp-microvolt = <80>;
>> };
>> opp02 {
>> opp-hz = /bits/ 64 <13400>;
>> opp-microvolt = <80>;
>> };
>> opp03 {
>> opp-hz = /bits/ 64 <2>;
>> opp-microvolt = <80>;
>> };
>> opp04 {
>> opp-hz = /bits/ 64 <4>;
>> opp-microvolt = <875000>;
>> };
>> };
>>
>> - Usage case to handle the frequency and voltage of bus on runtime
>> in exynos3250-rinato.dts are listed below:
>>
>> _dmc {
>> devfreq-events = <_dmc0_3>, <_dmc1_3>;
>> vdd-supply = <_reg>; /* VDD_MIF */
>> status = "okay";
>> };
>>
Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
Hi Anand,
On 2015년 12월 10일 13:14, Anand Moon wrote:
> Hi Chanwoo Choi,
>
> On 10 December 2015 at 05:42, Chanwoo Choi <cw00.c...@samsung.com> wrote:
>> Hi Anand,
>>
>> First of all, thanks for trying to test this series.
>>
>> On 2015년 12월 10일 04:05, Anand Moon wrote:
>>> Hi Chanwoo Choi,
>>>
>>> On 9 December 2015 at 09:37, Chanwoo Choi <cw00.c...@samsung.com> wrote:
>>>> This patch-set includes the two features as following. The generic exynos
>>>> bus
>>>> frequency driver is able to support almost Exynos SoCs for bus frequency
>>>> scaling. And the new passive governor is able to make the dependency on
>>>> between devices for frequency/voltage scaling. I had posted the
>>>> patch-set[1]
>>>> with the similiar concept. This is is revised version for exynos bus
>>>> frequency.
>>>> - Generic exynos bus frequency driver
>>>> - New passive governor of DEVFREQ framework
>>>>
>>>> Depends on:
>>>> - This patch-set is based on devfreq.git[2].
>>>> [1] https://lkml.org/lkml/2015/1/7/872
>>>>: [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
>>>> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch:
>>>> for-rafael)
>>>>
>>>> Changes from v1:
>>>> (https://lkml.org/lkml/2015/11/26/260)
>>>> - Check whether the instance of regulator is NULL or not
>>>> when executing regulator_disable() because of only parent
>>>> devfreq device has the regulator instance. After fixing it,
>>>> the wake-up from suspend state is well working. (patch1)
>>>> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>>>> after calling devm_clk_get() (on patch1)
>>>> - Update the documentation to remove the description about
>>>> DEVFREQ-EVENT subsystem (on patch2)
>>>> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
>>>> - Modify the detailed correlation of buses for Exynos3250
>>>> on documentation (patch2)
>>>> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
>>>> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
>>>> - Add the PPMU node for exynos4412-odroidu3
>>>> - Add the support of bus frequency for exynos4412-odroidu3
>>>>
>>>> Detailed descirption for patch-set:
>>>> 1. Add generic exynos bus frequency driver
>>>> : This patch-set adds the generic exynos bus frequency driver for AXI bus
>>>> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
>>>> architecture for bus between DRAM and sub-blocks in SoC.
>>>>
>>>> There are the different buses according to Exynos SoC because Exynos SoC
>>>> has the differnt sub-blocks and bus speed. In spite of this difference
>>>> among Exynos SoCs, this driver is able to support almost Exynos SoC by
>>>> adding
>>>> unique data of each bus in the devicetree file.
>>>>
>>>> In devicetree, each bus node has a bus clock, regulator, operation-point
>>>> and devfreq-event devices which measure the utilization of each bus block.
>>>>
>>>> For example,
>>>> - The bus of DMC block in exynos3250.dtsi are listed below:
>>>>
>>>> bus_dmc: bus_dmc {
>>>> compatible = "samsung,exynos-bus";
>>>> clocks = <_dmc CLK_DIV_DMC>;
>>>> clock-names = "bus";
>>>> operating-points-v2 = <_dmc_opp_table>;
>>>> status = "disabled";
>>>> };
>>>>
>>>> bus_dmc_opp_table: opp_table0 {
>>>> compatible = "operating-points-v2";
>>>> opp-shared;
>>>>
>>>> opp00 {
>>>> opp-hz = /bits/ 64 <5000>;
>>>> opp-microvolt = <80>;
>>>> };
>>>> opp01 {
>>>> opp-hz = /bits/ 64 <1>;
>>>> opp-microvolt = <80>;
>>>> };
>>>> opp02 {
>>>> opp-hz = /bits/ 64 <13400>;
>>>>
Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
> On 10.12.2015 15:43, Chanwoo Choi wrote:
>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>>>> Exynos4x12 has the following AXI buses to translate data between
>>>>>> DRAM and sub-blocks.
>>>>>>
>>>>>> Following list specifies the detailed relation between DRAM and
>>>>>> sub-blocks:
>>>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>>>> - ACLK160 clock for CAM/TV/LCD
>>>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>>> When drop the clock under 160MHz, show the broken image.
>>>>>> - ACLK133 clock for FSYS
>>>>>> - GDL clock for LEFTBUS
>>>>>> - GDR clock for RIGHTBUS
>>>>>> - SCLK_MFC clock for MFC
>>>>>>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>>>>>> ---
>>>>>> arch/arm/boot/dts/exynos4x12.dtsi | 112
>>>>>> ++
>>>>>> 1 file changed, 112 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> @@ -354,6 +354,118 @@
>>>>>> opp-microvolt = <95>;
>>>>>> };
>>>>>> };
>>>>>> +
>>>>>> +bus_leftbus: bus_leftbus {
>>>>>> +compatible = "samsung,exynos-bus";
>>>>>> +clocks = < CLK_DIV_GDL>;
>>>>>> +clock-names = "bus";
>>>>>> +operating-points-v2 = <_leftbus_opp_table>;
>>>>>> +status = "disabled";
>>>>>> +};
>>>>>> +
>>>>>> +bus_rightbus: bus_rightbus {
>>>>>> +compatible = "samsung,exynos-bus";
>>>>>> +clocks = < CLK_DIV_GDR>;
>>>>>> +clock-names = "bus";
>>>>>> +operating-points-v2 = <_leftbus_opp_table>;
>>>>>> +status = "disabled";
>>>>>> +};
>>>>>
>>>>> These two nodes are symmetrical. The MFC below and other buses in other
>>>>> DTS share opps. How about changing the binding so multiple clocks could
>>>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>>>> bus device for each clock.
>>>>
>>>> The your commented method is possible.
>>>>
>>>> But, I focus on implementing the generic bus frequency driver.
>>>>
>>>> If specific bus device-tree node includes the one more clocks,
>>>> when adding the new Exynos SoC, the exynos-bus.c should be added
>>>> for new Exynos SoC. Because, each Exynos SoC has the different
>>>> set of bus device.
>>>>
>>>> If we use my approach, we don't need to modify the exynos-bus.c
>>>> driver to support for the bus frequency of new Exynos SoC.
>>>
>>> This won't change. The driver will just support from 1 to N clocks for
>>> given bus device and set the same OPP to all of them. This will only
>>> limit the number of duplicated entries. This won't affect the generic
>>> approach of driver itself.
>>
>> You're right aspect of only implementation of device driver.
>>
>> But,
>> If we use your commented approach, we can show the information
>> of only parent device through sysfs. We cannot see the information
>> of passive device. The some information includes the current
>> frequency and correlation of parent device. (But, current patchset
>> don' include the topology information between parent device and
>> passive device. I'll do it on later patches).
>>
>> For e
Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>> Exynos4x12 has the following AXI buses to translate data between
>> DRAM and sub-blocks.
>>
>> Following list specifies the detailed relation between DRAM and sub-blocks:
>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>> - ACLK160 clock for CAM/TV/LCD
>> : The minimum clock of ACLK160 should be over 160MHz.
>> When drop the clock under 160MHz, show the broken image.
>> - ACLK133 clock for FSYS
>> - GDL clock for LEFTBUS
>> - GDR clock for RIGHTBUS
>> - SCLK_MFC clock for MFC
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos4x12.dtsi | 112
>> ++
>> 1 file changed, 112 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
>> b/arch/arm/boot/dts/exynos4x12.dtsi
>> index 3bcf0939755e..8bc4aee156b5 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -354,6 +354,118 @@
>> opp-microvolt = <95>;
>> };
>> };
>> +
>> +bus_leftbus: bus_leftbus {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_GDL>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_rightbus: bus_rightbus {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_GDR>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>
> These two nodes are symmetrical. The MFC below and other buses in other
> DTS share opps. How about changing the binding so multiple clocks could
> be specified at once ("bus0", "bus1")? I think there is no need for a
> bus device for each clock.
The your commented method is possible.
But, I focus on implementing the generic bus frequency driver.
If specific bus device-tree node includes the one more clocks,
when adding the new Exynos SoC, the exynos-bus.c should be added
for new Exynos SoC. Because, each Exynos SoC has the different
set of bus device.
If we use my approach, we don't need to modify the exynos-bus.c
driver to support for the bus frequency of new Exynos SoC.
Best Regards,
Chanwoo Choi
>
> Best regards,
> Krzysztof
>
>> +
>> +bus_display: bus_display {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_ACLK160>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_display_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_fsys: bus_fsys {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_ACLK133>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_fsys_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_peri: bus_peri {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_ACLK100>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_peri_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_mfc: bus_mfc {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_SCLK_MFC>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_leftbus_opp_table: opp_table3 {
>> +compatible = "operating-points-v2";
>> +opp-shared;
>> +
>> +opp00 {
>> +opp-hz = /bits/ 64 <1>;
>> +opp-microvolt = <90>;
>> +};
>> +opp01 {
>> +opp-hz = /bits/ 64 <13400>;
>> +opp-microvolt = <925000>;
>> +};
>> +opp02 {
>> +opp-hz = /bits/ 64 <16000>;
>> +
Re: [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
On 2015년 12월 10일 15:58, Krzysztof Kozlowski wrote: > On 09.12.2015 13:08, Chanwoo Choi wrote: >> This patch adds the bus device-tree node of INT (internal) block >> to enable the bus frequency. The following sub-blocks share > > "to enable the bus frequency scaling" > >> the VDD_INT power source: >> - LEFTBUS (parent device) >> - RIGHTBUS >> - PERIL >> - LCD0 >> - FSYS >> - MCUISP / ISP >> - MFC >> >> The LEFTBUS is parent device with devfreq ondemand governor >> and the rest devices has the dependency on LEFTBUS bus. > > How about: > "and the rest of devices depend on the LEFTBUS device." > ? OK, I'll modify it. > > The patch is good: > > Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Thanks for your review. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
On 2015년 12월 10일 16:08, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> THis patch adds the bus device tree nodes for both MIF (Memory) and INT
>> (Internal) block to enable the bus frequency.
>>
>> The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
>> bus is parent device in INT block using VDD_INT.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47
>> +
>> arch/arm/boot/dts/exynos4412-trats2.dts | 47
>> +
>> 2 files changed, 94 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> index 171dea1e3e4a..12d08242a179 100644
>> --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> @@ -544,3 +544,50 @@
>> };
>> };
>> };
>> +
>> +_dmc {
>> +devfreq-events = <_dmc0_3>, <_dmc1_3>;
>> +vdd-supply = <_reg>;
>> +status = "okay";
>> +};
>> +
>> +_acp {
>> +devfreq = <_dmc>;
>> +status = "okay";
>> +};
>> +
>> +_c2c {
>> +devfreq = <_dmc>;
>> +status = "okay";
>> +};
>> +
>> +_leftbus {
>> +devfreq-events = <_leftbus_3>, <_rightbus_3>;
>> +vdd-supply = <_reg>;
>> +status = "okay";
>> +};
>> +
>> +_rightbus {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_display {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_fsys {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_peri {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_mfc {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
>> b/arch/arm/boot/dts/exynos4412-trats2.dts
>> index 40a474c4374b..aecd545803ad 100644
>> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
>> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
>> @@ -1286,3 +1286,50 @@
>> vtmu-supply = <_reg>;
>> status = "okay";
>> };
>> +
>> +_dmc {
>> +devfreq-events = <_dmc0_3>, <_dmc1_3>;
>> +vdd-supply = <_reg>;
>> +status = "okay";
>> +};
>> +
>> +_acp {
>> +devfreq = <_dmc>;
>> +status = "okay";
>> +};
>> +
>> +_c2c {
>> +devfreq = <_dmc>;
>> +status = "okay";
>> +};
>> +
>> +_leftbus {
>> +devfreq-events = <_leftbus_3>, <_rightbus_3>;
>> +vdd-supply = <_reg>;
>> +status = "okay";
>> +};
>> +
>> +_rightbus {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_display {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_fsys {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_peri {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>> +
>> +_mfc {
>> +devfreq = <_leftbus>;
>> +status = "okay";
>> +};
>
> The nodes in both files are mostly sorted alphabetically. Could you
> place them in such order as well?
Okay. I'll sort them alphabetically.
Best Regards,
Chanwoo Choi
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Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
On 2015년 12월 10일 12:17, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
>
> s/noes/nodes/
OK.
>
>> Exynos4x12 has the following AXI buses to translate data
>> between DRAM and DMC/ACP/C2C.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos4x12.dtsi | 72
>> +++
>> 1 file changed, 72 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
>> b/arch/arm/boot/dts/exynos4x12.dtsi
>> index b77dac61ffb5..3bcf0939755e 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -282,6 +282,78 @@
>> clocks = < CLK_SMMU_LITE1>, < CLK_FIMC_LITE1>;
>> #iommu-cells = <0>;
>> };
>> +
>> +bus_dmc: bus_dmc {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_DMC>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_dmc_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_acp: bus_acp {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_ACP>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_acp_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_c2c: bus_c2c {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_C2C>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_dmc_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_dmc_opp_table: opp_table1 {
>> +compatible = "operating-points-v2";
>> +opp-shared;
>> +
>> +opp00 {
>> +opp-hz = /bits/ 64 <1>;
>> +opp-microvolt = <90>;
>> +};
>> +opp01 {
>> +opp-hz = /bits/ 64 <13400>;
>> +opp-microvolt = <90>;
>> +};
>> +opp02 {
>> +opp-hz = /bits/ 64 <16000>;
>> +opp-microvolt = <90>;
>> +};
>> +opp03 {
>> +opp-hz = /bits/ 64 <2>;
>> +opp-microvolt = <95>;
>
> The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?
There is no special reason.
I'll change it (200MHz -> 267MHz).
Best Regards,
Chanwoo Choi
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Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
On 2015년 12월 10일 16:12, Krzysztof Kozlowski wrote:
> On 10.12.2015 16:07, Chanwoo Choi wrote:
>> On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 15:43, Chanwoo Choi wrote:
>>>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>>>>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>>>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>>>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>>>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>>>>>> Exynos4x12 has the following AXI buses to translate data between
>>>>>>>> DRAM and sub-blocks.
>>>>>>>>
>>>>>>>> Following list specifies the detailed relation between DRAM and
>>>>>>>> sub-blocks:
>>>>>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>>>>>> - ACLK160 clock for CAM/TV/LCD
>>>>>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>>>>> When drop the clock under 160MHz, show the broken image.
>>>>>>>> - ACLK133 clock for FSYS
>>>>>>>> - GDL clock for LEFTBUS
>>>>>>>> - GDR clock for RIGHTBUS
>>>>>>>> - SCLK_MFC clock for MFC
>>>>>>>>
>>>>>>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>>>>>>>> ---
>>>>>>>> arch/arm/boot/dts/exynos4x12.dtsi | 112
>>>>>>>> ++
>>>>>>>> 1 file changed, 112 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>>>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> @@ -354,6 +354,118 @@
>>>>>>>>opp-microvolt = <95>;
>>>>>>>>};
>>>>>>>>};
>>>>>>>> +
>>>>>>>> + bus_leftbus: bus_leftbus {
>>>>>>>> + compatible = "samsung,exynos-bus";
>>>>>>>> + clocks = < CLK_DIV_GDL>;
>>>>>>>> + clock-names = "bus";
>>>>>>>> + operating-points-v2 = <_leftbus_opp_table>;
>>>>>>>> + status = "disabled";
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + bus_rightbus: bus_rightbus {
>>>>>>>> + compatible = "samsung,exynos-bus";
>>>>>>>> + clocks = < CLK_DIV_GDR>;
>>>>>>>> + clock-names = "bus";
>>>>>>>> + operating-points-v2 = <_leftbus_opp_table>;
>>>>>>>> + status = "disabled";
>>>>>>>> + };
>>>>>>>
>>>>>>> These two nodes are symmetrical. The MFC below and other buses in other
>>>>>>> DTS share opps. How about changing the binding so multiple clocks could
>>>>>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>>>>>> bus device for each clock.
>>>>>>
>>>>>> The your commented method is possible.
>>>>>>
>>>>>> But, I focus on implementing the generic bus frequency driver.
>>>>>>
>>>>>> If specific bus device-tree node includes the one more clocks,
>>>>>> when adding the new Exynos SoC, the exynos-bus.c should be added
>>>>>> for new Exynos SoC. Because, each Exynos SoC has the different
>>>>>> set of bus device.
>>>>>>
>>>>>> If we use my approach, we don't need to modify the exynos-bus.c
>>>>>> driver to support for the bus frequency of new Exynos SoC.
>>>>>
>>>>> This won't change. The driver will just support from 1 to N clocks for
>>>>> given bus device and set the same OPP to all of them. This will only
>>>>&
Re: [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
On 2015년 12월 10일 16:02, Krzysztof Kozlowski wrote: > On 09.12.2015 13:08, Chanwoo Choi wrote: >> This patch expands the voltage range of buck1/3 regulator due to as >> following: >> - MIF (Memory Interface) bus frequency needs the 9uV ~ 105uV V. >> - INT (Internal) bus frequency needs 9uV ~ 100uV. > > 9->90 and duplicated "uV V". Maybe just: > 900 - 1050 mV > 900 - 1000 mV > ? OK. I'll modify the patch description. > >> >> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >> --- >> arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> > > For the contents of patch: > > Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best Regards, Chanwoo CHoi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
On 2015년 12월 10일 11:09, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
>> Exynos3250 has following AXI buses to translate data between
>> DRAM and sub-blocks.
>>
>> Following list specifies the detailed relation between DRAM and sub-blocks:
>> - ACLK400 clock for MCUISP
>> - ACLK266 clock for ISP
>> - ACLK200 clock for FSYS
>> - ACLK160 clock for LCD0
>> - ACLK100 clock for PERIL
>> - GDL clock for LEFTBUS
>> - GDR clock for RIGHTBUS
>> - SCLK_MFC clock for MFC
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos3250.dtsi | 160
>> ++
>> 1 file changed, 160 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
>> b/arch/arm/boot/dts/exynos3250.dtsi
>> index 7214c5e42150..46dee1951ec1 100644
>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -721,6 +721,166 @@
>> opp-microvolt = <875000>;
>> };
>> };
>> +
>> +bus_leftbus: bus_leftbus {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_GDL>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_rightbus: bus_rightbus {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_GDR>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_lcd0: bus_lcd0 {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_ACLK_160>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_fsys: bus_fsys {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_ACLK_200>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_mcuisp: bus_mcuisp {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_ACLK_400_MCUISP>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_mcuisp_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_isp: bus_isp {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_ACLK_266>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_isp_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_peril: bus_peril {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_DIV_ACLK_100>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_peril_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_mfc: bus_mfc {
>> +compatible = "samsung,exynos-bus";
>> +clocks = < CLK_SCLK_MFC>;
>> +clock-names = "bus";
>> +operating-points-v2 = <_leftbus_opp_table>;
>> +status = "disabled";
>> +};
>> +
>> +bus_leftbus_opp_table: opp_table2 {
>> +compatible = "operating-points-v2";
>> +opp-shared;
>> +
>> +opp00 {
>> +opp-hz = /bits/ 64 <5000>;
>> +
[PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
This patch adds the documentation for generic exynos bus frequency
driver.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 94 ++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
new file mode 100644
index ..54a1f9c46c88
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,94 @@
+* Generic Exynos Bus frequency device
+
+The Samsung Exynos SoC have many buses for data transfer between DRAM
+and sub-blocks in SoC. Almost Exynos SoC have the common architecture
+for buses. Generally, the each bus of Exynos SoC includes the source clock
+and power line and then is able to change the clock according to the usage
+of each buses on runtime. When gathering the usage of each buses on runtime,
+thie driver uses the PPMU (Platform Performance Monitoring Unit) which
+is able to measure the current load of sub-blocks.
+
+There are a little different composition among Exynos SoC because each Exynos
+SoC has the different sub-blocks. So, this difference should be specified
+in devicetree file instead of each device driver. In result, this driver
+is able to support the bus frequency for all Exynos SoCs.
+
+Required properties for bus device:
+- compatible: Should be "samsung,exynos-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- #clock-cells: should be 1.
+- operating-points-v2: the OPP table including frequency/voltage information
+ to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- vdd-supply: the regulator to provide the buses with the voltage.
+- devfreq-events: the devfreq-event device to monitor the curret utilization
+ of buses.
+
+Optional properties for bus device:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+ the performance count againt total cycle count.
+
+Example1:
+ Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
+ power line (regulator). The MIF (Memory Interface) AXI bus is used to
+ transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
+
+ - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+
+ - MIF bus's frequency/voltage table
+ ---
+ |Lv| Freq | Voltage |
+ ---
+ |L1| 5 |80 |
+ |L2| 10 |80 |
+ |L3| 134000 |80 |
+ |L4| 20 |80 |
+ |L5| 40 |875000 |
+ ---
+
+Example2 :
+ The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
+ are listed below:
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <80>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <80>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
+
+ Usage case to handle the frequency and voltage of bus on runtime
+ in exynos3250-rinato.dts are listed below:
+
+ _dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>; /* VDD_MIF */
+ status = "okay";
+ };
--
1.9.1
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[PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
This patch adds the bus device-tree node of INT (internal) block
to enable the bus frequency. The following sub-blocks share
the VDD_INT power source:
- LEFTBUS (parent device)
- RIGHTBUS
- PERIL
- LCD0
- FSYS
- MCUISP / ISP
- MFC
The LEFTBUS is parent device with devfreq ondemand governor
and the rest devices has the dependency on LEFTBUS bus.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250-rinato.dts | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 61477943015b..3a6ca68b68c3 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -681,6 +681,47 @@
status = "okay";
};
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_lcd0 {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mcuisp {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_isp {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peril {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
{
clock-frequency = <2400>;
};
--
1.9.1
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[PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
ne (e.g., regulator). So, LEFTBUS bus
driver is operated as parent with ondemand governor and then the rest
device driver with passive governor.
The buses of Internal block in exynos3250.dtsi are listed below:
When LEFTBUS bus driver (parent) changes the bus frequency with
ondemand governor on runtime, the rest bus devices which sharing
the same power line (VDD_INT) will change the each bus frequency
according to the decision of LEFTBUS bus driver (parent).
- INT (Internal) block
: VDD_INT |--- LEFTBUS
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAM
- The buss of INT block in exynos3250.dtsi are listed below:
bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDL>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
bus_rightbus: bus_rightbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDR>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
(Omit the rest bus dt node)
- Usage case to handle the frequency and voltage of bus on runtime
in exynos3250-rinato.dts are listed below:
/* Parent bus device of VDD_INT */
_leftbus {
devfreq-events = <_leftbus_3>, <_rightbus_3>;
vdd-supply = <_reg>;
status = "okay";
};
/* Passive bus device depend on LEFTBUS bus. */
_rightbus {
devfreq = <_leftbus>; /* 'devfreq' property indicates
the phandle of parent device. */
status = "okay";
};
(Omit the rest bus dt node)
Chanwoo Choi (19):
PM / devfreq: exynos: Add generic exynos bus frequency driver
PM / devfreq: exynos: Add documentation for generic exynos bus frequency
driver
ARM: dts: Add DMC bus node for Exynos3250
ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
PM / devfreq: Add new passive governor
PM / devfreq: Add devfreq_get_devfreq_by_phandle()
PM / devfreq: Show the related information according to governor type
PM / devfreq: exynos: Add support of bus frequency of sub-blocks using
passive governor
PM / devfreq: exynos: Update documentation for bus devices using passive
governor
PM / devfreq: exynos: Add the detailed correlation between sub-blocks and
power line
PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
ARM: dts: Add bus nodes using VDD_INT for Exynos3250
ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
ARM: dts: Add PPMU node for exynos4412-odroidu3
ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
ARM: dts: Expand the voltage range of buck1/3 regulator for
exynos4412-odroidu3
ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
.../devicetree/bindings/devfreq/exynos-bus.txt | 383 +++
arch/arm/boot/dts/exynos3250-monk.dts |6 +
arch/arm/boot/dts/exynos3250-rinato.dts| 47 +
arch/arm/boot/dts/exynos3250.dtsi | 194
arch/arm/boot/dts/exynos4210.dtsi | 172
arch/arm/boot/dts/exynos4412-odroid-common.dtsi| 93 +-
arch/arm/boot/dts/exynos4412-trats2.dts| 47 +
arch/arm/boot/dts/exynos4x12.dtsi | 184
drivers/devfreq/Kconfig| 37 +-
drivers/devfreq/Makefile |2 +
drivers/devfreq/devfreq.c | 120 ++-
drivers/devfreq/exynos/Makefile|3 +-
drivers/devfreq/exynos/exynos-bus.c| 549 ++
drivers/devfreq/exynos/exynos4_bus.c | 1055
drivers/devfreq/exynos/exynos4_bus.h | 110 --
drivers/devfreq/exynos/exynos5_bus.c | 431
drivers/devfreq/exynos/exynos_ppmu.c | 119 ---
drivers/devfreq/exynos/exynos_ppmu.h | 86 --
drivers/devfreq/governor.h |7 +
drivers/devfreq/governor_passive.c | 109 ++
drivers/devfreq/governor_performance.c |1 +
drivers/devfreq/governor_powersave.c |1 +
drivers/devfreq/governor_simpleondemand.c |1 +
drivers/devfreq/governor_userspace.c |1 +
include/linux/devfreq.h
[PATCH v2 01/19] PM / devfreq: exynos: Add generic exynos bus frequency driver
This patch adds the generic exynos bus frequency driver for AMBA AXI bus
of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
have the common architecture for bus between DRAM and sub-blocks in SoC.
This driver can support the generic bus frequency driver for Exynos SoCs.
In devicetree, Each bus block has a bus clock, regulator, operation-point
and devfreq-event devices which measure the utilization of each bus block.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/Kconfig | 15 ++
drivers/devfreq/Makefile| 1 +
drivers/devfreq/exynos/Makefile | 1 +
drivers/devfreq/exynos/exynos-bus.c | 449
4 files changed, 466 insertions(+)
create mode 100644 drivers/devfreq/exynos/exynos-bus.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 64281bb2f650..55ec774f794c 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE
comment "DEVFREQ Drivers"
+config ARM_EXYNOS_BUS_DEVFREQ
+ bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
+ depends on ARCH_EXYNOS
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_EVENT_EXYNOS_PPMU
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+ Memory bus has one more group of memory bus (e.g, MIF and INT block).
+ Each memory bus group could contain many memoby bus block. It reads
+ PPMU counters of memory controllers by using DEVFREQ-event device
+ and adjusts the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
config ARM_EXYNOS4_BUS_DEVFREQ
bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
!ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 5134f9ee983d..375ebbb4fcfb 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
# DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS) += exynos/
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_TEGRA_DEVFREQ)+= tegra-devfreq.o
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 49bc9175f923..4ec06d322996 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,3 +1,4 @@
# Exynos DEVFREQ Drivers
+obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos-bus.c
b/drivers/devfreq/exynos/exynos-bus.c
new file mode 100644
index ..f1bc20839650
--- /dev/null
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -0,0 +1,449 @@
+/*
+ * Generic Exynos Bus frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi <cw00.c...@samsung.com>
+ *
+ * This driver support Exynos Bus frequency feature by using
+ * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DEFAULT_SATURATION_RATIO 40
+
+struct exynos_bus {
+ struct device *dev;
+
+ struct devfreq *devfreq;
+ struct devfreq_event_dev **edev;
+ unsigned int edev_count;
+ struct mutex lock;
+
+ struct dev_pm_opp *curr_opp;
+
+ struct regulator *regulator;
+ struct clk *clk;
+ int ratio;
+};
+
+/*
+ * Control the devfreq-event device to get the current state of bus
+ */
+#define exynos_bus_ops_edev(ops) \
+static int exynos_bus_##ops(struct exynos_bus *bus)\
+{ \
+ int i, ret; \
+ \
+ for (i = 0; i < bus->edev_count; i++) { \
+ if (!bus->edev[i]) \
+ continue; \
+ ret = devfreq_event_##ops(bus->edev[i]);\
+ if (ret < 0)
[PATCH v2 11/19] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
This patch removes the unused exynos4/5 busfreq driver. Instead,
generic exynos-bus frequency driver support the all Exynos SoCs.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/Kconfig | 22 -
drivers/devfreq/exynos/Makefile |2 -
drivers/devfreq/exynos/exynos4_bus.c | 1055 --
drivers/devfreq/exynos/exynos4_bus.h | 110
drivers/devfreq/exynos/exynos5_bus.c | 431 --
drivers/devfreq/exynos/exynos_ppmu.c | 119
drivers/devfreq/exynos/exynos_ppmu.h | 86 ---
7 files changed, 1825 deletions(-)
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 88f7cc4539b8..e82b1d8cd200 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -91,28 +91,6 @@ config ARM_EXYNOS_BUS_DEVFREQ
and adjusts the operating frequencies and voltages with OPP support.
This does not yet operate with optimal voltages.
-config ARM_EXYNOS4_BUS_DEVFREQ
- bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
- depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) &&
!ARCH_MULTIPLATFORM
- select DEVFREQ_GOV_SIMPLE_ONDEMAND
- select PM_OPP
- help
- This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
- and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
- It reads PPMU counters of memory controllers and adjusts
- the operating frequencies and voltages with OPP support.
- This does not yet operate with optimal voltages.
-
-config ARM_EXYNOS5_BUS_DEVFREQ
- tristate "ARM Exynos5250 Bus DEVFREQ Driver"
- depends on SOC_EXYNOS5250
- select DEVFREQ_GOV_SIMPLE_ONDEMAND
- select PM_OPP
- help
- This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).
- It reads PPMU counters of memory controllers and adjusts the
- operating frequencies and voltages with OPP support.
-
config ARM_TEGRA_DEVFREQ
tristate "Tegra DEVFREQ Driver"
depends on ARCH_TEGRA_124_SOC
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 4ec06d322996..bc695ad81c7d 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,4 +1,2 @@
# Exynos DEVFREQ Drivers
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
-obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
-obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos4_bus.c
b/drivers/devfreq/exynos/exynos4_bus.c
deleted file mode 100644
index da9509205169..
--- a/drivers/devfreq/exynos/exynos4_bus.c
+++ /dev/null
@@ -1,1055 +0,0 @@
-/* drivers/devfreq/exynos4210_memorybus.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- * MyungJoo Ham <myungjoo@samsung.com>
- *
- * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
- * This version supports EXYNOS4210 only. This changes bus frequencies
- * and vddint voltages. Exynos4412/4212 should be able to be supported
- * with minor modifications.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include "exynos_ppmu.h"
-#include "exynos4_bus.h"
-
-#define MAX_SAFEVOLT 120 /* 1.2V */
-
-enum exynos4_busf_type {
- TYPE_BUSF_EXYNOS4210,
- TYPE_BUSF_EXYNOS4x12,
-};
-
-/* Assume that the bus is saturated if the utilization is 40% */
-#define BUS_SATURATION_RATIO 40
-
-enum busclk_level_idx {
- LV_0 = 0,
- LV_1,
- LV_2,
- LV_3,
- LV_4,
- _LV_END
-};
-
-enum exynos_ppmu_idx {
- PPMU_DMC0,
- PPMU_DMC1,
- PPMU_END,
-};
-
-#define EX4210_LV_MAX LV_2
-#define EX4x12_LV_MAX LV_4
-#define EX4210_LV_NUM (LV_2 + 1)
-#define EX4x12_LV_NUM (LV_4 + 1)
-
-/**
- * struct busfreq_opp_info - opp information for bus
- * @rate: Frequency in hertz
- * @volt: Voltage in microvolts corresponding to this OPP
- */
-struct busfreq_opp_info {
- unsigned long rate;
- unsigned long volt;
-};
-
-struct busfreq_data {
- enum exynos4_busf_type type;
- struct device *dev;
- struct devfreq *devfreq;
- bool disabled;
- struct regulator *vdd_int;
- struct regulator *vdd_mif; /* Exynos4412/421
[PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
This patch adds the DMC (Dynamic Memory Controller) bus frequency node
which includes the devfreq-events and regulator properties. The bus
frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
with ondemand governor.
The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
the DMC block.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250-monk.dts | 6 ++
arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 443a35085846..d982586a6533 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -498,6 +498,12 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
{
clock-frequency = <2400>;
};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 3e64d5dcdd60..61477943015b 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -675,6 +675,12 @@
};
};
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
{
clock-frequency = <2400>;
};
--
1.9.1
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[PATCH v2 08/19] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the source clock and
regulator at the same time. So, this patch uses the passive governor to support
the bus frequency for all buses which sharing the one power line.
For example,
Exynos3250 include the two power line for AXI buses as following:
: VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller)
with the power (regulator).
: VDD_INT : INT (Internal) provide the various sub-blocks with the power
(regulator).
Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus
use the power line. So, there is no any depencency between buese. But, in the
case of VDD_INT, various buses share the one power line of VDD_INT. We need to
make the depenency between buses. When using passive governor, there is no
problem to support the bus frequency as DVFS for all buses. One bus should be
operated as the parent bus device which gathering the current load of INT block
and then decides the new frequency with some governors except of passive
governor. After deciding the new frequency by the parent bus device, the rest
bus devices will change the each source clock according to new frequency of the
parent bus device.
- MIF (Memory Interface) block
: VDD_MIF |--- DMC
- INT (Internal) block
: VDD_INT |--- LEFTBUS (parent)
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAM
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/Kconfig | 1 +
drivers/devfreq/exynos/exynos-bus.c | 170
2 files changed, 136 insertions(+), 35 deletions(-)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index d03f635a93e1..88f7cc4539b8 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -79,6 +79,7 @@ config ARM_EXYNOS_BUS_DEVFREQ
bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
depends on ARCH_EXYNOS
select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_GOV_PASSIVE
select DEVFREQ_EVENT_EXYNOS_PPMU
select PM_DEVFREQ_EVENT
select PM_OPP
diff --git a/drivers/devfreq/exynos/exynos-bus.c
b/drivers/devfreq/exynos/exynos-bus.c
index f1bc20839650..2efc2bba757e 100644
--- a/drivers/devfreq/exynos/exynos-bus.c
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -91,7 +91,7 @@ static int exynos_bus_get_event(struct exynos_bus *bus,
}
/*
- * Must necessary function for devfreq governor
+ * Must necessary function for devfreq simple-ondemand governor
*/
static int exynos_bus_target(struct device *dev, unsigned long *freq, u32
flags)
{
@@ -205,57 +205,74 @@ static void exynos_bus_exit(struct device *dev)
dev_pm_opp_of_remove_table(dev);
}
-static int exynos_bus_parse_of(struct device_node *np,
- struct exynos_bus *bus)
+/*
+ * Must necessary function for devfreq passive governor
+ */
+static int exynos_bus_passive_target(struct device *dev, unsigned long *freq,
+ u32 flags)
{
- struct device *dev = bus->dev;
- unsigned long rate;
- int i, ret, count, size;
+ struct exynos_bus *bus = dev_get_drvdata(dev);
+ struct dev_pm_opp *new_opp;
+ unsigned long old_freq, new_freq;
+ int ret = 0;
- /* Get the clock to provide each bus with source clock */
- bus->clk = devm_clk_get(dev, "bus");
- if (IS_ERR(bus->clk)) {
- dev_err(dev, "failed to get bus clock\n");
- return PTR_ERR(bus->clk);
+ /* Get new opp-bus instance according to new bus clock */
+ rcu_read_lock();
+ new_opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR_OR_NULL(new_opp)) {
+ dev_err(dev, "failed to get recommed opp instance\n");
+ rcu_read_unlock();
+ return PTR_ERR(new_opp);
}
- ret = clk_prepare_enable(bus->clk);
- if (ret < 0) {
- dev_err(dev, "failed to get enable clock\n");
- return ret;
- }
+ new_freq = dev_pm_opp_get_freq(new_opp);
+ old_freq = dev_pm_opp_get_freq(bus->curr_opp);
+ rcu_read_unlock();
- /* Get the freq/voltage OPP table to scale the bus frequency */
- rcu_read_lock();
- ret = dev_pm_opp_of_add_table(dev);
+ if (old_freq == new_freq)
+ return 0;
+
+ /* Change the frequency according to new OPP level */
+ mutex_lock(>lock);
+
+ ret = clk_set_rate(bus->clk, new_freq);
if (ret < 0) {
-
[PATCH v2 10/19] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
This patch adds the detailed corrleation between sub-blocks and power line for Exynos3250, Exynos4210 and Exynos4x12. Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> --- .../devicetree/bindings/devfreq/exynos-bus.txt | 51 ++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index c4fdc70f8eac..ed639c4f6466 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -33,6 +33,57 @@ Optional properties for only parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count againt total cycle count. +Detailed correlation between sub-blocks and power line according to Exynos SoC: +- In case of Exynos3250, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- PERIR + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM + +- In case of Exynos4210, there is one power line as following: + VDD_INT |--- DMC (parent device) + |--- LEFTBUS + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- LCD0 + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- LCD1 + +- In case of Exynos4x12, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- IMAGE + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- ISP + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 06/19] PM / devfreq: Add devfreq_get_devfreq_by_phandle()
This patch adds the new devfreq_get_devfreq_by_phandle() OF helper function
which can find the instance of devfreq device by using phandle ("devfreq").
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/devfreq.c | 44
include/linux/devfreq.h | 9 +
2 files changed, 53 insertions(+)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 15e58779e4c0..78ea4cdaa82c 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "governor.h"
static struct class *devfreq_class;
@@ -686,6 +687,49 @@ struct devfreq *devm_devfreq_add_device(struct device *dev,
}
EXPORT_SYMBOL(devm_devfreq_add_device);
+#ifdef CONFIG_OF
+/*
+ * devfreq_get_devfreq_by_phandle - Get the devfreq device from devicetree
+ * @dev - instance to the given device
+ * @index - index into list of devfreq
+ *
+ * return the instance of devfreq device
+ */
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+ struct device_node *node;
+ struct devfreq *devfreq;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ if (!dev->of_node)
+ return ERR_PTR(-EINVAL);
+
+ node = of_parse_phandle(dev->of_node, "devfreq", index);
+ if (!node)
+ return ERR_PTR(-ENODEV);
+
+ mutex_lock(_list_lock);
+ list_for_each_entry(devfreq, _list, node) {
+ if (devfreq->dev.parent
+ && devfreq->dev.parent->of_node == node) {
+ mutex_unlock(_list_lock);
+ return devfreq;
+ }
+ }
+ mutex_unlock(_list_lock);
+
+ return ERR_PTR(-EPROBE_DEFER);
+}
+#else
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+ return ERR_PTR(-ENODEV);
+}
+#endif /* CONFIG_OF */
+EXPORT_SYMBOL_GPL(devfreq_get_devfreq_by_phandle);
+
/**
* devm_devfreq_remove_device() - Resource-managed devfreq_remove_device()
* @dev: the device to add devfreq feature.
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index f7a6e6bd716e..d648041145ba 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -211,6 +211,9 @@ extern int devm_devfreq_register_opp_notifier(struct device
*dev,
extern void devm_devfreq_unregister_opp_notifier(struct device *dev,
struct devfreq *devfreq);
+extern struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev,
+ int index);
+
/**
* devfreq_update_stats() - update the last_status pointer in struct devfreq
* @df:the devfreq instance whose status needs updating
@@ -324,6 +327,12 @@ static inline void
devm_devfreq_unregister_opp_notifier(struct device *dev,
{
}
+static inline struct devfreq *devfreq_get_devfreq_by_phandle(struct device
*dev,
+ int index)
+{
+ return ERR_PTR(-ENODEV);
+}
+
static inline int devfreq_update_stats(struct devfreq *df)
{
return -EINVAL;
--
1.9.1
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[PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD
: The minimum clock of ACLK160 should be over 160MHz.
When drop the clock under 160MHz, show the broken image.
- ACLK133 clock for FSYS
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 112 ++
1 file changed, 112 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 3bcf0939755e..8bc4aee156b5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -354,6 +354,118 @@
opp-microvolt = <95>;
};
};
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <925000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ };
+
+ bus_display_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ };
+
+ bus_fsys_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <925000>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <925000>;
+ };
+ };
};
{
--
1.9.1
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[PATCH v2 07/19] PM / devfreq: Show the related information according to governor type
This patch modifies the following sysfs entry of DEVFREQ framework
because the devfreq device using passive governor don't need the same
information of the devfreq device using rest governor.
- polling_interval: passive gov don't use the sampling rate.
- available_governors : passive gov don't be changed on runtime in this version.
- trans_stat : passive governor don't support trans_stat in this
version.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/devfreq.c | 31 +--
drivers/devfreq/governor.h| 7 +++
drivers/devfreq/governor_passive.c| 1 +
drivers/devfreq/governor_performance.c| 1 +
drivers/devfreq/governor_powersave.c | 1 +
drivers/devfreq/governor_simpleondemand.c | 1 +
drivers/devfreq/governor_userspace.c | 1 +
include/linux/devfreq.h | 2 ++
8 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 78ea4cdaa82c..18ad956fec93 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -597,7 +597,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
goto err_init;
}
- if (!strncmp(devfreq->governor_name, "passive", 7)) {
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
struct devfreq *parent_devfreq =
((struct devfreq_passive_data *)data)->parent;
@@ -963,13 +963,23 @@ static ssize_t available_governors_show(struct device *d,
struct device_attribute *attr,
char *buf)
{
- struct devfreq_governor *tmp_governor;
+ struct devfreq *devfreq = to_devfreq(d);
ssize_t count = 0;
mutex_lock(_list_lock);
- list_for_each_entry(tmp_governor, _governor_list, node)
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
count += scnprintf([count], (PAGE_SIZE - count - 2),
- "%s ", tmp_governor->name);
+ "%s ", devfreq->governor->name);
+ } else {
+ struct devfreq_governor *tmp_governor;
+
+ list_for_each_entry(tmp_governor, _governor_list, node)
{
+ if (tmp_governor->type == DEVFREQ_GOV_PASSIVE)
+ continue;
+ count += scnprintf([count], (PAGE_SIZE - count - 2),
+ "%s ", tmp_governor->name);
+ }
+ }
mutex_unlock(_list_lock);
/* Truncate the trailing space */
@@ -1006,6 +1016,11 @@ static DEVICE_ATTR_RO(target_freq);
static ssize_t polling_interval_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
+ struct devfreq *df = to_devfreq(dev);
+
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
return sprintf(buf, "%d\n", to_devfreq(dev)->profile->polling_ms);
}
@@ -1020,6 +1035,9 @@ static ssize_t polling_interval_store(struct device *dev,
if (!df->governor)
return -EINVAL;
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return -EINVAL;
+
ret = sscanf(buf, "%u", );
if (ret != 1)
return -EINVAL;
@@ -1137,11 +1155,12 @@ static ssize_t trans_stat_show(struct device *dev,
int i, j;
unsigned int max_state = devfreq->profile->max_state;
+ if (max_state == 0 || devfreq->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
if (!devfreq->stop_polling &&
devfreq_update_status(devfreq, devfreq->previous_freq))
return 0;
- if (max_state == 0)
- return sprintf(buf, "Not Supported.\n");
len = sprintf(buf, " From : To\n");
len += sprintf(buf + len, " :");
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index fad7d6321978..43513a58f5bf 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -18,6 +18,13 @@
#define to_devfreq(DEV)container_of((DEV), struct devfreq, dev)
+/* Devfreq governor type */
+#define DEVFREQ_GOV_ONDEMAND 0x1
+#define DEVFREQ_GOV_PERFORMANCE0x2
+#define DEVFREQ_GOV_POWERSAVE 0x3
+#define DEVFREQ_GOV_USERSPACE 0x4
+#define DEVFREQ_GOV_PASSIVE0x4
+
/* Devfreq events */
#define DEVFREQ_GOV_START 0x1
#define DEVFREQ_GOV_STOP
[PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 72 +++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index b77dac61ffb5..3bcf0939755e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -282,6 +282,78 @@
clocks = < CLK_SMMU_LITE1>, < CLK_FIMC_LITE1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_c2c: bus_c2c {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_C2C>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <90>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <90>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <95>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <105>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <90>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <90>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <95>;
+ };
+ };
};
{
--
1.9.1
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[PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
This patch expands the voltage range of buck1/3 regulator due to as following:
- MIF (Memory Interface) bus frequency needs the 9uV ~ 105uV V.
- INT (Internal) bus frequency needs 9uV ~ 100uV.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 90800a6da14b..171dea1e3e4a 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -359,8 +359,8 @@
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
- regulator-min-microvolt = <100>;
- regulator-max-microvolt = <100>;
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <105>;
regulator-always-on;
regulator-boot-on;
};
@@ -375,7 +375,7 @@
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
- regulator-min-microvolt = <100>;
+ regulator-min-microvolt = <90>;
regulator-max-microvolt = <100>;
regulator-always-on;
regulator-boot-on;
--
1.9.1
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[PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3
This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
exynos4412-odroidu3 board. Each PPMU dt node includes one event of
'PPMU Count3'.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40 +
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index edf0fc8db6ff..90800a6da14b 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -504,3 +504,43 @@
{
status = "okay";
};
+
+_dmc0 {
+ status = "okay";
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ };
+ };
+};
+
+_dmc1 {
+ status = "okay";
+
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = "ppmu-event3-dmc1";
+ };
+ };
+};
+
+_leftbus {
+ status = "okay";
+
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+ event-name = "ppmu-event3-leftbus";
+ };
+ };
+};
+
+_rightbus {
+ status = "okay";
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = "ppmu-event3-rightbus";
+ };
+ };
+};
--
1.9.1
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[PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
This patch updates the documentation for passive bus devices and adds the
detailed example of Exynos3250.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 244 -
1 file changed, 241 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index 54a1f9c46c88..c4fdc70f8eac 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference
should be specified
in devicetree file instead of each device driver. In result, this driver
is able to support the bus frequency for all Exynos SoCs.
-Required properties for bus device:
+Required properties for all bus devices:
- compatible: Should be "samsung,exynos-bus".
- clock-names : the name of clock used by the bus, "bus".
- clocks : phandles for clock specified in "clock-names" property.
- #clock-cells: should be 1.
- operating-points-v2: the OPP table including frequency/voltage information
to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+
+Required properties for only parent bus device:
- vdd-supply: the regulator to provide the buses with the voltage.
- devfreq-events: the devfreq-event device to monitor the curret utilization
of buses.
-Optional properties for bus device:
+Required properties for only passive bus device:
+- devfreq: the parent bus device.
+
+Optional properties for only parent bus device:
- exynos,saturation-ratio: the percentage value which is used to calibrate
the performance count againt total cycle count.
@@ -33,7 +38,20 @@ Example1:
power line (regulator). The MIF (Memory Interface) AXI bus is used to
transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
- - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+ - MIF (Memory Interface) block
+ : VDD_MIF |--- DMC (Dynamic Memory Controller)
+
+ - INT (Internal) block
+ : VDD_INT |--- LEFTBUS (parent device)
+ |--- PERIL
+ |--- MFC
+ |--- G3D
+ |--- RIGHTBUS
+ |--- FSYS
+ |--- LCD0
+ |--- PERIR
+ |--- ISP
+ |--- CAM
- MIF bus's frequency/voltage table
---
@@ -46,6 +64,24 @@ Example1:
|L5| 40 |875000 |
---
+ - INT bus's frequency/voltage table
+ --
+ |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP|PERIL ||VDD_INT |
+ | name| |LCD0| | | |||
+ | | |FSYS| | | |||
+ | | |MFC | | | |||
+ --
+ |Mode |*parent|passive |passive|passive|passive|||
+ --
+ |Lv |Frequency ||Voltage |
+ --
+ |L1 |5 |5 |5 |5 |5 ||90 |
+ |L2 |8 |8 |8 |8 |8 ||90 |
+ |L3 |10 |10 |10 |10 |10 ||100 |
+ |L4 |134000 |134000 |20 |20 | ||100 |
+ |L5 |20 |20 |40 |30 | ||100 |
+ --
+
Example2 :
The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
are listed below:
@@ -84,6 +120,167 @@ Example2 :
};
};
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_160>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible
[PATCH v2 15/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
one power line for all buses to translate data between DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- DMC/ACP clock for DMC (Dynamic Memory Controller)
- ACLK200 clock for LCD0
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD0/LCD1
- ACLK133 clock for FSYS/GPS
- GDL/GDR clock for LEFTBUS/RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 172 ++
1 file changed, 172 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 3e5ba665d200..658c5a1fe03c 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,178 @@
power-domains = <_lcd1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK200>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <1025000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <26700>;
+ opp-microvolt = <105>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <115>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <1025000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <105>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <2>;
[PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
THis patch adds the bus device tree nodes for both MIF (Memory) and INT
(Internal) block to enable the bus frequency.
The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
bus is parent device in INT block using VDD_INT.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47 +
arch/arm/boot/dts/exynos4412-trats2.dts | 47 +
2 files changed, 94 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 171dea1e3e4a..12d08242a179 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -544,3 +544,50 @@
};
};
};
+
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_acp {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_c2c {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_display {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peri {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 40a474c4374b..aecd545803ad 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -1286,3 +1286,50 @@
vtmu-supply = <_reg>;
status = "okay";
};
+
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_acp {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_c2c {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_display {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peri {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
--
1.9.1
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[PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
SDRAM devices. The bus includes the OPP tables and the source clock for DMC
block.
Following list specifies the detailed relation between the clock and DMC block:
- The source clock of DMC block : div_dmc
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2f30d632f1cc..7214c5e42150 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -687,6 +687,40 @@
clock-names = "ppmu";
status = "disabled";
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <80>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <80>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
};
};
--
1.9.1
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[PATCH v2 05/19] PM / devfreq: Add new passive governor
This patch adds the new passive governor for DEVFREQ framework. The following
governors are already present and used for DVFS (Dynamic Voltage and Frequency
Scaling) drivers. The following governors are independently used for one device
driver which don't give the influence to other device drviers and also don't
receive the effect from other device drivers.
- ondemand / performance / powersave / userspace
The passive governor depends on operation of parent driver with specific
governos extremely and is not able to decide the new frequency by oneself.
According to the decided new frequency of parent driver with governor,
the passive governor uses it to decide the appropriate frequency for own
device driver. The passive governor must need the following information
from device tree:
- the source clock and OPP tables
- the instance of parent device
For exameple,
there are one more devfreq device drivers which need to change their source
clock according to their utilization on runtime. But, they share the same
power line (e.g., regulator). So, specific device driver is operated as parent
with ondemand governor and then the rest device driver with passive governor
is influenced by parent device.
Suggested-by: Myungjoo Ham <myungjoo@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/Kconfig| 9
drivers/devfreq/Makefile | 1 +
drivers/devfreq/devfreq.c | 47
drivers/devfreq/governor_passive.c | 108 +
include/linux/devfreq.h| 17 ++
5 files changed, 182 insertions(+)
create mode 100644 drivers/devfreq/governor_passive.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 55ec774f794c..d03f635a93e1 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -64,6 +64,15 @@ config DEVFREQ_GOV_USERSPACE
Otherwise, the governor does not change the frequnecy
given at the initialization.
+config DEVFREQ_GOV_PASSIVE
+ tristate "Passive"
+ help
+ Sets the frequency by other governors (simple_ondemand, performance,
+ powersave, usersapce) of a parent devfreq device. This governor
+ always has the dependency on the chosen frequency from paired
+ governor. This governor does not change the frequency by oneself
+ through sysfs entry.
+
comment "DEVFREQ Drivers"
config ARM_EXYNOS_BUS_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 375ebbb4fcfb..f81c313b4b79 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +=
governor_simpleondemand.o
obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)+= governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)+= governor_userspace.o
+obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
# DEVFREQ Drivers
obj-$(CONFIG_ARCH_EXYNOS) += exynos/
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 984c5e9e7bdd..15e58779e4c0 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -190,6 +190,31 @@ static struct devfreq_governor
*find_devfreq_governor(const char *name)
/* Load monitoring helper functions for governors use */
+static int update_devfreq_passive(struct devfreq *devfreq, unsigned long freq)
+{
+ struct devfreq *passive;
+ unsigned long rate;
+ int ret;
+
+ list_for_each_entry(passive, >passive_dev_list, passive_node) {
+ if (!passive->governor)
+ continue;
+ rate = freq;
+
+ ret = passive->governor->get_target_freq(passive, );
+ if (ret)
+ return ret;
+
+ ret = passive->profile->target(passive->dev.parent, , 0);
+ if (ret)
+ return ret;
+
+ passive->previous_freq = rate;
+ }
+
+ return 0;
+}
+
/**
* update_devfreq() - Reevaluate the device and configure frequency.
* @devfreq: the devfreq instance.
@@ -233,10 +258,18 @@ int update_devfreq(struct devfreq *devfreq)
flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */
}
+ if (!list_empty(>passive_dev_list)
+ && devfreq->previous_freq > freq)
+ update_devfreq_passive(devfreq, freq);
+
err = devfreq->profile->target(devfreq->dev.parent, , flags);
if (err)
return err;
+ if (!list_empty(>passive_dev_list)
+ && devfreq->previous_freq < freq)
+ update_devfreq_passive(devfreq, freq);
+
if (devfreq->profile->freq_table)
if (devfreq_update_status(devfreq, freq))
dev_e
[PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 160 ++
1 file changed, 160 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 7214c5e42150..46dee1951ec1 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -721,6 +721,166 @@
opp-microvolt = <875000>;
};
};
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_160>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_200>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mcuisp: bus_mcuisp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "bus";
+ operating-points-v2 = <_mcuisp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_isp: bus_isp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_266>;
+ clock-names = "bus";
+ operating-points-v2 = <_isp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peril: bus_peril {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACLK_100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peril_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <8000>;
+ opp-microvolt = <90>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <100>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <13400>;
+ opp-microvolt = <100>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <1
Re: [RFC PATCH 01/15] PM / devfreq: exynos: Add generic exynos bus frequency driver
Hi Anand, On 2015년 11월 27일 09:34, Chanwoo Choi wrote: > Hi Anand, > > On 2015년 11월 27일 02:17, Anand Moon wrote: >> Hi Chanwoo, >> >> On 26 November 2015 at 21:42, Chanwoo Choi <cwcho...@gmail.com> wrote: >>> On Thu, Nov 26, 2015 at 11:00 PM, MyungJoo Ham <myungjoo@samsung.com> >>> wrote: >>>> On Thu, Nov 26, 2015 at 10:47 PM, Chanwoo Choi <cw00.c...@samsung.com> >>>> wrote: >>>>> This patch adds the generic exynos bus frequency driver for AMBA AXI bus >>>>> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC >>>>> have the common architecture for bus between DRAM and sub-blocks in SoC. >>>>> This driver can support the generic bus frequency driver for Exynos SoCs. >>>>> >>>>> In devicetree, Each bus block has a bus clock, regulator, operation-point >>>>> and devfreq-event devices which measure the utilization of each bus block. >>>>> >>>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >>>>> --- >>>>> drivers/devfreq/Kconfig | 15 ++ >>>>> drivers/devfreq/Makefile| 1 + >>>>> drivers/devfreq/exynos/Makefile | 1 + >>>>> drivers/devfreq/exynos/exynos-bus.c | 443 >>>>> >>>>> 4 files changed, 460 insertions(+) >>>>> create mode 100644 drivers/devfreq/exynos/exynos-bus.c >>>>> >>>> >>>> Are we finally getting a common Exynos bus driver with full DT support? >>>> (can this replace both Exynos4/5 drivers and support Exynos7 series?) >>> >>> Yes. >>> This patch-set would support all Exynos SoCs for bus frequency driver. >>> To make sure the support for Exynos7 series, I need to check the TRM >>> document of Exynos7. I think it is possible for support Exynos7. >>> >>> I'm going to test this driver on various Exynos-based board. >>> >>> Regards, >>> Chanwoo Choi >> >> Please do consider Exynos 542x series as well. > > Sure. I'll to test it on Exynos5422-based Odroid-XU3. I send the v2 patchset but this patchset don't include the support of Odroid-XU3 because of only Exynos542x has the special addtional sequence to change the source clock of DRAM. So, I'm going to support the bus frequency on Exynos542x. After completing it, I'll send the separate patches. Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 09/15] PM / devfreq: exynos: Update documentation for bus devices using passive governor
Hi Rob, I'm sorry for delay reply due to the problem of email system on the company. On 2015년 12월 01일 06:14, Rob Herring wrote: > On Thu, Nov 26, 2015 at 10:47:33PM +0900, Chanwoo Choi wrote: >> This patch updates the documentation for passive bus devices and adds the >> detailed example of Exynos3250. >> >> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >> --- >> .../devicetree/bindings/devfreq/exynos-bus.txt | 226 >> - >> 1 file changed, 223 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> index 5d90623bd173..c4a6fe30075e 100644 >> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt >> @@ -12,18 +12,23 @@ SoC has the different sub-blocks. So, this difference >> should be specified >> in devicetree file instead of each device driver. In result, this driver >> is able to support the bus frequency for all Exynos SoCs. >> >> -Required properties for bus device: >> +Required properties for all bus devices: >> - compatible: Should be "samsung,exynos-bus". >> - clock-names : the name of clock used by the bus, "bus". >> - clocks : phandles for clock specified in "clock-names" property. >> - #clock-cells: should be 1. >> - operating-points-v2: the OPP table including frequency/voltage information >>to support DVFS (Dynamic Voltage/Frequency Scaling) feature. >> + >> +Required properties for only parent bus device: >> - vdd-supply: the regulator to provide the buses with the voltage. >> - devfreq-events: the devfreq-event device to monitor the curret utilization >>of buses. >> >> -Optional properties for bus device: >> +Required properties for only passive bus device: >> +- devfreq: the parent bus device. >> + >> +Optional properties for only parent bus device: >> - exynos,saturation-ratio: the percentage value which is used to calibrate >> the performance count againt total cycle count. >> >> @@ -32,7 +37,19 @@ Example1: >> power line (regulator). The MIF (Memory Interface) AXI bus is used to >> transfer data between DRAM and CPU and uses the VDD_MIF regualtor. >> >> -- power line(VDD_MIF) --> bus for DMC block (dmc clock) >> +- MIF (Memory Interface) block >> +: VDD_MIF |--- DMC >> + >> +- INT (Internal) block >> +: VDD_INT |--- LEFTBUS |--- PERIL >> + |(parent) |--- MFC >> + | |--- G3D >> + | >> + |--- RIGHTBUS |--- FSYS >> +|--- LCD0 >> +|--- PERIR >> +|--- ISP >> +|--- CAM > > I would expect the DT to mirror this topology which doesn't seem to be > the case in the example. You're right. The above topology is not appropriate to show the correlation between power line and sub blocks. I'll modify it as following. The all blocks which are included in the INT (internal) block share the one power line (VDD_INT). VDD_MIF |--- DMC VDD_INT |--- LEFTBUS |--- PERIL |--- MFC |--- G3D |--- RIGHTBUS |--- FSYS |--- LCD0 |--- PERIR |--- ISP |--- CAM > > >> - MIF bus's frequency/voltage table >> --- >> @@ -45,6 +62,20 @@ Example1: >> |L5| 40 |875000 | >> --- >> >> +- INT bus's frequency/voltage table >> +--- >> +|Lv| Freq | Voltage | >> +--- >> +| |LEFTBUS|RIGHTBUS|LCD0 |FSYS |MCUISP |ISP|PERIL |VDD_INT | >> +| |*parent|passive |passive|passive|passive|passive|passive| | >> +--- >> +|L1|5 |5 |5 |5 |5 |5 |5 |90 | >> +|L2|8 |8 |8 |8 |8 |8 |8 |90 | >> +|L3|10 |10 |10 |10 |10 |10 |10 |100 | >> +|L4|133000 |133000 |133000 |133000 |20 |20 | |100 | >> +|L
Re: [RFC PATCH 02/15] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
Hi Rob,
On Sat, Nov 28, 2015 at 5:30 AM, Rob Herring <r...@kernel.org> wrote:
> On Thu, Nov 26, 2015 at 10:47:26PM +0900, Chanwoo Choi wrote:
>> This patch adds the documentation for generic exynos bus frequency
>> driver.
>>
>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
>> ---
>> .../devicetree/bindings/devfreq/exynos-bus.txt | 92
>> ++
>> 1 file changed, 92 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> new file mode 100644
>> index ..5d90623bd173
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -0,0 +1,92 @@
>> +* Generic Exynos Bus frequency device
>> +
>> +The Samsung Exynos SoC have many buses for data transfer between DRAM
>> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture
>> +for buses. Generally, the each bus of Exynos SoC includes the source clock
>> +and power line and then is able to change the clock according to the usage
>> +of each buses on runtime. When gathering the usage of each buses on runtime,
>> +thie driver uses the exynos-ppmu.c driver with DEVFREQ-EVENT framework.
>
> Please don't refer to Linux subsystem specifics in bindings. It looks
> like you are creating devices to match what you have for drivers, not
> what the h/w looks like.
OK. I'll modify it on next patchiest.
>
>
>> +There are a little different composition among Exynos SoC because each
>> Exynos
>> +SoC has the different sub-blocks. So, this difference should be specified
>> +in devicetree file instead of each device driver. In result, this driver
>> +is able to support the bus frequency for all Exynos SoCs.
>> +
>> +Required properties for bus device:
>> +- compatible: Should be "samsung,exynos-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- #clock-cells: should be 1.
>> +- operating-points-v2: the OPP table including frequency/voltage information
>> + to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +- vdd-supply: the regulator to provide the buses with the voltage.
>> +- devfreq-events: the devfreq-event device to monitor the curret utilization
>> + of buses.
>> +
>> +Optional properties for bus device:
>> +- exynos,saturation-ratio: the percentage value which is used to calibrate
>> + the performance count againt total cycle count.
>> +
>> +Example1:
>> + Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
>> + power line (regulator). The MIF (Memory Interface) AXI bus is used to
>> + transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>> +
>> + - power line(VDD_MIF) --> bus for DMC block (dmc clock)
>> +
>> + - MIF bus's frequency/voltage table
>> + ---
>> + |Lv| Freq | Voltage |
>> + ---
>> + |L1| 5 |80 |
>> + |L2| 10 |80 |
>> + |L3| 133000 |80 |
>> + |L4| 20 |80 |
>> + |L5| 40 |875000 |
>> + ---
>> +
>> +Example2 :
>> + The bus of DMC block in exynos3250.dtsi are listed below:
>
> What is DMC?
DMC (DRAM Memory Controller)
>
>> +
>> + bus_dmc: bus_dmc {
>> + compatible = "samsung,exynos-bus";
>
> I would expect the children of this bus to be under this node.
I add the detailed description on patch9 which is included in this
patch-set as follwoing.
- [RFC PATCH 09/15] PM / devfreq: exynos: Update documentation for bus
devices usingpassive governor
This patch-set don' include the the list of children node in parent dt node.
Instead, I add the separate node and then each children node has the
the phandle of parent node
>
>> + clocks = <_dmc CLK_DIV_DMC>;
>> + clock-names = "bus";
>> + operating-points-v2 = <_dmc_opp_table>;
>> + status = "disabled";
>> + };
>> +
>> + bus_dmc_opp_table: opp_table0 {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp00 {
>> + opp-hz = /bits/ 64 <5000>;
>> + o
Re: [RFC PATCH 01/15] PM / devfreq: exynos: Add generic exynos bus frequency driver
Hi Anand, On 2015년 11월 27일 02:17, Anand Moon wrote: > Hi Chanwoo, > > On 26 November 2015 at 21:42, Chanwoo Choi <cwcho...@gmail.com> wrote: >> On Thu, Nov 26, 2015 at 11:00 PM, MyungJoo Ham <myungjoo@samsung.com> >> wrote: >>> On Thu, Nov 26, 2015 at 10:47 PM, Chanwoo Choi <cw00.c...@samsung.com> >>> wrote: >>>> This patch adds the generic exynos bus frequency driver for AMBA AXI bus >>>> of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC >>>> have the common architecture for bus between DRAM and sub-blocks in SoC. >>>> This driver can support the generic bus frequency driver for Exynos SoCs. >>>> >>>> In devicetree, Each bus block has a bus clock, regulator, operation-point >>>> and devfreq-event devices which measure the utilization of each bus block. >>>> >>>> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com> >>>> --- >>>> drivers/devfreq/Kconfig | 15 ++ >>>> drivers/devfreq/Makefile| 1 + >>>> drivers/devfreq/exynos/Makefile | 1 + >>>> drivers/devfreq/exynos/exynos-bus.c | 443 >>>> >>>> 4 files changed, 460 insertions(+) >>>> create mode 100644 drivers/devfreq/exynos/exynos-bus.c >>>> >>> >>> Are we finally getting a common Exynos bus driver with full DT support? >>> (can this replace both Exynos4/5 drivers and support Exynos7 series?) >> >> Yes. >> This patch-set would support all Exynos SoCs for bus frequency driver. >> To make sure the support for Exynos7 series, I need to check the TRM >> document of Exynos7. I think it is possible for support Exynos7. >> >> I'm going to test this driver on various Exynos-based board. >> >> Regards, >> Chanwoo Choi > > Please do consider Exynos 542x series as well. Sure. I'll to test it on Exynos5422-based Odroid-XU3. Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 00/15] PM / devferq: Add generic exynos bus frequency driver and new passive governor
ints-v2 = <_leftbus_opp_table>;
status = "disabled";
};
bus_rightbus: bus_rightbus {
compatible = "samsung,exynos-bus";
clocks = < CLK_DIV_GDR>;
clock-names = "bus";
operating-points-v2 = <_leftbus_opp_table>;
status = "disabled";
};
(Omit the rest bus dt node)
- Usage case to handle the frequency and voltage of bus on runtime
in exynos3250-rinato.dts are listed below:
/* Parent bus device of VDD_INT */
_leftbus {
devfreq-events = <_leftbus_3>, <_rightbus_3>;
vdd-supply = <_reg>;
status = "okay";
};
/* Passive bus device depend on LEFTBUS bus. */
_rightbus {
devfreq = <_leftbus>; /* 'devfreq' property indicates
the phandle of parent device. */
status = "okay";
};
(Omit the rest bus dt node)
Depends on:
- This patch-set is based on devfreq.git[2].
[1] https://lkml.org/lkml/2015/1/7/872
: [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
[2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch:
for-rafael)
Chanwoo Choi (15):
PM / devfreq: exynos: Add generic exynos bus frequency driver
PM / devfreq: exynos: Add documentation for generic exynos bus frequency
driver
ARM: dts: Add DMC bus node for Exynos3250
ARM: dts: Add DMC bus freqeuncy for exynos3250-rinato/monk
PM / devfreq: Add new passive governor
PM / devfreq: Add devfreq_get_devfreq_by_phandle()
PM / devfreq: Show the related information according to governor type
PM / devfreq: exynos: Add support of bus frequency of sub-blocks using
passive governor
PM / devfreq: exynos: Update documentation for bus devices using passive
governor
PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
ARM: dts: Add bus nodes using VDD_INT for Exynos3250
ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
ARM: dts: Add support of bus frequency for exynos4412-trats
.../devicetree/bindings/devfreq/exynos-bus.txt | 312 ++
arch/arm/boot/dts/exynos3250-monk.dts |6 +
arch/arm/boot/dts/exynos3250-rinato.dts| 42 +
arch/arm/boot/dts/exynos3250.dtsi | 186
arch/arm/boot/dts/exynos4412-trats2.dts| 47 +
arch/arm/boot/dts/exynos4x12.dtsi | 192
drivers/devfreq/Kconfig| 37 +-
drivers/devfreq/Makefile |2 +
drivers/devfreq/devfreq.c | 120 ++-
drivers/devfreq/exynos/Makefile|3 +-
drivers/devfreq/exynos/exynos-bus.c| 543 ++
drivers/devfreq/exynos/exynos4_bus.c | 1055
drivers/devfreq/exynos/exynos4_bus.h | 110 --
drivers/devfreq/exynos/exynos5_bus.c | 431
drivers/devfreq/exynos/exynos_ppmu.c | 119 ---
drivers/devfreq/exynos/exynos_ppmu.h | 86 --
drivers/devfreq/governor.h |7 +
drivers/devfreq/governor_passive.c | 109 ++
drivers/devfreq/governor_performance.c |1 +
drivers/devfreq/governor_powersave.c |1 +
drivers/devfreq/governor_simpleondemand.c |1 +
drivers/devfreq/governor_userspace.c |1 +
include/linux/devfreq.h| 28 +
23 files changed, 1614 insertions(+), 1825 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
create mode 100644 drivers/devfreq/exynos/exynos-bus.c
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
create mode 100644 drivers/devfreq/governor_passive.c
--
1.9.1
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[RFC PATCH 07/15] PM / devfreq: Show the related information according to governor type
This patch modifies the following sysfs entry of DEVFREQ framework
because the devfreq device using passive governor don't need the same
information of the devfreq device using rest governor.
- polling_interval: passive gov don't use the sampling rate.
- available_governors : passive gov don't be changed on runtime in this version.
- trans_stat : passive governor don't support trans_stat in this
version.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
drivers/devfreq/devfreq.c | 31 +--
drivers/devfreq/governor.h| 7 +++
drivers/devfreq/governor_passive.c| 1 +
drivers/devfreq/governor_performance.c| 1 +
drivers/devfreq/governor_powersave.c | 1 +
drivers/devfreq/governor_simpleondemand.c | 1 +
drivers/devfreq/governor_userspace.c | 1 +
include/linux/devfreq.h | 2 ++
8 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 78ea4cdaa82c..18ad956fec93 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -597,7 +597,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
goto err_init;
}
- if (!strncmp(devfreq->governor_name, "passive", 7)) {
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
struct devfreq *parent_devfreq =
((struct devfreq_passive_data *)data)->parent;
@@ -963,13 +963,23 @@ static ssize_t available_governors_show(struct device *d,
struct device_attribute *attr,
char *buf)
{
- struct devfreq_governor *tmp_governor;
+ struct devfreq *devfreq = to_devfreq(d);
ssize_t count = 0;
mutex_lock(_list_lock);
- list_for_each_entry(tmp_governor, _governor_list, node)
+ if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
count += scnprintf([count], (PAGE_SIZE - count - 2),
- "%s ", tmp_governor->name);
+ "%s ", devfreq->governor->name);
+ } else {
+ struct devfreq_governor *tmp_governor;
+
+ list_for_each_entry(tmp_governor, _governor_list, node)
{
+ if (tmp_governor->type == DEVFREQ_GOV_PASSIVE)
+ continue;
+ count += scnprintf([count], (PAGE_SIZE - count - 2),
+ "%s ", tmp_governor->name);
+ }
+ }
mutex_unlock(_list_lock);
/* Truncate the trailing space */
@@ -1006,6 +1016,11 @@ static DEVICE_ATTR_RO(target_freq);
static ssize_t polling_interval_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
+ struct devfreq *df = to_devfreq(dev);
+
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
return sprintf(buf, "%d\n", to_devfreq(dev)->profile->polling_ms);
}
@@ -1020,6 +1035,9 @@ static ssize_t polling_interval_store(struct device *dev,
if (!df->governor)
return -EINVAL;
+ if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+ return -EINVAL;
+
ret = sscanf(buf, "%u", );
if (ret != 1)
return -EINVAL;
@@ -1137,11 +1155,12 @@ static ssize_t trans_stat_show(struct device *dev,
int i, j;
unsigned int max_state = devfreq->profile->max_state;
+ if (max_state == 0 || devfreq->governor->type == DEVFREQ_GOV_PASSIVE)
+ return sprintf(buf, "Not Supported.\n");
+
if (!devfreq->stop_polling &&
devfreq_update_status(devfreq, devfreq->previous_freq))
return 0;
- if (max_state == 0)
- return sprintf(buf, "Not Supported.\n");
len = sprintf(buf, " From : To\n");
len += sprintf(buf + len, " :");
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index fad7d6321978..43513a58f5bf 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -18,6 +18,13 @@
#define to_devfreq(DEV)container_of((DEV), struct devfreq, dev)
+/* Devfreq governor type */
+#define DEVFREQ_GOV_ONDEMAND 0x1
+#define DEVFREQ_GOV_PERFORMANCE0x2
+#define DEVFREQ_GOV_POWERSAVE 0x3
+#define DEVFREQ_GOV_USERSPACE 0x4
+#define DEVFREQ_GOV_PASSIVE0x4
+
/* Devfreq events */
#define DEVFREQ_GOV_START 0x1
#define DEVFREQ_GOV_STOP
[RFC PATCH 15/15] ARM: dts: Add support of bus frequency for exynos4412-trats
THis patch adds the bus device tree nodes for both MIF (Memory) and INT
(Internal) block to enable the bus frequency.
The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
bus is parent device in INT block using VDD_INT.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4412-trats2.dts | 47 +
1 file changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 40a474c4374b..aecd545803ad 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -1286,3 +1286,50 @@
vtmu-supply = <_reg>;
status = "okay";
};
+
+_dmc {
+ devfreq-events = <_dmc0_3>, <_dmc1_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_acp {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_c2c {
+ devfreq = <_dmc>;
+ status = "okay";
+};
+
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_display {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peri {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mfc {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
--
1.9.1
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[RFC PATCH 03/15] ARM: dts: Add DMC bus node for Exynos3250
This patch adds the DMC (DRAM memory controller) bus node for Exynos3250 SoC.
The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
SDRAM devices. The bus includes the OPP tables and the source clock for DMC
block.
Following list specifies the detailed relation between the clock and DMC block:
- The source clock of DMC block : div_dmc
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index be0bb32c2d8c..45809f83c628 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -700,6 +700,40 @@
clock-names = "ppmu";
status = "disabled";
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5000>;
+ opp-microvolt = <80>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <80>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <13300>;
+ opp-microvolt = <80>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <80>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <875000>;
+ };
+ };
};
};
--
1.9.1
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[RFC PATCH 14/15] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data between
DRAM and sub-blocks.
Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD
- ACLK133 clock for FSYS
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 119 ++
1 file changed, 119 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index c7ab2825d7cd..1b90d4984e35 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -355,6 +355,125 @@
};
};
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <_fsys_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <_peri_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13300>;
+ opp-microvolt = <925000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ };
+
+ bus_display_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13300>;
+ opp-microvolt = <925000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <100>;
+ };
+ };
+
+ bus_fsys_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13300>;
+ opp-microvolt = <925000>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5000>;
+
[RFC PATCH 12/15] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
This patch adds the bus device-tree node of INT (internal) block
to enable the bus frequency. The following sub-blocks share
the VDD_INT power source:
- LEFTBUS (parent device)
- RIGHTBUS
- PERIL
- LCD0
- FSYS
- MCUISP / ISP
The LEFTBUS is parent device with devfreq ondemand governor
and the rest devices has the dependency on LEFTBUS bus.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos3250-rinato.dts | 36 +
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 61477943015b..9fc90d83968c 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -681,6 +681,42 @@
status = "okay";
};
+_leftbus {
+ devfreq-events = <_leftbus_3>, <_rightbus_3>;
+ vdd-supply = <_reg>;
+ status = "okay";
+};
+
+_rightbus {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_lcd0 {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_fsys {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_mcuisp {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_isp {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
+_peril {
+ devfreq = <_leftbus>;
+ status = "okay";
+};
+
{
clock-frequency = <2400>;
};
--
1.9.1
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[RFC PATCH 13/15] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.
Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 73 +++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index b77dac61ffb5..c7ab2825d7cd 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -282,6 +282,79 @@
clocks = < CLK_SMMU_LITE1>, < CLK_FIMC_LITE1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_c2c: bus_c2c {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_C2C>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <95>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13300>;
+ opp-microvolt = <95>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <110>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <1>;
+ opp-microvolt = <95>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <13300>;
+ opp-microvolt = <95>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <16000>;
+ opp-microvolt = <95>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <100>;
+ };
+ };
+
};
{
--
1.9.1
--
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