Re: [PATCH v11 0/19] Add Analogix Core Display Port Driver

2015-12-17 Thread Heiko Stübner
Hi Yakir,

Am Mittwoch, 16. Dezember 2015, 11:20:18 schrieb Yakir Yang:
>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM

I'm really sorry for not thinking of this earlier, but I think we'll be doing 
the atomic modesetting conversion of the drm/kms driver first - see v3 series 
from Mark Yao.

Could you handle necessary changes to make it apply and work _after_ the 
atomic modesetting conversion please?


Thanks
Heiko


> But  there are still three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>register).
> 
> This series have been well tested on Rockchip platform with eDP panel on
> Jerry Chromebook and Display Port Monitor on RK3288 board. Also I have
> tested on Samsung Snow and Peach Pit Chromebooks, and thanks to
> Javier@Samsung help to retest the whole series on Samsung Exynos5800 Peach
> Pi Chromebook, glad to say that things works rightlly.
> 
> Thanks,
> - Yakir
> 
> 
> Changes in v11:
> - Uses tabs to fix the indentation issues in analogix_dp_core.h (Heiko)
> - Correct the title of this rockchip dp phy document(Rob)
> - Add the ack from Rob Herring
> - Rename the "analogix,need-force-hpd" to common 'force-hpd' (Rob)
> - Add the ack from Rob Herring
> - Revert parts of Gustavo Padovan's changes in commit:
>   drm/exynos: do not start enabling DP at bind() phase
>   Add dp phy poweron function in bind time.
> - Move the panel prepare from get_modes time to bind time, and move
>   the panel unprepare from bridge->disable to unbind time. (Heiko)
> 
> Changes in v10:
> - Add the ack from Rob Herring
> - Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here
> (Heiko) - Add the ack from Rob Herring
> - Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
> BIT(4) -> BIT(20)
> - Remove the surplus "plat_data" check. (Heiko)
> -   switch (dp->plat_data && dp->plat_data->dev_type) {
> +   switch (dp->plat_data->dev_type) {
> 
> Changes in v9:
> - Document more details for 'ports' property.
> - Removed the unused the variable "res" in probe function. (Heiko)
> - Removed the unused head file.
> 
> Changes in v8:
> - Correct the right document path of display-timing.txt (Heiko)
> - Correct the misspell of 'from' to 'frm'. (Heiko)
> - Modify the commit subject name. (Heiko)
> - Fix the mixed spacers on macro definitions. (Heiko)
> - Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
> - Remove the specific address in the example node name. (Heiko)
> 
> Changes in v7:
> - Back to use the of_property_read_bool() interfacs to provoid backward
>   compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>   to avoid -EOVERFLOW error (Krzysztof)
> - Simply the commit message. (Kishon)
> - Symmetrical enable/disbale the phy clock and power. (Kishon)
> - Simplify the commit message. (Kishon)
> 
> Changes in v6:
> - Fix the Kconfig recursive dependency (Javier)
> - Fix Peach Pit hpd property name error:
> -   hpd-gpio = < 6 0>;
> +   hpd-gpios = < 6 0>;
> 
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>   the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>   attch function. Cause once platform failed at attach, core driver should
>   still failed, so no need to init connector before platform attached
> (Krzysztof) - Keep code style no changes with the previous exynos_dp_code.c
> in this patch, and update commit message about the new export symbol
> (Krzysztof) - Gather the device type patch (v4 11/16) into this one.
> (Krzysztof) - leave out the connector registration to analogix platform
> driver. (Thierry) - Resequence this patch after analogix_dp driver have
> been split
>   from exynos_dp code, and rephrase reasonable commit message, and
>   remove some controversial style (Krzysztof)
> - analogix_dp_write_byte_to_dpcd(
> - dp, DP_TEST_RESPONSE,
> + analogix_dp_write_byte_to_dpcd(dp,
> + DP_TEST_RESPONSE,
>   DP_TEST_EDID_CHECKSUM_WRITE);
> - Switch video timing type to "u32", so driver could use
> "of_property_read_u32" to get the backword timing values. Krzysztof suggest
> me that driver could use the "of_property_read_bool" to get backword timing
> values, but that interfacs would 

Re: [PATCH v10 0/17] Add Analogix Core Display Port Driver

2015-12-14 Thread Heiko Stübner
Hi Yakir,

Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang:
>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM

so it looks like the hotplug works nicely now. I was able to test it 
sucessfully on both a Jerry and a Minnie device without needing to force 
hotplug :-) .

As I needed to adapt some patches when applying the lastest ones, I think it 
would be good for a full send of the latest version as v11.

When going over the patches before sending, please also fix the indentation 
issues in analogix_dp_core.h - both newly added elements to analogix_dp_device 
use spaces between type and name, where the rest uses tabs.
[This should of course be fixed in the patches adding these lines :-) ]


Heiko
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Re: [PATCH v10 0/17] Add Analogix Core Display Port Driver

2015-12-09 Thread Heiko Stübner
Hi Yakir,

Am Mittwoch, 9. Dezember 2015, 11:49:10 schrieb Yakir Yang:
> Thanks a lot for great debugging.
> 
> On 12/08/2015 11:33 PM, Heiko Stübner wrote:
> > Hi Yakir,
> > 
> > Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang:
> >> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> >> 
> >> share the same IP, so a lot of parts can be re-used. I split the common
> >> code into bridge directory, then rk3288 and exynos only need to keep
> >> some platform code. Cause I can't find the exact IP name of exynos dp
> >> controller, so I decide to name dp core driver with "analogix" which I
> >> find in rk3288 eDP TRM
> > 
> > [...]
> > 
> >> Changes in v10:
> >> - Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here
> >> (Heiko) - Fix the wrong macro value of
> >> GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4) -> BIT(20)
> >> - Remove the surplus "plat_data" check. (Heiko)
> >> -   switch (dp->plat_data && dp->plat_data->dev_type) {
> >> +   switch (dp->plat_data->dev_type) {
> >> 
> >> - Revert parts of Gustavo Padovan's changes in commit:
> >>drm/exynos: do not start enabling DP at bind() phase
> >>
> >>Add dp phy poweron function in bind time.
> > 
> > The hotplug issue is still present, but I think I found the cause. When
> > the first detect call happens, the display simply is still off. I just did
> > some very basic tracing [0] and it seems the display simply is not enabled
> > when it is supposed to get detected.
> 
> Aha, thanks, make a lot of sense.
> 
> > And it seems injecting a drm_panel_prepare early for _testing_ [1] really
> > did make the hotplug work on both my jerry and minnie.
> > 
> > So I guess we should somehow make sure the panel is actually powered when
> > detection is running. Although I'm not sure yet, how that should look
> > like.
> 
> Agree, panel should be powered up before DP controller start to detect
> hotplug signal.
> 
> > Intuition suggests, making drm_panel calls nestable (similar to
> > clk_prepare/unprepare, etc) and simply wrapping the detection code
> > in a prepare-unprepare calls, but I'm not sure if Thierry might have other
> > ideas ;-)
> 
> Due to the panel power status would influence the hotplug status, so I
> think we don't
> need to unprepared the panel unless in driver enter into suspend time.
> Things I want:
> 
> 1. Prepared the panel in driver *bind time*
> 2. Enable the panel in driver *bridge->enable time*
> 3. Disable the panel in driver *bridge->disable time*
> 4. Unprepared the panel in driver*suspend time *
> 5. Re-prepared the panel in driver *resume time*
6. Unprepare the panel in driver at *unbind time*

otherwise going that way looks nice.


> > Also my "log" below suggests some sort of mismatch between
> > prepare/unprepare calls, as there are a lot more of the prepare-side.
> 
> Yes, it's a typo too. I shouldn't place the panel->prepare in
> connector->get_modes,
> cause userspace would try to call get_modes once it receive the hotplug
> event, so
> there wouldn't have a match between panel prepare/unprepare.
> 
> Previously, I just want to ensure that panel should be power-up when
> driver try to
> read the EDID from panel, so for now must remove the prepare from
> get_modes time  :)
> 
> > And the locking issue also seems to be still there [2].
> 
> Hmm, I haven't meet this dead lock on my chromebook (ChromeOS + 4.4-rc3
> Kernel)
> 
> After look at the dead lock trace, I guess this dead lock would happened
> when hotplug
> event happened in bridge->disable time, not sure.  Would try to find
> more in trace log
> and try to reproduce this.

It is not an actual deadlock, but a warning that a deadlock might happen.
So you need to have LOCKDEP on. My kernels are currently running with

CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
CONFIG_DEBUG_LOCKDEP=y
CONFIG_DEBUG_ATOMIC_SLEEP=y

and I see this mostly when changing between X11, console and back to X11.


Heiko

> > Heiko
> > 
> > 
> > [0]
> > [2.797383] analogix_dp_reset
> > [2.800709] analogix_dp_init_hpd
> > [2.803960] analogix_dp_init_video
> > [2.807653] rockchip-drm display-subsystem: bound ff97.dp (ops
> > rockchip_dp_component_ops) [2.817176] [drm] Supports vblank timestamp
> > caching Rev 2 (21.10.2013). [2.823799] [drm] No driver support for
> > vblank timestamp query. [2.829947] 

Re: [PATCH v10 0/17] Add Analogix Core Display Port Driver

2015-12-08 Thread Heiko Stübner
Hi Yakir,

Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang:
>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM

[...]

> Changes in v10:
> - Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here
> (Heiko) - Fix the wrong macro value of
> GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4) -> BIT(20)
> - Remove the surplus "plat_data" check. (Heiko)
> -   switch (dp->plat_data && dp->plat_data->dev_type) {
> +   switch (dp->plat_data->dev_type) {
> - Revert parts of Gustavo Padovan's changes in commit:
>   drm/exynos: do not start enabling DP at bind() phase
>   Add dp phy poweron function in bind time.

The hotplug issue is still present, but I think I found the cause. When
the first detect call happens, the display simply is still off. I just did
some very basic tracing [0] and it seems the display simply is not enabled
when it is supposed to get detected.

And it seems injecting a drm_panel_prepare early for _testing_ [1] really
did make the hotplug work on both my jerry and minnie.

So I guess we should somehow make sure the panel is actually powered when
detection is running. Although I'm not sure yet, how that should look like.


Intuition suggests, making drm_panel calls nestable (similar to
clk_prepare/unprepare, etc) and simply wrapping the detection code
in a prepare-unprepare calls, but I'm not sure if Thierry might have other
ideas ;-)


Also my "log" below suggests some sort of mismatch between
prepare/unprepare calls, as there are a lot more of the prepare-side.


And the locking issue also seems to be still there [2].


Heiko


[0]
[2.797383] analogix_dp_reset
[2.800709] analogix_dp_init_hpd
[2.803960] analogix_dp_init_video
[2.807653] rockchip-drm display-subsystem: bound ff97.dp (ops 
rockchip_dp_component_ops)
[2.817176] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[2.823799] [drm] No driver support for vblank timestamp query.
[2.829947] analogix_dp_detect
[2.833015] analogix_dp_get_plug_in_status: hpd status 0
...
[2.893425] analogix_dp_get_plug_in_status: hpd status 0
[2.893456] rockchip-dp ff97.dp: failed to get hpd plug status, try to 
force hpd
[2.893458] analogix_dp_force_hpd
[2.893464] analogix_dp_get_plug_in_status: hpd status 112
[2.893470] panel_simple_prepare
[2.952183] rockchip-dp ff97.dp: EDID data does not include any 
extensions.
[2.961727] panel_simple_get_modes
[3.432154] analogix_dp_detect
[3.432158] analogix_dp_get_plug_in_status: hpd status 120
[3.432160] panel_simple_prepare
[3.433731] rockchip-dp ff97.dp: EDID data does not include any 
extensions.
[3.443268] panel_simple_get_modes
[3.444668] panel_simple_prepare
[3.444755] analogix_dp_reset
[3.445078] analogix_dp_init_hpd
[3.445096] panel_simple_disable
[3.455349] analogix_dp_init_video
[3.558323] rockchip-dp ff97.dp: Timeout of video streamclk ok
[3.558326] rockchip-dp ff97.dp: unable to config video
[3.558328] panel_simple_enable
[3.573915] analogix_dp_detect
[3.573919] analogix_dp_get_plug_in_status: hpd status 72
[3.573921] panel_simple_prepare


[1]
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 3990951..0c2dca5 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -399,6 +399,8 @@ static int rockchip_dp_probe(struct platform_device *pdev)
 
dp->plat_data.panel = panel;
 
+drm_panel_prepare(dp->plat_data.panel);
+
/*
 * We just use the drvdata until driver run into component
 * add function, and then we would set drvdata to null, so


[2]
[   11.971277] panel_simple_get_modes
[  OK  ] Started LSB: X display manager for KDE.
[  OK  ] Started LSB: Speech Dispatcher.
[   12.007120] panel_simple_disable
[   12.012323] 
[   12.013820] ==
[   12.019993] [ INFO: possible circular locking dependency detected ]
[   12.026250] 4.4.0-rc3+ #2755 Not tainted
[   12.030165] ---
[  12.036417] Xorg/793 is trying to acquire lock:
[   12.040855]  ((>hotplug_work)){+.+...}[   12.040870] 
[   12.040870] but task is already holding lock:
[   12.040871]  (crtc_ww_class_mutex){+.+.+.}, at: [] 
drm_modeset_lock+0x84/0x104
[   12.040881] 
[   12.040881] which lock already depends on the new lock.
[   12.040881] 
[   12.040882] 
[   12.040882] the existing dependency chain (in reverse order) is:
[   12.040883] 
[   12.040883] -> #2 

Re: [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288

2015-11-27 Thread Heiko Stübner
Am Mittwoch, 28. Oktober 2015, 16:56:01 schrieb Yakir Yang:
> There are some IP limit on rk3288 that only support 4 physical lanes
> of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
> 
> Tested-by: Javier Martinez Canillas 
> Signed-off-by: Yakir Yang 
> ---

[...]

> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
> 6307060..563ffb1d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device
> *dp) return;
>   }
> 
> - ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> -  dp->video_info.link_rate);
> + ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
> +  dp->video_info.max_link_rate);
>   if (ret) {
>   dev_err(dp->dev, "unable to do link train\n");
>   return;
> @@ -1156,16 +1156,25 @@ static int analogix_dp_dt_parse_pdata(struct
> analogix_dp_device *dp) struct device_node *dp_node = dp->dev->of_node;
>   struct video_info *video_info = >video_info;
> 
> - if (of_property_read_u32(dp_node, "samsung,link-rate",
> -  _info->link_rate)) {
> - dev_err(dp->dev, "failed to get link-rate\n");
> - return -EINVAL;
> - }
> -
> - if (of_property_read_u32(dp_node, "samsung,lane-count",
> -  _info->lane_count)) {
> - dev_err(dp->dev, "failed to get lane-count\n");
> - return -EINVAL;
> + switch (dp->plat_data && dp->plat_data->dev_type) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c: In function 
‘analogix_dp_dt_parse_pdata’:
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:1191:10: warning: switch 
condition has boolean value [-Wswitch-bool]
  switch (dp->plat_data && dp->plat_data->dev_type) {
  ^

As I think we always will need to distinguish between implementations,
I guess it should be safe to exit with an error, it that implementation-data
is not available, like just doing before the switch a:

if (!dp->plat_data)
return -EINVAL;


Heiko
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Re: [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver

2015-11-27 Thread Heiko Stübner
Hi Yakir,

Am Mittwoch, 28. Oktober 2015, 16:27:45 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Tested-by: Javier Martinez Canillas 
> Signed-off-by: Yakir Yang 
> ---

> diff --git a/drivers/gpu/drm/rockchip/Kconfig
> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
> for the Synopsys DesignWare HDMI driver. If you want to
> enable HDMI on RK3288 based SoC, you should selet this
> option.
> +
> +config ROCKCHIP_ANALOGIX_DP
> +tristate "Rockchip specific extensions for Analogix DP driver"
> +depends on DRM_ROCKCHIP
> +select DRM_ANALOGIX_DP
> +help

the indentation should probably be tabs here, ROCKCHIP_DW_HDMI also does it 
wrong it seems, but DRM_ROCKCHIP looks correct :-)


Heiko
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Re: [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory

2015-11-26 Thread Heiko Stübner
Hi Yakir,

Am Mittwoch, 28. Oktober 2015, 16:21:59 schrieb Yakir Yang:
> Split the dp core driver from exynos directory to bridge directory,
> and rename the core driver to analogix_dp_*, rename the platform
> code to exynos_dp.
> 
> Beside the new analogix_dp driver would export four hooks.
> "analogix_dp_bind()" and "analogix_dp_unbind()"
> "analogix_dp_detect()" and "analogix_dp_get_modes()"
> 
> The bind/unbind symbols is used for analogix platform driver to connect
> with analogix_dp core driver. And the detect/get_modes is used for analogix
> platform driver to init the connector.
> 
> They reason why connector need register in helper driver is rockchip drm
> haven't implement the atomic API, but Exynos drm have implement it, so
> there would need two different connector helper functions, that's why we
> leave the connector register in helper driver.
> 
> Tested-by: Javier Martinez Canillas 
> Signed-off-by: Yakir Yang 

[...]

> diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
> index bd1a415..5f74f80 100644
> --- a/drivers/gpu/drm/exynos/Kconfig
> +++ b/drivers/gpu/drm/exynos/Kconfig
> @@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
> This enables support for Exynos MIPI-DSI device.
> 
>  config DRM_EXYNOS_DP
> - bool "EXYNOS DRM DP driver support"
> + bool "EXYNOS specific extensions for Analogix DP driver"
>   depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
> + select DRM_ANALOGIX_DP
>   default DRM_EXYNOS
>   select DRM_PANEL
>   help

This doesn't apply anymore to 4.4-rc due to other changes in there. The 
exynos/Makefile is affected as well.

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Re: [PATCH v3 1/3] dt-bindings: Consolidate SRAM bindings from all vendors

2015-10-23 Thread Heiko Stübner
Am Freitag, 23. Oktober 2015, 10:39:19 schrieb Krzysztof Kozlowski:
> SRAM bindings for various SoCs, using the mmio-sram genalloc
> API, are spread over different places - per SoC vendor. Since all of
> these are quite similar (they depend on mmio-sram) move them to a common
> place.
> 
> Signed-off-by: Krzysztof Kozlowski 
> Cc: Heiko Stuebner 
> Cc: Maxime Ripard 
> Cc: Chen-Yu Tsai 
> Cc: Kukjin Kim 
> Suggested-by: Rob Herring 
> 
> ---
> 
> Changes since v2:
> 1. Update paths to sram.txt.
> 
> Changes since v1:
> 1. New patch. Extended suggestion from Rob.
> ---

> .../bindings/{arm/rockchip/pmu-sram.txt => sram/rockchip-pmu-sram.txt} 
> .../bindings/{arm/rockchip/smp-sram.txt => sram/rockchip-smp-sram.txt} 

for the Rockchip parts
Acked-by: Heiko Stuebner 
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Re: [PATCH] mmc: pwrseq: Use highest priority for eMMC restart handler

2015-10-22 Thread Heiko Stübner
Am Donnerstag, 22. Oktober 2015, 08:34:38 schrieb Doug Anderson:
> Note that personally I would only choose the "highest" priority as an
> absolute last resort.  Leaving a little extra slack in there means
> that when the next person comes up with a really good reason to run
> before you do that they can do it without changing your code. 

just to reiterate, restart-handlers are generally not meant as "things to do 
before restart", but "are supposed to restart the system, nothing else" [0].

Just in this case there hasn't been a better solution found for the needed 
reset even in emergency-reboots ... but this misappropriation of restart-
handlers should not spread into further realms, so there shouldn't be a "next 
person" ;-) .


[0] http://permalink.gmane.org/gmane.linux.kernel/1968815



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Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY

2015-10-12 Thread Heiko Stübner
Am Montag, 12. Oktober 2015, 20:32:47 schrieb Kishon Vijay Abraham I:
> Hi,
> 
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> > This phy driver would control the Rockchip DisplayPort module
> > phy clock and phy power, it is relate to analogix_dp-rockchip
> > dp driver. If you want DP works rightly on rockchip platform,
> > then you should select both of them.
> 
> Add phy driver for the Rockchip DisplayPort PHY module. This is required
> to get DisplayPort working in Rockchip SoCs.
> 
> > Signed-off-by: Yakir Yang 
> > ---
> > Changes in v6: None
> > Changes in v5:
> > - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> > 
> >   the exist "grf" syscon already. And rename the example DT node from
> >   "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> > 
> > - Add deivce_node at the front of driver, update phy_ops type from "static
> > 
> >   struct" to "static const struct". And correct the input paramters of
> >   devm_phy_create() interfaces. (Heiko)
> > 
> > Changes in v4:
> > - Add commit message, and remove the redundant rockchip_dp_phy_init()
> > 
> >   function, move those code to probe() method. And remove driver .owner
> >   number. (Kishon)
> > 
> > Changes in v3:
> > - Suggest, add rockchip dp phy driver, collect the phy clocks and
> > 
> >   power control. (Heiko)
> > 
> > Changes in v2: None
> > 
> >  drivers/phy/Kconfig   |   7 ++
> >  drivers/phy/Makefile  |   1 +
> >  drivers/phy/phy-rockchip-dp.c | 151
> >  ++ 3 files changed, 159
> >  insertions(+)
> >  create mode 100644 drivers/phy/phy-rockchip-dp.c
> > 
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 47da573..8f2bc4f 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> > 
> > help
> > 
> >   Enable this to support the Rockchip USB 2.0 PHY.
> > 
> > +config PHY_ROCKCHIP_DP
> > +   tristate "Rockchip Display Port PHY Driver"
> > +   depends on ARCH_ROCKCHIP && OF
> > +   select GENERIC_PHY
> > +   help
> > + Enable this to support the Rockchip Display Port PHY.
> > +
> > 
> >  config PHY_ST_SPEAR1310_MIPHY
> >  
> > tristate "ST SPEAR1310-MIPHY driver"
> > select GENERIC_PHY
> > 
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index a5b18c1..e281f35 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+=
> > phy-s5pv210-usb2.o> 
> >  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
> >  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> > 
> > +obj-$(CONFIG_PHY_ROCKCHIP_DP)  += phy-rockchip-dp.o
> > 
> >  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
> > 
> > diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> > new file mode 100644
> > index 000..3a2ac120
> > --- /dev/null
> > +++ b/drivers/phy/phy-rockchip-dp.c
> > @@ -0,0 +1,151 @@
> > +/*
> > + * Rockchip DP PHY driver
> > + *
> > + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> > + * Author: Yakir Yang 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define GRF_SOC_CON12   0x0274
> > +#define GRF_EDP_REF_CLK_SEL_INTER  BIT(4)
> > +#define GRF_EDP_PHY_SIDDQ_WRITE_EN  BIT(21)
> > +#define GRF_EDP_PHY_SIDDQ_ON0
> > +#define GRF_EDP_PHY_SIDDQ_OFF   BIT(5)
> > +
> > +struct rockchip_dp_phy {
> > +   struct device  *dev;
> > +   struct regmap  *grf;
> > +   struct clk *phy_24m;
> > +};
> > +
> > +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> > +{
> > +   struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> > +   int ret;
> > +
> > +   if (enable) {
> > +   ret = clk_prepare_enable(dp->phy_24m);
> > +   if (ret < 0) {
> > +   dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> > +   return ret;
> > +   }
> > +
> > +   ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +  GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +  GRF_EDP_PHY_SIDDQ_ON);
> > +   } else {
> > +   clk_disable_unprepare(dp->phy_24m);
> 
> should clk_disable come after regmap_write? It'll be symmetric to enable?
> 
> > +   ret = 

Re: [RFC PATCH v5 1/9] mmc: dw_mmc: Add external dma interface support

2015-08-14 Thread Heiko Stübner
Hi Shawn,

Am Freitag, 14. August 2015, 16:34:35 schrieb Shawn Lin:
 DesignWare MMC Controller can supports two types of DMA
 mode: external dma and internal dma. We get a RK312x platform
 integrated dw_mmc and ARM pl330 dma controller. This patch add
 edmac ops to support these platforms. I've tested it on RK312x
 platform with edmac mode and RK3288 platform with idmac mode.
 
 Signed-off-by: Shawn Lin shawn@rock-chips.com

judging by your from, I guess you're running this on some older Rockchip soc 
without the idma? Because I tried testing this on a Radxa Rock, but only got 
failures, from the start (failed to read card status register). In PIO mode 
everything works again.


I guess I overlooked just some tiny detail, but to me the dma channel ids seem 
correct after all. Maybe you have any hints what I'm doing wrong?

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 4497d28..92d7156 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -217,6 +217,8 @@
interrupts = GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_SDMMC, cru SCLK_SDMMC;
clock-names = biu, ciu;
+ dmas = dmac2 1;
+ dma-names = rx-tx;
fifo-depth = 256;
status = disabled;
};
@@ -227,6 +229,8 @@
interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_SDIO, cru SCLK_SDIO;
clock-names = biu, ciu;
+ dmas = dmac2 3;
+ dma-names = rx-tx;
fifo-depth = 256;
status = disabled;
};
@@ -237,6 +241,8 @@
interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_EMMC, cru SCLK_EMMC;
clock-names = biu, ciu;
+ dmas = dmac2 4;
+ dma-names = rx-tx;
fifo-depth = 256;
status = disabled;
};


[...]

 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index fcbf552..e01ead3 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -2517,8 +2642,23 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot
 *slot, unsigned int id) static void dw_mci_init_dma(struct dw_mci *host)
  {
   int addr_config;
 + int trans_mode;
 + struct device *dev = host-dev;
 + struct device_node *np = dev-of_node;
 +
 + /* Check tansfer mode */
 + trans_mode = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
 + if (trans_mode == 0) {
 + trans_mode = TRANS_MODE_IDMAC;
 + } else if (trans_mode == 1 || trans_mode == 2) {
 + trans_mode = TRANS_MODE_EDMAC;
 + } else {
 + trans_mode = TRANS_MODE_PIO;
 + goto no_dma;
 + }
 +
   /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
 - addr_config = (mci_readl(host, HCON)  27)  0x01;
 + addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
 
   if (addr_config == 1) {
   /* host supports IDMAC in 64-bit address mode */

I guess the idmac address size checking block

/* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));

if (addr_config == 1) {
/* host supports IDMAC in 64-bit address mode */
host-dma_64bit_address = 1;
dev_info(host-dev, IDMAC supports 64-bit address mode.\n);
if (!dma_set_mask(host-dev, DMA_BIT_MASK(64)))
dma_set_coherent_mask(host-dev, DMA_BIT_MASK(64));
} else {
/* host supports IDMAC in 32-bit address mode */
host-dma_64bit_address = 0;
dev_info(host-dev, IDMAC supports 32-bit address mode.\n);
}

could either live inside the trans_mode == 0 conditional above or get its own
if (trans_mode == 0) conditional. Either way I guess it should not talk about 
idmac when either pio or extdmac are used.


Thanks
Heiko
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Re: [PATCH 2/2] clk: Convert __clk_get_name(hw-clk) to clk_hw_get_name(hw)

2015-08-13 Thread Heiko Stübner
Am Mittwoch, 12. August 2015, 16:12:41 schrieb Stephen Boyd:
 Use the provider based method to get a clock's name so that we
 can get rid of the clk member in struct clk_hw one day. Mostly
 converted with the following coccinelle script.
 
 @@
 struct clk_hw *E;
 @@
 
 -__clk_get_name(E-clk)
 +clk_hw_get_name(E)
 

For the Rockchip part
Reviewed-by: Heiko Stuebner he...@sntech.de


Heiko

 diff --git a/drivers/clk/rockchip/clk-inverter.c
 b/drivers/clk/rockchip/clk-inverter.c index 8054fdb5effb..7cbf43beb3c6
 100644
 --- a/drivers/clk/rockchip/clk-inverter.c
 +++ b/drivers/clk/rockchip/clk-inverter.c
 @@ -50,7 +50,7 @@ static int rockchip_inv_set_phase(struct clk_hw *hw, int
 degrees) val = !!degrees;
   } else {
   pr_err(%s: unsupported phase %d for %s\n,
 -__func__, degrees, __clk_get_name(hw-clk));
 +__func__, degrees, clk_hw_get_name(hw));
   return -EINVAL;
   }
 
 diff --git a/drivers/clk/rockchip/clk-mmc-phase.c
 b/drivers/clk/rockchip/clk-mmc-phase.c index 77e19097bdc7..9b613426e968
 100644
 --- a/drivers/clk/rockchip/clk-mmc-phase.c
 +++ b/drivers/clk/rockchip/clk-mmc-phase.c
 @@ -108,7 +108,7 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int
 degrees) writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock-shift),
 mmc_clock-reg);
 
   pr_debug(%s-set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x
 actual_degrees=%d\n, -   __clk_get_name(hw-clk), degrees, 
 delay_num,
 + clk_hw_get_name(hw), degrees, delay_num,
   mmc_clock-reg, raw_value(mmc_clock-shift),
   rockchip_mmc_get_phase(hw)
   );

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Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver

2015-08-10 Thread Heiko Stübner
Hi Yakir,

Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
  +static int rockchip_dp_init(struct rockchip_dp_device *dp)
  +{
  +  struct device *dev = dp-dev;
  +  struct device_node *np = dev-of_node;
  +  int ret;
  +
  +  dp-grf = syscon_regmap_lookup_by_phandle(np, rockchip,grf);
  +  if (IS_ERR(dp-grf)) {
  +  dev_err(dev,
  +  rk3288-dp needs rockchip,grf property\n);
  +  return PTR_ERR(dp-grf);
  +  }
  +
  +  dp-clk_dp = devm_clk_get(dev, clk_dp);
  
  I've looked at the manual, but couldn't find an actual clock-name
  used there. Is it really clk_dp or should it just be dp?
 
 This should be clk_dp, not dp.
 Cause analogix_dp_core would need a clock name with dp, so I would
 rather to pasted my rockchip-dp node here before I add dt-bindings in
 next version ;)

The clock we name PCLK_EDP_CTRL in the clock controller is probably the clock 
supplying the APB interface and named pclk already in the Figure 3-2 
DP_TXclock domain diagram on page 19 of the manual. So your clk_dp should 
actually be pclk.

So you would have dp, dp_24m and pclk for the 3 supplying clocks.


 
  edp: edp@ff97 {
  compatible = rockchip,rk3288-dp;
  reg = 0xff97 0x4000;
  interrupts = GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH;
 
  clocks = cru SCLK_EDP, cru SCLK_EDP_24M, cru
 PCLK_EDP_CTRL;
  clock-names = clk_dp, clk_dp_24m, dp;
 
  rockchip,grf = grf;
  resets = cru 111;
  reset-names = dp;
  power-domains = power RK3288_PD_VIO;
  status = disabled;
 
  hsync-active-high = 0;
  vsync-active-high = 0;
  interlaced = 0;
  samsung,color-space = 0;
  samsung,dynamic-range = 0;
  samsung,ycbcr-coeff = 0;
  samsung,color-depth = 1;
  samsung,link-rate = 0x0a;
  samsung,lane-count = 1;

Thierry already said, that these should probably be somehow auto-detected. 
Properties needing to stay around should probably also be analogix,... with 
a fallback to not break Samsung devicetrees, so
look for analogix,foo!, if not found try samsung,foo


  ports {
  edp_in: port {
  #address-cells = 1;
  #size-cells = 0;
  edp_in_vopb: endpoint@0 {
  reg = 0;
  remote-endpoint = vopb_out_edp;
  };
  };
  };



  +
  +  dp-clk_24m = devm_clk_get(dev, clk_dp_24m);
  
  Same here, maybe dp_24m.
 
 Like my previous reply. And actually as those two clocks all have
 a common prefix SCLK in rk3288 clock tree, I thinkt we can name
 them to sclk_dp  sclk_dp_24m, is it okay ?

As Thierry said, please don't add prefixes.


 
  +  if (IS_ERR(dp-clk_24m)) {
  +  dev_err(dev, cannot get clk_dp_24m\n);
  +  return PTR_ERR(dp-clk_24m);
  +  }
  
  I think you're missing the pclk here (PCLK_EDP_CTRL) or is this part of
  something else?
 
 Whops, as I refered in commit message I leave pclk_dp to
 analogix_dp_core driver ;-)
 
 The reason why I want to leave pclk is I thought this clock is more like
 analogix dp
 core driver want, like a IP controller clock (whatever analogix_dp do
 need a clock
 named with dp).

Hmm, I'd think what the core (and Samsung) driver use as dp clock is 
probably the generic clock for the IP and not the pclk for the APB interface.

So I think it still should be  dp for the core and dp_24m + pclk for the 
rockchip part?


 
  +
  +  dp-rst = devm_reset_control_get(dev, dp);
  +  if (IS_ERR(dp-rst)) {
  +  dev_err(dev, failed to get reset\n);
  +  return PTR_ERR(dp-rst);
  +  }
  +
  +  ret = rockchip_dp_clk_enable(dp);
  +  if (ret  0) {
  +  dev_err(dp-dev, cannot enable dp clk %d\n, ret);
  +  return ret;
  +  }
  +
  +  ret = rockchip_dp_pre_init(dp);
  +  if (ret  0) {
  +  dev_err(dp-dev, failed to pre init %d\n, ret);
  +  return ret;
  +  }
  +
  +  return 0;
  +}
  
  [...]
  
  +static int rockchip_dp_probe(struct platform_device *pdev)
  +{
  +  struct device *dev = pdev-dev;
  +  struct device_node *panel_node;
  +  struct rockchip_dp_device *dp;
  +  struct drm_panel *panel;
  +
  +  panel_node = of_parse_phandle(dev-of_node, rockchip,panel, 0);
  +  if (!panel_node) {
  +  DRM_ERROR(failed to find rockchip,panel dt node\n);
  +  return -ENODEV;
  +  }
  
  Personally I would prefer to continue with the of-graph framework to
  attach the panel instead of defining a special node. But I'm not
  authorative on this. But that way the dts could then look like [0].
  
  I've sucessfully modified the driver currently in use 

Re: [PATCH v2 4/8] drm: rockchip/dp: add rockchip platform dp driver

2015-08-07 Thread Heiko Stübner
Hi Yakir,


I think this Rockchip portion is missing a devicetree binding.

You have the ability to power down the actual edp phy by using
grf_edp_iddq_en from GRF_SOC_CON12. This is similar to how the
rk3288 usb-phy gets put into a deeper state. So maybe you could
provide a phy driver (drivers/phy) for this similar to what the
exynos-dp does.

Some more stuff inline. But I guess by no means complete, as I'm
still trying to integrate this into my development-tree.


Am Freitag, 7. August 2015, 05:46:20 schrieb Yakir Yang:
 Rockchip have three clocks for dp controller, we leave pclk_edp
 to analogix_dp driver control, and keep the sclk_edp_24m and
 sclk_edp in platform driver.
 
 Signed-off-by: Yakir Yang y...@rock-chips.com
 ---
 Changes in v2: None
 
  drivers/gpu/drm/rockchip/Kconfig|  10 +
  drivers/gpu/drm/rockchip/Makefile   |   1 +
  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 419
  3 files changed, 430 insertions(+)
  create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 
 diff --git a/drivers/gpu/drm/rockchip/Kconfig
 b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..096ed77 100644
 --- a/drivers/gpu/drm/rockchip/Kconfig
 +++ b/drivers/gpu/drm/rockchip/Kconfig
 @@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI
 for the Synopsys DesignWare HDMI driver. If you want to
 enable HDMI on RK3288 based SoC, you should selet this
 option.
 +
 +

nit: double blank line

 +config ROCKCHIP_ANALOGIX_DP
 +tristate Rockchip specific extensions for Analogix DP driver
 +depends on DRM_ROCKCHIP
 +select DRM_ANALOGIX_DP
 +help
 +   This selects support for Rockchip SoC specific extensions
 +   for the Analogix Core DP driver. If you want to enable DP
 +   on RK3288 based SoC, you should selet this option.

[...]


 diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
 index 000..2f86e5e
 --- /dev/null
 +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 @@ -0,0 +1,419 @@
 +/*
 + * Rockchip SoC DP (Display Port) interface driver.
 + *
 + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
 + * Author: Andy Yan andy@rock-chips.com
 + * Yakir Yang y...@rock-chips.com
 + * Jeff Chen jeff.c...@rock-chips.com
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or (at your
 + * option) any later version.
 + */
 +#include drm/drmP.h
 +#include drm/drm_crtc_helper.h
 +#include drm/drm_panel.h
 +#include drm/drm_of.h
 +#include drm/drm_dp_helper.h
 +
 +#include linux/component.h
 +#include linux/clk.h
 +#include linux/mfd/syscon.h
 +#include linux/regmap.h
 +#include linux/reset.h
 +
 +#include video/of_videomode.h
 +#include video/videomode.h
 +
 +#include drm/bridge/analogix_dp.h
 +
 +#include rockchip_drm_drv.h
 +#include rockchip_drm_vop.h
 +
 +#define encoder_to_dp(c) \
 + container_of(c, struct rockchip_dp_device, encoder)
 +
 +#define plat_data_to_dp(pd) \
 + container_of(pd, struct rockchip_dp_device, plat_data)
 +
 +/* dp grf register offset */
 +#define DP_VOP_SEL  0x025c /* grf_soc_con6 */
 +#define DP_REF_CLK_SEL  0x0274 /* grf_soc_con12 */
 +
 +#define GRF_DP_REF_CLK_SEL_INTERBIT(4)
 +#define DP_SEL_VOP_LIT   BIT(5)
 +
 +struct rockchip_dp_device {
 + struct drm_device*drm_dev;
 + struct device*dev;
 + struct drm_encoder   encoder;
 + struct drm_display_mode  mode;
 +
 + struct clk   *clk_dp;
 + struct clk   *clk_24m_parent;

this clk_24m_parent does not seem used at all

 + struct clk   *clk_24m;
 + struct regmap*grf;
 + struct reset_control *rst;
 +
 + struct analogix_dp_plat_data plat_data;
 +};
 +

[...]

 +static int rockchip_dp_init(struct rockchip_dp_device *dp)
 +{
 + struct device *dev = dp-dev;
 + struct device_node *np = dev-of_node;
 + int ret;
 +
 + dp-grf = syscon_regmap_lookup_by_phandle(np, rockchip,grf);
 + if (IS_ERR(dp-grf)) {
 + dev_err(dev,
 + rk3288-dp needs rockchip,grf property\n);
 + return PTR_ERR(dp-grf);
 + }
 +
 + dp-clk_dp = devm_clk_get(dev, clk_dp);

I've looked at the manual, but couldn't find an actual clock-name
used there. Is it really clk_dp or should it just be dp?


 + if (IS_ERR(dp-clk_dp)) {
 + dev_err(dev, cannot get clk_dp\n);
 + return PTR_ERR(dp-clk_dp);
 + }
 +
 + dp-clk_24m = devm_clk_get(dev, clk_dp_24m);

Same here, maybe dp_24m.


 + if (IS_ERR(dp-clk_24m)) {
 + dev_err(dev, cannot get clk_dp_24m\n);
 +  

Re: [PATCH v7 0/8] mfd: cros_ec: Add multi EC and proto v3 support

2015-06-11 Thread Heiko Stübner
Am Dienstag, 9. Juni 2015, 13:04:41 schrieb Javier Martinez Canillas:
 Hello,
 
 This is a v7 of a series that adds support for multiple EC in a system
 and also for the protocol version 3 that is used on newer ECs.
 
 Most patches were taken from the downstream ChromiumOS v3.14 tree with
 fixes squashed, split to minimise the cross subsystem churn and changes
 for mainline inclusion but were not modified functionality wise.
 
 This version addresses issues pointed out by Lee Jones on the v6 posted
 before [0] and also adds the Acked-by tags of all the needed maintainers.
 
 The patches are based on top of [PATCH 0/2] mfd: cros_ec: Small cleanups
 [1] that were posted before and already picked by Lee Jones.
 
 Testing was done on some Chromebooks that have a single EC and support
 protocol v2 such as the Exynos5250 Snow, Exynos5420 Peach Pit and Exynos5800
 Peach Pi to be sure that no regressions were introduced for these machines.
 
 The series were tested using a modified ectool [2] that supports the new
 cros_ec IOCTL API. They were also tested on a x86 Pixel Chromebook 2 (Samus)
 that uses the new protocol v3 and has 2 EC (cros_ec and cros_pd). But for
 testing on Samus, also the posted [PATCH 0/3] platform/chrome: Changes for
 cros_ec_lpc and cros_ec_dev series [3] are needed.

everything still works as expected on a rk3288-veyron-jerry

Tested-by: Heiko Stuebner he...@sntech.de
[tags are already present in the patches]


As the series now has Olof's Ack, can this still make it in time for 4.2 - as 
there is still a bit more than a week left till the merge window?


Heiko
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Re: [PATCH 1/8] cpufreq: arm_big_little: add cluster regulator support

2015-06-11 Thread Heiko Stübner
Hi,

Am Dienstag, 21. April 2015, 15:17:51 schrieb Bartlomiej Zolnierkiewicz:
 Add cluster regulator support as a preparation to adding
 generic arm_big_little_dt cpufreq_dt driver support for
 ODROID-XU3 board.  This allows arm_big_little[_dt] driver
 to set not only the frequency but also the voltage (which
 is obtained from operating point's voltage value) for CPU
 clusters.
 
 Cc: Kukjin Kim kgene@samsung.com
 Cc: Doug Anderson diand...@chromium.org
 Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
 Cc: Andreas Faerber afaer...@suse.de
 Cc: Sachin Kamat sachin.ka...@linaro.org
 Cc: Thomas Abraham thomas...@samsung.com
 Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com

I gave this a spin on the rk3368 arm64 soc from Rockchip, mainly to check if
my armclk handling was correct.

Your patch here only supports individual supplies per cluster but my
current board shares the supplies over both cpu clusters, so I've cooked
up a patch to also try to support shared supplies
[0].

Nevertheless,
Tested-by: Heiko Stuebner he...@sntech.de

Do you plan to continue working on this?


Thanks
Heiko


[0]  8 -
From: Heiko Stuebner he...@sntech.de
Subject: [PATCH] cpufreq: arm_big_little: add support for shared cluster 
regulators

In some socs or board designs the supplying regulator is shared between
more than one cluster but the current regulator support for big_little
sets the target voltage without any tolerance.

So when cluster0 requests 0.9V and cluster1 1.3V no suitable frequency
span is available that fits both. To accomodate this, look for shared
regulators and calculate the maximum voltage necessary. If the regulator
of the remote cluster has a lower voltage, its maximum also gets increased.

If cluster supplies are not shared, the behaviour is the same as before
with one specific voltage being set instead of a voltage-range.

When adapting shared voltages the remote clusters need to be locked too,
because cpufreq can very well try to change more than one cluster at the
same time. While the used mutex_trylock prevents deadlocks reliably,
it might also prevent some (or a lot) frequency changes from succeeding:

lock cluster0
lock cluster1
trylock cluster1
trylock cluster0
both fail

I'm probably simply overlooking some better way currently.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/cpufreq/arm_big_little.c | 102 ++-
 1 file changed, 91 insertions(+), 11 deletions(-)

diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c
index e04ca0c..c65b111 100644
--- a/drivers/cpufreq/arm_big_little.c
+++ b/drivers/cpufreq/arm_big_little.c
@@ -130,12 +130,78 @@ static unsigned int bL_cpufreq_get_rate(unsigned int cpu)
 }
 
 static int
+bL_adapt_shared_regulators(u32 cluster, unsigned long *volt_max)
+{
+   unsigned long other_volt;
+   int ret, i;
+
+   for (i = 0; i  MAX_CLUSTERS; i++) {
+   if (i == cluster || IS_ERR_OR_NULL(reg[i]))
+   continue;
+
+   if (regulator_is_match(reg[cluster], reg[i])) {
+   other_volt = regulator_get_voltage(reg[i]);
+   if (other_volt  *volt_max) {
+   *volt_max = other_volt;
+   } else {
+   pr_debug(%s: adapting shared regulator in 
cluster %d to %lu-%lu mV\n,
+__func__, i, other_volt / 1000, 
*volt_max / 1000);
+   ret = regulator_set_voltage(reg[i], other_volt, 
*volt_max);
+   if (ret) {
+   pr_err(%s: shared-supply for cluster: 
%d, failed to scale voltage up: %d\n,
+  __func__, cluster, ret);
+   return ret;
+   }
+   }
+   }
+   }
+
+   return 0;
+}
+
+static int
+bL_lock_shared_regulators(u32 cluster)
+{
+   int ret, i;
+
+   for (i = 0; i  MAX_CLUSTERS; i++) {
+   if (i == cluster || IS_ERR_OR_NULL(reg[i]))
+   continue;
+
+   if (regulator_is_match(reg[cluster], reg[i])) {
+   ret = mutex_trylock(cluster_lock[i]);
+   if (!ret) {
+   for (i--; i = 0; i--)
+   mutex_unlock(cluster_lock[i]);
+   return -EBUSY;
+   }
+   }
+   }
+
+   return 0;
+}
+
+static void
+bL_unlock_shared_regulators(u32 cluster)
+{
+   int i;
+
+   for (i = 0; i  MAX_CLUSTERS; i++) {
+   if (i == cluster || IS_ERR_OR_NULL(reg[i]))
+   continue;
+
+  

Re: [RFT v2 44/48] genirq, pinctrl: Kill the first parameter 'irq' of irq_flow_handler_t

2015-06-10 Thread Heiko Stübner
Am Donnerstag, 4. Juni 2015, 12:13:54 schrieb Jiang Liu:
 Now most IRQ flow handlers make no use of the first parameter 'irq'.
 And for those who do make use of 'irq', we could easily get the irq
 number through irq_desc-irq_data-irq. So kill the first parameter
 'irq' of irq_flow_handler_t.
 
 To ease review, I have split the changes into several parts, though
 they should be merge as one to support bisecting.
 
 Signed-off-by: Jiang Liu jiang@linux.intel.com
 ---

  drivers/pinctrl/pinctrl-rockchip.c|2 +-

For Rockchip
Acked-by: Heiko Stuebner he...@sntech.de

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Re: [RFT v2 06/48] pinctrl: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc

2015-06-10 Thread Heiko Stübner
Am Donnerstag, 4. Juni 2015, 12:13:16 schrieb Jiang Liu:
 Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
 already have a pointer to corresponding irq_desc.
 
 Signed-off-by: Jiang Liu jiang@linux.intel.com
 Acked-by: Linus Walleij linus.wall...@linaro.org
 ---
  drivers/pinctrl/pinctrl-rockchip.c|4 ++--


For Rockchip
Acked-by: Heiko Stuebner he...@sntech.de

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Re: [PATCH v4 0/8] mfd: cros_ec: Add multi EC and proto v3 support

2015-06-02 Thread Heiko Stübner
Am Dienstag, 2. Juni 2015, 10:11:03 schrieb Javier Martinez Canillas:
 Hello,
 
 Newer Chromebooks have more than one Embedded Controller (EC) in the
 system. These additional ECs are connected through I2C with a host EC
 which is the one that is connected to the Application Processor (AP)
 through different transports (I2C, SPI or LPC).
 
 So on these platforms, sub-processors are chained to each other:
 
 AP -- Host EC -- Power Delivery (PD) EC
 
 The AP sends commands to the additional EC through the host EC using
 a set of passthru commands and the host redirects to the correct EC.
 
 This is a v4 of a series that adds support for multiple EC in a system
 and also for the protocol version 3 that is used on newer ECs.
 
 Most patches were taken from the downstream ChromiumOS v3.14 tree with
 fixes squashed, split to minimise the cross subsystem churn and changes
 for mainline inclusion but were not modified functionality wise.
 
 This version addresses a lot of issues pointed out by Lee Jones on the v3
 posted before [0].
 
 The patches are based on top of [PATCH 0/2] mfd: cros_ec: Small cleanups
 [1] that were posted before and was already picked by Lee Jones.
 
 Testing was done on some Chromebooks that have a single EC and support
 protocol v2 such as the Exynos5250 Snow, Exynos5420 Peach Pit and Exynos5800
 Peach Pi to be sure that no regressions were introduced for these machines.

I just gave this a try on veyron and everything still works as expected.

All patches except [PATCH v4 6/8] mfd: cros_ec: Support multiple EC in a 
system already have Tested-by tags, so this patch now is also

Tested-by: Heiko Stuebner he...@sntech.de


Heiko
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Re: [PATCH 1/2] clk: change clk_ops' -round_rate() prototype

2015-04-19 Thread Heiko Stübner
Hi Boris,

Am Freitag, 17. April 2015, 09:29:28 schrieb Boris Brezillon:
 Clock rates are stored in an unsigned long field, but -round_rate()
 (which returns a rounded rate from a requested one) returns a long
 value (errors are reported using negative error codes), which can lead
 to long overflow if the clock rate exceed 2Ghz.
 
 Change -round_rate() prototype to return 0 or an error code, and pass the
 requested rate as a pointer so that it can be adjusted depending on
 hardware capabilities.
 
 Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com
 ---

On a rk3288-veyron-pinky with the fix described below:
Tested-by: Heiko Stuebner he...@sntech.de


 diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
 index fa5a00e..1462ddc 100644
 --- a/drivers/clk/clk.c
 +++ b/drivers/clk/clk.c
 @@ -1640,8 +1643,10 @@ static struct clk_core *clk_calc_new_rates(struct
 clk_core *clk, parent_hw);
   parent = parent_hw ? parent_hw-core : NULL;
   } else if (clk-ops-round_rate) {
 - new_rate = clk-ops-round_rate(clk-hw, rate,
 - best_parent_rate);
 + if (clk-ops-round_rate(clk-hw, new_rate,
 +  best_parent_rate))
 + return NULL;
 +
   if (new_rate  min_rate || new_rate  max_rate)
   return NULL;
   } else if (!parent || !(clk-flags  CLK_SET_RATE_PARENT)) {

This is using new_rate uninitialized when calling into the round_rate
callback. Which in turn pushed my PLLs up to 2.2GHz :-)

I guess you'll need something like the following:

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index db4e4b2..afc7733 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1605,6 +1605,7 @@ static struct clk_core *clk_calc_new_rates(struct 
clk_core *clk,
parent_hw);
parent = parent_hw ? parent_hw-core : NULL;
} else if (clk-ops-round_rate) {
+   new_rate = rate;
if (clk-ops-round_rate(clk-hw, new_rate,
 best_parent_rate))
return NULL;




 diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
 index f8d3baf..bd408ef 100644
 --- a/drivers/clk/rockchip/clk-pll.c
 +++ b/drivers/clk/rockchip/clk-pll.c
 @@ -63,8 +63,8 @@ static const struct rockchip_pll_rate_table
 *rockchip_get_pll_settings( return NULL;
  }
 
 -static long rockchip_pll_round_rate(struct clk_hw *hw,
 - unsigned long drate, unsigned long *prate)
 +static int rockchip_pll_round_rate(struct clk_hw *hw,
 + unsigned long *drate, unsigned long *prate)
  {
   struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
   const struct rockchip_pll_rate_table *rate_table = pll-rate_table;
 @@ -72,12 +72,15 @@ static long rockchip_pll_round_rate(struct clk_hw *hw,
 
   /* Assumming rate_table is in descending order */
   for (i = 0; i  pll-rate_count; i++) {
 - if (drate = rate_table[i].rate)
 - return rate_table[i].rate;
 + if (*drate = rate_table[i].rate) {
 + *drate = rate_table[i].rate;
 + return 0;
 + }
   }
 
   /* return minimum supported value */
 - return rate_table[i - 1].rate;
 + *drate = rate_table[i - 1].rate;
 + return 0;
  }
 
  /*

The rockchip-part:
Reviewed-by: Heiko Stuebner he...@sntech.de


And as I've stumbled onto this recently too, the clock-maintainership has
expanded to Stephen Boyd and linux-...@vger.kernel.org .


Heiko
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Re: [RESEND PATCH 4/8] mfd: cros_ec: Use a zero-length array for command data

2015-04-16 Thread Heiko Stübner
Am Montag, 6. April 2015, 18:15:02 schrieb Javier Martinez Canillas:
 Commit 1b84f2a4cd4a (mfd: cros_ec: Use fixed size arrays to transfer
 data with the EC) modified the struct cros_ec_command fields to not
 use pointers for the input and output buffers and use fixed length
 arrays instead.
 
 This change was made because the cros_ec ioctl API uses that struct
 cros_ec_command to allow user-space to send commands to the EC and
 to get data from the EC. So using pointers made the API not 64-bit
 safe. Unfortunately this approach was not flexible enough for all
 the use-cases since there may be a need to send larger commands
 on newer versions of the EC command protocol.
 
 So to avoid to choose a constant length that it may be too big for
 most commands and thus wasting memory and CPU cycles on copy from
 and to user-space or having a size that is too small for some big
 commands, use a zero-length array that is both 64-bit safe and
 flexible. The same buffer is used for both output and input data
 so the maximum of these values should be used to allocate it.
 
 Suggested-by: Gwendal Grignou gwen...@chromium.org
 Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
 ---

[...]

  /* Module initialization */
 @@ -269,3 +301,4 @@ void ec_dev_sysfs_remove(struct cros_ec_device *ec)
  {
   sysfs_remove_group(ec-vdev-kobj, ec_attr_group);
  }
 +

.git/rebase-apply/patch:893: new blank line at EOF.


 diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
 index 14cf522123dd..7eee38abd02a 100644
 --- a/include/linux/mfd/cros_ec.h
 +++ b/include/linux/mfd/cros_ec.h

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Re: [RESEND PATCH 0/8] cros_ec: Add multiple EC and protocol v3 support

2015-04-16 Thread Heiko Stübner
Hi Javier,

Am Donnerstag, 16. April 2015, 09:29:59 schrieb Javier Martinez Canillas:
 Hello,
 
 On 04/06/2015 06:14 PM, Javier Martinez Canillas wrote:
  Newer Chromebooks have more than one Embedded Controller (EC) in the
  system. These additional ECs are connected through I2C with a host EC
  which is the one that is connected to the Application Processor (AP)
  through I2C, SPI or LPC.
  
  So on these platforms, sub-processors are chained to each other:
  
  AP -- Host EC -- Power Delivery (PD) EC
  
  The AP sends commands to the additional EC through the host EC using
  a set of passthru commands and the host redirects to the correct EC.
  
  This series adds support for multiple EC in a system and also for the
  protocol version 3 that is used on newer ECs.
 
 Any comments about this series? I know that we are in the middle of the
 merge window but it would be great if I can get some feedback to get it
 ready and re-post for 4.2 (addressing any issue) once 4.1-rc1 is out.
 
  Most patches were taken from the downstream ChromiumOS v3.14 tree with
  fixes squashed, split to minimise the cross subsystem churn and changes
  for mainline inclusion but were not modified functionality wise.
  
  The series depend on platform/chrome: Add user-space dev inferface
  support [0] that is already merged in the chrome-platform tree so
  probably these patches should also go through that tree once the mfd
  patches are acked.
  
  The series is a resend of a patch-set posted a month ago [1]. The only big
 
 As I said, the original patchset was post about a month ago and this re-sent
 10 days ago so it would be great to have some feedback on the series.

on a veyron-pinky-rev2, with
cros-ec-spi spi0.0: using proto v3
cros-ec-spi spi0.0: no PD chip found: -19

Tested-by: Heiko Stuebner he...@sntech.de


with the catch of the device needing two additional patches from the Chromeos-
tree:

c7ae1e2ef996 mfd: cros ec: spi: put the delay and send msg in one cycle
8558460450c1 mfd: cros ec: spi: Add delay for asserting CS

and I'm not sure if they are submitted yet.


Heiko
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Re: [PATCH] ARM: SAMSUNG: remove unused DMA infrastructure

2015-01-15 Thread Heiko Stübner
Am Donnerstag, 15. Januar 2015, 16:16:03 schrieb Arnd Bergmann:
 Everything uses dmaengine now, so there is no reason to
 keep this around any longer. Thanks to everyone who was involved
 in moving the users over to use the dmaengine APIs.
 
 Signed-off-by: Arnd Bergmann a...@arndb.de

very nice to see this finished :-)

Reviewed-by: Heiko Stuebner he...@sntech.de
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Re: [PATCH] ARM: SAMSUNG: remove dead #elif CONFIG_S3C24XX_DMAC

2014-12-18 Thread Heiko Stübner
Hi Stefan,

Am Donnerstag, 18. Dezember 2014, 14:43:01 schrieb Stefan Hengelein:
 So you actually tested the code I removed in the patch? can you
 provide a configuration that compiles that piece of code?

Yep, one of my boards (Asus eeeReader DR-900) was actually able to transmit
stuff via the libertas spi wifi driver using the s3c64xx-spi driver.

The smdk2416 is currently the only board for the s3c2416 in the kernel. I don't
know if it had actual spi devices connected, but if it had, a suitable diff 
would
look something like the diff below. Of course hooking up spi devices would
work the same in any out-of-tree board for the supported socs.


For people reading along, the s3c24xx spi distribution is as follows:
s3c2410, s3c2412, s3c2440: (I think) two s3c24xx-spi
s3c2443: one s3c64xx-spi and one s3c24xx-spi
s3c2416: one s3c64xx-spi
s3c2450: two s3c64xx-spi


Heiko


 8 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 9eb2229..5210e5d 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -419,6 +419,8 @@ config MACH_SMDK2416
select S3C_DEV_HSMMC1
select S3C_DEV_NAND
select S3C_DEV_USB_HOST
+   select S3C64XX_DEV_SPI0
+   select S3C2443_SETUP_SPI
help
  Say Y here if you are using an SMDK2416
 
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c 
b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 86394f7..b6c6ff4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -52,6 +52,9 @@
 #include linux/platform_data/s3c-hsudc.h
 #include plat/samsung-time.h
 
+#include linux/spi/spi.h
+#include linux/platform_data/spi-s3c64xx.h
+
 #include plat/fb.h
 
 #include common.h
@@ -207,6 +210,26 @@ static struct s3c_sdhci_platdata smdk2416_hsmmc1_pdata 
__initdata = {
.cd_type= S3C_SDHCI_CD_NONE,
 };
 
+struct s3c64xx_spi_csinfo libertas_cs_info = {
+   .fb_delay = 0,
+   .line = 128, /* gpio cs line */
+};
+
+
+static struct spi_board_info spi_board_info[] = {
+{
+   .modalias   = libertas_spi,
+   .max_speed_hz   = 120,
+   .bus_num= 0,
+   .irq= 12, /* some interrupt number */
+   .chip_select= 0,
+   .mode   = SPI_MODE_3,
+   .controller_data= libertas_cs_info,
+/* .platform_data  = foo1_pdata, */
+},
+};
+
+
 static struct platform_device *smdk2416_devices[] __initdata = {
s3c_device_fb,
s3c_device_wdt,
@@ -216,6 +239,7 @@ static struct platform_device *smdk2416_devices[] 
__initdata = {
s3c_device_hsmmc1,
s3c_device_usb_hsudc,
s3c2443_device_dma,
+   s3c64xx_device_spi0,
 };
 
 static void __init smdk2416_init_time(void)
@@ -250,6 +274,9 @@ static void __init smdk2416_machine_init(void)
gpio_request(S3C2410_GPB(1), Display Reset);
gpio_direction_output(S3C2410_GPB(1), 1);
 
+   s3c64xx_spi0_set_platdata(NULL, 0, ARRAY_SIZE(spi_board_info));
+   spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
smdk_machine_init();
 }
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c 
b/arch/arm/mach-s3c24xx/setup-spi.c
index 3d47e02..d66c4e0 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -16,6 +16,7 @@
 
 #include mach/hardware.h
 #include mach/regs-gpio.h
+#include mach/gpio-samsung.h
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
 int s3c64xx_spi0_cfg_gpio(void)

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Re: [PATCH v7 00/11] kernel: Add support for restart handler call chain

2014-10-01 Thread Heiko Stübner
Am Dienstag, 30. September 2014, 15:30:00 schrieb Guenter Roeck:
 On Tue, Sep 30, 2014 at 02:20:02PM -0700, Andrew Morton wrote:
  On Tue, 19 Aug 2014 17:45:27 -0700 Guenter Roeck li...@roeck-us.net 
wrote:
   Introduce a system restart handler call chain to solve the described
   problems. 
  So someone has merged eight of these patches into linux-next but these
  three:
  
  watchdog-s3c2410-add-restart-handler.patch
  clk-samsung-register-restart-handlers-for-s3c2412-and-s3c2443.patch
  clk-rockchip-add-restart-handler.patch
  
  were omitted.  What's up?
 
 Most likely PBKC on my side; Looks like I forgot to add those when I created
 the immutable branch for others to merge. Sorry for that :-(.
 
 Having said that, I somehow thought that the clock patches would go in
 through the clock tree. Heiko, did I get that wrong ? Separately, I sent a
 pull request that includes the watchdog patch to Wim.

I didn't realise that the patches would get dropped from -mm until I the 
removal notices this morning. So meanwhile I've send a pull to Mike for the 
Rockchip and S3C2412/2416/2443 restart handling.

So, as your pull includes the samsung watchdog restart, we should be hopefully 
all set again :-) .


Heiko
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Re: [PATCH v6] mfd: syscon: Decouple syscon interface from platform devices

2014-09-30 Thread Heiko Stübner
Hi Pankaj,

Am Dienstag, 30. September 2014, 09:33:38 schrieb Pankaj Dubey:
 Hi,
 
 On Monday, September 29, 2014 9:38 PM, Heiko Stübner wrote,
 
  Am Montag, 29. September 2014, 14:17:38 schrieb Pankaj Dubey:
   Currently a syscon entity can be only registered directly through a
   platform device that binds to a dedicated syscon driver. However in
   certain use cases it is desirable to make a device used with another
   driver a syscon interface provider.
   
   For example, certain SoCs (e.g. Exynos) contain system controller
   blocks which perform various functions such as power domain control,
   CPU power management, low power mode control, but in addition contain
   certain IP integration glue, such as various signal masks, coprocessor
   power control, etc. In such case, there is a need to have a dedicated
   driver for such system controller but also share registers with other
   drivers. The latter is where the syscon interface is helpful.
   
   In case of DT based platforms, this patch decouples syscon object from
   syscon platform driver, and allows to create syscon objects first time
   when it is required by calling of syscon_regmap_lookup_by APIs and
   keep a list of such syscon objects along with syscon provider
   device_nodes and regmap handles.
   
   For non-DT based platforms, this patch keeps syscon platform driver
   structure where is can be probed and such non-DT based drivers can use
   syscon_regmap_lookup_by_pdev API and get access to regmap handles.
   Once all users of syscon_regmap_lookup_by_pdev migrated to DT based,
   we can completely remove platform driver of syscon, and keep only
   helper functions to get regmap handles.
   
   Suggested-by: Arnd Bergmann a...@arndb.de
   Suggested-by: Tomasz Figa tomasz.f...@gmail.com
   Tested-by: Vivek Gautam gautam.vi...@samsung.com
   Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
   Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
   ---
  
  On Rockchip boards during core clock init (aka before timers)
  Tested-by: Heiko Stuebner he...@sntech.de
 
 Thanks for testing.
 
  Except one issue described inline below
  Reviewed-by: Heiko Stuebner he...@sntech.de
  
  
  And I'm really looking forward to having this in the kernel :-)
  
  Thanks for working on this
  Heiko
 
 [snip]
 
drivers/mfd/syscon.c |  106
   
   +++--- 1 file
  
  changed, 84
  
   insertions(+), 22 deletions(-)
   
   diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c index
   ca15878..00a8410 100644
   --- a/drivers/mfd/syscon.c
   +++ b/drivers/mfd/syscon.c
   @@ -15,6 +15,7 @@
   
#include linux/err.h
#include linux/io.h
#include linux/module.h
   
   +#include linux/list.h
   
#include linux/of.h
#include linux/of_address.h
#include linux/of_platform.h
   
   @@ -22,31 +23,104 @@
   
#include linux/platform_device.h
#include linux/regmap.h
#include linux/mfd/syscon.h
   
   +#include linux/slab.h
   
static struct platform_driver syscon_driver;
   
   +static DEFINE_SPINLOCK(syscon_list_slock);
   +static LIST_HEAD(syscon_list);
   +
   
struct syscon {
   
   + struct device_node *np;
   
 struct regmap *regmap;
   
   + struct list_head list;
   +};
   +
   +static struct regmap_config syscon_regmap_config = {
   + .reg_bits = 32,
   + .val_bits = 32,
   + .reg_stride = 4,
   
};
   
   -static int syscon_match_node(struct device *dev, void *data)
   +static struct syscon *of_syscon_register(struct device_node *np)
   
{
   
   - struct device_node *dn = data;
   + struct syscon *syscon;
   + struct regmap *regmap;
   + void __iomem *base;
   + int ret;
   + enum regmap_endian endian = REGMAP_ENDIAN_DEFAULT;
   +
   + if (!of_device_is_compatible(np, syscon))
   + return ERR_PTR(-EINVAL);
   +
   + syscon = kzalloc(sizeof(*syscon), GFP_KERNEL);
   + if (!syscon)
   + return ERR_PTR(-ENOMEM);
   +
   + base = of_iomap(np, 0);
   + if (!base) {
   + ret = -ENOMEM;
   + goto err_map;
   + }
   +
   + /* Parse the device's DT node for an endianness specification */
   + if (of_property_read_bool(np, big-endian))
   + endian = REGMAP_ENDIAN_BIG;
   +  else if (of_property_read_bool(np, little-endian))
   + endian = REGMAP_ENDIAN_LITTLE;
   +
   + /* If the endianness was specified in DT, use that */
   + if (endian != REGMAP_ENDIAN_DEFAULT)
   + syscon_regmap_config.val_format_endian = endian;
   +
   + regmap = regmap_init_mmio(NULL, base, syscon_regmap_config);
   + if (IS_ERR(regmap)) {
   + pr_err(regmap init failed\n);
   + ret = PTR_ERR(regmap);
   + goto err_regmap;
   + }
   +
   + syscon-regmap = regmap;
   + syscon-np = np;
   +
   + spin_lock(syscon_list_slock);
   + list_add_tail(syscon-list, syscon_list);
   + spin_unlock(syscon_list_slock);
   
   - return (dev-of_node == dn) ? 1 : 0;
   + /* Change back endianness

Re: [PATCH v6] mfd: syscon: Decouple syscon interface from platform devices

2014-09-29 Thread Heiko Stübner
Am Montag, 29. September 2014, 14:17:38 schrieb Pankaj Dubey:
 Currently a syscon entity can be only registered directly through a
 platform device that binds to a dedicated syscon driver. However in
 certain use cases it is desirable to make a device used with another
 driver a syscon interface provider.
 
 For example, certain SoCs (e.g. Exynos) contain system controller
 blocks which perform various functions such as power domain control,
 CPU power management, low power mode control, but in addition contain
 certain IP integration glue, such as various signal masks,
 coprocessor power control, etc. In such case, there is a need to have
 a dedicated driver for such system controller but also share registers
 with other drivers. The latter is where the syscon interface is helpful.
 
 In case of DT based platforms, this patch decouples syscon object from
 syscon platform driver, and allows to create syscon objects first time
 when it is required by calling of syscon_regmap_lookup_by APIs and keep
 a list of such syscon objects along with syscon provider device_nodes
 and regmap handles.
 
 For non-DT based platforms, this patch keeps syscon platform driver
 structure where is can be probed and such non-DT based drivers can use
 syscon_regmap_lookup_by_pdev API and get access to regmap handles.
 Once all users of syscon_regmap_lookup_by_pdev migrated to DT based,
 we can completely remove platform driver of syscon, and keep only helper
 functions to get regmap handles.
 
 Suggested-by: Arnd Bergmann a...@arndb.de
 Suggested-by: Tomasz Figa tomasz.f...@gmail.com
 Tested-by: Vivek Gautam gautam.vi...@samsung.com
 Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
 Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
 ---

On Rockchip boards during core clock init (aka before timers)
Tested-by: Heiko Stuebner he...@sntech.de

Except one issue described inline below
Reviewed-by: Heiko Stuebner he...@sntech.de


And I'm really looking forward to having this in the kernel :-)

Thanks for working on this
Heiko


 Patch v5 and related discussions can be found here [1].
 
 Change since v5:
  - Dropping creation of dummy platform device in of_syscon_register.
  - As we are changing syscon to decouple from platform_device, creation of
dummy platform_device does not look good option, and as suggested by
 Arnd, I made another attempt so that regmap_mmio_init API should work with
 NULL dev pointer itself. Since regmap needs to know about Syscon device
 node properties so let's parse device node of syscon in syscon itself for
 any such properties and using regmap_config parameter pass all such
 information to regmap. Other concern of crashes due to NULL dev pointer in
 regmap already addressed in separate patches of regmap. Please see [2] and
 [3].
 
 
 Changes since v4:
  - Addressed Tomasz Figa's comments for v4.
  - Added error handing in of_syscon_register function.
  - Using devm_regmap_init_mmio instead of regmap_init_mmio.
 
 Changes since v3:
  - Addressed Arnd's comment for v2.
  - Updated of_syscon_register for adding dev pointer in regmap_init_mmio.
  - For early users created dummy platform device.
 
 Changes since v2:
  - Added back platform device support from syscon, with one change that
syscon will not be probed for DT based platform.
  - Added back syscon_regmap_lookup_by_pdevname API so that non-DT base
users of syscon will not be broken.
  - Removed unwanted change in syscon.h.
  - Modified Signed-off-by list, added Suggested-by of Tomasz Figa and
Arnd Bergmann.
  - Added Tested-by of Vivek Gautam for testing on Exynos platform.
 
 Changes since v1:
  - Removed of_syscon_unregister function.
  - Modified of_syscon_register function and it will be used by syscon.c
to create syscon objects whenever required.
  - Removed platform device support from syscon.
  - Removed syscon_regmap_lookup_by_pdevname API support.
  - As there are significant changes w.r.t patchset v1, I am taking over
author for this patchset from Tomasz Figa.
 
 [1]: https://lkml.org/lkml/2014/9/22/12
 [2]: https://lkml.org/lkml/2014/9/18/130
 [3]: https://lkml.org/lkml/2014/9/27/2
 
  drivers/mfd/syscon.c |  106
 +++--- 1 file changed, 84
 insertions(+), 22 deletions(-)
 
 diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
 index ca15878..00a8410 100644
 --- a/drivers/mfd/syscon.c
 +++ b/drivers/mfd/syscon.c
 @@ -15,6 +15,7 @@
  #include linux/err.h
  #include linux/io.h
  #include linux/module.h
 +#include linux/list.h
  #include linux/of.h
  #include linux/of_address.h
  #include linux/of_platform.h
 @@ -22,31 +23,104 @@
  #include linux/platform_device.h
  #include linux/regmap.h
  #include linux/mfd/syscon.h
 +#include linux/slab.h
 
  static struct platform_driver syscon_driver;
 
 +static DEFINE_SPINLOCK(syscon_list_slock);
 +static LIST_HEAD(syscon_list);
 +
  struct syscon {
 + struct device_node *np;
   struct regmap *regmap;
 + 

Re: [PATCH v5] mfd: syscon: Decouple syscon interface from platform devices

2014-09-24 Thread Heiko Stübner
Hi Pankaj, Joachim,

Am Dienstag, 23. September 2014, 20:12:50 schrieb Joachim Eastwood:
 On 22 September 2014 06:40, Pankaj Dubey pankaj.du...@samsung.com wrote:
  Currently a syscon entity can be only registered directly through a
  platform device that binds to a dedicated syscon driver. However in
  certain use cases it is desirable to make a device used with another
  driver a syscon interface provider.
  
  For example, certain SoCs (e.g. Exynos) contain system controller
  blocks which perform various functions such as power domain control,
  CPU power management, low power mode control, but in addition contain
  certain IP integration glue, such as various signal masks,
  coprocessor power control, etc. In such case, there is a need to have
  a dedicated driver for such system controller but also share registers
  with other drivers. The latter is where the syscon interface is helpful.
  
  In case of DT based platforms, this patch decouples syscon object from
  syscon platform driver, and allows to create syscon objects first time
  when it is required by calling of syscon_regmap_lookup_by APIs and keep
  a list of such syscon objects along with syscon provider device_nodes
  and regmap handles.
  
  For non-DT based platforms, this patch keeps syscon platform driver
  structure where is can be probed and such non-DT based drivers can use
  syscon_regmap_lookup_by_pdev API and get access to regmap handles.
  Once all users of syscon_regmap_lookup_by_pdev migrated to DT based,
  we can completly remove platform driver of syscon, and keep only helper
  functions to get regmap handles.
  
  Suggested-by: Arnd Bergmann a...@arndb.de
  Suggested-by: Tomasz Figa tomasz.f...@gmail.com
  Tested-by: Vivek Gautam gautam.vi...@samsung.com
  Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
  Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
 
 I wrote a clk driver using syscon and your patch. clk driver uses
 CLK_OF_DECLARE, btw.
 
 It works but I get a '(null): Failed to create debugfs directory'
 message in the boot log.
 
 Tested-by: Joachim Eastwood manab...@gmail.com

on Rockchip platforms this syscon support also helps quite a bit, as the
pll lock-status is sitting in an external syscon register, so setting target
pll-rates through assigned-clocks is not easily doable without it.
Therefore I'm very much looking forward to this.


Similar to Joachim I get an error about debugfs from regmap, which seems
to be caused by
name = dev_name(map-dev);
returning NULL in regmap_debugfs_init in regmap-debugfs.c for such an early
syscon.

[...]
__set_clk_rates: setting cpll from 38400 to 89100
rockchip_rk3066_pll_set_rate: trying to get grf
rockchip_rk3066_pll_set_rate: changing pll_cpll from 38400 to 89100 
with a parent rate of 2400
__set_clk_rates: cpll is now 89100
Architected cp15 timer(s) running at 24.00MHz (virt).
[...]
regulator-dummy: no parameters
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
Unable to handle kernel NULL pointer dereference at virtual address 
pgd = c0004000
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.17.0-rc1+ #1184
task: ee069b40 ti: ee06a000 task.ti: ee06a000
PC is at strlen+0xc/0x20
LR is at __create_file+0x6c/0x1d0
pc : [c01a02f8]lr : [c01725f0]psr: 6153
sp : ee06bea8  ip : 000e  fp : 
r10: ee06a000  r9 :   r8 : 
r7 : c07ecb20  r6 : edc02cc0  r5 : 41ed  r4 : 
r3 : 0001  r2 :   r1 : a153  r0 : 
Flags: nZCv  IRQs on  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 406a  DAC: 0015
Process swapper/0 (pid: 1, stack limit = 0xee06a240)
Stack: (0xee06bea8 to 0xee06c000)
bea0:    41ed ee002400 c07efc60  c05a9e50
bec0: c058c510 c01727c8  edc02cc0 ee0024b0 c021d410 ee002400 
bee0: ee02ff40 c0793494 c07ab080 c021d6b4  ee11bbc0 c0782c58 c058c518
bf00:  c0008970 ee0f7f00 c00f9f54 ee0f7f00 ee0f7c80 ee0f7c00 c03fddc4
bf20: c07cda04  c054c8a4 c00fa0e0 c0575514 ef7fccc5  c0034fd0
bf40:   c054c8a4 c054bcd4 00bd 0002 c0786394 0002
bf60: c059e840 c07ab080 c05a9e50 00bd    c0575c94
bf80: 0002 0002 c0575514 ee06a000  c03f38f8  
bfa0:  c03f3900  c000e7f8    
bfc0:        
bfe0:     0013   
[c01a02f8] (strlen) from [c01725f0] (__create_file+0x6c/0x1d0)
[c01725f0] (__create_file) from [c01727c8] (debugfs_create_dir+0x18/0x1c)
[c01727c8] (debugfs_create_dir) from [c021d410] 
(regmap_debugfs_init+0xd0/0x254)
[c021d410] (regmap_debugfs_init) from [c021d6b4] 

[PATCH] ARM: S3C24XX: remove separate restart code

2014-09-08 Thread Heiko Stübner
The restart-handler series from Guenter Roeck got accepted recently and
implements among other things also the restart handler in the samsung
watchdog driver and where applicable in the clock drivers. So there is
no need for having the restart callbacks in s3c24xx boards anymore.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/mach-s3c24xx/Kconfig  |  2 --
 arch/arm/mach-s3c24xx/common.c |  4 
 arch/arm/mach-s3c24xx/common.h |  5 -
 .../mach-s3c24xx/include/mach/regs-s3c2443-clock.h |  2 --
 arch/arm/mach-s3c24xx/mach-amlm5900.c  |  1 -
 arch/arm/mach-s3c24xx/mach-anubis.c|  1 -
 arch/arm/mach-s3c24xx/mach-at2440evb.c |  1 -
 arch/arm/mach-s3c24xx/mach-bast.c  |  1 -
 arch/arm/mach-s3c24xx/mach-gta02.c |  1 -
 arch/arm/mach-s3c24xx/mach-h1940.c |  1 -
 arch/arm/mach-s3c24xx/mach-jive.c  |  1 -
 arch/arm/mach-s3c24xx/mach-mini2440.c  |  1 -
 arch/arm/mach-s3c24xx/mach-n30.c   |  2 --
 arch/arm/mach-s3c24xx/mach-nexcoder.c  |  1 -
 arch/arm/mach-s3c24xx/mach-osiris.c|  1 -
 arch/arm/mach-s3c24xx/mach-otom.c  |  1 -
 arch/arm/mach-s3c24xx/mach-qt2410.c|  1 -
 arch/arm/mach-s3c24xx/mach-rx1950.c|  1 -
 arch/arm/mach-s3c24xx/mach-rx3715.c|  1 -
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c|  1 -
 arch/arm/mach-s3c24xx/mach-smdk2410.c  |  1 -
 arch/arm/mach-s3c24xx/mach-smdk2413.c  |  3 ---
 arch/arm/mach-s3c24xx/mach-smdk2416.c  |  1 -
 arch/arm/mach-s3c24xx/mach-smdk2440.c  |  1 -
 arch/arm/mach-s3c24xx/mach-smdk2443.c  |  1 -
 arch/arm/mach-s3c24xx/mach-tct_hammer.c|  1 -
 arch/arm/mach-s3c24xx/mach-vr1000.c|  1 -
 arch/arm/mach-s3c24xx/mach-vstms.c |  1 -
 arch/arm/mach-s3c24xx/s3c2410.c| 13 
 arch/arm/mach-s3c24xx/s3c2412.c| 23 --
 arch/arm/mach-s3c24xx/s3c2416.c|  8 
 arch/arm/mach-s3c24xx/s3c2443.c|  8 
 arch/arm/mach-s3c24xx/s3c244x.c| 12 ---
 33 files changed, 104 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index ad5316a..9eb2229 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -32,7 +32,6 @@ config CPU_S3C2410
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
select S3C2410_PM if PM
-   select SAMSUNG_WDT_RESET
help
  Support for S3C2410 and S3C2410A family from the S3C24XX line
  of Samsung Mobile CPUs.
@@ -76,7 +75,6 @@ config CPU_S3C2442
 config CPU_S3C244X
def_bool y
depends on CPU_S3C2440 || CPU_S3C2442
-   select SAMSUNG_WDT_RESET
 
 config CPU_S3C2443
bool SAMSUNG S3C2443
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 44fa95d..bf50328 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -51,7 +51,6 @@
 #include plat/devs.h
 #include plat/cpu-freq.h
 #include plat/pwm-core.h
-#include plat/watchdog-reset.h
 
 #include common.h
 
@@ -513,7 +512,6 @@ struct platform_device s3c2443_device_dma = {
 void __init s3c2410_init_clocks(int xtal)
 {
s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
-   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 #endif
 
@@ -535,7 +533,6 @@ void __init s3c2416_init_clocks(int xtal)
 void __init s3c2440_init_clocks(int xtal)
 {
s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
-   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 #endif
 
@@ -543,7 +540,6 @@ void __init s3c2440_init_clocks(int xtal)
 void __init s3c2442_init_clocks(int xtal)
 {
s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
-   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 #endif
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ac3ff12..c7ac7e6 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -22,7 +22,6 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -38,7 +37,6 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 

Re: [PATCH v7 00/11] kernel: Add support for restart handler call chain

2014-08-23 Thread Heiko Stübner
Am Samstag, 23. August 2014, 09:35:05 schrieb Guenter Roeck:
 On Tue, Aug 19, 2014 at 05:45:27PM -0700, Guenter Roeck wrote:
  Various drivers implement architecture and/or device specific means
  to restart (reset) the system. Various mechanisms have been implemented
  to support those schemes. The best known mechanism is arm_pm_restart,
  which is a function pointer to be set either from platform specific code
  or from drivers. Another mechanism is to use hardware watchdogs to issue
  a reset; this mechanism is used if there is no other method available
  to reset a board or system. Two examples are alim7101_wdt, which currently
  uses the reboot notifier to trigger a reset, and moxart_wdt, which
  registers the arm_pm_restart function. Several other restart drivers for
  arm, all directly calling arm_pm_restart, are in the process of being
  integrated into the kernel. All those drivers would benefit from the new
  API.
  
  The existing mechanisms have a number of drawbacks. Typically only one
  scheme to restart the system is supported (at least if arm_pm_restart is
  used). At least in theory there can be multiple means to restart the
  system, some of which may be less desirable (for example one mechanism
  may only reset the CPU, while another may reset the entire system). Using
  arm_pm_restart can also be racy if the function pointer is set from a
  driver, as the driver may be in the process of being unloaded when
  arm_pm_restart is called.
  Using the reboot notifier is always racy, as it is unknown if and when
  other functions using the reboot notifier have completed execution
  by the time the watchdog fires.
  
  Introduce a system restart handler call chain to solve the described
  problems. This call chain is expected to be executed from the
  architecture specific machine_restart() function. Drivers providing
  system restart functionality (such as the watchdog drivers mentioned
  above) are expected to register with this call chain. By using the
  priority field in the notifier block, callers can control restart handler
  execution sequence and thus ensure that the restart handler with the
  optimal restart capabilities for a given system is called first.
  
  Since the first revision of this patchset, a number of separate patch
  submissions have been made which either depend on it or could make use of
  it.
  
  http://www.spinics.net/linux/lists/arm-kernel/msg344796.html
  
  registers three notifiers.
  
  https://lkml.org/lkml/2014/7/8/962
  
  would benefit from it.
  
  Patch 1 of this series implements the restart handler function. Patches 2
  and 3 implement calling the restart handler chain from arm and arm64
  restart code.
  
  Patch 4 modifies the restart-poweroff driver to no longer call
  arm_pm_restart directly but machine_restart. This is done to avoid
  calling arm_pm_restart from more than one place. The change makes the
  driver architecture independent, so it would be possible to drop the arm
  dependency from its Kconfig entry.
  
  Patch 5 and 6 convert existing restart handlers in the watchdog subsystem
  to use the restart handler. Patch 7 unexports arm_pm_restart to ensure
  that no one gets the idea to implement a restart handler as module.
  
  The entire patch series, including additional patches depending on it,
  is available from
  https://git.kernel.org/cgit/linux/kernel/git/groeck/linux-staging.git/
  in branch 'restart-staging'.
 
 Hi Andrew,
 
 I think this series is ready for upstream integration. Question now
 is how we should proceed to get it actually integrated.
 
 I can see a number of options:
 - You take patch #1, the rest goes in through maintainer trees.

I don't think you can split the patches like this. Patch1 introduces 
(un)register_restart_handler functions used by later patches in the series. 
You therefore cannot really split the series, as otherwise you would get build 
failures in the individual trees.


Heiko


 - You take all patches after we get missing maintainer Acks.
 - I send a pull request directly to Linus after we get missing
   maintainer Acks.
 
 What do you think would be the best way to proceed ?
 
 Thanks,
 Guenter

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Re: [PATCH v7 11/11] clk: rockchip: add restart handler

2014-08-21 Thread Heiko Stübner
Am Mittwoch, 20. August 2014, 21:15:10 schrieb Doug Anderson:
 Guenter / Heiko,
 
 On Tue, Aug 19, 2014 at 5:45 PM, Guenter Roeck li...@roeck-us.net wrote:
  From: Heiko Stübner he...@sntech.de
  
  Add infrastructure to write the correct value to the restart register and
  register the restart notifier for both rk3188 (including rk3066) and
  rk3288.
  
  Signed-off-by: Heiko Stuebner he...@sntech.de
  Signed-off-by: Guenter Roeck li...@roeck-us.net
  ---
  v7: Added patch to series.
  
   drivers/clk/rockchip/clk-rk3188.c |  2 ++
   drivers/clk/rockchip/clk-rk3288.c |  2 ++
   drivers/clk/rockchip/clk.c| 25 +
   drivers/clk/rockchip/clk.h|  1 +
   4 files changed, 30 insertions(+)
 
 This patch doesn't apply cleanly with the in-flight (clk: rockchip:
 protect critical clocks from getting disabled) patch from Heiko.  It's
 trivial to resolve and unclear which will land first, so I think it's
 fine...

This should be expected :-) .

The patch about critical clocks will (hopefully soon) go through Mike's tree, 
while this series will most likely go through somewhere else (Linus' tree 
directly or something), so I guess the merge conflic will be resolved by Linus 
when both trees meet each other during the merge window.
So both this patch as well as the other one should stay independent of each 
other.


Heiko
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Re: [PATCHv10 5/5] ARM: dts: rockchip: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-08-11 Thread Heiko Stübner
Am Donnerstag, 7. August 2014, 16:38:02 schrieb Jaehoon Chung:
 dw-mmc controller can support multiple slots.
 But, there are no use-cases anywhere. So we don't need to support the
 slot-node for dw-mmc controller.
 And supports-highspeed property in dw-mmc is deprecated.
 supports-highspeed property can be replaced with cap-sd/mmc-highspeed.
 
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 Reviewed-by: Tushar Behera trbli...@gmail.com
 Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
 Reviewed-by: Heiko Stuebner he...@sntech.de
 Acked-by: Seungwon Jeon tgih@samsung.com

I've added this one to my queue for 3.18


Heiko

 ---
  arch/arm/boot/dts/rk3066a-bqcurie2.dts |   15 ---
  arch/arm/boot/dts/rk3188-radxarock.dts |7 ++-
  2 files changed, 6 insertions(+), 16 deletions(-)
 
 diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 042f821d..665dd56 100644
 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 @@ -150,12 +150,8 @@
   num-slots = 1;
   status = okay;
   vmmc-supply = vcc_sd0;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
  };
 
  mmc1 { /* wifi */
 @@ -166,11 +162,8 @@
   pinctrl-names = default;
   pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
 
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
  };
 
  uart0 {
 diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts
 b/arch/arm/boot/dts/rk3188-radxarock.dts index 171b610..ef72faf 100644
 --- a/arch/arm/boot/dts/rk3188-radxarock.dts
 +++ b/arch/arm/boot/dts/rk3188-radxarock.dts
 @@ -181,11 +181,8 @@
   status = okay;
   vmmc-supply = vcc_sd0;
 
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
  };
 
  pinctrl {

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Re: [PATCHv9 1/5] mmc: dw_mmc: Slot quirk disable-wp is deprecated.

2014-08-01 Thread Heiko Stübner
Am Freitag, 1. August 2014, 13:26:43 schrieb Jaehoon Chung:
 Hi, All.
 
 It seems too late that this patch-set is merged into linux-3.16.
 Also there are some conflicts in device-tree. (I will remove the conflicts)
 So if everybody is ok, I will rebase on linux-next after released
 linux-3.16. At that time, i will send this patch-set to stable kernel, too.
 how about?

 And I want to know who can apply this patch-set(#3~#5).

I guess each SoC maintainer could take the changes to their work-area, once 
the core changes have landed in the mmc tree. So I would take the Rockchip 
patch, Kukjin the Exynos one and Dinh the socfpga patch.


Heiko

 
 Best Regards,
 Jaehoon Chung
 
 On 08/01/2014 03:36 AM, Kukjin Kim wrote:
  On 08/01/14 01:02, Doug Anderson wrote:
  Jaehoon
  
  On Wed, Jul 30, 2014 at 10:35 PM, Jaehoon Chungjh80.ch...@samsung.com  
wrote:
  Slot quirks disable-wp is deprecated.
  Instead, use the host quirk disable-wp.
  (Because the slot-node is removed in dt-file.)
  
  Signed-off-by: Jaehoon Chungjh80.ch...@samsung.com
  Tested-by: Sachin Kamatsachin.ka...@samsung.com
  Acked-by: Seungwon Jeontgih@samsung.com
  ---
  
drivers/mmc/host/dw_mmc.c  |   11 +--
include/linux/mmc/dw_mmc.h |2 ++
2 files changed, 11 insertions(+), 2 deletions(-)
  
  Thanks for taking my suggestion and making it backward compatible.
  This looks great to me.  It tested this in both the backward
  compatible way (with the warning) and the non-backward compatible way.
  I think we should land and patch #2 ASAP and then we can land the rest
  of the series as SoC maintainers see fit.
  
  Yes, right if we don't want to see useless merge conflicts...
  
  When I sent ack on exynos stuff, there was no conflict with my tree but
  happens it now.
  
  - Kukjin
  
  Reviewed-by: Doug Andersondiand...@chromium.org
  Tested-by: Doug Andersondiand...@chromium.org

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Re: [PATCHv8 4/5] ARM: dts: rockchip: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-30 Thread Heiko Stübner
Hi,

Am Mittwoch, 30. Juli 2014, 20:05:09 schrieb Jaehoon Chung:
 dw-mmc controller can support multiple slots.
 But, there are no use-cases anywhere. So we don't need to support the
 slot-node for dw-mmc controller.
 And supports-highspeed property in dw-mmc is deprecated.
 supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
 
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 Reviewed-by: Tushar Behera trbli...@gmail.com
 Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
 Reviewed-by: Heiko Stuebner he...@sntech.de
 Acked-by: Seungwon Jeon tgih@samsung.com

we might get a conflict, with recent Rockchip-specific devicetree changes [0].
So depending on when the core changes of this series land, this patch
might use a respin.


Heiko


[0] 
https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=rockchip/dtid=fcbbf965254ff1693c26a5646e4e62adc3a6118d
https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=rockchip/dtid=b09e35a388ad23eb90497a352b8e5e5cb4b97bf2

 ---
  arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
  1 file changed, 4 insertions(+), 12 deletions(-)
 
 diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index afb3273..ecea889 100644
 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 @@ -59,12 +59,8 @@
   pinctrl-names = default;
   pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
   vmmc-supply = vcc_sd0;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
   };
 
   dwmmc@10218000 { /* wifi */
 @@ -74,12 +70,8 @@
 
   pinctrl-names = default;
   pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
   };
 
   gpio-keys {

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Re: [PATCH v2] iio: exynos-adc: add experimental touchscreen support

2014-07-27 Thread Heiko Stübner
Am Sonntag, 27. Juli 2014, 23:10:21 schrieb Hartmut Knaack:
 Arnd Bergmann schrieb:
  @@ -205,6 +217,9 @@ static void exynos_adc_v1_init_hw(struct exynos_adc
  *info) 
  /* Enable 12-bit ADC resolution */
  con1 |= ADC_V1_CON_RES;
  writel(con1, ADC_V1_CON(info-regs));
  
  +
  +   /* set default touchscreen delay */
 
 Any information about how many µs/ms it is actually set with this value?

ADC conversion is delayed by counting this value. Counting clock is pclk.
So, I guess here 1 pclk ticks.


Heiko

 
  +   writel(1, ADC_V1_DLY(info-regs));
  
   }
   

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Re: [PATCH 2/2] iio: adc: exynos_adc: Add support for S3C24xx ADC

2014-07-22 Thread Heiko Stübner
Am Dienstag, 22. Juli 2014, 10:39:38 schrieb Arnd Bergmann:
 On Tuesday 22 July 2014 11:11:14 Chanwoo Choi wrote:
  This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The
  s3c24xx
  is alomost same as ADCv1. But, There are a little difference as following:
  - ADCMUX register address to select channel
  - ADCDAT mask (10bit or 12bit ADC resolution according to SoC version)
 
 Very good, thanks for doing this patch!
 
 (adding Heiko to Cc, he's probably interested in seeing this as well.

indeed. Thanks for implementing this.

While trying to build a test setup for this, I noticed two points:

(1) I'm not sure what the second register (a phy enable register according
to the binding) is supposed to be.
According to binding and adc code it is mandatory, but I didn't find any
lone adc register in the s3c2416 manual.


(2) You might need something along the lines of:

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 11b048a..088c99a 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -129,7 +129,7 @@ config AT91_ADC
 
 config EXYNOS_ADC
tristate Exynos ADC driver support
-   depends on ARCH_EXYNOS || (OF  COMPILE_TEST)
+   depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || (OF  
COMPILE_TEST)
help
  Core support for the ADC block found in the Samsung EXYNOS series
  of SoCs for drivers such as the touchscreen and hwmon to use to share


Thanks
Heiko

 
 One comment:
  @@ -101,12 +107,14 @@ struct exynos_adc {
  
  struct completion   completion;
  
  u32 value;
  
  +   u32 value2;
  
  unsigned intversion;
   
   };
  
  ...
  @@ -365,7 +448,7 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
  
  ret = -ETIMEDOUT;
  
  } else {
  
  *val = info-value;
  
  -   *val2 = 0;
  +   *val2 = info-value2;
  
  ret = IIO_VAL_INT;
  
  }
  
  @@ -377,9 +460,11 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
  
   static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
   {
   
  struct exynos_adc *info = (struct exynos_adc *)dev_id;
  
  +   u32 mask = info-data-mask;
  
  /* Read value */
  
  -   info-value = readl(ADC_V1_DATX(info-regs))  ADC_DATX_MASK;
  +   info-value = readl(ADC_V1_DATX(info-regs))  mask;
  +   info-value2 = readl(ADC_V1_DATY(info-regs))  mask;
  
  /* clear irq */
  if (info-data-clear_irq)
 
 If I understand it right, this would only be necessary if we want
 to do the touchscreen driver as a separate iio client using the
 in-kernel interfaces. As Jonathan Cameron commented, we probably
 don't want to do that though. Even if we do, it should be a separate
 patch and not mixed in with the s3c24xx support.
 
 Aside from this:
 
 Acked-by: Arnd Bergmann a...@arndb.de
 
   Arnd

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[RFC PATCH 0/3] ARM: restart-notifier support for some architectures

2014-07-06 Thread Heiko Stübner
This series provides restart-notifier integration for the architectures
I care about - S3C24XX and Rockchip.

It of course depends on kernel: Add support for restart notifier call chain
from Guenter Roeck.

Samsung machines can generally be reset using their watchdog, but some
also provide a special software-reset register in their system controller.

The rockchip reset integration of course also depends on the core clock
support series, currently still under review.


Heiko Stuebner (3):
  watchdog: s3c2410: add restart notifier
  clk: samsung: register restart notifiers for s3c2412 and s3c2443
  clk: rockchip: add restart notifier

 drivers/clk/rockchip/clk-rk3188.c |  2 ++
 drivers/clk/rockchip/clk-rk3288.c |  2 ++
 drivers/clk/rockchip/clk.c| 23 +++
 drivers/clk/rockchip/clk.h|  1 +
 drivers/clk/samsung/clk-s3c2412.c | 28 
 drivers/clk/samsung/clk-s3c2443.c | 18 ++
 drivers/watchdog/s3c2410_wdt.c| 33 +
 7 files changed, 107 insertions(+)

-- 
1.9.0


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[RFC PATCH 2/3] clk: samsung: register restart notifiers for s3c2412 and s3c2443

2014-07-06 Thread Heiko Stübner
S3C2412, S3C2443 and their derivatives contain a special software-reset
register in their system-controller.

Therefore register a restart-notifier for those.

Tested on a s3c2416-based board, s3c2412 compile-tested.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/clk/samsung/clk-s3c2412.c | 28 
 drivers/clk/samsung/clk-s3c2443.c | 18 ++
 2 files changed, 46 insertions(+)

diff --git a/drivers/clk/samsung/clk-s3c2412.c 
b/drivers/clk/samsung/clk-s3c2412.c
index 23e4313..840f9bd 100644
--- a/drivers/clk/samsung/clk-s3c2412.c
+++ b/drivers/clk/samsung/clk-s3c2412.c
@@ -14,6 +14,7 @@
 #include linux/of.h
 #include linux/of_address.h
 #include linux/syscore_ops.h
+#include linux/reboot.h
 
 #include dt-bindings/clock/s3c2412.h
 
@@ -26,6 +27,7 @@
 #define CLKCON 0x0c
 #define CLKDIVN0x14
 #define CLKSRC 0x1c
+#define SWRST  0x30
 
 /* list of PLLs to be registered */
 enum s3c2412_plls {
@@ -204,6 +206,27 @@ struct samsung_clock_alias s3c2412_aliases[] __initdata = {
ALIAS(MSYSCLK, NULL, fclk),
 };
 
+static int s3c2412_restart_notify(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+   /* errata Watch-dog/Software Reset Problem specifies that
+* this reset must be done with the SYSCLK sourced from
+* EXTCLK instead of FOUT to avoid a glitch in the reset
+* mechanism.
+*
+* See the watchdog section of the S3C2412 manual for more
+* information on this fix.
+*/
+
+   __raw_writel(0x00, reg_base + CLKSRC);
+   __raw_writel(0x533C2412, reg_base + SWRST);
+   return NOTIFY_DONE;
+}
+
+static struct notifier_block s3c2412_restart_notifier = {
+   .notifier_call = s3c2412_restart_notify,
+};
+
 /*
  * fixed rate clocks generated outside the soc
  * Only necessary until the devicetree-move is complete
@@ -233,6 +256,7 @@ void __init s3c2412_common_clk_init(struct device_node *np, 
unsigned long xti_f,
unsigned long ext_f, void __iomem *base)
 {
struct samsung_clk_provider *ctx;
+   int ret;
reg_base = base;
 
if (np) {
@@ -265,6 +289,10 @@ void __init s3c2412_common_clk_init(struct device_node 
*np, unsigned long xti_f,
   ARRAY_SIZE(s3c2412_aliases));
 
s3c2412_clk_sleep_init();
+
+   ret = register_restart_notifier(s3c2412_restart_notifier);
+   if (ret)
+   pr_warn(cannot register restart notifier, %d\n, ret);
 }
 
 static void __init s3c2412_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c2443.c 
b/drivers/clk/samsung/clk-s3c2443.c
index c4bbdab..0be33cc 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -14,6 +14,7 @@
 #include linux/of.h
 #include linux/of_address.h
 #include linux/syscore_ops.h
+#include linux/reboot.h
 
 #include dt-bindings/clock/s3c2443.h
 
@@ -33,6 +34,7 @@
 #define HCLKCON0x30
 #define PCLKCON0x34
 #define SCLKCON0x38
+#define SWRST  0x44
 
 /* the soc types */
 enum supported_socs {
@@ -354,6 +356,17 @@ struct samsung_clock_alias s3c2450_aliases[] __initdata = {
ALIAS(PCLK_I2C1, s3c2410-i2c.1, i2c),
 };
 
+static int s3c2443_restart_notify(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+   __raw_writel(0x533c2443, reg_base + SWRST);
+   return NOTIFY_DONE;
+}
+
+static struct notifier_block s3c2443_restart_notifier = {
+   .notifier_call = s3c2443_restart_notify,
+};
+
 /*
  * fixed rate clocks generated outside the soc
  * Only necessary until the devicetree-move is complete
@@ -378,6 +391,7 @@ void __init s3c2443_common_clk_init(struct device_node *np, 
unsigned long xti_f,
void __iomem *base)
 {
struct samsung_clk_provider *ctx;
+   int ret;
reg_base = base;
 
if (np) {
@@ -445,6 +459,10 @@ void __init s3c2443_common_clk_init(struct device_node 
*np, unsigned long xti_f,
}
 
s3c2443_clk_sleep_init();
+
+   ret = register_restart_notifier(s3c2443_restart_notifier);
+   if (ret)
+   pr_warn(cannot register restart notifier, %d\n, ret);
 }
 
 static void __init s3c2416_clk_init(struct device_node *np)
-- 
1.9.0


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[RFC PATCH 1/3] watchdog: s3c2410: add restart notifier

2014-07-06 Thread Heiko Stübner
On a lot of Samsung systems the watchdog is responsible for restarting the
system and until now this code was contained in plat-samsung/watchdog-reset.c .

With the introduction of the restart notifiers, this code can now move into
driver itself, removing the need for arch-specific code.

Tested on a S3C2442 based GTA02
Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/watchdog/s3c2410_wdt.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 7c6ccd0..3f89912 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -41,6 +41,7 @@
 #include linux/of.h
 #include linux/mfd/syscon.h
 #include linux/regmap.h
+#include linux/reboot.h
 
 #define S3C2410_WTCON  0x00
 #define S3C2410_WTDAT  0x04
@@ -438,6 +439,31 @@ static inline void s3c2410wdt_cpufreq_deregister(struct 
s3c2410_wdt *wdt)
 }
 #endif
 
+static struct s3c2410_wdt *s3c2410wdt_restart_ctx;
+static int s3c2410wdt_restart_notify(struct notifier_block *this,
+unsigned long mode, void *cmd)
+{
+   void __iomem *wdt_base = s3c2410wdt_restart_ctx-reg_base;
+
+   /* disable watchdog, to be safe  */
+   writel(0, wdt_base + S3C2410_WTCON);
+
+   /* put initial values into count and data */
+   writel(0x80, wdt_base + S3C2410_WTCNT);
+   writel(0x80, wdt_base + S3C2410_WTDAT);
+
+   /* set the watchdog to go and reset... */
+   writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
+   S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
+   wdt_base + S3C2410_WTCON);
+
+   return NOTIFY_DONE;
+}
+
+static struct notifier_block s3c2410wdt_restart_notifier = {
+   .notifier_call = s3c2410wdt_restart_notify,
+};
+
 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
 {
unsigned int rst_stat;
@@ -592,6 +618,11 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
 
platform_set_drvdata(pdev, wdt);
 
+   s3c2410wdt_restart_ctx = wdt;
+   ret = register_restart_notifier(s3c2410wdt_restart_notifier);
+   if (ret)
+   pr_err(cannot register restart notifier, %d\n, ret);
+
/* print out a statement of readiness */
 
wtcon = readl(wdt-reg_base + S3C2410_WTCON);
@@ -621,6 +652,8 @@ static int s3c2410wdt_remove(struct platform_device *dev)
int ret;
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 
+   unregister_restart_notifier(s3c2410wdt_restart_notifier);
+
ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
if (ret  0)
return ret;
-- 
1.9.0


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[RFC PATCH 3/3] clk: rockchip: add restart notifier

2014-07-06 Thread Heiko Stübner
Add infrastructure to write the correct value to the restart register and
register the restart notifier for both rk3188 (including rk3066) and rk3188.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/clk/rockchip/clk-rk3188.c |  2 ++
 drivers/clk/rockchip/clk-rk3288.c |  2 ++
 drivers/clk/rockchip/clk.c| 23 +++
 drivers/clk/rockchip/clk.h|  1 +
 4 files changed, 28 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index a83a6d8..71b661a 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -631,6 +631,8 @@ static void __init rk3188_common_clk_init(struct 
device_node *np)
 
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
  ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+   rockchip_register_restart_notifier(RK2928_GLB_SRST_FST);
 }
 
 static void __init rk3066a_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 0d8c6c5..b604217 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -713,5 +713,7 @@ static void __init rk3288_clk_init(struct device_node *np)
 
rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
  ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+   rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
 }
 CLK_OF_DECLARE(rk3288_cru, rockchip,rk3288-cru, rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 278cf9d..0594941 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -25,6 +25,7 @@
 #include linux/clk-provider.h
 #include linux/mfd/syscon.h
 #include linux/regmap.h
+#include linux/reboot.h
 #include clk.h
 
 /**
@@ -242,3 +243,25 @@ void __init rockchip_clk_register_branches(
rockchip_clk_add_lookup(clk, list-id);
}
 }
+
+static unsigned int reg_restart;
+static int rockchip_restart_notify(struct notifier_block *this,
+  unsigned long mode, void *cmd)
+{
+   writel(0xfdb9, reg_base + reg_restart);
+   return NOTIFY_DONE;
+}
+
+static struct notifier_block rockchip_restart_notifier = {
+   .notifier_call = rockchip_restart_notify,
+};
+
+void __init rockchip_register_restart_notifier(unsigned int reg)
+{
+   int ret;
+
+   reg_restart = reg;
+   ret = register_restart_notifier(rockchip_restart_notifier);
+   if (ret)
+   pr_err(cannot register restart notifier, %d\n, ret);
+}
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 887cbde..0b5eab5 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -329,6 +329,7 @@ void rockchip_clk_register_branches(struct 
rockchip_clk_branch *clk_list,
unsigned int nr_clk);
 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
unsigned int nr_pll, int grf_lock_offset);
+void rockchip_register_restart_notifier(unsigned int reg);
 
 #define ROCKCHIP_SOFTRST_HIWORD_MASK   BIT(0)
 
-- 
1.9.0


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Re: [PATCH 00/19] ARM: SAMSUNG: S5PV210 platform clean-up

2014-07-05 Thread Heiko Stübner
Am Samstag, 5. Juli 2014, 13:00:43 schrieb Tomasz Figa:
 On 05.07.2014 06:46, Viresh Kumar wrote:
  On Fri, Jul 4, 2014 at 11:14 PM, Tomasz Figa t.f...@samsung.com wrote:
  This huge series is a (hopefully final) attempt to convert Samsung
  S5PV210
  into a DT-only and multiplatform-aware platform. It consists of several
  steps to gradually replace legacy code with one meeting current standards
  and then finally remove unused remnants.
  
  Patches 1-6 migrate the platform to fully use the Common Clock Framework
  and get rid of legacy private clock code, of which s5pv210 was the last
  user. Then patch 7 adds generic PHY driver for USB PHY on S5PV210 to
  allow
  USB to be supported when using DT. Further three patches (8-10) add DT
  support for mach-s5pv210 and necessary DT sources for currently supported
  boards. Patch 11 removes board files and code directly related to them,
  effectively making s5pv210 a DT-only platform. In next step, patches
  12-15
  prepare remaining code for multiplatform enablement, which is finally
  done
  in patch 16. Patches 17-19 are a final clean-up, which remove a lot of
  unused code left after making the last S5P platform DT-only.
  
  Build tested patch by patch on following configs:
   - s3c2410_defconfig (with DT support enabled),
   - s3c6400_defconfig (with DT support enabled),
   - s5pv210_defconfig (with DT support enabled after patches adding it),
   - exynos_defconfig,
   - exynos_defconfig with S5PV210 enabled in multiplatform configuration.
  
  Boot tested on s5pv210-goni board.
  
  Note that support for smdkc110, smdkv210 and torbreck boards is provided
  by moving data from existing board files to new device tree sources. No
  testing was performed due to mentioned board not being available anymore.
  However I believe we agreed on this approach, because apparently there
  are no active users of them. See the RFC from August 2013 asking for
  removal of the whole platform [1].
  
  [1]
  http://www.mail-archive.com/linux-samsung-soc%40vger.kernel.org/msg21882
  .html 
  Tomasz Figa (13):
cpufreq: s3c24xx: Remove some dead code
cpufreq: s5pv210: Make the driver multiplatform aware
  
  Looks like you used --suppress-cc=all while sending these and none of
  CPUFreq/PM guys received it :(
 
 Oops, I had a feeling that I has screwed up something with this series
 and now we know what. Sorry for this. Will resend properly next Tuesday.

I got the cover-letter 3 times (19:44, 19:46 and 19:48). The one from 19:48 
also did contain all 19 patches ;-)


Heiko

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Re: [PATCHv2 4/5] ARM: dts: rockchip: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-04 Thread Heiko Stübner
Am Montag, 30. Juni 2014, 20:49:18 schrieb Jaehoon Chung:
 dw-mmc controller can support multiple slots.
 But, there are no use-cases anywhere. So we don't need to support the
 slot-node for dw-mmc controller.
 And supports-highspeed property in dw-mmc is deprecated.
 supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
 
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 Reviewed-by: Tushar Behera trbli...@gmail.com
 Reviewed-by: Ulf Hansson ulf.hans...@linaro.org

Reviewed-by: Heiko Stuebner he...@sntech.de

 ---
  arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
  1 file changed, 4 insertions(+), 12 deletions(-)
 
 diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index afb3273..ecea889 100644
 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
 @@ -59,12 +59,8 @@
   pinctrl-names = default;
   pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
   vmmc-supply = vcc_sd0;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
   };
 
   dwmmc@10218000 { /* wifi */
 @@ -74,12 +70,8 @@
 
   pinctrl-names = default;
   pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 4;
 - disable-wp;
 - };
 + bus-width = 4;
 + disable-wp;
   };
 
   gpio-keys {

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Re: [PATCH 1/2] clk: samsung: fix several typos to fix boot on s3c2410

2014-06-23 Thread Heiko Stübner
Am Montag, 23. Juni 2014, 23:29:09 schrieb Vasily Khoruzhick:
 There's a several typos in a driver: 2410 instead of S3C2410
 and wrong argument to ARRAY_SIZE(). They prevent s3c2410
 from properly booting.
 
 Signed-off-by: Vasily Khoruzhick anars...@gmail.com

Thanks for catching these.
Reviewed-by: Heiko Stuebner he...@sntech.de

 ---
  drivers/clk/samsung/clk-s3c2410.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/clk/samsung/clk-s3c2410.c
 b/drivers/clk/samsung/clk-s3c2410.c index ba07168..bd9a873 100644
 --- a/drivers/clk/samsung/clk-s3c2410.c
 +++ b/drivers/clk/samsung/clk-s3c2410.c
 @@ -378,7 +378,7 @@ void __init s3c2410_common_clk_init(struct device_node
 *np, unsigned long xti_f, if (!np)
   s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
 
 - if (current_soc == 2410) {
 + if (current_soc == S3C2410) {
   if (_get_rate(xti) == 12 * MHZ) {
   s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
   s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
 @@ -432,7 +432,7 @@ void __init s3c2410_common_clk_init(struct device_node
 *np, unsigned long xti_f, samsung_clk_register_fixed_factor(ctx,
 s3c2410_ffactor,
   ARRAY_SIZE(s3c2410_ffactor));
   samsung_clk_register_alias(ctx, s3c2410_aliases,
 - ARRAY_SIZE(s3c2410_common_aliases));
 + ARRAY_SIZE(s3c2410_aliases));
   break;
   case S3C2440:
   samsung_clk_register_mux(ctx, s3c2440_muxes,

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Re: [PATCH 2/2] clk: samsung: add more aliases for s3c24xx

2014-06-23 Thread Heiko Stübner
Am Montag, 23. Juni 2014, 23:29:10 schrieb Vasily Khoruzhick:
 Without these aliases clock lookup fails in s3c2410fb,
 s3cmci, s3c2410-nand, s3c24xx-i2s, and i2c-s3c2410 drivers.
 
 Signed-off-by: Vasily Khoruzhick anars...@gmail.com
Reviewed-by: Heiko Stuebner he...@sntech.de

 ---
  drivers/clk/samsung/clk-s3c2410.c | 5 +
  1 file changed, 5 insertions(+)
 
 diff --git a/drivers/clk/samsung/clk-s3c2410.c
 b/drivers/clk/samsung/clk-s3c2410.c index bd9a873..140f473 100644
 --- a/drivers/clk/samsung/clk-s3c2410.c
 +++ b/drivers/clk/samsung/clk-s3c2410.c
 @@ -152,6 +152,11 @@ struct samsung_clock_alias s3c2410_common_aliases[]
 __initdata = { ALIAS(HCLK, NULL, hclk),
   ALIAS(MPLL, NULL, mpll),
   ALIAS(FCLK, NULL, fclk),
 + ALIAS(PCLK, NULL, watchdog),
 + ALIAS(PCLK_SDI, NULL, sdi),
 + ALIAS(HCLK_NAND, NULL, nand),
 + ALIAS(PCLK_I2S, NULL, iis),
 + ALIAS(PCLK_I2C, NULL, i2c),
  };
 
  /* S3C2410 specific clocks */

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Re: [PATCHv3 4/4] ARM: dts: replace the slot property into slot sub-node for dwmmc.

2014-05-30 Thread Heiko Stübner
Am Freitag, 30. Mai 2014, 21:54:13 schrieb Seungwon Jeon:
 + Dinh Nguyen dingu...@altera.com
 + Heiko Stuebner he...@sntech.de
 
 On Wed, May 28, 2014, Jaehoon Chung wrote:
  dw-mmc controller can support the multiple slot.
  So each slot's property can be difference.
  And support-highspeed property in dw-mmc is deprecated.
  support-highspeed property can be replaced to cap-sd/mmc-highspeed.
  
  Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 
 Looks good to me.
 
 Acked-by: Seungwon Jeon tgih@samsung.com

the rockchip part also looks ok to me

Acked-by: Heiko Stuebner he...@sntech.de


 
 Thanks,
 Seungwon Jeon
 
  ---
  
  Changelog V3:
  - Merge [PATCH 2/5] mmc: dw_mmc: rmove the supports-highspeed
  property
  
  Changelog V2:
  - None
  
   .../devicetree/bindings/mmc/exynos-dw-mshc.txt |5 +++--
   .../devicetree/bindings/mmc/k3-dw-mshc.txt |3 ++-
   .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |6 --
   arch/arm/boot/dts/exynos4412-odroidx.dts   |4 ++--
   arch/arm/boot/dts/exynos4412-origen.dts|4 ++--
   arch/arm/boot/dts/exynos4412-trats2.dts|6 +++---
   arch/arm/boot/dts/exynos5250-arndale.dts   |6 +++---
   arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   10 +-
   arch/arm/boot/dts/exynos5250-smdk5250.dts  |6 +++---
   arch/arm/boot/dts/exynos5420-arndale-octa.dts  |6 +++---
   arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 ++--
   arch/arm/boot/dts/rk3066a-bqcurie2.dts |2 +-
   arch/arm/boot/dts/socfpga_arria5.dtsi  |5 +++--
   arch/arm/boot/dts/socfpga_cyclone5.dtsi|5 +++--
   arch/arm/boot/dts/socfpga_vt.dts   |5 +++--
   15 files changed, 42 insertions(+), 35 deletions(-)
  
  diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
  b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
  index 532b1d4..41cc703 100644
  --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
  +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
  
  @@ -69,8 +69,6 @@ Example:
  dwmmc0@1220 {
  
  num-slots = 1;
  
  -   supports-highspeed;
  -   broken-cd;
  
  fifo-depth = 0x80;
  card-detect-delay = 200;
  samsung,dw-mshc-ciu-div = 3;
  
  @@ -85,5 +83,8 @@ Example:
  gpc1 2 2 3 3, gpc1 3 2 3 3,
  gpc0 3 2 3 3, gpc0 4 2 3 3,
  gpc0 5 2 3 3, gpc0 6 2 3 3;
  
  +   broken-cd;
  +   cap-mmc-highspeed;
  +   cap-sd-highspeed;
  
  };
  
  };
  
  diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
  b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
  index b8653ea..b1844c5 100644
  --- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
  +++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
  
  @@ -34,7 +34,6 @@ Example:
  num-slots = 1;
  vmmc-supply = ldo12;
  fifo-depth = 0x100;
  
  -   supports-highspeed;
  
  pinctrl-names = default;
  pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
  slot@0 {
  
  @@ -42,5 +41,7 @@ Example:
  bus-width = 4;
  disable-wp;
  cd-gpios = gpio10 3 0;
  
  +   cap-mmc-highspeed;
  +   cap-sd-highspeed;
  
  };
  
  };
  
  diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
  b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
  index 2d4a725..ff393ab 100644
  --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
  +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
  
  @@ -67,7 +67,8 @@ Optional properties:
   * card-detect-delay: Delay in milli-seconds before detecting card after
   card  
 insert event. The default value is 0.
  
  -* supports-highspeed: Enables support for high speed cards (up to 50MHz)
  +* supports-highspeed (DEPRECATED): Enables support for high speed cards
  (up to 50MHz) +(use cap-mmc-highspeed or cap-sd-
highspeed
  instead)
  
   * broken-cd: as documented in mmc core bindings.
  
  @@ -98,7 +99,6 @@ board specific portions as listed below.
  
  clock-frequency = 4;
  clock-freq-min-max = 40 2;
  num-slots = 1;
  
  -   supports-highspeed;
  
  broken-cd;
  fifo-depth = 0x80;
  card-detect-delay = 200;
  
  @@ -107,5 +107,7 @@ board specific portions as listed below.
  
  slot@0 {
  
  reg = 0;
  bus-width = 8;
  
  +   cap-mmc-highspeed;
  +   cap-sd-highspeed;
  
  

Re: [PATCH v2 04/18] video: add command mode and command mode display timing

2014-05-26 Thread Heiko Stübner
Am Montag, 26. Mai 2014, 12:14:43 schrieb Thierry Reding:
 On Wed, May 21, 2014 at 01:42:56PM +0900, YoungJun Cho wrote:
  This patch is based on videomode and display_timing relevant codes.
  To support command mode panel, it does not need to guide its timing
  information to the display controller like video mode panel,
  but it requires signal timings to transfer video data.
  So this patch adds cmdmode struct, cmdmode_display_timing struct and
  the according helper functions to convert cmdmode_display_timing
  to a generic cmdmode.
  
  Signed-off-by: YoungJun Cho yj44@samsung.com
  Acked-by: Inki Dae inki@samsung.com
  Acked-by: Kyungmin Park kyungmin.p...@samsung.com
  ---
  
   drivers/video/Kconfig |3 +
   drivers/video/Makefile|2 +
   drivers/video/cmdmode.c   |   42 ++
   drivers/video/cmdmode_display_timing.c|   26 
   drivers/video/of_cmdmode.c|   55 
   drivers/video/of_cmdmode_display_timing.c |  212
   + include/video/cmdmode.h  
   |   67 +
   include/video/cmdmode_display_timing.h|   59 
   include/video/of_cmdmode.h|   19 +++
   include/video/of_cmdmode_display_timing.h |   26 
   10 files changed, 511 insertions(+)
   create mode 100644 drivers/video/cmdmode.c
   create mode 100644 drivers/video/cmdmode_display_timing.c
   create mode 100644 drivers/video/of_cmdmode.c
   create mode 100644 drivers/video/of_cmdmode_display_timing.c
   create mode 100644 include/video/cmdmode.h
   create mode 100644 include/video/cmdmode_display_timing.h
   create mode 100644 include/video/of_cmdmode.h
   create mode 100644 include/video/of_cmdmode_display_timing.h
 
 Cc'ing Heiko Stübner on this. Heiko, you seem to have done some work on
 i80 in the past[0] and I'm wondering if you could share any insights you
 may have here.
 
 In particular I'd like your take on the approach taken in this patch to
 describe i80 parameters to a generic command-mode display timings
 structure. However it seems to me that these timings are really very i80
 specific and don't apply in general to command-mode displays.
 
 As such I'm beginning to think that this should rather be a property of
 the attached display/panel rather than the interface that generates the
 signal.

OMG ... your digging in my ancient history :-D

I always got the impression, i80 is somehow related to the MIPI-DBI protocol 
[1].

Also the display I was working on (AUO-K190x epaper controller) used the 
command mode to also transfer the display region to update and had a 
completely dfferent command set [2].

In the end, I temporarily settled in adding a glue driver, driving the s3c2416 
i80 controller [3]. But someday I'd like to integrate this into a real 
solution, as the s3c2416 lcd-controller can do the i80 also in hardware, maybe 
speeding things up a little.

So I guess the transfer method itself is generic, but the commands used seem 
to differ. But I of course don't know if regular MIPI-DBI/i80 displays use a 
command set of commands for their timings.


Heiko


[1] https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg29100.html
[2] 
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/video/fbdev/auo_k190x.h
[3] 
https://github.com/mmind/linux-es600/blob/topic/es600-devel/drivers/video/es600-epd.c

  diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
  index c7b4f0f..7090ee5 100644
  --- a/drivers/video/Kconfig
  +++ b/drivers/video/Kconfig
  @@ -38,6 +38,9 @@ config VGASTATE
  
   config VIDEOMODE_HELPERS
   
  bool
  
  +config CMDMODE_HELPERS
  +   bool
  +
  
   config HDMI
   
  bool
  
  diff --git a/drivers/video/Makefile b/drivers/video/Makefile
  index 9ad3c17..619dd99 100644
  --- a/drivers/video/Makefile
  +++ b/drivers/video/Makefile
  @@ -8,6 +8,8 @@ obj-y += backlight/
  
   obj-y+= fbdev/
   
   obj-$(CONFIG_VIDEOMODE_HELPERS) += display_timing.o videomode.o
  
  +obj-$(CONFIG_CMDMODE_HELPERS) += cmdmode_display_timing.o cmdmode.o
  
   ifeq ($(CONFIG_OF),y)
   obj-$(CONFIG_VIDEOMODE_HELPERS) += of_display_timing.o of_videomode.o
  
  +obj-$(CONFIG_CMDMODE_HELPERS) += of_cmdmode_display_timing.o of_cmdmode.o
  
   endif
  
  diff --git a/drivers/video/cmdmode.c b/drivers/video/cmdmode.c
  new file mode 100644
  index 000..3d3eeb8
  --- /dev/null
  +++ b/drivers/video/cmdmode.c
  @@ -0,0 +1,42 @@
  +/*
  + * generic cmdmode display timing functions
  + *
  + * Copyright (c) 2014 YoungJun Cho yj44@samsung.com
  + *
  + * This program is free software; you can redistribute it and/or modify
  + * it under the terms of the GNU General Public License version 2 as
  + * published by the Free Software Foundation.
  + */
  +
  +#include linux/errno.h
  +#include linux/export.h
  +#include video/cmdmode_display_timing.h

Re: [alsa-devel] [PATCH v2 1/2] ASoC: samsung: s3c24{xx, 12}-i2s: port to use generic dmaengine API

2014-05-21 Thread Heiko Stübner
Am Mittwoch, 21. Mai 2014, 17:07:47 schrieb Tomasz Figa:
 On 21.05.2014 16:53, Vasily Khoruzhick wrote:
  On Wed, May 21, 2014 at 4:28 PM, Tomasz Figa t.f...@samsung.com wrote:
  Please remember to keep linux-samsung-soc ML on Cc when sending patches
  related to Samsung platforms. It is essential to let Samsung people
  review them.
  
  Ok, I'll keep it in mind. I've just checked and get_maintainer.pl
  outputs linux-samsung-soc ML for these
  patches. I've omitted it occasionally, because it wasn't necessary to
  keep it in CC back in 2011
  (year of my last sound-related patch for s3c24xx).
  
  Please resend the series with this in mind.
  
  Is it really necessary? This patch is supposed to go through ASoC
  tree, not through Samsung's.
  And I really doubt that Samsung guys test kernel for s3c24xx boards
  nowadays.
 Maybe not test, but at least review the code. Also there might be other
 people following that list that might be interested in looking at this
 series, while not subscribed to alsa-devel - I can name at least Heiko
 Stübner, who should be able to test it on further s3c24xx-based boards.

Sadly, I don't have a working sound setup on my 2 s3c boards.


Heiko
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Re: [alsa-devel] [PATCH v2 1/2] ASoC: samsung: s3c24{xx, 12}-i2s: port to use generic dmaengine API

2014-05-21 Thread Heiko Stübner
Am Mittwoch, 21. Mai 2014, 18:39:26 schrieb Vasily Khoruzhick:
 On Wed, May 21, 2014 at 6:29 PM, Heiko Stübner he...@sntech.de wrote:
  Am Mittwoch, 21. Mai 2014, 17:07:47 schrieb Tomasz Figa:
  On 21.05.2014 16:53, Vasily Khoruzhick wrote:
   On Wed, May 21, 2014 at 4:28 PM, Tomasz Figa t.f...@samsung.com wrote:
   Please remember to keep linux-samsung-soc ML on Cc when sending
   patches
   related to Samsung platforms. It is essential to let Samsung people
   review them.
   
   Ok, I'll keep it in mind. I've just checked and get_maintainer.pl
   outputs linux-samsung-soc ML for these
   patches. I've omitted it occasionally, because it wasn't necessary to
   keep it in CC back in 2011
   (year of my last sound-related patch for s3c24xx).
   
   Please resend the series with this in mind.
   
   Is it really necessary? This patch is supposed to go through ASoC
   tree, not through Samsung's.
   And I really doubt that Samsung guys test kernel for s3c24xx boards
   nowadays.
  
  Maybe not test, but at least review the code. Also there might be other
  people following that list that might be interested in looking at this
  series, while not subscribed to alsa-devel - I can name at least Heiko
  Stübner, who should be able to test it on further s3c24xx-based boards.
  
  Sadly, I don't have a working sound setup on my 2 s3c boards.
 
 What are they btw? Is it too time-consuming to make sound working on them?
 It would be nice if anyone except me could test these patches.

Openmoko Freerunner (S3C2440) where there may be sound reachable someway and a 
Oyo ebook-reader (S3C2416) whose i2s is I think compatible with the s3c64xx 
instead of the s3c24xx ones and with a completely unsupported codec.

But in general I'm fairly confident that if you hear sounds on your device your 
conversion would be fine test-wise :-)


Heiko
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Re: [alsa-devel] [PATCH v2 1/2] ASoC: samsung: s3c24{xx, 12}-i2s: port to use generic dmaengine API

2014-05-21 Thread Heiko Stübner
Am Mittwoch, 21. Mai 2014, 19:09:19 schrieb Vasily Khoruzhick:
 On Wed, May 21, 2014 at 6:56 PM, Heiko Stübner he...@sntech.de wrote:
  Openmoko Freerunner (S3C2440) where there may be sound reachable someway
  and a Oyo ebook-reader (S3C2416) whose i2s is I think compatible with
  the s3c64xx instead of the s3c24xx ones and with a completely unsupported
  codec.
 Freerunner is s3c2442, and actually I can test s3c2442 on my iPAQ rx1950.
 s3c2416 may be supported by s3c2412-i2s, I have no spec at the hand,
 so I can't check.

I'm quite sure, s3c2416 shares the s3c64xx i2s ... at some point I matched the 
registers and it also shares the hsspi, sdhci and fb drivers with the newer 
generations (s3c64xx onward).

Heiko
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Re: [PATCH v4 3/8] clk: samsung: add infrastructure to register cpu clocks

2014-05-15 Thread Heiko Stübner
Am Donnerstag, 15. Mai 2014, 11:18:44 schrieb Doug Anderson:
 Thomas,
 
 On Tue, May 13, 2014 at 6:11 PM, Thomas Abraham ta.oma...@gmail.com wrote:
  From: Thomas Abraham thomas...@samsung.com
  +static int exynos4210_armclk_pre_rate_change(struct clk_notifier_data
  *ndata, +   struct exynos_cpuclk *armclk, void
  __iomem *base) +{
  +   struct exynos4210_armclk_data *armclk_data = armclk-data;
  +   unsigned long alt_prate = clk_get_rate(armclk-alt_parent);
  +   unsigned long alt_div, div0, div1, tdiv0, mux_reg;
  +   unsigned long cur_armclk_rate, timeout;
  +   unsigned long flags;
  +
  +   /* find out the divider values to use for clock data */
  +   while (armclk_data-prate != ndata-new_rate) {
  +   if (armclk_data-prate == 0)
  +   return -EINVAL;
  +   armclk_data++;
  +   }
  +
  +   div0 = armclk_data-div0;
  +   div1 = armclk_data-div1;
  +   if (readl(base + SRC_CPU)  EXYNOS4210_MUX_HPM_MASK) {
  +   div1 = readl(base + DIV_CPU1)  EXYNOS4210_DIV1_HPM_MASK;
  +   div1 |= ((armclk_data-div1)  ~EXYNOS4210_DIV1_HPM_MASK);
  +   }
  +
  +   /*
  +* if the new and old parent clock speed is less than the clock
  speed +* of the alternate parent, then it should be ensured that
  at no point +* the armclk speed is more than the old_prate until
  the dividers are +* set.
  +*/
  +   tdiv0 = readl(base + DIV_CPU0);
  +   cur_armclk_rate = ndata-old_rate / EXYNOS4210_ARM_DIV1(tdiv0) /
  +   EXYNOS4210_ARM_DIV2(tdiv0);
  +   if (alt_prate  cur_armclk_rate) {
  +   alt_div = _calc_div(alt_prate, cur_armclk_rate);
  +   _exynos4210_set_armclk_div(base, alt_div);
  +   div0 |= alt_div;
 
 Don't you need to up the voltage here, too?  ...I haven't reviewed
 this whole patch (so perhaps it's elsewhere in the patch or in the
 series), but I stumbled upon this while trying to solve a different
 problem and figured I'd check...

setting the voltage should be done by the cpufreq driver like cpufreq-cpu0 - 
whose usage this series intents to allow.

As I've hijacked Thomas' concept for my current rockchip clock work, I've 
already seen this working nicely :-) .


Heiko
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Re: [PATCH v4 3/8] clk: samsung: add infrastructure to register cpu clocks

2014-05-15 Thread Heiko Stübner
Hi Doug,

Am Donnerstag, 15. Mai 2014, 12:36:45 schrieb Doug Anderson:
 On Thu, May 15, 2014 at 12:17 PM, Heiko Stübner he...@sntech.de wrote:
  Am Donnerstag, 15. Mai 2014, 11:18:44 schrieb Doug Anderson:
  Thomas,
  
  On Tue, May 13, 2014 at 6:11 PM, Thomas Abraham ta.oma...@gmail.com 
wrote:
   From: Thomas Abraham thomas...@samsung.com
   +static int exynos4210_armclk_pre_rate_change(struct clk_notifier_data
   *ndata, +   struct exynos_cpuclk *armclk, void
   __iomem *base) +{
   +   struct exynos4210_armclk_data *armclk_data = armclk-data;
   +   unsigned long alt_prate = clk_get_rate(armclk-alt_parent);
   +   unsigned long alt_div, div0, div1, tdiv0, mux_reg;
   +   unsigned long cur_armclk_rate, timeout;
   +   unsigned long flags;
   +
   +   /* find out the divider values to use for clock data */
   +   while (armclk_data-prate != ndata-new_rate) {
   +   if (armclk_data-prate == 0)
   +   return -EINVAL;
   +   armclk_data++;
   +   }
   +
   +   div0 = armclk_data-div0;
   +   div1 = armclk_data-div1;
   +   if (readl(base + SRC_CPU)  EXYNOS4210_MUX_HPM_MASK) {
   +   div1 = readl(base + DIV_CPU1) 
   EXYNOS4210_DIV1_HPM_MASK;
   +   div1 |= ((armclk_data-div1) 
   ~EXYNOS4210_DIV1_HPM_MASK);
   +   }
   +
   +   /*
   +* if the new and old parent clock speed is less than the clock
   speed +* of the alternate parent, then it should be ensured
   that
   at no point +* the armclk speed is more than the old_prate
   until
   the dividers are +* set.
   +*/
   +   tdiv0 = readl(base + DIV_CPU0);
   +   cur_armclk_rate = ndata-old_rate / EXYNOS4210_ARM_DIV1(tdiv0)
   /
   +   EXYNOS4210_ARM_DIV2(tdiv0);
   +   if (alt_prate  cur_armclk_rate) {
   +   alt_div = _calc_div(alt_prate, cur_armclk_rate);
   +   _exynos4210_set_armclk_div(base, alt_div);
   +   div0 |= alt_div;
  
  Don't you need to up the voltage here, too?  ...I haven't reviewed
  this whole patch (so perhaps it's elsewhere in the patch or in the
  series), but I stumbled upon this while trying to solve a different
  problem and figured I'd check...
  
  setting the voltage should be done by the cpufreq driver like cpufreq-cpu0
  - whose usage this series intents to allow.
  
  As I've hijacked Thomas' concept for my current rockchip clock work, I've
  already seen this working nicely :-) .
 
 I guess I should have been more clear.  I was talking more
 specifically about upping the voltage as part of the mux switch in the
 case that alt_prate  cur_armclk_rate.

from earlier discussions I remember Thomas and me talked about setting a 
divider to make sure that alt_prate = cur_armclk_rate, so the voltage can 
stay at its current level. I haven't looked deeply into this revision, but the 
last one did exactly this.


 ...if you're switching from 200MHz to 300MHz and the alt_prate is
 800MHz, you need to account for that fact.  The code here accounts for
 the fact in setting the armclk_div, but (I don't think) it accounts
 for the fact that 800MHz will need a higher voltage.
 
 As per a separate discussion, a clean solution might be to move the
 mux switching to the core of CPU_FREQ.  That would have the side
 effect of also making it very easy to send notifications.

I'll just wait until you all decide what the best solution is :-), but 
personally I like the concept of keeping the clock logic inside the clock 
driver, especially as this is not limited to setting the mux but also adapting 
tightly bound child clocks and this all may not fit into a generic 
implementation of a cpufreq driver.

And this is also working really nice on my rockchip platform.


Heiko
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Re: [PATCH v4 7/8] ARM: Exynos: switch to using generic cpufreq-cpu0 driver

2014-05-14 Thread Heiko Stübner
Am Mittwoch, 14. Mai 2014, 18:35:29 schrieb Viresh Kumar:
 On 14 May 2014 18:20, Arnd Bergmann a...@arndb.de wrote:
  Could we please come up with a way to probe this from DT in the
  cpufreq-cpu0 driver itself, so we don't have to add a device in every
  platform using it?
 Its followed that way because DT Maintainers had strong objections
 to creating virtual device nodes and haven't allowed creation of nodes
 for cpufreq drivers.. For which there is no physical device, as CPU already
 has a separate node..

as we already have the enable-method property for enabling/disabling cpus, 
would something like a scaling-method be feasible?

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Re: [PATCH v2.1 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-05-12 Thread Heiko Stübner
Hi Kukjin,

Am Dienstag, 13. Mai 2014, 07:47:57 schrieb Kukjin Kim:
 On 05/10/14 08:33, Heiko Stübner wrote:
  Hi Tomasz,
  
  It seems this one just hit linux-next (in next-20140509).
  
  Which is bad, because:
  a) it conflicts with patches already applied in samsung-clk tree,
  
  I remember seeing patches regarding more than one clk-samsung clock
  providers. Do you need any additional changes for s3c24xx from me for
  this?
  
  Yes, that's the problem here. If you could do it, I would appreciate it,
  but if you don't have time then I can handle this. The changes needed
  are mostly trivial - basically every common samsung_clk function gets
  new argument to a context structure. The branch to base on would be
  for_3.16/exynos5260 in samsung-clk tree.
 
 I think, would be better if we could fix the conflicts with Hekio's
 additional patches...basically nobody wants revert something for next
 tree once it is landed. But in this case, it's up to Tomasz...
 
 Probably, Heiko resubmitted? Is it based on the branch Tomasz memtioned,
 I didn't check it yet?..
 
 Tomasz, do you still want me to drop this series in samsung tree now?
 Additional patches would be helpful to me because other dependency i.e.,
 exynos5260...for me.

I submitted a v3 series yesterday, that is based on Tomasz' branch. This 
prevents build errors from happening. I'll let you two decide how you want to 
handle this :-)

I can also produce fixup patches if you two decide to keep the v2 series and 
just fix the conflicts.


Heiko
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[PATCH v3 0/9] ARM: S3C24XX: convert s3c2410, s3c2440 s3c2442 to common clock framework

2014-05-11 Thread Heiko Stübner
It is meant to go on top of for_3.16/exynos5260 in tfiga/samsung-clk git
which introduces an API change for the samsung ccf.

The separate patch
ARM: S3C24XX: remove SAMSUNG_CLOCK remnants after ccf conversion
should still go on top of this series.

changes since v2.1:
- adapt to changed samsung clock api in conjunction with
  samsung_clk_provider struct
- fix type in Kconfig found by Paul Bolle (S3C24XX_COMMON_DCLK)
- fix type in dt-binding wrongly referencing clocks/samsung,s3c2410-clock.h
changes since v2:
- adapt to 3.15 changes
- use the mpll clk already aquired by the cpufreq base
changes since v1:
- add already received Acks and Reviews
- remove patches that were already part of the s3c2412 submission
- implement suggestions from Tomasz Figa:
- in cpufreq-utils only request mpll clock the first time
- in dclk driver
  - use variant list to describe SoC differences
  - do not provide a dt binding at this time, as the dclk
parts should probably be part of the pinctrl driver
In any case this can be solved when the first dt platform needs
support for the external clock outputs
- in clk-s3c2410
  - fix sentinels
  - rename dt-bindings header
  - don't export XTI clock id

Heiko Stuebner (9):
  ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when
using ccf
  clk: samsung: add clock driver for external clock outputs
  ARM: S3C24XX: enable usage of common dclk if common clock framework is
enabled
  dt-bindings: add documentation for s3c2410 clock controller
  clk: samsung: add clock controller driver for s3c2410, s3c2440 and
s3c2442
  ARM: S3C24XX: add platform code for conversion to the common clock
framework
  ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework
  ARM: S3C24XX: convert s3c2410 to common clock framework
  ARM: S3C24XX: remove legacy clock code

 .../bindings/clock/samsung,s3c2410-clock.txt   |  50 +++
 arch/arm/mach-s3c24xx/Kconfig  |  50 ++-
 arch/arm/mach-s3c24xx/Makefile |   6 +-
 arch/arm/mach-s3c24xx/clock-dclk.c | 195 -
 arch/arm/mach-s3c24xx/clock-s3c2410.c  | 284 
 arch/arm/mach-s3c24xx/clock-s3c2440.c  | 217 --
 arch/arm/mach-s3c24xx/clock-s3c244x.c  | 141 --
 arch/arm/mach-s3c24xx/common.c |  45 +-
 arch/arm/mach-s3c24xx/common.h |  11 +-
 arch/arm/mach-s3c24xx/cpufreq-utils.c  |   8 +
 arch/arm/mach-s3c24xx/include/mach/regs-clock.h|  18 -
 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h |   3 -
 arch/arm/mach-s3c24xx/mach-amlm5900.c  |   9 +-
 arch/arm/mach-s3c24xx/mach-anubis.c|  15 +-
 arch/arm/mach-s3c24xx/mach-at2440evb.c |  10 +-
 arch/arm/mach-s3c24xx/mach-bast.c  |  15 +-
 arch/arm/mach-s3c24xx/mach-gta02.c |   8 +-
 arch/arm/mach-s3c24xx/mach-h1940.c |  10 +-
 arch/arm/mach-s3c24xx/mach-mini2440.c  |  10 +-
 arch/arm/mach-s3c24xx/mach-n30.c   |  12 +-
 arch/arm/mach-s3c24xx/mach-nexcoder.c  |  10 +-
 arch/arm/mach-s3c24xx/mach-osiris.c|  15 +-
 arch/arm/mach-s3c24xx/mach-otom.c  |  10 +-
 arch/arm/mach-s3c24xx/mach-qt2410.c|   9 +-
 arch/arm/mach-s3c24xx/mach-rx1950.c|  15 +-
 arch/arm/mach-s3c24xx/mach-rx3715.c|  10 +-
 arch/arm/mach-s3c24xx/mach-smdk2410.c  |   9 +-
 arch/arm/mach-s3c24xx/mach-smdk2440.c  |  10 +-
 arch/arm/mach-s3c24xx/mach-tct_hammer.c|   9 +-
 arch/arm/mach-s3c24xx/mach-vr1000.c|  15 +-
 arch/arm/mach-s3c24xx/pm.c |  12 -
 arch/arm/mach-s3c24xx/s3c2410.c|  56 ---
 arch/arm/mach-s3c24xx/s3c2442.c| 111 -
 arch/arm/mach-s3c24xx/s3c244x.c|  59 +--
 arch/arm/plat-samsung/include/plat/cpu-freq-core.h |   1 +
 drivers/clk/samsung/Makefile   |   2 +
 drivers/clk/samsung/clk-s3c2410-dclk.c | 440 +++
 drivers/clk/samsung/clk-s3c2410.c  | 482 +
 drivers/cpufreq/s3c24xx-cpufreq.c  |   1 +
 include/dt-bindings/clock/s3c2410.h|  62 +++
 40 files changed, 1277 insertions(+), 1178 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
 delete mode 100644 arch/arm/mach-s3c24xx/clock-dclk.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2410.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2440.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c244x.c
 create mode 100644 drivers/clk/samsung/clk-s3c2410-dclk.c
 create mode 100644 drivers/clk/samsung/clk-s3c2410.c
 create mode 100644 include/dt-bindings/clock/s3c2410.h

-- 
1.9.0


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[PATCH v3 1/9] ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccf

2014-05-11 Thread Heiko Stübner
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table into the MPLLCON
register.

Change this to use a regular clk_set_rate call when using the common
clock framework and only write the raw value in the samsung_clock case.

The s3c cpufreq driver does already aquire the mpll, so simply add a reference
to struct s3c_cpufreq_config to let set_fvco access it.

While struct clk is opaque the differenciation between samsung clock and
common clock is kept, as the samsung-clock mpll clk does not implement a
real set_rate.

Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/cpufreq-utils.c  | 8 
 arch/arm/plat-samsung/include/plat/cpu-freq-core.h | 1 +
 drivers/cpufreq/s3c24xx-cpufreq.c  | 1 +
 3 files changed, 10 insertions(+)

diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c 
b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 2a0aa56..c1b7508 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -14,6 +14,7 @@
 #include linux/errno.h
 #include linux/cpufreq.h
 #include linux/io.h
+#include linux/clk.h
 
 #include mach/map.h
 #include mach/regs-clock.h
@@ -60,5 +61,12 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config 
*cfg)
  */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
+#ifdef CONFIG_SAMSUNG_CLOCK
__raw_writel(cfg-pll.driver_data, S3C2410_MPLLCON);
+#endif
+
+#ifdef CONFIG_COMMON_CLK
+   if (!IS_ERR(cfg-mpll))
+   clk_set_rate(cfg-mpll, cfg-pll.frequency);
+#endif
 }
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h 
b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 7231c8e..72d4178 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -119,6 +119,7 @@ struct s3c_plltab {
 struct s3c_cpufreq_config {
struct s3c_freq freq;
struct s3c_freq max;
+   struct clk  *mpll;
struct cpufreq_frequency_table pll;
struct s3c_clkdivs  divs;
struct s3c_cpufreq_info *info;  /* for core, not drivers */
diff --git a/drivers/cpufreq/s3c24xx-cpufreq.c 
b/drivers/cpufreq/s3c24xx-cpufreq.c
index be1b2b5..227ebf7 100644
--- a/drivers/cpufreq/s3c24xx-cpufreq.c
+++ b/drivers/cpufreq/s3c24xx-cpufreq.c
@@ -141,6 +141,7 @@ static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config 
*cfg)
 
 static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
 {
+   cfg-mpll = _clk_mpll;
(cfg-info-set_fvco)(cfg);
 }
 
-- 
1.9.0


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[PATCH v3 2/9] clk: samsung: add clock driver for external clock outputs

2014-05-11 Thread Heiko Stübner
This adds a driver for controlling the external clock outputs of
s3c24xx architectures including the dclk muxes and dividers.

The driver at the moment only supports the legacy non-dt boards using these
clock outputs. The clock-output control itself is part of the system-controller
mainly controlled by the pinctrl drivers. So it should most likely be
integrated there for dt platforms.

Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Mike Turquette mturque...@linaro.org
Acked-by: Tomasz Figa t.f...@samsung.com
---
 drivers/clk/samsung/Makefile   |   1 +
 drivers/clk/samsung/clk-s3c2410-dclk.c | 440 +
 2 files changed, 441 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-s3c2410-dclk.c

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 56e7d38..28ba4eb 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_EXYNOS5260)+= clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5420)   += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)  += clk-exynos-audss.o
+obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
 obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c 
b/drivers/clk/samsung/clk-s3c2410-dclk.c
new file mode 100644
index 000..8d8dff0
--- /dev/null
+++ b/drivers/clk/samsung/clk-s3c2410-dclk.c
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner he...@sntech.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for s3c24xx external clock output.
+ */
+
+#include linux/platform_device.h
+#include linux/module.h
+#include clk.h
+
+/* legacy access to misccr, until dt conversion is finished */
+#include mach/hardware.h
+#include mach/regs-gpio.h
+
+#define MUX_DCLK0  0
+#define MUX_DCLK1  1
+#define DIV_DCLK0  2
+#define DIV_DCLK1  3
+#define GATE_DCLK0 4
+#define GATE_DCLK1 5
+#define MUX_CLKOUT06
+#define MUX_CLKOUT17
+#define DCLK_MAX_CLKS  (MUX_CLKOUT1 + 1)
+
+enum supported_socs {
+   S3C2410,
+   S3C2412,
+   S3C2440,
+   S3C2443,
+};
+
+struct s3c24xx_dclk_drv_data {
+   const char **clkout0_parent_names;
+   int clkout0_num_parents;
+   const char **clkout1_parent_names;
+   int clkout1_num_parents;
+   const char **mux_parent_names;
+   int mux_num_parents;
+};
+
+/*
+ * Clock for output-parent selection in misccr
+ */
+
+struct s3c24xx_clkout {
+   struct clk_hw   hw;
+   u32 mask;
+   u8  shift;
+};
+
+#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
+
+static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
+{
+   struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
+   int num_parents = __clk_get_num_parents(hw-clk);
+   u32 val;
+
+   val = readl_relaxed(S3C24XX_MISCCR)  clkout-shift;
+   val = clkout-shift;
+   val = clkout-mask;
+
+   if (val = num_parents)
+   return -EINVAL;
+
+   return val;
+}
+
+static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
+   int ret = 0;
+
+   s3c2410_modify_misccr((clkout-mask  clkout-shift),
+ (index  clkout-shift));
+
+   return ret;
+}
+
+const struct clk_ops s3c24xx_clkout_ops = {
+   .get_parent = s3c24xx_clkout_get_parent,
+   .set_parent = s3c24xx_clkout_set_parent,
+   .determine_rate = __clk_mux_determine_rate,
+};
+
+struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
+   const char **parent_names, u8 num_parents,
+   u8 shift, u32 mask)
+{
+   struct s3c24xx_clkout *clkout;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the clkout */
+   clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
+   if (!clkout)
+   return ERR_PTR(-ENOMEM);
+
+   init.name = name;
+   init.ops = s3c24xx_clkout_ops;
+   init.flags = CLK_IS_BASIC;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   clkout-shift = shift;
+   clkout-mask = mask;
+   clkout-hw.init = init;
+
+   clk = clk_register(dev, clkout-hw);
+
+   return clk;
+}
+
+/*
+ * dclk and clkout init
+ */
+
+struct s3c24xx_dclk {
+   struct device *dev;
+   void __iomem *base;
+   struct clk_onecell_data clk_data;
+   struct notifier_block dclk0_div_change_nb;
+   struct notifier_block dclk1_div_change_nb;
+   spinlock_t dclk_lock;
+   unsigned long reg_save;
+};
+
+#define 

[PATCH v3 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-05-11 Thread Heiko Stübner
Add platform device and select the correct implementation automatically
depending on wether the old samsung_clock or the common clock framework
is enabled.

This is only done for machines already using the old dclk implementation,
as everybody else should move to use dt anyway.

The machine-specific settings for the external clocks will have to be set
by somebody with knowledge about the specific hardware.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   | 22 +-
 arch/arm/mach-s3c24xx/common.c  | 14 ++
 arch/arm/mach-s3c24xx/common.h  |  2 ++
 arch/arm/mach-s3c24xx/mach-anubis.c |  5 +
 arch/arm/mach-s3c24xx/mach-bast.c   |  5 +
 arch/arm/mach-s3c24xx/mach-osiris.c |  5 +
 arch/arm/mach-s3c24xx/mach-rx1950.c |  5 +
 arch/arm/mach-s3c24xx/mach-vr1000.c |  5 +
 arch/arm/mach-s3c24xx/s3c244x.c |  2 ++
 9 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index fbafb9a..b4c055b 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,13 @@ config PLAT_S3C24XX
help
  Base platform code for any Samsung S3C24XX device
 
+config S3C2410_COMMON_DCLK
+   bool
+   select REGMAP_MMIO
+   help
+ Temporary symbol to build the dclk driver based on the common clock
+ framework.
+
 menu SAMSUNG S3C24XX SoCs Support
 
 comment S3C24XX SoCs
@@ -264,7 +271,8 @@ config ARCH_BAST
select ISA
select MACH_BAST_IDE
select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
select S3C24XX_SIMTEC_USB
@@ -345,7 +353,8 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
bool Thorcom VR1000
select MACH_BAST_IDE
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
select S3C24XX_SIMTEC_USB
@@ -530,7 +539,8 @@ config MACH_ANUBIS
bool Simtec Electronics ANUBIS
select HAVE_PATA_PLATFORM
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_USB_HOST
help
@@ -570,7 +580,8 @@ config MACH_OSIRIS
bool Simtec IM2440D20 (OSIRIS) module
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_NAND
select S3C_DEV_USB_HOST
@@ -641,7 +652,8 @@ config MACH_RX1950
select PM_H1940 if PM
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_16934400
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_PWM
select S3C_DEV_NAND
help
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index ad5b76b..7cc6d94 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -553,3 +553,17 @@ void __init s3c2443_init_clocks(int xtal)
s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 }
 #endif
+
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
+   defined(CONFIG_CPU_S3C2442)
+static struct resource s3c2410_dclk_resource[] = {
+   [0] = DEFINE_RES_MEM(0x5684, 0x4),
+};
+
+struct platform_device s3c2410_device_dclk = {
+   .name   = s3c2410-dclk,
+   .id = 0,
+   .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
+   .resource   = s3c2410_dclk_resource,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 3fade6d..50504c7 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -114,6 +114,8 @@ extern struct platform_device s3c2412_device_dma;
 extern struct platform_device s3c2440_device_dma;
 extern struct platform_device s3c2443_device_dma;
 
+extern struct platform_device s3c2410_device_dclk;
+
 #ifdef CONFIG_S3C2412_COMMON_CLK
 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long 
xti_f,
unsigned long ext_f, void __iomem *reg_base);
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c 
b/arch/arm/mach-s3c24xx/mach-anubis.c
index 81a270a..f81944f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -352,6 +352,7 @@ static struct platform_device 

[PATCH v3 4/9] dt-bindings: add documentation for s3c2410 clock controller

2014-05-11 Thread Heiko Stübner
Describe the clock controller of s3c2410, s3c2440 and s3c2442.

Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Tomasz Figa t.f...@samsung.com
---
 .../bindings/clock/samsung,s3c2410-clock.txt   | 50 ++
 1 file changed, 50 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt 
b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
new file mode 100644
index 000..822505e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
@@ -0,0 +1,50 @@
+* Samsung S3C2410 Clock Controller
+
+The S3C2410 clock controller generates and supplies clock to various 
controllers
+within the SoC. The clock binding described here is applicable to the s3c2410,
+s3c2440 and s3c2442 SoCs in the s3c24x family.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - samsung,s3c2410-clock - controller compatible with S3C2410 SoC.
+  - samsung,s3c2440-clock - controller compatible with S3C2440 SoC.
+  - samsung,s3c2442-clock - controller compatible with S3C2442 SoC.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Some of the clocks are available only
+on a particular SoC.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/s3c2410.h header and can be used in device
+tree sources.
+
+External clocks:
+
+The xti clock used as input for the plls is generated outside the SoC. It is
+expected that is are defined using standard clock bindings with a
+clock-output-names value of xti.
+
+Example: Clock controller node:
+
+   clocks: clock-controller@4c00 {
+   compatible = samsung,s3c2410-clock;
+   reg = 0x4c00 0x20;
+   #clock-cells = 1;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller (refer to the standard clock bindings for information about
+  clocks and clock-names properties):
+
+   serial@50004000 {
+   compatible = samsung,s3c2440-uart;
+   reg = 0x50004000 0x4000;
+   interrupts = 1 23 3 4, 1 23 4 4;
+   clock-names = uart, clk_uart_baud2;
+   clocks = clocks PCLK_UART0, clocks PCLK_UART0;
+   status = disabled;
+   };
-- 
1.9.0


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[PATCH v3 5/9] clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442

2014-05-11 Thread Heiko Stübner
This driver can handle the clock controllers of the socs mentioned above,
as they share a common clock tree with only small differences.

The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure.

As pll-rate-tables only the 12mhz variants are currently included.
The original code was wrongly checking for 169mhz xti values [a 0 to much
at the end], so the original 16mhz pll table would have never been
included and its values are so obscure that I have no possibility to
at least check their sane-ness. When using the formula from the manual
the resulting frequency is near the table value but still slightly off.

Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Mike Turquette mturque...@linaro.org
Acked-by: Tomasz Figa t.f...@samsung.com
---
 drivers/clk/samsung/Makefile|   1 +
 drivers/clk/samsung/clk-s3c2410.c   | 482 
 include/dt-bindings/clock/s3c2410.h |  62 +
 3 files changed, 545 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-s3c2410.c
 create mode 100644 include/dt-bindings/clock/s3c2410.h

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 28ba4eb..9160494 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_EXYNOS5260)+= clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5420)   += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)  += clk-exynos-audss.o
+obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
diff --git a/drivers/clk/samsung/clk-s3c2410.c 
b/drivers/clk/samsung/clk-s3c2410.c
new file mode 100644
index 000..ba07168
--- /dev/null
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner he...@sntech.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for S3C2410 and following SoCs.
+ */
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clock/s3c2410.h
+
+#include clk.h
+#include clk-pll.h
+
+#define LOCKTIME   0x00
+#define MPLLCON0x04
+#define UPLLCON0x08
+#define CLKCON 0x0c
+#define CLKSLOW0x10
+#define CLKDIVN0x14
+#define CAMDIVN0x18
+
+/* the soc types */
+enum supported_socs {
+   S3C2410,
+   S3C2440,
+   S3C2442,
+};
+
+/* list of PLLs to be registered */
+enum s3c2410_plls {
+   mpll, upll,
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s3c2410_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long s3c2410_clk_regs[] __initdata = {
+   LOCKTIME,
+   MPLLCON,
+   UPLLCON,
+   CLKCON,
+   CLKSLOW,
+   CLKDIVN,
+   CAMDIVN,
+};
+
+static int s3c2410_clk_suspend(void)
+{
+   samsung_clk_save(reg_base, s3c2410_save,
+   ARRAY_SIZE(s3c2410_clk_regs));
+
+   return 0;
+}
+
+static void s3c2410_clk_resume(void)
+{
+   samsung_clk_restore(reg_base, s3c2410_save,
+   ARRAY_SIZE(s3c2410_clk_regs));
+}
+
+static struct syscore_ops s3c2410_clk_syscore_ops = {
+   .suspend = s3c2410_clk_suspend,
+   .resume = s3c2410_clk_resume,
+};
+
+static void s3c2410_clk_sleep_init(void)
+{
+   s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
+   ARRAY_SIZE(s3c2410_clk_regs));
+   if (!s3c2410_save) {
+   pr_warn(%s: failed to allocate sleep save data, no sleep 
support!\n,
+   __func__);
+   return;
+   }
+
+   register_syscore_ops(s3c2410_clk_syscore_ops);
+   return;
+}
+#else
+static void s3c2410_clk_sleep_init(void) {}
+#endif
+
+PNAME(fclk_p) = { mpll, div_slow };
+
+struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
+   MUX(FCLK, fclk, fclk_p, CLKSLOW, 4, 1),
+};
+
+static struct clk_div_table divslow_d[] = {
+   { .val = 0, .div = 1 },
+   { .val = 1, .div = 2 },
+   { .val = 2, .div = 4 },
+   { .val = 3, .div = 6 },
+   { .val = 4, .div = 8 },
+   { .val = 5, .div = 10 },
+   { .val = 6, .div = 12 },
+   { .val = 7, .div = 14 },
+   { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
+   DIV_T(0, div_slow, xti, CLKSLOW, 0, 3, divslow_d),
+   DIV(PCLK, 

[PATCH v3 6/9] ARM: S3C24XX: add platform code for conversion to the common clock framework

2014-05-11 Thread Heiko Stübner
This adds the necessary init functions to init the clocks from the common
clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy
clock code.

This also includes empty stubs for the *_setup_clocks functions that are
called from the cpufreq driver on resume.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   |  5 +
 arch/arm/mach-s3c24xx/common.c  | 25 +
 arch/arm/mach-s3c24xx/common.h  |  7 +++
 arch/arm/mach-s3c24xx/s3c2410.c |  6 ++
 arch/arm/mach-s3c24xx/s3c2442.c |  3 ++-
 arch/arm/mach-s3c24xx/s3c244x.c |  6 ++
 6 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index b4c055b..5c9cffd 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,11 @@ config PLAT_S3C24XX
help
  Base platform code for any Samsung S3C24XX device
 
+config S3C2410_COMMON_CLK
+   bool
+   help
+ Build the s3c2410 clock driver based on the common clock framework.
+
 config S3C2410_COMMON_DCLK
bool
select REGMAP_MMIO
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 7cc6d94..35cf88e 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -53,6 +53,7 @@
 #include plat/cpu-freq.h
 #include plat/pll.h
 #include plat/pwm-core.h
+#include plat/watchdog-reset.h
 
 #include common.h
 
@@ -533,6 +534,14 @@ struct platform_device s3c2443_device_dma = {
 };
 #endif
 
+#if defined(CONFIG_COMMON_CLK)  defined(CONFIG_CPU_S3C2410)
+void __init s3c2410_init_clocks(int xtal)
+{
+   s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
 #ifdef CONFIG_CPU_S3C2412
 void __init s3c2412_init_clocks(int xtal)
 {
@@ -547,6 +556,22 @@ void __init s3c2416_init_clocks(int xtal)
 }
 #endif
 
+#if defined(CONFIG_COMMON_CLK)  defined(CONFIG_CPU_S3C2440)
+void __init s3c2440_init_clocks(int xtal)
+{
+   s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
+#if defined(CONFIG_COMMON_CLK)  defined(CONFIG_CPU_S3C2442)
+void __init s3c2442_init_clocks(int xtal)
+{
+   s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
+   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
 #ifdef CONFIG_CPU_S3C2443
 void __init s3c2443_init_clocks(int xtal)
 {
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 50504c7..2d65541 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -77,6 +77,7 @@ extern void s3c244x_restart(enum reboot_mode mode, const char 
*cmd);
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
 extern void s3c2440_map_io(void);
+extern void s3c2440_init_clocks(int xtal);
 extern void s3c2440_init_irq(void);
 #else
 #define s3c2440_init NULL
@@ -86,6 +87,7 @@ extern void s3c2440_init_irq(void);
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
 extern void s3c2442_map_io(void);
+extern void s3c2442_init_clocks(int xtal);
 extern void s3c2442_init_irq(void);
 #else
 #define s3c2442_init NULL
@@ -116,6 +118,11 @@ extern struct platform_device s3c2443_device_dma;
 
 extern struct platform_device s3c2410_device_dclk;
 
+#ifdef CONFIG_S3C2410_COMMON_CLK
+void __init s3c2410_common_clk_init(struct device_node *np, unsigned long 
xti_f,
+   int current_soc,
+   void __iomem *reg_base);
+#endif
 #ifdef CONFIG_S3C2412_COMMON_CLK
 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long 
xti_f,
unsigned long ext_f, void __iomem *reg_base);
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 04b58cb..5280173 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -83,6 +83,7 @@ void __init s3c2410_map_io(void)
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 void __init_or_cpufreq s3c2410_setup_clocks(void)
 {
struct clk *xtal_clk;
@@ -142,6 +143,11 @@ void __init s3c2410_init_clocks(int xtal)
clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
+#else
+void __init_or_cpufreq s3c2410_setup_clocks(void)
+{
+}
+#endif
 
 struct bus_type s3c2410_subsys = {
.name = s3c2410-core,
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 2c8adc0..564c6503 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -53,6 +53,7 @@
 
 #include common.h
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 /* S3C2442 extended clock support */
 
 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
@@ -162,7 +163,7 @@ 

[PATCH v3 7/9] ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework

2014-05-11 Thread Heiko Stübner
Convert all machines using these cpus to use the ccf clock driver
instead of the legacy Samsung clock implementation.

Some of the more esotheric machines will probably need a fixup, as they
do strange things to the clkout outputs, that I did not really understand
nor have the hardware to check.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig  |  8 
 arch/arm/mach-s3c24xx/Makefile |  4 ++--
 arch/arm/mach-s3c24xx/common.c |  4 
 arch/arm/mach-s3c24xx/mach-anubis.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-at2440evb.c | 10 +++---
 arch/arm/mach-s3c24xx/mach-gta02.c |  8 ++--
 arch/arm/mach-s3c24xx/mach-mini2440.c  | 10 +++---
 arch/arm/mach-s3c24xx/mach-nexcoder.c  | 15 ---
 arch/arm/mach-s3c24xx/mach-osiris.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-rx1950.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-rx3715.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-smdk2440.c  | 10 +++---
 12 files changed, 73 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 5c9cffd..ddd6574 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -73,10 +73,10 @@ config CPU_S3C2416
 
 config CPU_S3C2440
bool SAMSUNG S3C2440
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_PM if PM
select S3C2440_DMA if S3C24XX_DMA
help
@@ -84,10 +84,10 @@ config CPU_S3C2440
 
 config CPU_S3C2442
bool SAMSUNG S3C2442
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select S3C2410_PM if PM
help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index f254797..9010eba 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -29,9 +29,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP)+= sleep-s3c2412.o
 obj-$(CONFIG_CPU_S3C2416)  += s3c2416.o
 obj-$(CONFIG_S3C2416_PM)   += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)  += s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)  += s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)  += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)  += s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)  += s3c244x.o
 obj-$(CONFIG_S3C2440_DMA)  += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_1200) += pll-s3c2440-1200.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 35cf88e..bda9dd4 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -92,7 +92,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x3244,
.idmask = 0x,
.map_io = s3c2440_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2440_init,
.name   = name_s3c2440
@@ -101,7 +100,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32440001,
.idmask = 0x,
.map_io = s3c2440_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2440_init,
.name   = name_s3c2440a
@@ -110,7 +108,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32440aaa,
.idmask = 0x,
.map_io = s3c2442_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2442_init,
.name   = name_s3c2442
@@ -119,7 +116,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32440aab,
.idmask = 0x,
.map_io = s3c2442_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2442_init,
.name   = name_s3c2442b
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c 
b/arch/arm/mach-s3c24xx/mach-anubis.c
index f81944f..7a0d83b 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -46,7 +46,6 @@
 
 #include net/ax88796.h
 
-#include plat/clock.h
 #include plat/devs.h
 #include plat/cpu.h
 #include linux/platform_data/asoc-s3c24xx_simtec.h
@@ 

[PATCH v3 8/9] ARM: S3C24XX: convert s3c2410 to common clock framework

2014-05-11 Thread Heiko Stübner
Convert the machines using the s3c2410 to use the new driver based
on the common clock framework instead of the legacy Samsung clock driver.

As with the s3c244x, machines using the clkout output will need a fixup
from someone with the hardware.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   |  4 ++--
 arch/arm/mach-s3c24xx/common.c  |  2 --
 arch/arm/mach-s3c24xx/mach-amlm5900.c   |  9 +++--
 arch/arm/mach-s3c24xx/mach-bast.c   | 10 +++---
 arch/arm/mach-s3c24xx/mach-h1940.c  | 10 +++---
 arch/arm/mach-s3c24xx/mach-n30.c| 12 
 arch/arm/mach-s3c24xx/mach-nexcoder.c   |  7 +--
 arch/arm/mach-s3c24xx/mach-otom.c   | 10 +++---
 arch/arm/mach-s3c24xx/mach-qt2410.c |  9 +++--
 arch/arm/mach-s3c24xx/mach-smdk2410.c   |  9 +++--
 arch/arm/mach-s3c24xx/mach-tct_hammer.c |  9 +++--
 arch/arm/mach-s3c24xx/mach-vr1000.c | 10 +++---
 12 files changed, 67 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index ddd6574..82602dc 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -37,10 +37,10 @@ comment S3C24XX SoCs
 config CPU_S3C2410
bool SAMSUNG S3C2410
default y
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2410
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
select S3C2410_PM if PM
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index bda9dd4..600a1be 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -74,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x3241,
.idmask = 0x,
.map_io = s3c2410_map_io,
-   .init_clocks= s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init   = s3c2410_init,
.name   = name_s3c2410
@@ -83,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32410002,
.idmask = 0x,
.map_io = s3c2410_map_io,
-   .init_clocks= s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init   = s3c2410a_init,
.name   = name_s3c2410a
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c 
b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 8ac9554..5157e25 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -161,11 +161,16 @@ static struct platform_device *amlm5900_devices[] 
__initdata = {
 static void __init amlm5900_map_io(void)
 {
s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
-   s3c24xx_init_clocks(0);
s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init amlm5900_init_time(void)
+{
+   s3c2410_init_clocks(1200);
+   samsung_timer_init();
+}
+
 #ifdef CONFIG_FB_S3C2410
 static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
.width  = 160,
@@ -241,6 +246,6 @@ MACHINE_START(AML_M5900, AML_M5900)
.map_io = amlm5900_map_io,
.init_irq   = s3c2410_init_irq,
.init_machine   = amlm5900_init,
-   .init_time  = samsung_timer_init,
+   .init_time  = amlm5900_init_time,
.restart= s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c 
b/arch/arm/mach-s3c24xx/mach-bast.c
index dcdc4a5..ea762f2 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -51,7 +51,6 @@
 #include mach/regs-lcd.h
 #include mach/gpio-samsung.h
 
-#include plat/clock.h
 #include plat/cpu.h
 #include plat/cpu-freq.h
 #include plat/devs.h
@@ -581,11 +580,16 @@ static void __init bast_map_io(void)
s3c_hwmon_set_platdata(bast_hwmon_info);
 
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
-   s3c24xx_init_clocks(0);
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init bast_init_time(void)
+{
+   s3c2410_init_clocks(1200);
+   samsung_timer_init();
+}
+
 static void __init bast_init(void)
 {
register_syscore_ops(bast_pm_syscore_ops);
@@ -613,6 +617,6 @@ MACHINE_START(BAST, Simtec-BAST)
.map_io = bast_map_io,
.init_irq   = s3c2410_init_irq,
.init_machine   = bast_init,
-   .init_time  = samsung_timer_init,
+   .init_time  = 

[PATCH v3 9/9] ARM: S3C24XX: remove legacy clock code

2014-05-11 Thread Heiko Stübner
With the move to the common clock framework completed for s3c2410, s3c2440
and s3c2442, the legacy clock code for these machines can go away too.

This also includes the legacy dclk code, as all legacy users are converted.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   |  11 -
 arch/arm/mach-s3c24xx/Makefile  |   2 -
 arch/arm/mach-s3c24xx/clock-dclk.c  | 195 
 arch/arm/mach-s3c24xx/clock-s3c2410.c   | 284 
 arch/arm/mach-s3c24xx/clock-s3c2440.c   | 217 --
 arch/arm/mach-s3c24xx/clock-s3c244x.c   | 141 
 arch/arm/mach-s3c24xx/common.h  |   2 -
 arch/arm/mach-s3c24xx/include/mach/regs-clock.h |  18 --
 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h  |   3 -
 arch/arm/mach-s3c24xx/pm.c  |  12 -
 arch/arm/mach-s3c24xx/s3c2410.c |  62 --
 arch/arm/mach-s3c24xx/s3c2442.c | 112 --
 arch/arm/mach-s3c24xx/s3c244x.c |  63 --
 13 files changed, 1122 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/clock-dclk.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2410.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2440.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c244x.c

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 82602dc..93dc265 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -110,17 +110,6 @@ config CPU_S3C2443
 
 # common code
 
-config S3C2410_CLOCK
-   bool
-   help
- Clock code for the S3C2410, and similar processors which
- is currently includes the S3C2410, S3C2440, S3C2442.
-
-config S3C24XX_DCLK
-   bool
-   help
- Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
-
 config S3C24XX_SMDK
bool
help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 9010eba..2235d0d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -44,10 +44,8 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
 
 # common code
 
-obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
 obj-$(CONFIG_S3C24XX_DMA)  += dma.o
 
-obj-$(CONFIG_S3C2410_CLOCK)+= clock-s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
 
 obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c 
b/arch/arm/mach-s3c24xx/clock-dclk.c
deleted file mode 100644
index 1edd9b2..000
--- a/arch/arm/mach-s3c24xx/clock-dclk.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Simtec Electronics
- * Ben Dooks b...@simtec.co.uk
- * http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX - definitions for DCLK and CLKOUT registers
- */
-
-#include linux/kernel.h
-#include linux/errno.h
-#include linux/clk.h
-#include linux/io.h
-
-#include mach/regs-clock.h
-#include mach/regs-gpio.h
-
-#include plat/clock.h
-#include plat/cpu.h
-
-/* clocks that could be registered by external code */
-
-static int s3c24xx_dclk_enable(struct clk *clk, int enable)
-{
-   unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-   if (enable)
-   dclkcon |= clk-ctrlbit;
-   else
-   dclkcon = ~clk-ctrlbit;
-
-   __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-   return 0;
-}
-
-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
-{
-   unsigned long dclkcon;
-   unsigned int uclk;
-
-   if (parent == clk_upll)
-   uclk = 1;
-   else if (parent == clk_p)
-   uclk = 0;
-   else
-   return -EINVAL;
-
-   clk-parent = parent;
-
-   dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-   if (clk-ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
-   if (uclk)
-   dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
-   else
-   dclkcon = ~S3C2410_DCLKCON_DCLK0_UCLK;
-   } else {
-   if (uclk)
-   dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
-   else
-   dclkcon = ~S3C2410_DCLKCON_DCLK1_UCLK;
-   }
-
-   __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-   return 0;
-}
-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
-{
-   unsigned long div;
-
-   if ((rate == 0) || !clk-parent)
-   return 0;
-
-   div = clk_get_rate(clk-parent) / rate;
-   if (div  2)
-   div = 2;
-   else if (div  16)
-   div = 16;
-
-   return div;
-}
-
-static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
-   unsigned 

Re: [PATCH v2.1 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-05-09 Thread Heiko Stübner
Am Freitag, 9. Mai 2014, 18:49:41 schrieb Paul Bolle:
  @@ -643,7 +654,8 @@ config MACH_RX1950
  
  select PM_H1940 if PM
  select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
  select S3C2440_XTAL_16934400
  
  -   select S3C24XX_DCLK
  +   select S3C24XX_DCLK if SAMSUNG_CLOCK
  +   select S3C24XX_COMMON_DCLK if COMMON_CLK
 
 This looks like a typo. Did you mean S3C2410_COMMON_DCLK?

yep that is a typo, S3C2410_COMMON_DCLK is the correct one.

Heiko
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Re: [PATCH v2.1 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-05-09 Thread Heiko Stübner
Am Freitag, 9. Mai 2014, 19:53:21 schrieb Tomasz Figa:
 On 09.05.2014 18:49, Paul Bolle wrote:
  On Wed, 2014-04-23 at 22:09 +0200, Heiko Stübner wrote:
  Add platform device and select the correct implementation automatically
  depending on wether the old samsung_clock or the common clock framework
  is enabled.
  
  This is only done for machines already using the old dclk implementation,
  as everybody else should move to use dt anyway.
  
  The machine-specific settings for the external clocks will have to be set
  by somebody with knowledge about the specific hardware.
  
  Signed-off-by: Heiko Stuebner he...@sntech.de
  Reviewed-by: Tomasz Figa t.f...@samsung.com
  
  It seems this one just hit linux-next (in next-20140509).
 
 Which is bad, because:
 a) it conflicts with patches already applied in samsung-clk tree,

I remember seeing patches regarding more than one clk-samsung clock providers.
Do you need any additional changes for s3c24xx from me for this?


 b) the DT binding added by patch 4/9 has not been acked .

I'm not 100% sure if this is necessary, as the binding is similar to most 
other Samsung bindings and looking through recent clock binding changes I 
didn't find any that seemed to have a special dt-maintainer ack - including 
Exynos ones. Also if I remember correctly there was this if we don't respond, 
carry on policy around :-) .


Heiko

 Kukjin, might I ask you to drop this series from your tree and let me
 send you a pull request with necessary dependencies and this series
 applied properly to resolve merge conflicts, as I suggested before in
 one of my replies to this thread?
 
 Best regards,
 Tomasz

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Re: [PATCH v2.1 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-05-09 Thread Heiko Stübner
Hi Tomasz,

Am Samstag, 10. Mai 2014, 01:11:45 schrieb Tomasz Figa:
 On 10.05.2014 01:07, Heiko Stübner wrote:
  Am Freitag, 9. Mai 2014, 19:53:21 schrieb Tomasz Figa:
  On 09.05.2014 18:49, Paul Bolle wrote:
  On Wed, 2014-04-23 at 22:09 +0200, Heiko Stübner wrote:
  Add platform device and select the correct implementation automatically
  depending on wether the old samsung_clock or the common clock framework
  is enabled.
  
  This is only done for machines already using the old dclk
  implementation,
  as everybody else should move to use dt anyway.
  
  The machine-specific settings for the external clocks will have to be
  set
  by somebody with knowledge about the specific hardware.
  
  Signed-off-by: Heiko Stuebner he...@sntech.de
  Reviewed-by: Tomasz Figa t.f...@samsung.com
  
  It seems this one just hit linux-next (in next-20140509).
  
  Which is bad, because:
  a) it conflicts with patches already applied in samsung-clk tree,
  
  I remember seeing patches regarding more than one clk-samsung clock
  providers. Do you need any additional changes for s3c24xx from me for
  this?
 
 Yes, that's the problem here. If you could do it, I would appreciate it,
 but if you don't have time then I can handle this. The changes needed
 are mostly trivial - basically every common samsung_clk function gets
 new argument to a context structure. The branch to base on would be
 for_3.16/exynos5260 in samsung-clk tree.
 
  b) the DT binding added by patch 4/9 has not been acked .
  
  I'm not 100% sure if this is necessary, as the binding is similar to most
  other Samsung bindings and looking through recent clock binding changes I
  didn't find any that seemed to have a special dt-maintainer ack -
  including
  Exynos ones. Also if I remember correctly there was this if we don't
  respond, carry on policy around :-) .
 
 Well, for me this could go as is, but rules should be followed and the
 rules are ACK or 3 weeks and a ping without response. So we need to wait
 at least to next Wednesday to bypass DT review.

so I only remembered the abbreviated version of this :-) [without the 3 weeks 
requirement]. My guess is I should be able to adapt it to this change and also 
fix the typo Paul found until then.


Heiko
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Re: [PATCH v2 0/4] ARM: S3C24XX: cleanup debug macro/earlyprintk

2014-05-06 Thread Heiko Stübner
Am Dienstag, 6. Mai 2014, 13:16:14 schrieb Kukjin Kim:
 Heiko Stübner wrote:
  This series tries to simplify the s3c24xx debug macro, removing
  dependencies
  on mach/ includes, static mappings and finally moving it into
  include/debug.
 
 I think, it's good way :)
 
  The one slightly invasive change is the need for the developer to select
  the uart type by himself, which gets rid of the debug macro trying to
  determine the uart type itself.
  
  But as usage of the debug-uart is not the common case - especially in a
  multiplatform scenario - I didn't worry to much.
 
 Yeah, I also don't want s3c24xx to support multiplatform in near future.
 
  Based on 3.15-rc1 and tested on a S3C2442 Openmoko Freerunner (GTA02)
  
  changes since v1:
  - do not introduce a secondary choice option, instead implement the
  
s3c2410 debug uarts as separate options
  
  Heiko Stuebner (4):
ARM: compressed/head.S: remove s3c24xx special case
ARM: S3C24XX: trim down debug uart handling
ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
ARM: S3C24XX: move debug-macro.S into the common space
   
   arch/arm/Kconfig.debug   |  54 +++-
   arch/arm/boot/compressed/head.S  |   5 --
   arch/arm/include/debug/s3c24xx.S |  46 +++
   arch/arm/mach-s3c24xx/Kconfig|  28 ---
   arch/arm/mach-s3c24xx/include/mach/debug-macro.S | 101 --
  
  -
  
   5 files changed, 98 insertions(+), 136 deletions(-)
   create mode 100644 arch/arm/include/debug/s3c24xx.S
   delete mode 100644 arch/arm/mach-s3c24xx/include/mach/debug-macro.S
  
  --
  1.9.0
 
 Basically I'm OK on this series but need to get review from Russell?

Russell pointed out a bad decision on my part in v1, so I guess he is aware of 
this series :-) . I've also added a...@kernel.org now, so they can complain, if 
anything is done wrong [should've probably done that from the beginning].


Heiko
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Re: [PATCH 13/15] ASoC: SND_S3C_DMA_LEGACY needs S3C24XX_DMA

2014-05-02 Thread Heiko Stübner
Hi Arnd,

Am Freitag, 2. Mai 2014, 00:35:21 schrieb Arnd Bergmann:
 On Thursday 01 May 2014 12:11:25 Mark Brown wrote:
  On Tue, Apr 29, 2014 at 07:18:34PM +0800, Xia Kaixu wrote:
   From: Arnd Bergmann a...@arndb.de
   
   SND_S3C_DMA_LEGACY can only be set on S3C24xx, which does not
   (yet) support the dmaengine framework, so samsung_dma_get_ops()
  
   fails to link if S3C24XX_DMA is disabled:
  Why is the fix for this not to ensure that s3c24xx always enables the
  DMA controller - how likely is it that it would be sane to build a
  kernel without DMA after all?
 
 S3C24XX_DMA is only needed for ASoC and for s3cmci. The latter
 uses 'depends on S3C24XX_DMA'. arch/arm/configs/tct_hammer_defconfig
 is an example of a configuration that does not include DMA because
 it uses neither of the two drivers.
 
 On a related topic, I looked at the overall DMA situation for
 plat-samsung again now, and it looks much nicer now than it used to,
 with mach-s3c64xx fully migrated to dmaengine, so there might be an
 even better way to deal with this.
 
 From all I can tell, sound/soc/samsung is the only remaining user
 of the plat/dma.h interfaces, and there is only one other  driver
 using the s3c24xx_dma interface directly, drivers/mmc/host/s3cmci.c.
 
 How about the patch below?
 8---
 ASoC: s3c24xx: use legacy DMA interface directly
 
 The samsung platform code has a wrapper around the legacy s3c24xx
 DMA API as an alternative to the dmaengine API. This is only used
 by the legacy s3c24xx sound support, which is never used in combination
 with the dmaengine API.

Just to mention, we have a dmaengine driver for s3c24xx :-) . Correct 
platform-data is present for all s3c24xx socs (in mach-s3c24xx/common.c) .

Mark already removed support for the legacy API from the s3c64xx spi driver 
(used by s3c2416 and s3c2443), so I guess to way forward would be to simply 
convert asoc and s3cmci to dmaengine and get rid of it altogether.

I just never had hardware using the old mci driver or with any previously 
working sound and didn't trust my experience to be enough to be able to do 
such a conversion on the fly like you below in the opposite direction ;-)


Heiko

 
 We can simplify the ASoC code significantly, and thereby completely
 obsoleting arch/arm/plat-samsung/dma-ops.c,
 arch/arm/plat-samsung/s3c-dma-ops.c and
 arch/arm/plat-samsung/include/plat/dma-ops.h.
 
 This patch achieves this by open-coding the implementation of this
 wrapper, which ends up saving us more code than we have to add.
 s3c24xx does not support cyclic DMA, so anything referring to that
 gets deleted in the process.
 
 The plat-samsung dma wrapper code is now dead code and can be removed
 subsequently.
 
 Signed-off--by: Arnd Bergmann a...@arndb.de
 ---
 
  sound/soc/samsung/ac97.c | 10 ++
  sound/soc/samsung/dma.c  | 79
 +++- sound/soc/samsung/dma.h  |
  2 --
  3 files changed, 27 insertions(+), 64 deletions(-)
 
 diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
 index 76b072b..28fe097 100644
 --- a/sound/soc/samsung/ac97.c
 +++ b/sound/soc/samsung/ac97.c
 @@ -253,10 +253,7 @@ static int s3c_ac97_trigger(struct snd_pcm_substream
 *substream, int cmd,
 
   writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 
 - if (!dma_data-ops)
 - dma_data-ops = samsung_dma_get_ops();
 -
 - dma_data-ops-started(dma_data-channel);
 + s3c2410_dma_ctrl(dma_data-channel, S3C2410_DMAOP_STARTED);
 
   return 0;
  }
 @@ -287,10 +284,7 @@ static int s3c_ac97_mic_trigger(struct
 snd_pcm_substream *substream,
 
   writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 
 - if (!dma_data-ops)
 - dma_data-ops = samsung_dma_get_ops();
 -
 - dma_data-ops-started(dma_data-channel);
 + s3c2410_dma_ctrl(dma_data-channel, S3C2410_DMAOP_STARTED);
 
   return 0;
  }
 diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
 index dc09b71..3c6e2f2 100644
 --- a/sound/soc/samsung/dma.c
 +++ b/sound/soc/samsung/dma.c
 @@ -54,8 +54,6 @@ struct runtime_data {
   struct s3c_dma_params *params;
  };
 
 -static void audio_buffdone(void *data);
 -
  /* dma_enqueue
   *
   * place a dma buffer onto the queue for the dma system
 @@ -66,7 +64,6 @@ static void dma_enqueue(struct snd_pcm_substream
 *substream) struct runtime_data *prtd = substream-runtime-private_data;
   dma_addr_t pos = prtd-dma_pos;
   unsigned int limit;
 - struct samsung_dma_prep dma_info;
 
   pr_debug(Entered %s\n, __func__);
 
 @@ -75,33 +72,11 @@ static void dma_enqueue(struct snd_pcm_substream
 *substream) pr_debug(%s: loaded %d, limit %d\n,
   __func__, prtd-dma_loaded, limit);
 
 - dma_info.cap = (samsung_dma_has_circular() ? DMA_CYCLIC : DMA_SLAVE);
 - dma_info.direction =
 - (substream-stream == SNDRV_PCM_STREAM_PLAYBACK
 - ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
 - dma_info.fp = audio_buffdone;
 - 

Re: [PATCH 1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings

2014-05-01 Thread Heiko Stübner
Hi Sachin,

Am Donnerstag, 1. Mai 2014, 16:14:44 schrieb Sachin Kamat:
 Instead of hardcoding the SYSRAM details for each SoC,
 pass this information through device tree (DT) and make
 the code SoC agnostic. Generic SRAM bindings are used
 for achieving this.
 
 Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
 Cc: Heiko Stuebner he...@sntech.de
 Cc: Arnd Bergmann a...@arndb.de

very cool :-).

I've found one little thing I do not understand, which I describe below. 
Otherwise
Acked-by: Heiko Stuebner he...@sntech.de

 ---
 This patch is based on linux next (next-20140501) on top of
 my Kconfig consolidation patch
 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/28642
 
 Tested on 4210/4412 Origen, 5250/5420 Arndale and SMDK5420 boards.
 ---
  arch/arm/Kconfig|1 +
  arch/arm/boot/dts/exynos4210-universal_c210.dts |   17 ++
  arch/arm/boot/dts/exynos4210.dtsi   |   18 +++
  arch/arm/boot/dts/exynos4x12.dtsi   |   18 +++
  arch/arm/boot/dts/exynos5250.dtsi   |   18 +++
  arch/arm/boot/dts/exynos5420.dtsi   |   18 +++
  arch/arm/mach-exynos/common.h   |1 +
  arch/arm/mach-exynos/exynos.c   |   64
 --- arch/arm/mach-exynos/firmware.c |  
  5 +-
  arch/arm/mach-exynos/include/mach/map.h |7 ---
  arch/arm/mach-exynos/platsmp.c  |   39 +-
  11 files changed, 133 insertions(+), 73 deletions(-)
 
 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
 index a6d19b1a..f66ea9453df9 100644
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
 @@ -855,6 +855,7 @@ config ARCH_EXYNOS
   select S5P_DEV_MFC
   select SAMSUNG_DMADEV
   select SPARSE_IRQ
 + select SRAM
   select USE_OF
   help
 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
 b/arch/arm/boot/dts/exynos4210-universal_c210.dts index
 63e34b24b04f..8d4de5c0d0c7 100644
 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
 +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
 @@ -28,6 +28,23 @@
   bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw 
 rootwait
 earlyprintk panic=5 maxcpus=1; };
 
 + sram@0202 {
 + status = disabled;
 + };
 +
 + sram@02025000 {
 + compatible = mmio-sram;
 + reg = 0x02025000 0x1000;
 + #address-cells = 1;
 + #size-cells = 1;
 + ranges = 0 0x02025000 0x1000;
 +
 + smp-sram@0 {
 + compatible = samsung,exynos4210-sram;
 + reg = 0x0 0x1000;
 + };
 + };

exynos_smp_prepare_sram returns -ENODEV if it can't find
samsung,exynos4210-sram-ns, so are you sure your universal_c210 will run 
without it? I didn't dig to deep into this, so it can also simply be something 
I overlooked :-)


Heiko

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Re: [PATCH 1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings

2014-05-01 Thread Heiko Stübner
Am Donnerstag, 1. Mai 2014, 15:32:14 schrieb Arnd Bergmann:
 On Thursday 01 May 2014 16:14:44 Sachin Kamat wrote:
  Instead of hardcoding the SYSRAM details for each SoC,
  pass this information through device tree (DT) and make
  the code SoC agnostic. Generic SRAM bindings are used
  for achieving this.
  
  Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
  Cc: Heiko Stuebner he...@sntech.de
  Cc: Arnd Bergmann a...@arndb.de
 
 Looks good to me. Both patches
 
 Acked-by: Arnd Bergmann a...@arndb.de
 
 Heiko, can you also have a look?

Already did :-)
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Re: [PATCH 00/16] Another 16 L2C patches

2014-04-28 Thread Heiko Stübner
Am Montag, 28. April 2014, 17:56:31 schrieb Russell King - ARM Linux:
 So, in response to Matt Porter's complaint about breaking prima2, here's
 another 16 patches which changes the way the L2 cache is initialised on
 many platforms.  This series moves towards a situation where the generic
 code initialises the L2 cache itself, with as little help as possible
 from board specific code.

Patches 2/16 (ARM: l2c: add platform independent core L2 cache
initialisation) and 3/16 (ARM: l2c:  convert rockchip to generic l2c 
initialisation) applied on a linux-next from 20140428,

Tested-by: Heiko Stuebner he...@sntech.de

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[PATCH] ARM: S3C24XX: remove SAMSUNG_CLOCK remnants after ccf conversion

2014-04-24 Thread Heiko Stübner
This finally removes all remaining SAMSUNG_CLOCK conditional code
from s3c24xx architectures.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
This is of course meant to go on top of the s3c2410 ccf conversion

 arch/arm/mach-s3c24xx/Kconfig |  5 -
 arch/arm/mach-s3c24xx/common.c| 17 -
 arch/arm/mach-s3c24xx/cpufreq-utils.c |  6 --
 arch/arm/mach-s3c24xx/mach-anubis.c   | 27 ---
 arch/arm/mach-s3c24xx/mach-bast.c | 27 ---
 arch/arm/mach-s3c24xx/mach-osiris.c   | 27 ---
 arch/arm/mach-s3c24xx/mach-rx1950.c   | 14 --
 arch/arm/mach-s3c24xx/mach-vr1000.c   | 27 ---
 arch/arm/mach-s3c24xx/pm.c| 12 
 9 files changed, 162 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 77b0fb5..4500802 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -265,7 +265,6 @@ config ARCH_BAST
select ISA
select MACH_BAST_IDE
select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
-   select S3C24XX_DCLK if SAMSUNG_CLOCK
select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
@@ -347,7 +346,6 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
bool Thorcom VR1000
select MACH_BAST_IDE
-   select S3C24XX_DCLK if SAMSUNG_CLOCK
select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
@@ -533,7 +531,6 @@ config MACH_ANUBIS
bool Simtec Electronics ANUBIS
select HAVE_PATA_PLATFORM
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK if SAMSUNG_CLOCK
select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_USB_HOST
@@ -574,7 +571,6 @@ config MACH_OSIRIS
bool Simtec IM2440D20 (OSIRIS) module
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK if SAMSUNG_CLOCK
select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_NAND
@@ -646,7 +642,6 @@ config MACH_RX1950
select PM_H1940 if PM
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_16934400
-   select S3C24XX_DCLK if SAMSUNG_CLOCK
select S3C24XX_COMMON_DCLK if COMMON_CLK
select S3C24XX_PWM
select S3C_DEV_NAND
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 600a1be..c0763b8 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -307,23 +307,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] 
__initdata = {
},
 };
 
-/* initialise all the clocks */
-
-#ifdef CONFIG_SAMSUNG_CLOCK
-void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
-  unsigned long hclk,
-  unsigned long pclk)
-{
-   clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
-   clk_xtal.rate);
-
-   clk_mpll.rate = fclk;
-   clk_h.rate = hclk;
-   clk_p.rate = pclk;
-   clk_f.rate = fclk;
-}
-#endif
-
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 static struct resource s3c2410_dma_resource[] = {
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c 
b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index c1b7508..d4d9514 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -61,12 +61,6 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config 
*cfg)
  */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
-#ifdef CONFIG_SAMSUNG_CLOCK
-   __raw_writel(cfg-pll.driver_data, S3C2410_MPLLCON);
-#endif
-
-#ifdef CONFIG_COMMON_CLK
if (!IS_ERR(cfg-mpll))
clk_set_rate(cfg-mpll, cfg-pll.frequency);
-#endif
 }
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c 
b/arch/arm/mach-s3c24xx/mach-anubis.c
index 7a0d83b..e053581 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -364,16 +364,6 @@ static struct platform_device *anubis_devices[] __initdata 
= {
anubis_device_sm501,
 };
 
-#ifdef CONFIG_SAMSUNG_CLOCK
-static struct clk *anubis_clocks[] __initdata = {
-   s3c24xx_dclk0,
-   s3c24xx_dclk1,
-   s3c24xx_clkout0,
-   s3c24xx_clkout1,
-   s3c24xx_uclk,
-};
-#endif
-
 /* I2C devices. */
 
 static struct i2c_board_info anubis_i2c_devs[] __initdata = {
@@ -396,23 +386,6 @@ static struct s3c24xx_audio_simtec_pdata __initdata 
anubis_audio = {
 
 static void __init anubis_map_io(void)
 {
-#ifdef CONFIG_SAMSUNG_CLOCK
-   /* initialise the clocks */
-
-   s3c24xx_dclk0.parent = clk_upll;
-   

[PATCH 0/4] ARM: S3C24XX: cleanup debug macro/earlyprintk

2014-04-24 Thread Heiko Stübner
This series tries to simplify the s3c24xx debug macro, removing dependencies
on mach/ includes, static mappings and finally moving it into include/debug.

The one slightly invasive change is the need for the developer to select
the uart type by himself, which gets rid of the debug macro trying to
determine the uart type itself.

But as usage of the debug-uart is not the common case - especially in a
multiplatform scenario - I didn't worry to much.

Based on 3.15-rc1 and tested on a S3C2442 Openmoko Freerunner (GTA02)


Heiko Stuebner (4):
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: S3C24XX: trim down debug uart handling
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: move debug-macro.S into the common space

 arch/arm/Kconfig.debug   |  36 +++-
 arch/arm/boot/compressed/head.S  |   5 --
 arch/arm/include/debug/s3c24xx.S |  46 +++
 arch/arm/mach-s3c24xx/Kconfig|  28 ---
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S | 101 ---
 5 files changed, 80 insertions(+), 136 deletions(-)
 create mode 100644 arch/arm/include/debug/s3c24xx.S
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/debug-macro.S

-- 
1.9.0


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[PATCH 1/4] ARM: compressed/head.S: remove s3c24xx special case

2014-04-24 Thread Heiko Stübner
addruart from the generic debug macro is doing exactly the same using
the common lowlevel uart definition, so there is no cause for this
special casing for s3c24xx.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/boot/compressed/head.S | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 066b034..3a8b32d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -60,11 +60,6 @@
add \rb, \rb, #0x0001   @ Ser1
 #endif
.endm
-#elif defined(CONFIG_ARCH_S3C24XX)
-   .macro loadsp, rb, tmp
-   mov \rb, #0x5000
-   add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
-   .endm
 #else
.macro  loadsp, rb, tmp
addruart \rb, \tmp
-- 
1.9.0


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[PATCH 2/4] ARM: S3C24XX: trim down debug uart handling

2014-04-24 Thread Heiko Stübner
Using the lowlevel debug uart is a corner case - even more so in a
multiplatform environment. So it seems reasonable to simply let the
developer set the appropriate uart type for the debugged SoC.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/Kconfig.debug   | 16 
 arch/arm/mach-s3c24xx/Kconfig| 28 -
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S | 52 +---
 3 files changed, 17 insertions(+), 79 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 4a2fc0b..43b94a9 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -918,6 +918,22 @@ choice
 
 endchoice
 
+choice
+   prompt S3C24XX low-level debugging port type
+   depends on DEBUG_LL  ARCH_S3C24XX
+
+   config DEBUG_S3C24XX_UART_S3C2440
+   bool S3C2440 uart type
+   help
+ Select this if you're debugging S3C2416, S3C2440, S3C2442,
+ S3C2443 or S3C2450 SoCs.
+
+   config DEBUG_S3C24XX_UART_S3C2410
+   bool S3C2410 uart type
+   help
+ Select this if you're debugging S3C2410 or S3C2412 SoCs.
+endchoice
+
 config DEBUG_EXYNOS_UART
bool
 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 40cf50b..98d17af 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -26,7 +26,6 @@ config CPU_S3C2410
bool SAMSUNG S3C2410
default y
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2410
select S3C2410_CLOCK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
@@ -39,7 +38,6 @@ config CPU_S3C2410
 config CPU_S3C2412
bool SAMSUNG S3C2412
select CPU_ARM926T
-   select CPU_LLSERIAL_S3C2440
select S3C2412_DMA if S3C24XX_DMA
select S3C2412_PM if PM
help
@@ -48,7 +46,6 @@ config CPU_S3C2412
 config CPU_S3C2416
bool SAMSUNG S3C2416/S3C2450
select CPU_ARM926T
-   select CPU_LLSERIAL_S3C2440
select S3C2416_PM if PM
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
@@ -59,7 +56,6 @@ config CPU_S3C2416
 config CPU_S3C2440
bool SAMSUNG S3C2440
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2440
select S3C2410_CLOCK
select S3C2410_PM if PM
select S3C2440_DMA if S3C24XX_DMA
@@ -69,7 +65,6 @@ config CPU_S3C2440
 config CPU_S3C2442
bool SAMSUNG S3C2442
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2440
select S3C2410_CLOCK
select S3C2410_DMA if S3C24XX_DMA
select S3C2410_PM if PM
@@ -84,7 +79,6 @@ config CPU_S3C244X
 config CPU_S3C2443
bool SAMSUNG S3C2443
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2440
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
select SAMSUNG_CLKSRC
@@ -158,28 +152,6 @@ config S3C2410_PM
help
  Power Management code common to S3C2410 and better
 
-# low-level serial option nodes
-
-config CPU_LLSERIAL_S3C2410_ONLY
-   bool
-   default y if CPU_LLSERIAL_S3C2410  !CPU_LLSERIAL_S3C2440
-
-config CPU_LLSERIAL_S3C2440_ONLY
-   bool
-   default y if CPU_LLSERIAL_S3C2440  !CPU_LLSERIAL_S3C2410
-
-config CPU_LLSERIAL_S3C2410
-   bool
-   help
- Selected if there is an S3C2410 (or register compatible) serial
- low-level implementation needed
-
-config CPU_LLSERIAL_S3C2440
-   bool
-   help
- Selected if there is an S3C2440 (or register compatible) serial
- low-level implementation needed
-
 config S3C24XX_PLL
bool Support CPUfreq changing of PLL frequency (EXPERIMENTAL)
depends on ARM_S3C24XX_CPUFREQ
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S 
b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 2f39737..3077a5f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -13,11 +13,9 @@
 */
 
 #include mach/map.h
-#include mach/regs-gpio.h
 #include linux/serial_s3c.h
 
 #define S3C2410_UART1_OFF (0x4000)
-#define SHIFT_2440TXF (14-9)
 
.macro addruart, rp, rv, tmp
ldr \rp, = S3C24XX_PA_UART
@@ -28,56 +26,11 @@
 #endif
.endm
 
-   .macro fifo_full_s3c24xx rd, rx
-   @ check for arm920 vs arm926. currently assume all arm926
-   @ devices have an 64 byte FIFO identical to the s3c2440
-   mrc p15, 0, \rd, c0, c0
-   and \rd, \rd, #0xff0
-   teq \rd, #0x260
-   beq 1004f
-   mrc p15, 0, \rd, c1, c0
-   tst \rd, #1
-   addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-   addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-   bic \rd, \rd, #0xff000
-   ldr

[PATCH 3/4] ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro

2014-04-24 Thread Heiko Stübner
This removes the need for mach/-headers in the debug macro.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/Kconfig.debug   | 19 +--
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S |  9 ++---
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 43b94a9..2476f84 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -625,6 +625,7 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+   select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool Use S3C UART 0 for low-level debug
help
  Say Y here if you want the debug print routines to direct
@@ -637,6 +638,7 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+   select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool Use S3C UART 1 for low-level debug
help
  Say Y here if you want the debug print routines to direct
@@ -649,6 +651,7 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+   select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool Use S3C UART 2 for low-level debug
help
  Say Y here if you want the debug print routines to direct
@@ -661,6 +664,7 @@ choice
config DEBUG_S3C_UART3
depends on PLAT_SAMSUNG  ARCH_EXYNOS
select DEBUG_EXYNOS_UART
+   select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool Use S3C UART 3 for low-level debug
help
  Say Y here if you want the debug print routines to direct
@@ -937,6 +941,9 @@ endchoice
 config DEBUG_EXYNOS_UART
bool
 
+config DEBUG_S3C24XX_UART
+   bool
+
 config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
@@ -1045,6 +1052,10 @@ config DEBUG_UART_PHYS
default 0x4009 if ARCH_LPC32XX
default 0x4010 if DEBUG_PXA_UART1
default 0x4200 if ARCH_GEMINI
+   default 0x5000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART0
+   default 0x50004000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART1
+   default 0x50008000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART2
+   default 0x5000C000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART3
default 0x7c0003f8 if FOOTBRIDGE
default 0x8023 if DEBUG_PICOXCELL_UART
default 0x8007 if DEBUG_IMX23_UART
@@ -1074,7 +1085,7 @@ config DEBUG_UART_PHYS
default 0xf700 if ARCH_IOP33X
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \
-   DEBUG_UART_8250 || DEBUG_UART_PL01X
+   DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
 
 config DEBUG_UART_VIRT
hex Virtual base address of debug UART
@@ -1091,6 +1102,10 @@ config DEBUG_UART_VIRT
default 0xf210 if DEBUG_PXA_UART1
default 0xf409 if ARCH_LPC32XX
default 0xf420 if ARCH_GEMINI
+   default 0xf700 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART0
+   default 0xf7004000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART1
+   default 0xf7008000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART2
+   default 0xf700c000 if DEBUG_S3C24XX_UART  DEBUG_S3C_UART3
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf809 if DEBUG_VEXPRESS_UART0_RS1
@@ -1132,7 +1147,7 @@ config DEBUG_UART_VIRT
default 0xff003000 if DEBUG_U300_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
-   DEBUG_UART_8250 || DEBUG_UART_PL01X
+   DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
 
 config DEBUG_UART_8250_SHIFT
int Register offset shift for the 8250 debug UART
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S 
b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 3077a5f..5b165d8 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -12,18 +12,13 @@
  * published by the Free Software Foundation.
 */
 
-#include mach/map.h
 #include linux/serial_s3c.h
 
 #define S3C2410_UART1_OFF (0x4000)
 
.macro addruart, rp, rv, tmp
-   ldr \rp, = S3C24XX_PA_UART
-   ldr \rv, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-   add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-   add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-#endif
+   ldr \rp, = CONFIG_DEBUG_UART_PHYS
+   ldr \rv, = CONFIG_DEBUG_UART_VIRT
.endm
 
.macro  fifo_full_s3c2410 rd, rx
-- 

[PATCH 4/4] ARM: S3C24XX: move debug-macro.S into the common space

2014-04-24 Thread Heiko Stübner
Move debug-macro.S from mach/include to include/debug where all other common
debug macros are.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/Kconfig.debug   | 1 +
 .../{mach-s3c24xx/include/mach/debug-macro.S = include/debug/s3c24xx.S} | 0
 2 files changed, 1 insertion(+)
 rename arch/arm/{mach-s3c24xx/include/mach/debug-macro.S = 
include/debug/s3c24xx.S} (100%)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 2476f84..00d3ee6 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -996,6 +996,7 @@ config DEBUG_LL_INCLUDE
 DEBUG_IMX6SL_UART
default debug/msm.S if DEBUG_MSM_UART
default debug/omap2plus.S if DEBUG_OMAP2PLUS_UART
+   default debug/s3c24xx.S if DEBUG_S3C24XX_UART
default debug/sirf.S if DEBUG_SIRFPRIMA2_UART1 || 
DEBUG_SIRFMARCO_UART1
default debug/sti.S if DEBUG_STI_UART
default debug/tegra.S if DEBUG_TEGRA_UART
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S 
b/arch/arm/include/debug/s3c24xx.S
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/debug-macro.S
rename to arch/arm/include/debug/s3c24xx.S
-- 
1.9.0


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Re: [PATCH 2/4] ARM: S3C24XX: trim down debug uart handling

2014-04-24 Thread Heiko Stübner
Am Donnerstag, 24. April 2014, 11:34:55 schrieb Russell King - ARM Linux:
 On Thu, Apr 24, 2014 at 12:24:31PM +0200, Heiko Stübner wrote:
  +choice
  +   prompt S3C24XX low-level debugging port type
  +   depends on DEBUG_LL  ARCH_S3C24XX
  +
  +   config DEBUG_S3C24XX_UART_S3C2440
  +   bool S3C2440 uart type
  +   help
  + Select this if you're debugging S3C2416, S3C2440, S3C2442,
  + S3C2443 or S3C2450 SoCs.
  +
  +   config DEBUG_S3C24XX_UART_S3C2410
  +   bool S3C2410 uart type
  +   help
  + Select this if you're debugging S3C2410 or S3C2412 SoCs.
  +endchoice
 
 Why does this need to be a separate choice statement?  What's special
 about S3C24XX?  Is there something wrong with the main choice statement
 just above this where everyone else lists their debugging UART?

The special case is that s3c24xx as architecture has two different uart types. 
Everything else is the same so I didn't want to duplicate the s3c_debug_uartX 
entries.

The other option would have been to duplicate these, like having

- s3c_debug_uart[0-3] for the more common s3c2440 type and
- s3c2410_debug_uart[0-3] for the named type

I guess, judging from your comment this would be better?
[or I'm just overlooking the obvious third way :-) ]


Heiko
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[PATCH v2 0/4] ARM: S3C24XX: cleanup debug macro/earlyprintk

2014-04-24 Thread Heiko Stübner
This series tries to simplify the s3c24xx debug macro, removing dependencies
on mach/ includes, static mappings and finally moving it into include/debug.

The one slightly invasive change is the need for the developer to select
the uart type by himself, which gets rid of the debug macro trying to
determine the uart type itself.

But as usage of the debug-uart is not the common case - especially in a
multiplatform scenario - I didn't worry to much.

Based on 3.15-rc1 and tested on a S3C2442 Openmoko Freerunner (GTA02)

changes since v1:
- do not introduce a secondary choice option, instead implement the
  s3c2410 debug uarts as separate options

Heiko Stuebner (4):
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: S3C24XX: trim down debug uart handling
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: move debug-macro.S into the common space

 arch/arm/Kconfig.debug   |  54 +++-
 arch/arm/boot/compressed/head.S  |   5 --
 arch/arm/include/debug/s3c24xx.S |  46 +++
 arch/arm/mach-s3c24xx/Kconfig|  28 ---
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S | 101 ---
 5 files changed, 98 insertions(+), 136 deletions(-)
 create mode 100644 arch/arm/include/debug/s3c24xx.S
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/debug-macro.S

-- 
1.9.0


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[PATCH v2 1/4] ARM: compressed/head.S: remove s3c24xx special case

2014-04-24 Thread Heiko Stübner
addruart from the generic debug macro is doing exactly the same using
the common lowlevel uart definition, so there is no cause for this
special casing for s3c24xx.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/boot/compressed/head.S | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 066b034..3a8b32d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -60,11 +60,6 @@
add \rb, \rb, #0x0001   @ Ser1
 #endif
.endm
-#elif defined(CONFIG_ARCH_S3C24XX)
-   .macro loadsp, rb, tmp
-   mov \rb, #0x5000
-   add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
-   .endm
 #else
.macro  loadsp, rb, tmp
addruart \rb, \tmp
-- 
1.9.0


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[PATCH v2 2/4] ARM: S3C24XX: trim down debug uart handling

2014-04-24 Thread Heiko Stübner
Using the lowlevel debug uart is a corner case - even more so in a
multiplatform environment. So it seems reasonable to simply let the
developer set the appropriate uart type for the debugged SoC.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/Kconfig.debug   | 30 ++
 arch/arm/mach-s3c24xx/Kconfig| 28 -
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S | 52 +---
 3 files changed, 31 insertions(+), 79 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 4a2fc0b..cb5751f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -670,6 +670,33 @@ choice
  The uncompressor code port configuration is now handled
  by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+   config DEBUG_S3C2410_UART0
+   depends on ARCH_S3C24XX
+   select DEBUG_S3C2410_UART
+   bool Use S3C2410/S3C2412 UART 0 for low-level debug
+   help
+ Say Y here if you want the debug print routines to direct
+ their output to UART 0. The port must have been initialised
+ by the boot-loader before use.
+
+   config DEBUG_S3C2410_UART1
+   depends on ARCH_S3C24XX
+   select DEBUG_S3C2410_UART
+   bool Use S3C2410/S3C2412 UART 1 for low-level debug
+   help
+ Say Y here if you want the debug print routines to direct
+ their output to UART 1. The port must have been initialised
+ by the boot-loader before use.
+
+   config DEBUG_S3C2410_UART2
+   depends on ARCH_S3C24XX
+   select DEBUG_S3C2410_UART
+   bool Use S3C2410/S3C2412 UART 2 for low-level debug
+   help
+ Say Y here if you want the debug print routines to direct
+ their output to UART 2. The port must have been initialised
+ by the boot-loader before use.
+
config DEBUG_SOCFPGA_UART
depends on ARCH_SOCFPGA
bool Use SOCFPGA UART for low-level debug
@@ -921,6 +948,9 @@ endchoice
 config DEBUG_EXYNOS_UART
bool
 
+config DEBUG_S3C2410_UART
+   bool
+
 config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 40cf50b..98d17af 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -26,7 +26,6 @@ config CPU_S3C2410
bool SAMSUNG S3C2410
default y
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2410
select S3C2410_CLOCK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
@@ -39,7 +38,6 @@ config CPU_S3C2410
 config CPU_S3C2412
bool SAMSUNG S3C2412
select CPU_ARM926T
-   select CPU_LLSERIAL_S3C2440
select S3C2412_DMA if S3C24XX_DMA
select S3C2412_PM if PM
help
@@ -48,7 +46,6 @@ config CPU_S3C2412
 config CPU_S3C2416
bool SAMSUNG S3C2416/S3C2450
select CPU_ARM926T
-   select CPU_LLSERIAL_S3C2440
select S3C2416_PM if PM
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
@@ -59,7 +56,6 @@ config CPU_S3C2416
 config CPU_S3C2440
bool SAMSUNG S3C2440
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2440
select S3C2410_CLOCK
select S3C2410_PM if PM
select S3C2440_DMA if S3C24XX_DMA
@@ -69,7 +65,6 @@ config CPU_S3C2440
 config CPU_S3C2442
bool SAMSUNG S3C2442
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2440
select S3C2410_CLOCK
select S3C2410_DMA if S3C24XX_DMA
select S3C2410_PM if PM
@@ -84,7 +79,6 @@ config CPU_S3C244X
 config CPU_S3C2443
bool SAMSUNG S3C2443
select CPU_ARM920T
-   select CPU_LLSERIAL_S3C2440
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
select SAMSUNG_CLKSRC
@@ -158,28 +152,6 @@ config S3C2410_PM
help
  Power Management code common to S3C2410 and better
 
-# low-level serial option nodes
-
-config CPU_LLSERIAL_S3C2410_ONLY
-   bool
-   default y if CPU_LLSERIAL_S3C2410  !CPU_LLSERIAL_S3C2440
-
-config CPU_LLSERIAL_S3C2440_ONLY
-   bool
-   default y if CPU_LLSERIAL_S3C2440  !CPU_LLSERIAL_S3C2410
-
-config CPU_LLSERIAL_S3C2410
-   bool
-   help
- Selected if there is an S3C2410 (or register compatible) serial
- low-level implementation needed
-
-config CPU_LLSERIAL_S3C2440
-   bool
-   help
- Selected if there is an S3C2440 (or register compatible) serial
- low-level implementation needed
-
 config S3C24XX_PLL
bool Support CPUfreq changing of PLL frequency (EXPERIMENTAL)
depends on ARM_S3C24XX_CPUFREQ
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S 

[PATCH v2 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-04-23 Thread Heiko Stübner
Add platform device and select the correct implementation automatically
depending on wether the old samsung_clock or the common clock framework
is enabled.

This is only done for machines already using the old dclk implementation,
as everybody else should move to use dt anyway.

The machine-specific settings for the external clocks will have to be set
by somebody with knowledge about the specific hardware.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   | 22 +-
 arch/arm/mach-s3c24xx/common.c  | 14 ++
 arch/arm/mach-s3c24xx/common.h  |  2 ++
 arch/arm/mach-s3c24xx/mach-anubis.c |  5 +
 arch/arm/mach-s3c24xx/mach-bast.c   |  5 +
 arch/arm/mach-s3c24xx/mach-osiris.c |  5 +
 arch/arm/mach-s3c24xx/mach-rx1950.c |  5 +
 arch/arm/mach-s3c24xx/mach-vr1000.c |  5 +
 arch/arm/mach-s3c24xx/s3c244x.c |  2 ++
 9 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d067f76..6036e77 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,13 @@ config PLAT_S3C24XX
help
  Base platform code for any Samsung S3C24XX device
 
+config S3C2410_COMMON_DCLK
+   bool
+   select REGMAP_MMIO
+   help
+ Temporary symbol to build the dclk driver based on the common clock
+ framework.
+
 menu SAMSUNG S3C24XX SoCs Support
 
 comment S3C24XX SoCs
@@ -264,7 +271,8 @@ config ARCH_BAST
select ISA
select MACH_BAST_IDE
select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
select S3C24XX_SIMTEC_USB
@@ -345,7 +353,8 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
bool Thorcom VR1000
select MACH_BAST_IDE
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
select S3C24XX_SIMTEC_USB
@@ -530,7 +539,8 @@ config MACH_ANUBIS
bool Simtec Electronics ANUBIS
select HAVE_PATA_PLATFORM
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_GPIO_EXTRA64
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_USB_HOST
@@ -571,7 +581,8 @@ config MACH_OSIRIS
bool Simtec IM2440D20 (OSIRIS) module
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_GPIO_EXTRA128
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_NAND
@@ -643,7 +654,8 @@ config MACH_RX1950
select PM_H1940 if PM
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_16934400
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C24XX_COMMON_DCLK if COMMON_CLK
select S3C24XX_PWM
select S3C_DEV_NAND
help
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 92a1e3a..8e930e0 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -554,3 +554,17 @@ void __init s3c2443_init_clocks(int xtal)
s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 }
 #endif
+
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
+   defined(CONFIG_CPU_S3C2442)
+static struct resource s3c2410_dclk_resource[] = {
+   [0] = DEFINE_RES_MEM(0x5684, 0x4),
+};
+
+struct platform_device s3c2410_device_dclk = {
+   .name   = s3c2410-dclk,
+   .id = 0,
+   .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
+   .resource   = s3c2410_dclk_resource,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 3fade6d..50504c7 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -114,6 +114,8 @@ extern struct platform_device s3c2412_device_dma;
 extern struct platform_device s3c2440_device_dma;
 extern struct platform_device s3c2443_device_dma;
 
+extern struct platform_device s3c2410_device_dclk;
+
 #ifdef CONFIG_S3C2412_COMMON_CLK
 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long 
xti_f,
unsigned long ext_f, void __iomem *reg_base);
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c 
b/arch/arm/mach-s3c24xx/mach-anubis.c
index 2a16f8f..6a1a781 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -352,6 +352,7 @@ static 

[PATCH v2 4/9] dt-bindings: add documentation for s3c2410 clock controller

2014-04-23 Thread Heiko Stübner
Describe the clock controller of s3c2410, s3c2440 and s3c2442.

Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Tomasz Figa t.f...@samsung.com
---
 .../bindings/clock/samsung,s3c2410-clock.txt   | 50 ++
 1 file changed, 50 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt 
b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
new file mode 100644
index 000..0b64ad8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
@@ -0,0 +1,50 @@
+* Samsung S3C2410 Clock Controller
+
+The S3C2410 clock controller generates and supplies clock to various 
controllers
+within the SoC. The clock binding described here is applicable to the s3c2410,
+s3c2440 and s3c2442 SoCs in the s3c24x family.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - samsung,s3c2410-clock - controller compatible with S3C2410 SoC.
+  - samsung,s3c2440-clock - controller compatible with S3C2440 SoC.
+  - samsung,s3c2442-clock - controller compatible with S3C2442 SoC.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Some of the clocks are available only
+on a particular SoC.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s3c2410-clock.h header and can be used in device
+tree sources.
+
+External clocks:
+
+The xti clock used as input for the plls is generated outside the SoC. It is
+expected that is are defined using standard clock bindings with a
+clock-output-names value of xti.
+
+Example: Clock controller node:
+
+   clocks: clock-controller@4c00 {
+   compatible = samsung,s3c2410-clock;
+   reg = 0x4c00 0x20;
+   #clock-cells = 1;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller (refer to the standard clock bindings for information about
+  clocks and clock-names properties):
+
+   serial@50004000 {
+   compatible = samsung,s3c2440-uart;
+   reg = 0x50004000 0x4000;
+   interrupts = 1 23 3 4, 1 23 4 4;
+   clock-names = uart, clk_uart_baud2;
+   clocks = clocks PCLK_UART0, clocks PCLK_UART0;
+   status = disabled;
+   };
-- 
1.9.0


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[PATCH v2 5/9] clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442

2014-04-23 Thread Heiko Stübner
This driver can handle the clock controllers of the socs mentioned above,
as they share a common clock tree with only small differences.

The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure.

As pll-rate-tables only the 12mhz variants are currently included.
The original code was wrongly checking for 169mhz xti values [a 0 to much
at the end], so the original 16mhz pll table would have never been
included and its values are so obscure that I have no possibility to
at least check their sane-ness. When using the formula from the manual
the resulting frequency is near the table value but still slightly off.

Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Mike Turquette mturque...@linaro.org
---
 drivers/clk/samsung/Makefile|   1 +
 drivers/clk/samsung/clk-s3c2410.c   | 477 
 include/dt-bindings/clock/s3c2410.h |  62 +
 3 files changed, 540 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-s3c2410.c
 create mode 100644 include/dt-bindings/clock/s3c2410.h

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 9892de4..2cb62f8 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_EXYNOS5250)+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5420)   += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)  += clk-exynos-audss.o
+obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
diff --git a/drivers/clk/samsung/clk-s3c2410.c 
b/drivers/clk/samsung/clk-s3c2410.c
new file mode 100644
index 000..7b41821
--- /dev/null
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner he...@sntech.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for S3C2410 and following SoCs.
+ */
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clock/s3c2410.h
+
+#include clk.h
+#include clk-pll.h
+
+#define LOCKTIME   0x00
+#define MPLLCON0x04
+#define UPLLCON0x08
+#define CLKCON 0x0c
+#define CLKSLOW0x10
+#define CLKDIVN0x14
+#define CAMDIVN0x18
+
+/* the soc types */
+enum supported_socs {
+   S3C2410,
+   S3C2440,
+   S3C2442,
+};
+
+/* list of PLLs to be registered */
+enum s3c2410_plls {
+   mpll, upll,
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s3c2410_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long s3c2410_clk_regs[] __initdata = {
+   LOCKTIME,
+   MPLLCON,
+   UPLLCON,
+   CLKCON,
+   CLKSLOW,
+   CLKDIVN,
+   CAMDIVN,
+};
+
+static int s3c2410_clk_suspend(void)
+{
+   samsung_clk_save(reg_base, s3c2410_save,
+   ARRAY_SIZE(s3c2410_clk_regs));
+
+   return 0;
+}
+
+static void s3c2410_clk_resume(void)
+{
+   samsung_clk_restore(reg_base, s3c2410_save,
+   ARRAY_SIZE(s3c2410_clk_regs));
+}
+
+static struct syscore_ops s3c2410_clk_syscore_ops = {
+   .suspend = s3c2410_clk_suspend,
+   .resume = s3c2410_clk_resume,
+};
+
+static void s3c2410_clk_sleep_init(void)
+{
+   s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
+   ARRAY_SIZE(s3c2410_clk_regs));
+   if (!s3c2410_save) {
+   pr_warn(%s: failed to allocate sleep save data, no sleep 
support!\n,
+   __func__);
+   return;
+   }
+
+   register_syscore_ops(s3c2410_clk_syscore_ops);
+   return;
+}
+#else
+static void s3c2410_clk_sleep_init(void) {}
+#endif
+
+PNAME(fclk_p) = { mpll, div_slow };
+
+struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
+   MUX(FCLK, fclk, fclk_p, CLKSLOW, 4, 1),
+};
+
+static struct clk_div_table divslow_d[] = {
+   { .val = 0, .div = 1 },
+   { .val = 1, .div = 2 },
+   { .val = 2, .div = 4 },
+   { .val = 3, .div = 6 },
+   { .val = 4, .div = 8 },
+   { .val = 5, .div = 10 },
+   { .val = 6, .div = 12 },
+   { .val = 7, .div = 14 },
+   { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
+   DIV_T(0, div_slow, xti, CLKSLOW, 0, 3, divslow_d),
+   DIV(PCLK, pclk, hclk, CLKDIVN, 0, 1),
+};
+
+struct 

[PATCH v2 6/9] ARM: S3C24XX: add platform code for conversion to the common clock framework

2014-04-23 Thread Heiko Stübner
This adds the necessary init functions to init the clocks from the common
clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy
clock code.

This also includes empty stubs for the *_setup_clocks functions that are
called from the cpufreq driver on resume.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   |  5 +
 arch/arm/mach-s3c24xx/common.c  | 25 +
 arch/arm/mach-s3c24xx/common.h  |  7 +++
 arch/arm/mach-s3c24xx/s3c2410.c |  6 ++
 arch/arm/mach-s3c24xx/s3c2442.c |  3 ++-
 arch/arm/mach-s3c24xx/s3c244x.c |  6 ++
 6 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 6036e77..daab788 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,11 @@ config PLAT_S3C24XX
help
  Base platform code for any Samsung S3C24XX device
 
+config S3C2410_COMMON_CLK
+   bool
+   help
+ Build the s3c2410 clock driver based on the common clock framework.
+
 config S3C2410_COMMON_DCLK
bool
select REGMAP_MMIO
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 8e930e0..5307bb7 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -53,6 +53,7 @@
 #include plat/cpu-freq.h
 #include plat/pll.h
 #include plat/pwm-core.h
+#include plat/watchdog-reset.h
 
 #include common.h
 
@@ -534,6 +535,14 @@ struct platform_device s3c2443_device_dma = {
 };
 #endif
 
+#if defined(CONFIG_COMMON_CLK)  defined(CONFIG_CPU_S3C2410)
+void __init s3c2410_init_clocks(int xtal)
+{
+   s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
 #ifdef CONFIG_CPU_S3C2412
 void __init s3c2412_init_clocks(int xtal)
 {
@@ -548,6 +557,22 @@ void __init s3c2416_init_clocks(int xtal)
 }
 #endif
 
+#if defined(CONFIG_COMMON_CLK)  defined(CONFIG_CPU_S3C2440)
+void __init s3c2440_init_clocks(int xtal)
+{
+   s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
+#if defined(CONFIG_COMMON_CLK)  defined(CONFIG_CPU_S3C2442)
+void __init s3c2442_init_clocks(int xtal)
+{
+   s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
+   samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
 #ifdef CONFIG_CPU_S3C2443
 void __init s3c2443_init_clocks(int xtal)
 {
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 50504c7..2d65541 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -77,6 +77,7 @@ extern void s3c244x_restart(enum reboot_mode mode, const char 
*cmd);
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
 extern void s3c2440_map_io(void);
+extern void s3c2440_init_clocks(int xtal);
 extern void s3c2440_init_irq(void);
 #else
 #define s3c2440_init NULL
@@ -86,6 +87,7 @@ extern void s3c2440_init_irq(void);
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
 extern void s3c2442_map_io(void);
+extern void s3c2442_init_clocks(int xtal);
 extern void s3c2442_init_irq(void);
 #else
 #define s3c2442_init NULL
@@ -116,6 +118,11 @@ extern struct platform_device s3c2443_device_dma;
 
 extern struct platform_device s3c2410_device_dclk;
 
+#ifdef CONFIG_S3C2410_COMMON_CLK
+void __init s3c2410_common_clk_init(struct device_node *np, unsigned long 
xti_f,
+   int current_soc,
+   void __iomem *reg_base);
+#endif
 #ifdef CONFIG_S3C2412_COMMON_CLK
 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long 
xti_f,
unsigned long ext_f, void __iomem *reg_base);
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index ffb92cbc..a1ce4b0 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -83,6 +83,7 @@ void __init s3c2410_map_io(void)
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 void __init_or_cpufreq s3c2410_setup_clocks(void)
 {
struct clk *xtal_clk;
@@ -142,6 +143,11 @@ void __init s3c2410_init_clocks(int xtal)
clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
+#else
+void __init_or_cpufreq s3c2410_setup_clocks(void)
+{
+}
+#endif
 
 struct bus_type s3c2410_subsys = {
.name = s3c2410-core,
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 2c8adc0..564c6503 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -53,6 +53,7 @@
 
 #include common.h
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 /* S3C2442 extended clock support */
 
 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
@@ -162,7 +163,7 @@ 

[PATCH v2 7/9] ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework

2014-04-23 Thread Heiko Stübner
Convert all machines using these cpus to use the ccf clock driver
instead of the legacy Samsung clock implementation.

Some of the more esotheric machines will probably need a fixup, as they
do strange things to the clkout outputs, that I did not really understand
nor have the hardware to check.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig  |  8 
 arch/arm/mach-s3c24xx/Makefile |  4 ++--
 arch/arm/mach-s3c24xx/common.c |  4 
 arch/arm/mach-s3c24xx/mach-anubis.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-at2440evb.c | 10 +++---
 arch/arm/mach-s3c24xx/mach-gta02.c |  8 ++--
 arch/arm/mach-s3c24xx/mach-mini2440.c  | 10 +++---
 arch/arm/mach-s3c24xx/mach-nexcoder.c  | 15 ---
 arch/arm/mach-s3c24xx/mach-osiris.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-rx1950.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-rx3715.c| 10 +++---
 arch/arm/mach-s3c24xx/mach-smdk2440.c  | 10 +++---
 12 files changed, 73 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index daab788..96d1e54 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -73,10 +73,10 @@ config CPU_S3C2416
 
 config CPU_S3C2440
bool SAMSUNG S3C2440
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_PM if PM
select S3C2440_DMA if S3C24XX_DMA
help
@@ -84,10 +84,10 @@ config CPU_S3C2440
 
 config CPU_S3C2442
bool SAMSUNG S3C2442
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select S3C2410_PM if PM
help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index f254797..9010eba 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -29,9 +29,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP)+= sleep-s3c2412.o
 obj-$(CONFIG_CPU_S3C2416)  += s3c2416.o
 obj-$(CONFIG_S3C2416_PM)   += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)  += s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)  += s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)  += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)  += s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)  += s3c244x.o
 obj-$(CONFIG_S3C2440_DMA)  += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_1200) += pll-s3c2440-1200.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 5307bb7..def8627 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -92,7 +92,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x3244,
.idmask = 0x,
.map_io = s3c2440_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2440_init,
.name   = name_s3c2440
@@ -101,7 +100,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32440001,
.idmask = 0x,
.map_io = s3c2440_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2440_init,
.name   = name_s3c2440a
@@ -110,7 +108,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32440aaa,
.idmask = 0x,
.map_io = s3c2442_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2442_init,
.name   = name_s3c2442
@@ -119,7 +116,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32440aab,
.idmask = 0x,
.map_io = s3c2442_map_io,
-   .init_clocks= s3c244x_init_clocks,
.init_uarts = s3c244x_init_uarts,
.init   = s3c2442_init,
.name   = name_s3c2442b
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c 
b/arch/arm/mach-s3c24xx/mach-anubis.c
index 6a1a781..6b4f188 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -46,7 +46,6 @@
 
 #include net/ax88796.h
 
-#include plat/clock.h
 #include plat/devs.h
 #include plat/cpu.h
 #include linux/platform_data/asoc-s3c24xx_simtec.h
@@ 

[PATCH v2 8/9] ARM: S3C24XX: convert s3c2410 to common clock framework

2014-04-23 Thread Heiko Stübner
Convert the machines using the s3c2410 to use the new driver based
on the common clock framework instead of the legacy Samsung clock driver.

As with the s3c244x, machines using the clkout output will need a fixup
from someone with the hardware.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   |  4 ++--
 arch/arm/mach-s3c24xx/common.c  |  2 --
 arch/arm/mach-s3c24xx/mach-amlm5900.c   |  9 +++--
 arch/arm/mach-s3c24xx/mach-bast.c   | 10 +++---
 arch/arm/mach-s3c24xx/mach-h1940.c  | 10 +++---
 arch/arm/mach-s3c24xx/mach-n30.c| 12 
 arch/arm/mach-s3c24xx/mach-nexcoder.c   |  7 +--
 arch/arm/mach-s3c24xx/mach-otom.c   | 10 +++---
 arch/arm/mach-s3c24xx/mach-qt2410.c |  9 +++--
 arch/arm/mach-s3c24xx/mach-smdk2410.c   |  9 +++--
 arch/arm/mach-s3c24xx/mach-tct_hammer.c |  9 +++--
 arch/arm/mach-s3c24xx/mach-vr1000.c | 10 +++---
 12 files changed, 67 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 96d1e54..57ebb13 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -37,10 +37,10 @@ comment S3C24XX SoCs
 config CPU_S3C2410
bool SAMSUNG S3C2410
default y
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2410
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
select S3C2410_PM if PM
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index def8627..a7b1269 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -74,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x3241,
.idmask = 0x,
.map_io = s3c2410_map_io,
-   .init_clocks= s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init   = s3c2410_init,
.name   = name_s3c2410
@@ -83,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32410002,
.idmask = 0x,
.map_io = s3c2410_map_io,
-   .init_clocks= s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init   = s3c2410a_init,
.name   = name_s3c2410a
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c 
b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 284ea1f..0e175e0 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -161,11 +161,16 @@ static struct platform_device *amlm5900_devices[] 
__initdata = {
 static void __init amlm5900_map_io(void)
 {
s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
-   s3c24xx_init_clocks(0);
s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init amlm5900_init_time(void)
+{
+   s3c2410_init_clocks(1200);
+   samsung_timer_init();
+}
+
 #ifdef CONFIG_FB_S3C2410
 static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
.width  = 160,
@@ -241,6 +246,6 @@ MACHINE_START(AML_M5900, AML_M5900)
.map_io = amlm5900_map_io,
.init_irq   = s3c2410_init_irq,
.init_machine   = amlm5900_init,
-   .init_time  = samsung_timer_init,
+   .init_time  = amlm5900_init_time,
.restart= s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c 
b/arch/arm/mach-s3c24xx/mach-bast.c
index 13e078c..ab075a6 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -50,7 +50,6 @@
 #include mach/regs-lcd.h
 #include mach/gpio-samsung.h
 
-#include plat/clock.h
 #include plat/cpu.h
 #include plat/cpu-freq.h
 #include plat/devs.h
@@ -581,11 +580,16 @@ static void __init bast_map_io(void)
s3c_hwmon_set_platdata(bast_hwmon_info);
 
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
-   s3c24xx_init_clocks(0);
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init bast_init_time(void)
+{
+   s3c2410_init_clocks(1200);
+   samsung_timer_init();
+}
+
 static void __init bast_init(void)
 {
register_syscore_ops(bast_pm_syscore_ops);
@@ -613,6 +617,6 @@ MACHINE_START(BAST, Simtec-BAST)
.map_io = bast_map_io,
.init_irq   = s3c2410_init_irq,
.init_machine   = bast_init,
-   .init_time  = samsung_timer_init,
+   .init_time  = 

[PATCH v2 9/9] ARM: S3C24XX: remove legacy clock code

2014-04-23 Thread Heiko Stübner
With the move to the common clock framework completed for s3c2410, s3c2440
and s3c2442, the legacy clock code for these machines can go away too.

This also includes the legacy dclk code, as all legacy users are converted.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-s3c24xx/Kconfig   |  11 -
 arch/arm/mach-s3c24xx/Makefile  |   2 -
 arch/arm/mach-s3c24xx/clock-dclk.c  | 195 
 arch/arm/mach-s3c24xx/clock-s3c2410.c   | 285 
 arch/arm/mach-s3c24xx/clock-s3c2440.c   | 217 --
 arch/arm/mach-s3c24xx/clock-s3c244x.c   | 141 
 arch/arm/mach-s3c24xx/common.h  |   2 -
 arch/arm/mach-s3c24xx/include/mach/regs-clock.h |  18 --
 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h  |   3 -
 arch/arm/mach-s3c24xx/pm.c  |  12 -
 arch/arm/mach-s3c24xx/s3c2410.c |  62 --
 arch/arm/mach-s3c24xx/s3c2442.c | 112 --
 arch/arm/mach-s3c24xx/s3c244x.c |  63 --
 13 files changed, 1123 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/clock-dclk.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2410.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2440.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c244x.c

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 57ebb13..02b1adf 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -110,17 +110,6 @@ config CPU_S3C2443
 
 # common code
 
-config S3C2410_CLOCK
-   bool
-   help
- Clock code for the S3C2410, and similar processors which
- is currently includes the S3C2410, S3C2440, S3C2442.
-
-config S3C24XX_DCLK
-   bool
-   help
- Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
-
 config S3C24XX_SMDK
bool
help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 9010eba..2235d0d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -44,10 +44,8 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
 
 # common code
 
-obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
 obj-$(CONFIG_S3C24XX_DMA)  += dma.o
 
-obj-$(CONFIG_S3C2410_CLOCK)+= clock-s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
 
 obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c 
b/arch/arm/mach-s3c24xx/clock-dclk.c
deleted file mode 100644
index 1edd9b2..000
--- a/arch/arm/mach-s3c24xx/clock-dclk.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Simtec Electronics
- * Ben Dooks b...@simtec.co.uk
- * http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX - definitions for DCLK and CLKOUT registers
- */
-
-#include linux/kernel.h
-#include linux/errno.h
-#include linux/clk.h
-#include linux/io.h
-
-#include mach/regs-clock.h
-#include mach/regs-gpio.h
-
-#include plat/clock.h
-#include plat/cpu.h
-
-/* clocks that could be registered by external code */
-
-static int s3c24xx_dclk_enable(struct clk *clk, int enable)
-{
-   unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-   if (enable)
-   dclkcon |= clk-ctrlbit;
-   else
-   dclkcon = ~clk-ctrlbit;
-
-   __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-   return 0;
-}
-
-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
-{
-   unsigned long dclkcon;
-   unsigned int uclk;
-
-   if (parent == clk_upll)
-   uclk = 1;
-   else if (parent == clk_p)
-   uclk = 0;
-   else
-   return -EINVAL;
-
-   clk-parent = parent;
-
-   dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-   if (clk-ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
-   if (uclk)
-   dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
-   else
-   dclkcon = ~S3C2410_DCLKCON_DCLK0_UCLK;
-   } else {
-   if (uclk)
-   dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
-   else
-   dclkcon = ~S3C2410_DCLKCON_DCLK1_UCLK;
-   }
-
-   __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-   return 0;
-}
-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
-{
-   unsigned long div;
-
-   if ((rate == 0) || !clk-parent)
-   return 0;
-
-   div = clk_get_rate(clk-parent) / rate;
-   if (div  2)
-   div = 2;
-   else if (div  16)
-   div = 16;
-
-   return div;
-}
-
-static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
-   unsigned 

[PATCH v2.1 3/9] ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled

2014-04-23 Thread Heiko Stübner
Add platform device and select the correct implementation automatically
depending on wether the old samsung_clock or the common clock framework
is enabled.

This is only done for machines already using the old dclk implementation,
as everybody else should move to use dt anyway.

The machine-specific settings for the external clocks will have to be set
by somebody with knowledge about the specific hardware.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
adapted to apply against v3.16-next/clk-s3c24xx

 arch/arm/mach-s3c24xx/Kconfig   | 22 +-
 arch/arm/mach-s3c24xx/common.c  | 14 ++
 arch/arm/mach-s3c24xx/common.h  |  2 ++
 arch/arm/mach-s3c24xx/mach-anubis.c |  5 +
 arch/arm/mach-s3c24xx/mach-bast.c   |  5 +
 arch/arm/mach-s3c24xx/mach-osiris.c |  5 +
 arch/arm/mach-s3c24xx/mach-rx1950.c |  5 +
 arch/arm/mach-s3c24xx/mach-vr1000.c |  5 +
 arch/arm/mach-s3c24xx/s3c244x.c |  2 ++
 9 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d067f76..6036e77 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,13 @@ config PLAT_S3C24XX
help
  Base platform code for any Samsung S3C24XX device
 
+config S3C2410_COMMON_DCLK
+   bool
+   select REGMAP_MMIO
+   help
+ Temporary symbol to build the dclk driver based on the common clock
+ framework.
+
 menu SAMSUNG S3C24XX SoCs Support
 
 comment S3C24XX SoCs
@@ -264,7 +271,8 @@ config ARCH_BAST
select ISA
select MACH_BAST_IDE
select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
select S3C24XX_SIMTEC_USB
@@ -345,7 +353,8 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
bool Thorcom VR1000
select MACH_BAST_IDE
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_NOR
select S3C24XX_SIMTEC_PM if PM
select S3C24XX_SIMTEC_USB
@@ -530,7 +539,8 @@ config MACH_ANUBIS
bool Simtec Electronics ANUBIS
select HAVE_PATA_PLATFORM
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_USB_HOST
help
@@ -571,7 +581,8 @@ config MACH_OSIRIS
bool Simtec IM2440D20 (OSIRIS) module
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_1200
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C2410_COMMON_DCLK if COMMON_CLK
select S3C24XX_SIMTEC_PM if PM
select S3C_DEV_NAND
select S3C_DEV_USB_HOST
@@ -643,7 +654,8 @@ config MACH_RX1950
select PM_H1940 if PM
select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
select S3C2440_XTAL_16934400
-   select S3C24XX_DCLK
+   select S3C24XX_DCLK if SAMSUNG_CLOCK
+   select S3C24XX_COMMON_DCLK if COMMON_CLK
select S3C24XX_PWM
select S3C_DEV_NAND
help
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 92a1e3a..8e930e0 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -554,3 +554,17 @@ void __init s3c2443_init_clocks(int xtal)
s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 }
 #endif
+
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
+   defined(CONFIG_CPU_S3C2442)
+static struct resource s3c2410_dclk_resource[] = {
+   [0] = DEFINE_RES_MEM(0x5684, 0x4),
+};
+
+struct platform_device s3c2410_device_dclk = {
+   .name   = s3c2410-dclk,
+   .id = 0,
+   .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
+   .resource   = s3c2410_dclk_resource,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 3fade6d..50504c7 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -114,6 +114,8 @@ extern struct platform_device s3c2412_device_dma;
 extern struct platform_device s3c2440_device_dma;
 extern struct platform_device s3c2443_device_dma;
 
+extern struct platform_device s3c2410_device_dclk;
+
 #ifdef CONFIG_S3C2412_COMMON_CLK
 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long 
xti_f,
unsigned long ext_f, void __iomem *reg_base);
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c 
b/arch/arm/mach-s3c24xx/mach-anubis.c
index 2a16f8f..6a1a781 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ 

[PATCH v2.1 8/9] ARM: S3C24XX: convert s3c2410 to common clock framework

2014-04-23 Thread Heiko Stübner
Convert the machines using the s3c2410 to use the new driver based
on the common clock framework instead of the legacy Samsung clock driver.

As with the s3c244x, machines using the clkout output will need a fixup
from someone with the hardware.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
adapted to apply against v3.16-next/clk-s3c24xx

 arch/arm/mach-s3c24xx/Kconfig   |  4 ++--
 arch/arm/mach-s3c24xx/common.c  |  2 --
 arch/arm/mach-s3c24xx/mach-amlm5900.c   |  9 +++--
 arch/arm/mach-s3c24xx/mach-bast.c   | 10 +++---
 arch/arm/mach-s3c24xx/mach-h1940.c  | 10 +++---
 arch/arm/mach-s3c24xx/mach-n30.c| 12 
 arch/arm/mach-s3c24xx/mach-nexcoder.c   |  7 +--
 arch/arm/mach-s3c24xx/mach-otom.c   | 10 +++---
 arch/arm/mach-s3c24xx/mach-qt2410.c |  9 +++--
 arch/arm/mach-s3c24xx/mach-smdk2410.c   |  9 +++--
 arch/arm/mach-s3c24xx/mach-tct_hammer.c |  9 +++--
 arch/arm/mach-s3c24xx/mach-vr1000.c | 10 +++---
 12 files changed, 67 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 96d1e54..57ebb13 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -37,10 +37,10 @@ comment S3C24XX SoCs
 config CPU_S3C2410
bool SAMSUNG S3C2410
default y
-   depends on SAMSUNG_CLOCK
+   select COMMON_CLK
select CPU_ARM920T
select CPU_LLSERIAL_S3C2410
-   select S3C2410_CLOCK
+   select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
select S3C2410_PM if PM
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index def8627..a7b1269 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -74,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x3241,
.idmask = 0x,
.map_io = s3c2410_map_io,
-   .init_clocks= s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init   = s3c2410_init,
.name   = name_s3c2410
@@ -83,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = 0x32410002,
.idmask = 0x,
.map_io = s3c2410_map_io,
-   .init_clocks= s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init   = s3c2410a_init,
.name   = name_s3c2410a
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c 
b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 284ea1f..0e175e0 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -161,11 +161,16 @@ static struct platform_device *amlm5900_devices[] 
__initdata = {
 static void __init amlm5900_map_io(void)
 {
s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
-   s3c24xx_init_clocks(0);
s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init amlm5900_init_time(void)
+{
+   s3c2410_init_clocks(1200);
+   samsung_timer_init();
+}
+
 #ifdef CONFIG_FB_S3C2410
 static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
.width  = 160,
@@ -241,6 +246,6 @@ MACHINE_START(AML_M5900, AML_M5900)
.map_io = amlm5900_map_io,
.init_irq   = s3c2410_init_irq,
.init_machine   = amlm5900_init,
-   .init_time  = samsung_timer_init,
+   .init_time  = amlm5900_init_time,
.restart= s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c 
b/arch/arm/mach-s3c24xx/mach-bast.c
index 13e078c..ab075a6 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -50,7 +50,6 @@
 #include mach/regs-lcd.h
 #include mach/gpio-samsung.h
 
-#include plat/clock.h
 #include plat/cpu.h
 #include plat/cpu-freq.h
 #include plat/devs.h
@@ -581,11 +580,16 @@ static void __init bast_map_io(void)
s3c_hwmon_set_platdata(bast_hwmon_info);
 
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
-   s3c24xx_init_clocks(0);
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init bast_init_time(void)
+{
+   s3c2410_init_clocks(1200);
+   samsung_timer_init();
+}
+
 static void __init bast_init(void)
 {
register_syscore_ops(bast_pm_syscore_ops);
@@ -613,6 +617,6 @@ MACHINE_START(BAST, Simtec-BAST)
.map_io = bast_map_io,
.init_irq   = s3c2410_init_irq,
.init_machine   = bast_init,
-   .init_time  = 

[PATCH v2.1 9/9] ARM: S3C24XX: remove legacy clock code

2014-04-23 Thread Heiko Stübner
With the move to the common clock framework completed for s3c2410, s3c2440
and s3c2442, the legacy clock code for these machines can go away too.

This also includes the legacy dclk code, as all legacy users are converted.

Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
adapted to apply against v3.16-next/clk-s3c24xx

 arch/arm/mach-s3c24xx/Kconfig   |  11 -
 arch/arm/mach-s3c24xx/Makefile  |   2 -
 arch/arm/mach-s3c24xx/clock-dclk.c  | 195 
 arch/arm/mach-s3c24xx/clock-s3c2410.c   | 284 
 arch/arm/mach-s3c24xx/clock-s3c2440.c   | 217 --
 arch/arm/mach-s3c24xx/clock-s3c244x.c   | 141 
 arch/arm/mach-s3c24xx/common.h  |   2 -
 arch/arm/mach-s3c24xx/include/mach/regs-clock.h |  18 --
 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h  |   3 -
 arch/arm/mach-s3c24xx/pm.c  |  12 -
 arch/arm/mach-s3c24xx/s3c2410.c |  62 --
 arch/arm/mach-s3c24xx/s3c2442.c | 112 --
 arch/arm/mach-s3c24xx/s3c244x.c |  63 --
 13 files changed, 1122 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/clock-dclk.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2410.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2440.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c244x.c

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 7b99740..77b0fb5 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -110,17 +110,6 @@ config CPU_S3C2443
 
 # common code
 
-config S3C2410_CLOCK
-   bool
-   help
- Clock code for the S3C2410, and similar processors which
- is currently includes the S3C2410, S3C2440, S3C2442.
-
-config S3C24XX_DCLK
-   bool
-   help
- Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
-
 config S3C24XX_SMDK
bool
help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 9010eba..2235d0d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -44,10 +44,8 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
 
 # common code
 
-obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
 obj-$(CONFIG_S3C24XX_DMA)  += dma.o
 
-obj-$(CONFIG_S3C2410_CLOCK)+= clock-s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
 
 obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c 
b/arch/arm/mach-s3c24xx/clock-dclk.c
deleted file mode 100644
index 1edd9b2..000
--- a/arch/arm/mach-s3c24xx/clock-dclk.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Simtec Electronics
- * Ben Dooks b...@simtec.co.uk
- * http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX - definitions for DCLK and CLKOUT registers
- */
-
-#include linux/kernel.h
-#include linux/errno.h
-#include linux/clk.h
-#include linux/io.h
-
-#include mach/regs-clock.h
-#include mach/regs-gpio.h
-
-#include plat/clock.h
-#include plat/cpu.h
-
-/* clocks that could be registered by external code */
-
-static int s3c24xx_dclk_enable(struct clk *clk, int enable)
-{
-   unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-   if (enable)
-   dclkcon |= clk-ctrlbit;
-   else
-   dclkcon = ~clk-ctrlbit;
-
-   __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-   return 0;
-}
-
-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
-{
-   unsigned long dclkcon;
-   unsigned int uclk;
-
-   if (parent == clk_upll)
-   uclk = 1;
-   else if (parent == clk_p)
-   uclk = 0;
-   else
-   return -EINVAL;
-
-   clk-parent = parent;
-
-   dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-   if (clk-ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
-   if (uclk)
-   dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
-   else
-   dclkcon = ~S3C2410_DCLKCON_DCLK0_UCLK;
-   } else {
-   if (uclk)
-   dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
-   else
-   dclkcon = ~S3C2410_DCLKCON_DCLK1_UCLK;
-   }
-
-   __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-   return 0;
-}
-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
-{
-   unsigned long div;
-
-   if ((rate == 0) || !clk-parent)
-   return 0;
-
-   div = clk_get_rate(clk-parent) / rate;
-   if (div  2)
-   div = 2;
-   else if (div  16)
-   div = 16;
-
-   return div;
-}
-
-static unsigned long 

Re: [PATCH v2 1/9] ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccf

2014-04-23 Thread Heiko Stübner
Am Mittwoch, 23. April 2014, 22:55:51 schrieb Tomasz Figa:
 Hi,
 
 On 23.04.2014 22:42, Sergei Shtylyov wrote:
  Hello.
  
  On 04/23/2014 11:34 PM, Heiko Stübner wrote:
  The s3c24xx cpufreq driver needs to change the mpll speed and was doing
  this by writing raw values from a translation table into the MPLLCON
  register.
  
  Change this to use a regular clk_set_rate call when using the common
  clock framework and only write the raw value in the samsung_clock case.
  
  To not needing to create additional infrastructure for this, the mpll
  clock
  is requested at the first call to s3c2410_set_fvco().
  
  Signed-off-by: Heiko Stuebner he...@sntech.de
  ---
  
arch/arm/mach-s3c24xx/cpufreq-utils.c | 14 ++
1 file changed, 14 insertions(+)
  
  diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c
  b/arch/arm/mach-s3c24xx/cpufreq-utils.c
  index 2a0aa56..d5e797b 100644
  --- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
  +++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
  
  [...]
  
  @@ -60,5 +61,18 @@ void s3c2410_cpufreq_setrefresh(struct
  s3c_cpufreq_config *cfg)
  
 */

void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
{
  
  +#ifdef CONFIG_SAMSUNG_CLOCK
  
__raw_writel(cfg-pll.driver_data, S3C2410_MPLLCON);
  
  +#endif
  +
  +#ifdef CONFIG_COMMON_CLK
  +static struct clk *mpll;
  +
  +if (!mpll)
  
  You are testing uninitialized variable. This check wouldn't make
  
  much sense even if the variable was initialized.
 
 I should probably add that NULL is considered a valid clock handle by
 Common Clock Framework.
 
 If there is really no way to pass the clock to this function then
 probably a global variable initialized by some code running earlier than
 this function could be called would be a better choice.

*grrr* :-) ... ok I'll try to find another way (again) to do this


 Anyway, Heiko, thanks for working on this. I'll try to review rest of
 the series soon. (I'm attending the ELC next week, though, so I'm not
 sure if I find some time then, though.)

Just as a reminder, there isn't this much to still review, as you 
Acked/Reviewed most of the series in v1 and only this patch as well as 2 and 5 
still need a review/ack - and the only changes are fixes for your comments ;-)


Heiko
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[PATCH v2.1 1/9] ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccf

2014-04-23 Thread Heiko Stübner
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table into the MPLLCON
register.

Change this to use a regular clk_set_rate call when using the common
clock framework and only write the raw value in the samsung_clock case.

The s3c cpufreq driver does already aquire the mpll, so simply add a reference
to struct s3c_cpufreq_config to let set_fvco access it.

While struct clk is opaque the differenciation between samsung clock and
common clock is kept, as the samsung-clock mpll clk does not implement a
real set_rate.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/mach-s3c24xx/cpufreq-utils.c  | 8 
 arch/arm/plat-samsung/include/plat/cpu-freq-core.h | 1 +
 drivers/cpufreq/s3c24xx-cpufreq.c  | 1 +
 3 files changed, 10 insertions(+)

diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c 
b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 2a0aa56..c1b7508 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -14,6 +14,7 @@
 #include linux/errno.h
 #include linux/cpufreq.h
 #include linux/io.h
+#include linux/clk.h
 
 #include mach/map.h
 #include mach/regs-clock.h
@@ -60,5 +61,12 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config 
*cfg)
  */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
+#ifdef CONFIG_SAMSUNG_CLOCK
__raw_writel(cfg-pll.driver_data, S3C2410_MPLLCON);
+#endif
+
+#ifdef CONFIG_COMMON_CLK
+   if (!IS_ERR(cfg-mpll))
+   clk_set_rate(cfg-mpll, cfg-pll.frequency);
+#endif
 }
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h 
b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 7231c8e..72d4178 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -119,6 +119,7 @@ struct s3c_plltab {
 struct s3c_cpufreq_config {
struct s3c_freq freq;
struct s3c_freq max;
+   struct clk  *mpll;
struct cpufreq_frequency_table pll;
struct s3c_clkdivs  divs;
struct s3c_cpufreq_info *info;  /* for core, not drivers */
diff --git a/drivers/cpufreq/s3c24xx-cpufreq.c 
b/drivers/cpufreq/s3c24xx-cpufreq.c
index be1b2b5..227ebf7 100644
--- a/drivers/cpufreq/s3c24xx-cpufreq.c
+++ b/drivers/cpufreq/s3c24xx-cpufreq.c
@@ -141,6 +141,7 @@ static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config 
*cfg)
 
 static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
 {
+   cfg-mpll = _clk_mpll;
(cfg-info-set_fvco)(cfg);
 }
 
-- 
1.9.0


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Re: [PATCH Resend] ARM: EXYNOS: Map SYSRAM address through DT

2014-04-16 Thread Heiko Stübner
Hi,

Am Mittwoch, 16. April 2014, 16:35:36 schrieb Arnd Bergmann:
 On Wednesday 16 April 2014 17:20:51 Sachin Kamat wrote:
  Instead of hardcoding the SYSRAM details for each SoC,
  pass this information through device tree (DT) and make
  the code SoC agnostic.
  
  Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
  ---
  Rebased on latest linux-next.
 
 Thanks for sending this again. I'd like Heiko to have a look
 and provide an Ack if he's happy with it.
 
 It seems similar to what he did with the SRAM for mach-rockchip,
 and if it is we should use the same binding that he introduced,
 which would be a minor variation of this.

The sram binding is derived from the generic reserved-memory bindings to 
enable the sram in general to be used generically through the sram driver, 
while still retaining some areas for special purposes, like the smp-trampoline 
in my case.

From my reading of platsmp.c, it looks like offset+0x4 starts the so called 
boot-registesr, which get the smp-start-address written to.

So I guess it all depends on what is contained in the rest of the sysram. If 
it is all covered with such special registers or other special uses, the code 
below is fine. But if the most of the area is just general purpose sram, a 
solution like on rockchip might be nicer - i.e. handling the sysram via the 
sram driver and declaring a reserved section for the boot registers.

So, depending on the above:
Acked-by: Heiko Stuebner he...@sntech.de


Heiko

 
   Arnd
 
   .../devicetree/bindings/arm/samsung-boards.txt |   11 +++
   arch/arm/boot/dts/exynos4210-universal_c210.dts|9 ++
   arch/arm/boot/dts/exynos4210.dtsi  |   10 ++
   arch/arm/boot/dts/exynos4x12.dtsi  |   10 ++
   arch/arm/boot/dts/exynos5.dtsi |5 +
   arch/arm/boot/dts/exynos5250.dtsi  |5 +
   arch/arm/boot/dts/exynos5420.dtsi  |5 +
   arch/arm/mach-exynos/exynos.c  |  104
    arch/arm/mach-exynos/include/mach/map.h   
   |7 --
   9 files changed, 95 insertions(+), 71 deletions(-)
  
  diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt
  b/Documentation/devicetree/bindings/arm/samsung-boards.txt index
  2168ed31e1b0..f79710eb7e79 100644
  --- a/Documentation/devicetree/bindings/arm/samsung-boards.txt
  +++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
  
  @@ -7,6 +7,17 @@ Required root node properties:
   (a) samsung,smdkv310 - for Samsung's SMDKV310 eval board.
   (b) samsung,exynos4210  - for boards based on Exynos4210 SoC.
  
  +- sysram node, specifying the type (secure or non-secure) of SYSRAM
  +   - compatible: following types are supported
  +   samsung,exynos4210-sysram : Secure SYSRAM
  +   samsung,exynos4210-sysram-ns : Non-secure SYSRAM
  +   - reg: address of SYSRAM bank
  +
  +   sysram@0202 {
  +   compatible = samsung,exynos4210-sysram;
  +   reg = 0x0202 0x1000;
  +   };
  +
  
   Optional:
   - firmware node, specifying presence and type of secure firmware:
   - compatible: only samsung,secure-firmware is currently
   supported
  
  diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
  b/arch/arm/boot/dts/exynos4210-universal_c210.dts index
  63e34b24b04f..cf4158728108 100644
  --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
  +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
  @@ -28,6 +28,15 @@
  
  bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw 
rootwait
  earlyprintk panic=5 maxcpus=1;
  };
  
  +   sysram@0202 {
  +   status = disabled;
  +   };
  +
  +   sysram@02025000 {
  +   compatible = samsung,exynos4210-sysram;
  +   reg = 0x02025000 0x1000;
  +   };
  +
  
  mct@1005 {
  
  compatible = none;
  
  };
  
  diff --git a/arch/arm/boot/dts/exynos4210.dtsi
  b/arch/arm/boot/dts/exynos4210.dtsi index cacf6140dd2f..a3f4bba099e6
  100644
  --- a/arch/arm/boot/dts/exynos4210.dtsi
  +++ b/arch/arm/boot/dts/exynos4210.dtsi
  @@ -31,6 +31,16 @@
  
  pinctrl2 = pinctrl_2;
  
  };
  
  +   sysram@0202 {
  +   compatible = samsung,exynos4210-sysram;
  +   reg = 0x0202 0x1000;
  +   };
  +
  +   sysram-ns@0203F000 {
  +   compatible = samsung,exynos4210-sysram-ns;
  +   reg = 0x0203F000 0x1000;
  +   };
  +
  
  pd_lcd1: lcd1-power-domain@10023CA0 {
  
  compatible = samsung,exynos4210-pd;
  reg = 0x10023CA0 0x20;
  
  diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
  b/arch/arm/boot/dts/exynos4x12.dtsi index c4a9306f8529..d57e3120223f
  100644
  --- a/arch/arm/boot/dts/exynos4x12.dtsi
  +++ b/arch/arm/boot/dts/exynos4x12.dtsi
  @@ -37,6 +37,16 @@
  
  interrupts = 2 2, 3 2, 18 2, 19 2;
  
  };
  
  +   sysram@0202 

Re: [GIT PULL 5/6] Samsung PM updates for v3.15

2014-04-03 Thread Heiko Stübner
Am Donnerstag, 3. April 2014, 18:24:25 schrieb Kukjin Kim:
 Mike Turquette wrote:
  Quoting Kukjin Kim (2014-04-01 21:25:45)
  
   Heiko Stübner wrote:
Hi Arnd,

Am Samstag, 29. März 2014, 02:47:33 schrieb Arnd Bergmann:
 On Friday 28 March 2014, Kukjin Kim wrote:
  Kukjin Kim wrote:
   On 03/19/14 13:01, Mike Turquette wrote:
   
   Thanks :-)
   
Acked-by: Mike Turquettemturque...@linaro.org
   
   It's time. Please pull this [5/6] and [GIT PULL 6/6] Samsung
   clk-s3c24xx updates for v3.15.
  
  Hi Arnd, Olof and Mike,
  
  Still I cannot see this in arm-soc. Any problems?
 
 Sorry, I didn't have this one on my radar any more, merged into
 next/drivers now.

maybe you could also take a look at the depending [GIT PULL 6/6]
  
  Samsung
  
clk-
s3c24xx updates for v3.15 we walked about at the beginning of the
week? :-)
   
   Yeah, so I've informed that [5/6] and [6/6] is needed...
   
   Arnd, Olof and Mike,
   
   Probably you guys missed [6/6] Samsung clk-s3c24xx updates when
  
  dependency
  
   with [5/6] has been cleared but since it's already 3.15 merge window,
  
  I'm
  
   not sure it can be sent to Linus in this time...
  
  Both PRs were Acked by me, so no problems from my end. Pretty late for
  3.15 though.
 
 Yeah, I know. I mean 'Arnd, Olof and Kevin' ;-)
 
 BTW, hmm...I know, it's too late for v3.15...so...unfortunately maybe I
 should queue it for v3.16?...

I guess this would be the best option. I should also be able to finish the 
s3c2410/2440/2442 conversion until then, which needs a bit more work.


Heiko
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Re: [GIT PULL 5/6] Samsung PM updates for v3.15

2014-03-29 Thread Heiko Stübner
Hi Arnd,

Am Samstag, 29. März 2014, 02:47:33 schrieb Arnd Bergmann:
 On Friday 28 March 2014, Kukjin Kim wrote:
  Kukjin Kim wrote:
   On 03/19/14 13:01, Mike Turquette wrote:
   
   Thanks :-)
   
Acked-by: Mike Turquettemturque...@linaro.org
   
   It's time. Please pull this [5/6] and [GIT PULL 6/6] Samsung
   clk-s3c24xx updates for v3.15.
  
  Hi Arnd, Olof and Mike,
  
  Still I cannot see this in arm-soc. Any problems?
 
 Sorry, I didn't have this one on my radar any more, merged into
 next/drivers now.

maybe you could also take a look at the depending [GIT PULL 6/6] Samsung clk-
s3c24xx updates for v3.15 we walked about at the beginning of the week? :-)


Thanks
Heiko
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Re: [PATCH 3/3] ARM: S3C24XX: select COMMON_CLK_SAMSUNG for S3C24XX

2014-02-26 Thread Heiko Stübner
Am Donnerstag, 27. Februar 2014, 10:48:26 schrieb Pankaj Dubey:
 On 02/27/2014 09:16 AM, Mike Turquette wrote:
  Quoting Pankaj Dubey (2014-02-25 21:24:07)
  
  CC: Ben Dooks ben-li...@fluff.org
  CC: Kukjin Kim kgene@samsung.com
  CC: Russell King li...@arm.linux.org.uk
  Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
  ---
  
arch/arm/mach-s3c24xx/Kconfig |3 +++
1 file changed, 3 insertions(+)
  
  diff --git a/arch/arm/mach-s3c24xx/Kconfig
  b/arch/arm/mach-s3c24xx/Kconfig
  index 80373da..5cf82a1 100644
  --- a/arch/arm/mach-s3c24xx/Kconfig
  +++ b/arch/arm/mach-s3c24xx/Kconfig
  @@ -40,6 +40,7 @@ config CPU_S3C2410
  
config CPU_S3C2412

   bool SAMSUNG S3C2412
   select COMMON_CLK
  
  +   select COMMON_CLK_SAMSUNG
  
  I guess this depends on Heiko's [PATCH 00/12] ARM: S3C24XX: convert
  s3c2410, s3c2440 s3c2442 to common clock framework series?
  
  Regards,
  Mike
 
 Yes, this series is based on latest kgene/for-next branch where Heiko's
 series is merged.

Just to clarify, converted are the s3c2416/s3c2443 (first series) and s3c2412 
(second series), because the clockout for s3c2410 etc seems to need a bit more 
work. I've just moved two comon patches (shared plls and a platform change) 
from the s3c2410,et-all series into the s3c2412 one.

Both of these series are merged in kgenes tree as mentioned. And at this point 
I'm not sure if I will have the time to respin the s3c2410 series for 3.15.
Which might also be good to let all the other series touching samsung clock 
code settle.


Heiko

 
   select CPU_ARM926T
   select CPU_LLSERIAL_S3C2440
   select S3C2412_COMMON_CLK
  
  @@ -51,6 +52,7 @@ config CPU_S3C2412
  
config CPU_S3C2416

   bool SAMSUNG S3C2416/S3C2450
   select COMMON_CLK
  
  +   select COMMON_CLK_SAMSUNG
  
   select CPU_ARM926T
   select CPU_LLSERIAL_S3C2440
   select S3C2416_PM if PM
  
  @@ -89,6 +91,7 @@ config CPU_S3C244X
  
config CPU_S3C2443

   bool SAMSUNG S3C2443
   select COMMON_CLK
  
  +   select COMMON_CLK_SAMSUNG
  
   select CPU_ARM920T
   select CPU_LLSERIAL_S3C2440
   select S3C2443_COMMON_CLK
  
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Re: [PATCH 0/2] ARM: SAMSUNG: move all arches to generic uncompress.h

2014-02-25 Thread Heiko Stübner
Am Sonntag, 16. Februar 2014, 18:32:24 schrieb Heiko Stübner:
 On 2014-01-06 Sachin Kamat posted two patches converting Exynos to use
 the generic uncompress.h.
 
 But in fact all Samsung platforms can go this route, as all Samsung
 uncompress.h files are simply used to set up the serial port.
 
 As the original patches were not yet applied, this series includes the
 original Exynos-specific change.
 
 Tested on a s3c2416 and s3c2442 based machine.

ping?


Thanks
Heiko
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Re: [PATCH 0/2] ARM: SAMSUNG: move all arches to generic uncompress.h

2014-02-25 Thread Heiko Stübner
Am Dienstag, 25. Februar 2014, 21:11:09 schrieb Sachin Kamat:
  Hi Heiko,
 
 On 25 February 2014 19:47, Heiko Stübner he...@sntech.de wrote:
  Am Sonntag, 16. Februar 2014, 18:32:24 schrieb Heiko Stübner:
  On 2014-01-06 Sachin Kamat posted two patches converting Exynos to use
  the generic uncompress.h.
  
  But in fact all Samsung platforms can go this route, as all Samsung
  uncompress.h files are simply used to set up the serial port.
  
  As the original patches were not yet applied, this series includes the
  original Exynos-specific change.
  
  Tested on a s3c2416 and s3c2442 based machine.
  
  ping?
 
 Kukjin has already applied my 2 patches doing this for Exynos.
 You might need to rebase your patches on top of his for-next and re-send.

now I've seen that he applied them yesterday ... will rebase mine as 
suggested.


Heiko
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[PATCH v2 0/2] ARM: SAMSUNG: remove the rest of local uncompress.h files

2014-02-25 Thread Heiko Stübner
Two patches from Sachin Kamat already removed the Exynos-uncompress.h .
But in fact all Samsung platforms can use the generic uncompress code
without needing local implementation.

Therefore this two-part series removes the rest of the uncompress.h files
from all Samsung platforms.

Tested on a s3c2416 and s3c2442 based machine.

The patches should be applied on top of the patches from Sachin Kamat in
the v3.15-next/cleanup-samsung branch in the linux-samsung.git


Heiko Stuebner (2):
  ARM: SAMSUNG: use generic uncompress.h
  ARM: SAMSUNG: remove all custom uncompress.h

 arch/arm/Kconfig.debug  |   4 +-
 arch/arm/mach-s3c24xx/include/mach/uncompress.h |  57 
 arch/arm/mach-s3c64xx/include/mach/uncompress.h |  31 -
 arch/arm/mach-s5p64x0/include/mach/uncompress.h |  34 -
 arch/arm/mach-s5pc100/include/mach/uncompress.h |  30 
 arch/arm/mach-s5pv210/include/mach/uncompress.h |  28 
 arch/arm/plat-samsung/include/plat/uncompress.h | 175 
 7 files changed, 2 insertions(+), 357 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/uncompress.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/uncompress.h

-- 
1.8.5.3


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