Re: [RFC PATCH v8 10/10] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

2015-10-28 Thread Jaehoon Chung
Hi, All.

Is there any other opinion about this patch?


Best Regards,
Jaehoon Chung

On 09/16/2015 03:43 PM, Shawn Lin wrote:
> DesignWare MMC Controller's transfer mode should be decided
> at runtime instead of compile-time. So we remove this config
> option and read dw_mmc's register to select DMA master.
> 
> Signed-off-by: Shawn Lin <shawn@rock-chips.com>
> ---
> 
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/configs/zx_defconfig | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
> index b200bb0..ab683fb 100644
> --- a/arch/arm/configs/zx_defconfig
> +++ b/arch/arm/configs/zx_defconfig
> @@ -83,7 +83,6 @@ CONFIG_MMC=y
>  CONFIG_MMC_UNSAFE_RESUME=y
>  CONFIG_MMC_BLOCK_MINORS=16
>  CONFIG_MMC_DW=y
> -CONFIG_MMC_DW_IDMAC=y
>  CONFIG_EXT2_FS=y
>  CONFIG_EXT4_FS=y
>  CONFIG_EXT4_FS_POSIX_ACL=y
> 

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Re: [RFC PATCH v8 09/10] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC

2015-10-28 Thread Jaehoon Chung
Hi, All.

Is there any other opinion about this patch?

Best Regards,
Jaehoon Chung

On 09/16/2015 03:43 PM, Shawn Lin wrote:
> DesignWare MMC Controller's transfer mode should be decided
> at runtime instead of compile-time. So we remove this config
> option and read dw_mmc's register to select DMA master.
> 
> Signed-off-by: Shawn Lin <shawn@rock-chips.com>
> ---
> 
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/configs/multi_v7_defconfig | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/configs/multi_v7_defconfig 
> b/arch/arm/configs/multi_v7_defconfig
> index 03deb7f..ad929ea 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -539,7 +539,6 @@ CONFIG_MMC_ATMELMCI=y
>  CONFIG_MMC_MVSDIO=y
>  CONFIG_MMC_SDHI=y
>  CONFIG_MMC_DW=y
> -CONFIG_MMC_DW_IDMAC=y
>  CONFIG_MMC_DW_PLTFM=y
>  CONFIG_MMC_DW_EXYNOS=y
>  CONFIG_MMC_DW_ROCKCHIP=y
> 

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[PATCHv2] ARM: dts: change the compatible from exynos5250 to exynos5420 for mshc

2015-10-22 Thread Jaehoon Chung
Exynos3250 and exnos5250 are some differences in Mobile Storage Host.
(For example, exynos3250 support the HS400 mode, but exynos5250 doesn't
support it.)
Exynos3250 can perform the similar function with exynos5420 compatible.
So this patch changes the compatible from exynos5250 to exynos5420
for mshc.

Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
Changelog v2:
- Drop "mmc: dw_mmc: exynos: Add the exynos3250 compatible" patch.
- Describe commit-message more detailedly than before.
- Change to exynos5420, not add new compatible (exynos3250).

 arch/arm/boot/dts/exynos3250.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def4..2f30d63 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -333,7 +333,7 @@
};
 
mshc_0: mshc@1251 {
-   compatible = "samsung,exynos5250-dw-mshc";
+   compatible = "samsung,exynos5420-dw-mshc";
reg = <0x1251 0x1000>;
interrupts = <0 142 0>;
clocks = < CLK_SDMMC0>, < CLK_SCLK_MMC0>;
@@ -345,7 +345,7 @@
};
 
mshc_1: mshc@1252 {
-   compatible = "samsung,exynos5250-dw-mshc";
+   compatible = "samsung,exynos5420-dw-mshc";
reg = <0x1252 0x1000>;
interrupts = <0 143 0>;
clocks = < CLK_SDMMC1>, < CLK_SCLK_MMC1>;
-- 
1.9.1

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Re: [PATCH 1/2] mmc: dw_mmc: exynos: Add the exynos3250 compatible

2015-10-21 Thread Jaehoon Chung
On 10/22/2015 12:51 PM, Krzysztof Kozlowski wrote:
> On 22.10.2015 11:54, Jaehoon Chung wrote:
>> Hi, Krzysztof.
>>
>> On 10/22/2015 09:06 AM, Krzysztof Kozlowski wrote:
>>> On 21.10.2015 15:39, Jaehoon Chung wrote:
>>>> To check more exactly, add the exynos3250 compatible.
>>>> Not use exynos5250 compatibility.
>>>
>>> Hi,
>>>
>>> I can't find any difference between old and new compatible. Maybe I am
>>> missing something? Maybe there is a difference for these devices?
>>
>> Sorry, I needs to add more explanation about changing compatible.
>> Exynos3250 has more registers than exynos5250 in dwmmc IP.
>> Now, we used dwmmc controller with exynos5250 compatible.
>> Then some codes can't run in dw-mmc.c, if SoC is exynos3250.
>> For example, there is the checking point in dw_mci_exynos_config_hs400().
>>
>> static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
>> {
>> struct dw_mci_exynos_priv_data *priv = host->priv;
>> u32 dqs, strobe;
>>
>> /*
>>  * Not supported to configure register
>>  * related to HS400
>>  */
>> if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
>> return;
>>
>> dqs = priv->saved_dqs_en;
>> strobe = priv->saved_strobe_ctrl;
>>
>> It can't use this feature with exynos5250 compatible.
> 
> Ahh, I see it now. I missed that context and commit message wasn't
> explaining this real reason. This real reason - supporting HS400 or
> other features not present on Exynos5250 - was not mentioned.

Right, it's not enough to explain why needs this patch.

> 
> The new compatible make sense now... but I am wondering if instead just
> "samsung,exynos5420-dw-mshc" should be used? I think it would give the
> same result as your change and if new compatible is not required then it
> will be better not to add it.

I need to check whether it can be used with "samsung,exynos5420-dw-mshc".
If you don't want to add new compatible, then i will check Exynos5420 TRM.
Maybe, i think it can be used with it.

Is it good that use more exact compatible?

Best Regards,
Jaehoon Chung

> 
> Best regards,
> Krzysztof
> 
>>
>> Does it need to change the compatible from exynos5250 to exynos3250?
>>
>> Beset Regards,
>> Jaehoon Chung
>>
>>>
>>> Anyway if the code is the same then it should use exactly the same
>>> compatible.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>>>
>>>> Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++
>>>>  drivers/mmc/host/dw_mmc-exynos.c | 7 +++
>>>>  2 files changed, 9 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
>>>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>>>> index aad9844..cd22ac9 100644
>>>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>>>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>>>> @@ -22,6 +22,8 @@ Required Properties:
>>>>  specific extensions.
>>>>- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
>>>>  specific extensions having an SMU.
>>>> +  - "samsung,exynos3250-dw-mshc": for controllers with Samsung Exynos3250
>>>> +specific extensions.
>>>>  
>>>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card 
>>>> interface
>>>>unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
>>>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>>>> b/drivers/mmc/host/dw_mmc-exynos.c
>>>> index 1e75309..1c96218 100644
>>>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>>>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>>>> @@ -32,6 +32,7 @@ enum dw_mci_exynos_type {
>>>>DW_MCI_TYPE_EXYNOS5420_SMU,
>>>>DW_MCI_TYPE_EXYNOS7,
>>>>DW_MCI_TYPE_EXYNOS7_SMU,
>>>> +  DW_MCI_TYPE_EXYNOS3250,
>>>>  };
>>>>  
>>>>  /* Exynos implementation specific driver private data */
>>>> @@ -73,6 +74,9 @@ static struct dw_mci_exynos_compatible {
>>>>}, {
>>>>.compatible = "samsung,exynos7-dw-m

Re: [PATCH 1/2] mmc: dw_mmc: exynos: Add the exynos3250 compatible

2015-10-21 Thread Jaehoon Chung
Hi, Krzysztof.

On 10/22/2015 09:06 AM, Krzysztof Kozlowski wrote:
> On 21.10.2015 15:39, Jaehoon Chung wrote:
>> To check more exactly, add the exynos3250 compatible.
>> Not use exynos5250 compatibility.
> 
> Hi,
> 
> I can't find any difference between old and new compatible. Maybe I am
> missing something? Maybe there is a difference for these devices?

Sorry, I needs to add more explanation about changing compatible.
Exynos3250 has more registers than exynos5250 in dwmmc IP.
Now, we used dwmmc controller with exynos5250 compatible.
Then some codes can't run in dw-mmc.c, if SoC is exynos3250.
For example, there is the checking point in dw_mci_exynos_config_hs400().

static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
{
struct dw_mci_exynos_priv_data *priv = host->priv;
u32 dqs, strobe;

/*
 * Not supported to configure register
 * related to HS400
 */
if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
return;

dqs = priv->saved_dqs_en;
strobe = priv->saved_strobe_ctrl;

It can't use this feature with exynos5250 compatible.

Does it need to change the compatible from exynos5250 to exynos3250?

Beset Regards,
Jaehoon Chung

> 
> Anyway if the code is the same then it should use exactly the same
> compatible.
> 
> Best regards,
> Krzysztof
> 
>>
>> Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
>> ---
>>  Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++
>>  drivers/mmc/host/dw_mmc-exynos.c | 7 +++
>>  2 files changed, 9 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index aad9844..cd22ac9 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -22,6 +22,8 @@ Required Properties:
>>specific extensions.
>>  - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
>>specific extensions having an SMU.
>> +- "samsung,exynos3250-dw-mshc": for controllers with Samsung Exynos3250
>> +  specific extensions.
>>  
>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card 
>> interface
>>unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 1e75309..1c96218 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -32,6 +32,7 @@ enum dw_mci_exynos_type {
>>  DW_MCI_TYPE_EXYNOS5420_SMU,
>>  DW_MCI_TYPE_EXYNOS7,
>>  DW_MCI_TYPE_EXYNOS7_SMU,
>> +DW_MCI_TYPE_EXYNOS3250,
>>  };
>>  
>>  /* Exynos implementation specific driver private data */
>> @@ -73,6 +74,9 @@ static struct dw_mci_exynos_compatible {
>>  }, {
>>  .compatible = "samsung,exynos7-dw-mshc-smu",
>>  .ctrl_type  = DW_MCI_TYPE_EXYNOS7_SMU,
>> +}, {
>> +.compatible = "samsung,exynos3250-dw-mshc",
>> +.ctrl_type  = DW_MCI_TYPE_EXYNOS3250,
>>  },
>>  };
>>  
>> @@ -467,6 +471,7 @@ static int dw_mci_exynos_execute_tuning(struct 
>> dw_mci_slot *slot)
>>  } while (start_smpl != smpl);
>>  
>>  found = dw_mci_exynos_get_best_clksmpl(candiates);
>> +
>>  if (found >= 0) {
>>  dw_mci_exynos_set_clksmpl(host, found);
>>  priv->tuned_sample = found;
>> @@ -520,6 +525,8 @@ static const struct of_device_id dw_mci_exynos_match[] = 
>> {
>>  .data = _drv_data, },
>>  { .compatible = "samsung,exynos7-dw-mshc-smu",
>>  .data = _drv_data, },
>> +{ .compatible = "samsung,exynos3250-dw-mshc",
>> +.data = _drv_data, },
>>  {},
>>  };
>>  MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
>>
> 
> 

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[PATCH 2/2] ARM: dts: change the compatible from exynos5250 to exynos3250

2015-10-21 Thread Jaehoon Chung
To use more excatly, change compatible from exynos5250 to exynos3250.
Exynos3250 and exnos5250 are some difference.

Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
 arch/arm/boot/dts/exynos3250.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def4..05ed242 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -333,7 +333,7 @@
};
 
mshc_0: mshc@1251 {
-   compatible = "samsung,exynos5250-dw-mshc";
+   compatible = "samsung,exynos3250-dw-mshc";
reg = <0x1251 0x1000>;
interrupts = <0 142 0>;
clocks = < CLK_SDMMC0>, < CLK_SCLK_MMC0>;
@@ -345,7 +345,7 @@
};
 
mshc_1: mshc@1252 {
-   compatible = "samsung,exynos5250-dw-mshc";
+   compatible = "samsung,exynos3250-dw-mshc";
reg = <0x1252 0x1000>;
interrupts = <0 143 0>;
clocks = < CLK_SDMMC1>, < CLK_SCLK_MMC1>;
-- 
1.9.1

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[PATCH 1/2] mmc: dw_mmc: exynos: Add the exynos3250 compatible

2015-10-21 Thread Jaehoon Chung
To check more exactly, add the exynos3250 compatible.
Not use exynos5250 compatibility.

Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
 Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++
 drivers/mmc/host/dw_mmc-exynos.c | 7 +++
 2 files changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index aad9844..cd22ac9 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -22,6 +22,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
  specific extensions having an SMU.
+   - "samsung,exynos3250-dw-mshc": for controllers with Samsung Exynos3250
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 1e75309..1c96218 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -32,6 +32,7 @@ enum dw_mci_exynos_type {
DW_MCI_TYPE_EXYNOS5420_SMU,
DW_MCI_TYPE_EXYNOS7,
DW_MCI_TYPE_EXYNOS7_SMU,
+   DW_MCI_TYPE_EXYNOS3250,
 };
 
 /* Exynos implementation specific driver private data */
@@ -73,6 +74,9 @@ static struct dw_mci_exynos_compatible {
}, {
.compatible = "samsung,exynos7-dw-mshc-smu",
.ctrl_type  = DW_MCI_TYPE_EXYNOS7_SMU,
+   }, {
+   .compatible = "samsung,exynos3250-dw-mshc",
+   .ctrl_type  = DW_MCI_TYPE_EXYNOS3250,
},
 };
 
@@ -467,6 +471,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot 
*slot)
} while (start_smpl != smpl);
 
found = dw_mci_exynos_get_best_clksmpl(candiates);
+
if (found >= 0) {
dw_mci_exynos_set_clksmpl(host, found);
priv->tuned_sample = found;
@@ -520,6 +525,8 @@ static const struct of_device_id dw_mci_exynos_match[] = {
.data = _drv_data, },
{ .compatible = "samsung,exynos7-dw-mshc-smu",
.data = _drv_data, },
+   { .compatible = "samsung,exynos3250-dw-mshc",
+   .data = _drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.9.1

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Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

2015-10-21 Thread Jaehoon Chung
Hi, Anand.

On 10/14/2015 12:58 PM, Anand Moon wrote:
> hi Krzysztof,
> 
> On 14 October 2015 at 05:29, Krzysztof Kozlowski
> <k.kozlow...@samsung.com> wrote:
>> On 14.10.2015 01:27, Anand Moon wrote:
>>> Hi Krzysztof,
>>>
>>> On 13 October 2015 at 09:13, Krzysztof Kozlowski
>>> <k.kozlow...@samsung.com> wrote:
>>>>
>>>> On 13.10.2015 12:08, Anand Moon wrote:
>>>>> Hi Krzysztof,
>>>>>
>>>>> On 13 October 2015 at 05:44, Krzysztof Kozlowski
>>>>> <k.kozlow...@samsung.com> wrote:
>>>>>> On 13.10.2015 00:32, Anand Moon wrote:
>>>>>>> Hi Krzysztof,
>>>>>>>
>>>>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski
>>>>>>> <k.kozlow...@samsung.com> wrote:
>>>>>>>> On 12.10.2015 00:46, Anand Moon wrote:
>>>>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s 
>>>>>>>>> (SDR104)
>>>>>>>>
>>>>>>>> This description is not entirely correct. The MMC driver already
>>>>>>>> supports these UHS speeds (you did not any code) so you rather enabled
>>>>>>>> it (description of bindings says "is supported").
>>>>>>>>
>>>>>>>> You mentioned DDR50 but I don't see respective property below.
>>>>>>>>
>>>>>>>> How do you know that these modes are really supported? I don't know. 
>>>>>>>> Can
>>>>>>>> you convince me?
>>>>>>>
>>>>>>> Setting this DDR50 capability give me this error. That's the reason to
>>>>>>> drop this capability.
>>>>>>
>>>>>> But you mentioned it in commit message! "Added support for UHS-I ...
>>>>>> (DDR50)"
>>>>>>
>>>>>> In the same time dropping DDR50 is not an sufficient proof that "SDR50
>>>>>> and SDR104 are really supported".
>>>>>>
>>>>>
>>>>> These changes are related to the microSD card capabilities.
>>>>> So SDR50 have better frequency over DDR50. On the same Sandisk card.
>>>>>
>>>>> When the card select the capability for DDR50
>>>>> ---
>>>>> [4.001477] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot
>>>>> req 5000Hz, actual 5000HZ div = 0)
>>>>> [4.001604] mmc1: new ultra high speed DDR50 SDHC card at address 
>>>>> [4.004505] mmcblk0: mmc1: SL32G 29.7 GiB
>>>>> [4.009179] mmcblk0: error -110 sending status command, retrying
>>>>> [4.009271] mmcblk0: error -115 sending stop command, original cmd
>>>>> response 0x900, card status 0x900
>>>>> [4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8,
>>>>> cmd response 0x900, card status 0x0
>>>>> [4.025563] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot
>>>>> req 40Hz, actual 396825HZ div = 63)
>>>>> [4.067770] Console: switching to colour frame buffer device 274x77
>>>>> [4.098782] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot
>>>>> req 5000Hz, actual 5000HZ div = 0)
>>>>> [4.099692] mmc1: tried to reset card
>>>>> [4.101332]  mmcblk0: p1 p2

I found this issue that produced on your board.
I will send the patch and test DDR50 on your board.

Best Regards,
Jaehoon Chung

>>>>>
>>>>>
>>>>> When the card select the capability for SDR50
>>>>> -
>>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot req
>>>>> 1Hz, actual 1HZ div = 0)
>>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address 
>>>>> [ 2.455984] mmcblk0: mmc1: SL32G 29.7 GiB
>>>>> [ 2.461743] mmcblk0: p1 p2
>>>>>
>>>>> Which will relate to better read/write speed.
>>>>
>>>> Which is not an answer to my question. To none of my previous questions.
>>>>
>>>
>>> Basically UHS-I capability  (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50,
>>> sd-uhs-sdr104) help tune speed s

Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

2015-10-13 Thread Jaehoon Chung
On 10/14/2015 10:15 AM, Krzysztof Kozlowski wrote:
> On 14.10.2015 10:06, Alim Akhtar wrote:
>> +Doug
>> Hello,
>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50
>> and SDR104 modes.
>>
>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html
>>
>> What I remember is, one need to set "broken-cd" property also in order
>> to make it work because of the vqmmc and vmmc connection on board. I
>> didn't find the link right now, but you can search on the web, there
>> was a long discussion about handling this.
>> Have not checked it recently, so not sure if this got broken somehow.
>>
> 
> Please, don't top post.
> 
> I am not a SD/MMC specialist (I do not feel enough confident in its
> internals) but the datasheet for 5422 does not mention UHS. However it
> mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This
> does not look like UHS...

You're right. It's not UHS mode. it mentions eMMC's HS400 mode.
UHS and HS400 are difference mode.

eMMC mode are supported 

> https://www.sdcard.org/developers/overview/bus_speed/
> This of course is not a definite proof that 5422 does not support UHS. I
> am just saying that I couldn't find any information that *it does*.

Well, I think you want to know whether it supported or not.
Then you can find the information at User manual.
In mobile storage part of User manual, it described the overview.
Mobile storage host supports these specification:
- Secure Digital memory (SD memory version 3.0)
- Secure Digital I/O SDIO (SDIO version 3.0)
- etc...

SD3.0 is supported UHS-I mode. 
If user manual of exynos5422 is mentioned this specification, it should be 
supported UHS-I mode.

If my understanding is wrong, let me know, plz.

Best Regards,
Jaehoon Chung

> 
> Best regards,
> Krzysztof
> 
> 

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Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

2015-10-12 Thread Jaehoon Chung
On 10/12/2015 07:46 PM, Anand Moon wrote:
> Hi Krzysztof,
> 
> On 12 October 2015 at 11:14, Krzysztof Kozlowski
> <k.kozlow...@samsung.com> wrote:
>> On 12.10.2015 00:46, Anand Moon wrote:
>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
>>
>> This description is not entirely correct. The MMC driver already
>> supports these UHS speeds (you did not any code) so you rather enabled
>> it (description of bindings says "is supported").
>>
>> You mentioned DDR50 but I don't see respective property below.
> Looks like I missed it, I will add this in the next patch,
>>
>> How do you know that these modes are really supported? I don't know. Can
>> you convince me?
>>
> 
>>>
>>> Signed-off-by: Anand Moon <linux.am...@gmail.com>
>>>
>>> ---
>>> Changes based on 
>>> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
>>> v4.4-next/dt-samsung branch
>>>
>>> Changes Fixed the UHS-I bus speed detedtion on cold boot.
>>
>> I don't get what is exactly fixed here. What was the error? What is the
>> outcome of this fix? The log below is before or after?
>>
>> Best regards,
>> Krzysztof
>>
>>>
>>> [2.439806] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot req 
>>> 1Hz, actual 1HZ div = 0)
>>> [2.449729] mmc1: new ultra high speed SDR50 SDHC card at address 
>>> [2.455984] mmcblk0: mmc1: SL32G 29.7 GiB
>>> [2.461743]  mmcblk0: p1 p2
>>
>>> ---
>>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 
>>> b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>> index 58c06d3..ba4a87b 100644
>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>> @@ -364,6 +364,10 @@
>>>   pinctrl-0 = <_clk _cmd _cd _bus4>;
>>>   bus-width = <4>;
>>>   cap-sd-highspeed;
>>> + sd-uhs-sdr12;
>>> + sd-uhs-sdr25;
>>> + sd-uhs-sdr50;
>>> + sd-uhs-sdr104;
>>>  };
>>>
>>>  _0 {
>>>
>>
> 
> Changes were made to support Sandisk Ultra UHS-I class 10 card support.
> OdroidXU3/XU4 board would not boot up using this card.
> 
> Depending on the capability of the UHS-I card, the speed of the card
> is selected.
> I have just added the enhance capability feature to support them.
> 
> On warm boot: i.e reboot of the board.
> [4.649073] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot
> req 5000Hz, actual 5000HZ div = 0)
> [4.657555] mmc1: new high speed SDHC card at address 
> [4.663787] mmcblk0: mmc1: SL32G 29.7 GiB
> [4.669206]  mmcblk0: p1 p2
> 
> On cold boot:: ie: power on the board.
> 
> [4.630237] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot
> req 1Hz, actual 1HZ div = 0)
> [4.639820] mmc1: new ultra high speed SDR50 SDHC card at address 
> [4.646266] mmcblk0: mmc1: SL32G 29.7 GiB
> [4.650293] IRQ56 no longer affine to CPU7
> [4.650581] CPU7: shutdown
> [4.658293]  mmcblk0: p1 p2
> 
> Note: Their is need to reset the PMIC
> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
>  to support this feature consistently on every reboot.

I don't understand...why needs to reset?
I know it needs to switch the voltage, doesn't it?

Best Regards,
Jaehoon Chung

> 
> -Anand Moon
> 

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Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

2015-10-12 Thread Jaehoon Chung
On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote:
> W dniu 12.10.2015 o 19:46, Anand Moon pisze:
>> Hi Krzysztof,
>>
>> On 12 October 2015 at 11:14, Krzysztof Kozlowski
>> <k.kozlow...@samsung.com> wrote:
>>> On 12.10.2015 00:46, Anand Moon wrote:
>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
>>>
>>> This description is not entirely correct. The MMC driver already
>>> supports these UHS speeds (you did not any code) so you rather enabled
>>> it (description of bindings says "is supported").
>>>
>>> You mentioned DDR50 but I don't see respective property below.
>> Looks like I missed it, I will add this in the next patch,
>>>
>>> How do you know that these modes are really supported? I don't know. Can
>>> you convince me?
> 
> That part was not answered...

In my experiment, it needs two requirements.
One is that Host controller supported UHS-I mode or others, other is SD-card.
In Anand's commit message, there is no information for this.

And 50MB/s or 104MB/s is not real performance. (Just theoretical values)
It seems that can get those performances.

> 
>>>
>>
>>>>
>>>> Signed-off-by: Anand Moon <linux.am...@gmail.com>
>>>>
>>>> ---
>>>> Changes based on 
>>>> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
>>>> v4.4-next/dt-samsung branch
>>>>
>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot.
>>>
>>> I don't get what is exactly fixed here. What was the error? What is the
>>> outcome of this fix? The log below is before or after?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>>>
>>>> [2.439806] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot req 
>>>> 1Hz, actual 1HZ div = 0)
>>>> [2.449729] mmc1: new ultra high speed SDR50 SDHC card at address 
>>>> [2.455984] mmcblk0: mmc1: SL32G 29.7 GiB
>>>> [2.461743]  mmcblk0: p1 p2
>>>
>>>> ---
>>>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 
>>>>  1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 
>>>> b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>> index 58c06d3..ba4a87b 100644
>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>> @@ -364,6 +364,10 @@
>>>>   pinctrl-0 = <_clk _cmd _cd _bus4>;
>>>>   bus-width = <4>;
>>>>   cap-sd-highspeed;
>>>> + sd-uhs-sdr12;
>>>> + sd-uhs-sdr25;
>>>> + sd-uhs-sdr50;
>>>> + sd-uhs-sdr104;
>>>>  };
>>>>
>>>>  _0 {
>>>>
>>>
>>
>> Changes were made to support Sandisk Ultra UHS-I class 10 card support.
>> OdroidXU3/XU4 board would not boot up using this card.
>>
>> Depending on the capability of the UHS-I card, the speed of the card
>> is selected.
>> I have just added the enhance capability feature to support them.
> 
> So without these capabilities mentioned microSD card cannot be used? So
> I have a UHS-I card, that one exactly:
> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC
> 
> It works:
> [2.628365] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot req
> 5000Hz, actual 5000HZ div = 0)
> [2.693296] mmc1: new high speed SDHC card at address 0001
> [2.703867] mmcblk0: mmc1:0001 0 29.8 GiB
> [2.708406]  mmcblk0: p1 p2
> 
> This is just HS mode.
> 
> In the same time isn't UHS-I backward compatible? Your report seems
> surprising.

Right. it's not issue. just working as lower mode than its capability.

Best Regards,
Jaehoon Chung

> 
> Best regards,
> Krzysztof
> 
>>
>> On warm boot: i.e reboot of the board.
>> [4.649073] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot
>> req 5000Hz, actual 5000HZ div = 0)
>> [4.657555] mmc1: new high speed SDHC card at address 
>> [4.663787] mmcblk0: mmc1: SL32G 29.7 GiB
>> [4.669206]  mmcblk0: p1 p2
>>
>> On cold boot:: ie: power on the board.
>>
>> [4.630237] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot
>> req 1Hz, actual 1HZ div = 0)
>> [4.639820] mmc1: new ultra high speed SDR50 SDHC card at address 
>> [4.646266] mmcblk0: mmc1: SL32G 29.7 GiB
>> [4.650293] IRQ56 no longer affine to CPU7
>> [4.650581] CPU7: shutdown
>> [4.658293]  mmcblk0: p1 p2
>>
>> Note: Their is need to reset the PMIC
>> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers
>>  to support this feature consistently on every reboot.
>>
>> -Anand Moon
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at  http://www.tux.org/lkml/
>>
> 
> 

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Re: [PATCH 1/3] ARM: dts: exynos5422-odroidxu3: use cd-gpio method to detect sd-card

2015-10-12 Thread Jaehoon Chung
Dear, Anand.


On 10/13/2015 09:12 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 23:47, Anand Moon wrote:
>>>
>>> Anand,
>>>
>>> You essentially reverted here af6ad88acbd6 ("ARM: dts: Mux XMMCnDATA[0]
>>> pad correctly for Exynos5420 boards"). Why? There is no explanation in
>>> the commit message about this.
>>
>> I don't remember to send the patch relevant to this. Hmm...
>> Well, Is this patch really signed-off by me?
>>
>> Best Regards,
>>
>> Jaehoon Chung
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>>>
>>
>>
>> Some how I don't receive these mail on my email id.
>>
>> I have picked up these changes from tizen repository for OdroidXU3.
>> I have tested with this changes to detect UHS-I micro cd cards.
>> That's the reason for this email. 

It seems to make manually, right?
I have checked the tizen repository. 

The below is 

--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -335,7 +335,9 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _cd _bus1 _bus4>;
+   cd-gpios = < 2 0>;
+   cd-inverted;
+   pinctrl-0 = <_clk _cmd _bus1 _bus4>;
bus-width = <4>;
cap-sd-highspeed;
 };



Yours

--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -352,8 +352,10 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
+   cd-gpios = < 2 GPIO_ACTIVE_HIGH>;
+   cd-inverted;
pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _cd _bus1 _bus4>;
+   pinctrl-0 = <_clk _cmd _cd _bus4>;

Did you know what differ? :)

Best Regards,
Jaehoon Chung

> 
> ... and you applied it blindly without looking at actual existing
> contents and at previous commits.
> 
> That is not how patches from different repositories should be cherry picked.
> 
> Best regards,
> Krzysztof
> 
> 

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Re: [PATCH 2/3] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3

2015-10-12 Thread Jaehoon Chung
-ramp-delay = <12000>;
>>>>>>>
>>>>>>> Where did you get this value from? It looks wrong... My datasheet does
>>>>>>> not have 12000 uV/uS.
>>>>>>
>>>>>
>>>>>> Anand,
>>>>>>
>>>>>> We have actually been here:
>>>>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351601.html
>>>>>>
>>>>>> That time you used 8000. I asked the same question - how did you figure
>>>>>> out the exact value.
>>>>>>
>>>>>> Now we have the same question - why 12000?
>>>>>>
>>>>>> It is completely fine to make a mistake (I do a lot of them) but please
>>>>>> try not to make the same mistake again.
>>>>>>
>>>>>> BR,
>>>>>> Krzysztof
>>>>>
>>>>> I will focus more in the future to clamp down my mistakes to minimal.
>>>>>
>>>>>>
>>>>>>>
>>>>>>>>  };
>>>>>>>>
>>>>>>>>  ldo24_reg: LDO24 {
>>>>>>>> @@ -338,6 +341,7 @@
>>>>>>>>  samsung,dw-mshc-ddr-timing = <0 2>;
>>>>>>>>  samsung,dw-mshc-hs400-timing = <0 2>;
>>>>>>>>  samsung,read-strobe-delay = <90>;
>>>>>>>> +vmmc-supply = <_reg>;
>>>>>>>>  pinctrl-names = "default";
>>>>>>>>  pinctrl-0 = <_clk _cmd _bus1 _bus4 _bus8 
>>>>>>>> _cd _rclk>;
>>>>>>>>  bus-width = <8>;
>>>>>>>> @@ -352,6 +356,8 @@
>>>>>>>>  samsung,dw-mshc-ciu-div = <3>;
>>>>>>>>  samsung,dw-mshc-sdr-timing = <0 4>;
>>>>>>>>  samsung,dw-mshc-ddr-timing = <0 2>;
>>>>>>>> +vmmc-supply = <_reg>;
>>>>>>>> +vqmmc-supply = <_reg>;
>>>>>>>
>>>>>>> It looks wrong. LDO13 is used in one place as VQMMC and in other as
>>>>>>> VMMC. How did you figure out which regulator supplies which power 
>>>>>>> domain?
>>>>>>>
>>>>>
>>>>> I refer Schematics diagram to XU4_MAIN_REV0.1.pdf
>>>>>
>>>>> From the PWR_PMCI_S2MPS11_LDO_CTRL document it LDO13 point to VDDQ_MMC2.
>>>>>
>>>>
>>>> Aaa right, by mistake I thought that you put LDO13 here and in the node
>>>> before, but there is LDO3, not 13. You did this correctly.
>>>>
>>>> But I have two other questions:
>>>> 1. Maybe these regulators now should not be always-enabled?
>>>
>>> regulator-always-on can be removed: I have tested this.
>>>
>>>> 2. Why changing minimum voltage of LDO13 to 1.8V? The schematics says 2.8V.
>>>>
>>>
>>> In the schematics diagram to XU4_MAIN_REV0.1.pdf
>>>
>>> >From the EXYNOS5422 MMC UFS diagram CH2 range is VDDQ_MMC2 (1.8V/2.8V).
>>
>> Okay, so try to setting it to 1.8V (min and max) and see if it works
>> correctly.
>>
>> On the same diagram few lines below:
>> VDDQ_MMC2: 2.8V 250mA
>>
> 
> You are correct.
> While working on this issue I tent to encounter make bugs.
> -
> [4.713553] random: nonblocking pool is initialized
> [4.718423] 1453.hdmi supply hdmi-en not found, using dummy regulator
> [4.726206] exynos-drm exynos-drm: bound 1440.fimd (ops
> fimd_component_ops)
> [4.732555] exynos-drm exynos-drm: bound 1445.mixer (ops
> mixer_component_ops)
> [4.740180] exynos-drm exynos-drm: bound 1453.hdmi (ops
> hdmi_component_ops)
> [4.746936] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> [4.753428] [drm] No driver support for vblank timestamp query.
> [4.940794] Console: switching to colour frame buffer device 274x77
> [4.995344] exynos-drm exynos-drm: fb0:  frame buffer device
> [5.024573] [drm] Initialized exynos 1.0.0 20110530 on minor 0
> [5.031164] exynos-dwc3 usb@1200: no suspend clk specified
> [5.054571] usb 2-1: new full-speed USB device number 2 using exynos-ohci
> [5.159527] dwmmc_exynos 1222.mmc: Busy; trying anyway
> [5.163705] mmc_host mmc1: Timeout sending command (cmd 0x202000
> arg 0x0 status 0x0)
> -
> This is one bug. related to this changes. It stops booting waiting for
> the mmc1 card.

It seems that it failed to switch voltage.

Best Regards,
Jaehoon Chung

> 
> -Anand Moon
> 
>> Best regards,
>> Krzysztof
> 

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Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

2015-10-12 Thread Jaehoon Chung
On 10/12/2015 10:16 PM, Krzysztof Kozlowski wrote:
> W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze:
>> On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote:
>>> W dniu 12.10.2015 o 19:46, Anand Moon pisze:
>>>> Hi Krzysztof,
>>>>
>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski
>>>> <k.kozlow...@samsung.com> wrote:
>>>>> On 12.10.2015 00:46, Anand Moon wrote:
>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104)
>>>>>
>>>>> This description is not entirely correct. The MMC driver already
>>>>> supports these UHS speeds (you did not any code) so you rather enabled
>>>>> it (description of bindings says "is supported").
>>>>>
>>>>> You mentioned DDR50 but I don't see respective property below.
>>>> Looks like I missed it, I will add this in the next patch,
>>>>>
>>>>> How do you know that these modes are really supported? I don't know. Can
>>>>> you convince me?
>>>
>>> That part was not answered...
>>
>> In my experiment, it needs two requirements.
>> One is that Host controller supported UHS-I mode or others, other is SD-card.
>> In Anand's commit message, there is no information for this.
>>
>> And 50MB/s or 104MB/s is not real performance. (Just theoretical values)
>> It seems that can get those performances.
> 
> Right. But do you know if the host actually supports these?

Actually, it needs to check the User Manual for SoC.
If i can't check the User manual, i can't also know whether it supports or not.
Especially, there is no register that can be known which SD specification 
version at dw-mmc controller.

Well, if i miss something, let me know. I will also check more.

Best Regards,
Jaehoon Chung

> 
>>
>>>
>>>>>
>>>>
>>>>>>
>>>>>> Signed-off-by: Anand Moon <linux.am...@gmail.com>
>>>>>>
>>>>>> ---
>>>>>> Changes based on 
>>>>>> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
>>>>>> v4.4-next/dt-samsung branch
>>>>>>
>>>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot.
>>>>>
>>>>> I don't get what is exactly fixed here. What was the error? What is the
>>>>> outcome of this fix? The log below is before or after?
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>>>
>>>>>> [2.439806] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot req 
>>>>>> 1Hz, actual 1HZ div = 0)
>>>>>> [2.449729] mmc1: new ultra high speed SDR50 SDHC card at address 
>>>>>> [2.455984] mmcblk0: mmc1: SL32G 29.7 GiB
>>>>>> [2.461743]  mmcblk0: p1 p2
>>>>>
>>>>>> ---
>>>>>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 
>>>>>>  1 file changed, 4 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 
>>>>>> b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>>>> index 58c06d3..ba4a87b 100644
>>>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>>>> @@ -364,6 +364,10 @@
>>>>>>   pinctrl-0 = <_clk _cmd _cd _bus4>;
>>>>>>   bus-width = <4>;
>>>>>>   cap-sd-highspeed;
>>>>>> + sd-uhs-sdr12;
>>>>>> + sd-uhs-sdr25;
>>>>>> + sd-uhs-sdr50;
>>>>>> + sd-uhs-sdr104;
>>>>>>  };
>>>>>>
>>>>>>  _0 {
>>>>>>
>>>>>
>>>>
>>>> Changes were made to support Sandisk Ultra UHS-I class 10 card support.
>>>> OdroidXU3/XU4 board would not boot up using this card.
>>>>
>>>> Depending on the capability of the UHS-I card, the speed of the card
>>>> is selected.
>>>> I have just added the enhance capability feature to support them.
>>>
>>> So without these capabilities mentioned microSD card cannot be used? So
>>> I have a UHS-I card, that one exactly:
>>> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC
>&

Re: [PATCH 1/3] ARM: dts: exynos5422-odroidxu3: use cd-gpio method to detect sd-card

2015-10-11 Thread Jaehoon Chung
Hi,

On 10/12/2015 01:29 PM, Krzysztof Kozlowski wrote:
> On 12.10.2015 00:46, Anand Moon wrote:
>> From: Jaehoon Chung <jh80.ch...@samsung.com>
>>
>> To detect sd-card use the cd-gpio method.
>> It can decrease the interrupt for detecting sd-card.
>>
>> Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
>> Signed-off-by: Anand Moon <linux.am...@gmail.com>
>>
>> ---
>> Changes based on 
>> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
>> v4.4-next/dt-samsung branch
>> ---
>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 
>> b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>> index 1af5bdc..26decbd 100644
>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>> @@ -352,8 +352,10 @@
>>  samsung,dw-mshc-ciu-div = <3>;
>>  samsung,dw-mshc-sdr-timing = <0 4>;
>>  samsung,dw-mshc-ddr-timing = <0 2>;
>> +cd-gpios = < 2 GPIO_ACTIVE_HIGH>;
>> +cd-inverted;
>>  pinctrl-names = "default";
>> -pinctrl-0 = <_clk _cmd _cd _bus1 _bus4>;
>> +pinctrl-0 = <_clk _cmd _cd _bus4>;

Don't do change this.

> 
> Anand,
> 
> You essentially reverted here af6ad88acbd6 ("ARM: dts: Mux XMMCnDATA[0]
> pad correctly for Exynos5420 boards"). Why? There is no explanation in
> the commit message about this.

I don't remember to send the patch relevant to this. Hmm...
Well, Is this patch really signed-off by me?

Best Regards,
Jaehoon Chung
> 
> Best regards,
> Krzysztof
> 
> 

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Re: [RFC PATCH v8 0/10] Add external dma support for Synopsys MSHC

2015-10-04 Thread Jaehoon Chung
Hi, Shawn.

On 10/02/2015 06:49 PM, Shawn Lin wrote:
> On 2015/10/1 17:14, Jaehoon Chung wrote:
>> Dear, All.
>>
>> I will apply patch 01-03 at my repository on today.
>> But i don't know better how i do about other patches relevant to config file.
>>
> 
> Thanks, Jaehoon. :)
> 
> I guess it would be acceptable to pick the config changes, already they were 
> acked by the soc maintainers, via dw_mmc tree when ulf merge dw_mmc tree into 
> his mmc-tree.

Some patches didn't get the maintainer's acked-by. 
I will wait for that..until this week. How about?

Best Regards,
Jaehoon Chung

> 
> 
>> Best Regards,
>> Jaehoon Chung
>>
>> On 09/16/2015 03:40 PM, Shawn Lin wrote:
>>> Synopsys DesignWare mobile storage host controller supports three
>>> types of transfer mode: pio, internal dma and external dma. However,
>>> dw_mmc can only supports pio and internal dma now. Thus some platforms
>>> using dw-mshc integrated with generic dma can't work in dma mode. So we
>>> submit this patch to achieve it.
>>>
>>> And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
>>> (commit:f95f3850) for the first version of dw_mmc and never be touched since
>>> then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
>>> we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
>>> time. Nowadays, device-tree helps us to support a variety of boards with one
>>> kernel. That's why we need to remove it and decide the transfer mode by 
>>> reading
>>> dw_mmc's HCON reg at runtime.
>>>
>>> This RFC patch needs lots of ACKs. I know it's hard, but it does need 
>>> someone
>>> to make the running.
>>>
>>> Patch does the following things:
>>> - remove CONFIG_MMC_DW_IDMAC config option
>>> - add bindings for edmac used by synopsys-dw-mshc
>>>at runtime
>>> - add edmac support for synopsys-dw-mshc
>>>
>>> Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc
>>>
>>> Test emmc throughput on my platform with edmac support and without edmac 
>>> support(pio only)
>>> iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile 
>>> -Rb out.xls > /mnt/result.txt
>>> (light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB 
>>> data in total)
>>>   ___
>>> |   external dma mode   |
>>> |---|
>>> |blksz | Random Read | Random Write | Seq Read   | Seq Write|
>>> |---|
>>> |4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
>>> |---|
>>> |64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
>>> |---|
>>> |128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
>>> |---|
>>> VS
>>>   ___
>>> |  pio mode |
>>> |---|
>>> |blksz | Random Read  | Random Write | Seq Read  | Seq Write|
>>> |---|
>>> |4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
>>> |---|
>>> |64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
>>> |---|
>>> |128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
>>> |---|
>>>
>>>
>>> Changes in v8:
>>> - remove trans_mode variable
>>> - remove unnecessary dma_ops check
>>> - remove unnecessary comment
>>> - fix coding style based on latest ulf's next
>>> - add Acked-by: Jaehoon Chung <jh80.ch...@samsung.com>
>>>for HCON's changes
>>>
>>> Changes in v7:
>>> - rebased on Ulf's next
>>> - combine condition state
>>> - elaborate more about DMA_INTERFACE
>>> - define some macro for DMA_INERFACE value
>>> - spilt HCON ops' changes into another patch
>>>
>&g

Re: [RFC PATCH v8 0/10] Add external dma support for Synopsys MSHC

2015-10-01 Thread Jaehoon Chung
Dear, All.

I will apply patch 01-03 at my repository on today.
But i don't know better how i do about other patches relevant to config file.

Best Regards,
Jaehoon Chung

On 09/16/2015 03:40 PM, Shawn Lin wrote:
> Synopsys DesignWare mobile storage host controller supports three
> types of transfer mode: pio, internal dma and external dma. However,
> dw_mmc can only supports pio and internal dma now. Thus some platforms
> using dw-mshc integrated with generic dma can't work in dma mode. So we
> submit this patch to achieve it.
> 
> And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
> (commit:f95f3850) for the first version of dw_mmc and never be touched since
> then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
> we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
> time. Nowadays, device-tree helps us to support a variety of boards with one
> kernel. That's why we need to remove it and decide the transfer mode by 
> reading
> dw_mmc's HCON reg at runtime.
> 
> This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
> to make the running.
> 
> Patch does the following things:
> - remove CONFIG_MMC_DW_IDMAC config option
> - add bindings for edmac used by synopsys-dw-mshc
>   at runtime
> - add edmac support for synopsys-dw-mshc
> 
> Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc
> 
> Test emmc throughput on my platform with edmac support and without edmac 
> support(pio only)
> iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile 
> -Rb out.xls > /mnt/result.txt
> (light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB data 
> in total)
>  ___
> |   external dma mode   |
> |---|
> |blksz | Random Read | Random Write | Seq Read   | Seq Write|
> |---|
> |4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
> |---|
> |64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
> |---|
> |128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
> |---|
>VS
>  ___
> |  pio mode |
> |---|
> |blksz | Random Read  | Random Write | Seq Read  | Seq Write|
> |---|
> |4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
> |---|
> |64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
> |---|
> |128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
> |---|
> 
> 
> Changes in v8:
> - remove trans_mode variable
> - remove unnecessary dma_ops check
> - remove unnecessary comment
> - fix coding style based on latest ulf's next
> - add Acked-by: Jaehoon Chung <jh80.ch...@samsung.com>
>   for HCON's changes
> 
> Changes in v7:
> - rebased on Ulf's next
> - combine condition state
> - elaborate more about DMA_INTERFACE
> - define some macro for DMA_INERFACE value
> - spilt HCON ops' changes into another patch
> 
> Changes in v6:
> - add trans_mode condition for IDMAC initialization
>   suggested by Heiko
> - re-test my patch on rk3188 platform and update commit msg
> - update performance of pio vs edmac in cover letter
> 
> Changes in v5:
> - add the title of cover letter
> - fix typo of comment
> - add macro for reading HCON register
> - add "Acked-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>" for 
> exynos_defconfig patch
> - add "Acked-by: Vineet Gupta <vgu...@synopsys.com>" for axs10x_defconfig 
> patch
> - add "Acked-by: Govindraj Raja <govindraj.r...@imgtec.com>" and
>   "Acked-by: Ralf Baechle <r...@linux-mips.org>" for pistachio_defconfig patch
> - add "Acked-by: Joachim Eastwood <manab...@gmail.com>" for lpc18xx_defconfig 
> patch
> - add "Acked-by: Wei Xu <xuw...@hisilicon.com>" for hisi_defconfig patch
> - rebase on "https://github.com/jh80chung/dw-mmc.git 
> tags/dw-mmc-for-ulf-v4.2" for merging easily
> 
> Changes in v4:
> - remove "host->trans_mode&q

Re: [RFC PATCH v7 02/10] mmc: dw_mmc: use macro for HCON register operations

2015-09-15 Thread Jaehoon Chung
Hi, Shawn.

Looks good to me.

Acked-by: Jaehoon Chung <jh80.ch...@samsung.com>

Best Regards,
Jaehoon Chung

On 08/24/2015 10:25 AM, Shawn Lin wrote:
> This patch add some macros for HCON register operations
> to make code more readable.
> 
> Signed-off-by: Shawn Lin <shawn@rock-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/mmc/host/dw_mmc.c | 6 +++---
>  drivers/mmc/host/dw_mmc.h | 3 +++
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 9c91983..0a3c63c 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -2678,7 +2678,7 @@ static void dw_mci_init_dma(struct dw_mci *host)
>   * Check ADDR_CONFIG bit in HCON to find
>   * IDMAC address bus width
>   */
> - addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
> + addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
>  
>   if (addr_config == 1) {
>   /* host supports IDMAC in 64-bit address mode */
> @@ -3060,7 +3060,7 @@ int dw_mci_probe(struct dw_mci *host)
>* Get the host data width - this assumes that HCON has been set with
>* the correct values.
>*/
> - i = (mci_readl(host, HCON) >> 7) & 0x7;
> + i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
>   if (!i) {
>   host->push_data = dw_mci_push_data16;
>   host->pull_data = dw_mci_pull_data16;
> @@ -3142,7 +3142,7 @@ int dw_mci_probe(struct dw_mci *host)
>   if (host->pdata->num_slots)
>   host->num_slots = host->pdata->num_slots;
>   else
> - host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
> + host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
>  
>   /*
>* Enable interrupts for command done, data over, data empty,
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 811d467..f2a88d4 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -154,6 +154,9 @@
>  #define DMA_INTERFACE_GDMA   (0x2)
>  #define DMA_INTERFACE_NODMA  (0x3)
>  #define SDMMC_GET_TRANS_MODE(x)  (((x)>>16) & 0x3)
> +#define SDMMC_GET_SLOT_NUM(x)x)>>1) & 0x1F) + 1)
> +#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
> +#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
>  /* Internal DMAC interrupt defines */
>  #define SDMMC_IDMAC_INT_AI   BIT(9)
>  #define SDMMC_IDMAC_INT_NI   BIT(8)
> 

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Re: [RFC PATCH v7 01/10] mmc: dw_mmc: Add external dma interface support

2015-09-15 Thread Jaehoon Chung
block
> + * 2b'11: Non DW DMA Interface -> pio only
> + * Compared to DesignWare DMA Interface, Generic DMA Interface has a
> + * simpler request/acknowledge handshake mechanism and both of them
> + * are regarded as external dma master for dw_mmc.
> + * Note: host->use_dma can't take HCON[17:16] value directly for the
> + * the reason mentioned above.
> + */

trans_mode can't take HCON value, but trans_mode reassigned to 
"TRANS_MODE_IDMAC" or "TRANS_MODE_EDMAC"..
It's reassigned to host->use_dma...why can't use the host->use_dma?

Your code..

1. trans_mode <- HCON value
2. Check trans_mode which interface use.
then trans_mode <- TRANS_MODE_IDMAC/EDMAC/PIO
3. host->use_dma <- trans_mode

isn't?

It can be replaced to "host->use_dma" instead of "trans_mode".

> + trans_mode = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
> + if (trans_mode == DMA_INTERFACE_IDMA) {
> + trans_mode = TRANS_MODE_IDMAC;
> + } else if (trans_mode == DMA_INTERFACE_DWDMA ||
> +trans_mode == DMA_INTERFACE_GDMA) {
> + trans_mode = TRANS_MODE_EDMAC;
> + } else {
> + trans_mode = TRANS_MODE_PIO;
>   goto no_dma;
>   }
>  
>   /* Determine which DMA interface to use */
> -#ifdef CONFIG_MMC_DW_IDMAC
> - host->dma_ops = _mci_idmac_ops;
> - dev_info(host->dev, "Using internal DMA controller.\n");
> -#endif
> + if (trans_mode == TRANS_MODE_IDMAC) {
> + /*
> + * Check ADDR_CONFIG bit in HCON to find
> + * IDMAC address bus width
> + */
> + addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
> +
> + if (addr_config == 1) {
> + /* host supports IDMAC in 64-bit address mode */
> + host->dma_64bit_address = 1;
> + dev_info(host->dev,
> +  "IDMAC supports 64-bit address mode.\n");
> + if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
> + dma_set_coherent_mask(host->dev,
> +   DMA_BIT_MASK(64));
> + } else {
> + /* host supports IDMAC in 32-bit address mode */
> + host->dma_64bit_address = 0;
> + dev_info(host->dev,
> +  "IDMAC supports 32-bit address mode.\n");
> + }
> +
> + /* Alloc memory for sg translation */
> + host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
> +>sg_dma, GFP_KERNEL);
> + if (!host->sg_cpu) {
> + dev_err(host->dev,
> + "%s: could not alloc DMA memory\n",
> + __func__);
> + goto no_dma;
> + }
> +
> + host->dma_ops = _mci_idmac_ops;
> + dev_info(host->dev, "Using internal DMA controller.\n");
> + } else {
> + /* TRANS_MODE_EDMAC: check dma bindings again */
> + if ((of_property_count_strings(np, "dma-names") < 0) ||
> + (!of_find_property(np, "dmas", NULL))) {
> + trans_mode = TRANS_MODE_PIO;
> + goto no_dma;
> + }
> + host->dma_ops = _mci_edmac_ops;
> + dev_info(host->dev, "Using external DMA controller.\n");
> + }
>  
>   if (!host->dma_ops)
>   goto no_dma;

This checking seems unnecessary, after applied your code.

Best Regards,
Jaehoon Chung

> @@ -2562,12 +2733,12 @@ static void dw_mci_init_dma(struct dw_mci *host)
>   goto no_dma;
>   }
>  
> - host->use_dma = 1;
> + host->use_dma = trans_mode;
>   return;
>  
>  no_dma:
>   dev_info(host->dev, "Using PIO mode.\n");
> - host->use_dma = 0;
> + host->use_dma = trans_mode;
>  }
>  
>  static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
> @@ -2650,10 +2821,9 @@ static bool dw_mci_reset(struct dw_mci *host)
>   }
>   }
>  
> -#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
> - /* It is also recommended that we reset and reprogram idmac */
> - dw_mci_idmac_reset(host);
> -#endif
> + if (host->use_dma == TRANS_MODE_IDMAC)
> + /* It is also recommended that we reset and reprogram idmac */
> + dw_mci_idmac_reset(host);
>  
&g

Re: [PATCH] ARM: dts: use vqmmc-supply of emmc/sd for exynos4412-odroid-common

2015-08-27 Thread Jaehoon Chung
On 08/27/2015 09:26 PM, Krzysztof Kozlowski wrote:
 W dniu 27.08.2015 o 18:29, Jaehoon Chung pisze:
 Currently vmmc's property is wrong.
 If it needs to control two supplies, then it has to use vmmc/vqmmc-supply.
 (Card supply power and I/O Line supply Power.)

 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 ---
  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
 b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 index ca7d168..4ddabfd 100644
 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 @@ -461,10 +461,10 @@
  mshc_0 {
  pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
  pinctrl-names = default;
 -vmmc-supply = ldo20_reg buck8_reg;
 +vmmc-supply = ldo20_reg;
 +vqmmc-supply = buck8_reg;
 
 Shouldn't this be reversed? LDO20 has 1.8V and it goes to MMC connector,
 so it should be VQMMC?

If my schematics is right thing, buck8 is used LAN card power.
I will send after removing buck8_reg. how about?
Anyway, Thanks for pointing out. :)

I don't know who this regulator applied. I have guessed that it used for eMMC.
Sorry for guessing.

Best Regards,
Jaehoon Chung

 
 In the same time I can't find on schematics where BUCK8 goes...
 
 The SDHCI_2 node below looks good.
 
 Best regards,
 Krzysztof
 
  mmc-pwrseq = emmc_pwrseq;
  status = okay;
 -
  num-slots = 1;
  broken-cd;
  card-detect-delay = 200;
 @@ -485,7 +485,8 @@
  bus-width = 4;
  pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
  pinctrl-names = default;
 -vmmc-supply = ldo4_reg ldo21_reg;
 +vmmc-supply = ldo21_reg;
 +vqmmc-supply = ldo4_reg;
  cd-gpios = gpk2 2 0;
  cd-inverted;
  status = okay;

 
 
 

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[PATCH] ARM: dts: use vqmmc-supply of emmc/sd for exynos4412-odroid-common

2015-08-27 Thread Jaehoon Chung
Currently vmmc's property is wrong.
If it needs to control two supplies, then it has to use vmmc/vqmmc-supply.
(Card supply power and I/O Line supply Power.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index ca7d168..4ddabfd 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -461,10 +461,10 @@
 mshc_0 {
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
-   vmmc-supply = ldo20_reg buck8_reg;
+   vmmc-supply = ldo20_reg;
+   vqmmc-supply = buck8_reg;
mmc-pwrseq = emmc_pwrseq;
status = okay;
-
num-slots = 1;
broken-cd;
card-detect-delay = 200;
@@ -485,7 +485,8 @@
bus-width = 4;
pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
pinctrl-names = default;
-   vmmc-supply = ldo4_reg ldo21_reg;
+   vmmc-supply = ldo21_reg;
+   vqmmc-supply = ldo4_reg;
cd-gpios = gpk2 2 0;
cd-inverted;
status = okay;
-- 
1.9.1

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Re: [RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

2015-08-21 Thread Jaehoon Chung
On 08/21/2015 03:30 PM, Shawn Lin wrote:
 On 2015/8/21 14:27, Jaehoon Chung wrote:
 Hi, Shawn.

 Is this based on Ulf's repository?
 
 
 no, it's based on https://github.com/jh80chung/dw-mmc.git 
 tags/dw-mmc-for-ulf-v4.2 :)

Oh..I will rebase to Ulf's next branch on this weekend.
Then could you rebase this patch? And i added more comments at below.. :)

Best Regards,
Jaehoon Chung

 

 On 08/20/2015 05:43 PM, Shawn Lin wrote:
 DesignWare MMC Controller can supports two types of DMA
 mode: external dma and internal dma. We get a RK312x platform
 integrated dw_mmc and ARM pl330 dma controller. This patch add
 edmac ops to support these platforms. I've tested it on RK31xx
 platform with edmac mode and RK3288 platform with idmac mode.

 Signed-off-by: Shawn Lin shawn@rock-chips.com

 ---

 Changes in v6:
 - add trans_mode condition for IDMAC initialization
suggested by Heiko
 - re-test my patch on rk3188 platform and update commit msg
 - update performance of pio vs edmac in cover letter

 Changes in v5:
 - add the title of cover letter
 - fix typo of comment
 - add macro for reading HCON register
 - add Acked-by: Krzysztof Kozlowski k.kozlow...@samsung.com for 
 exynos_defconfig patch
 - add Acked-by: Vineet Gupta vgu...@synopsys.com for axs10x_defconfig 
 patch
 - add Acked-by: Govindraj Raja govindraj.r...@imgtec.com and
Acked-by: Ralf Baechle r...@linux-mips.org for pistachio_defconfig 
 patch
 - add Acked-by: Joachim Eastwood manab...@gmail.com for 
 lpc18xx_defconfig patch
 - add Acked-by: Wei Xu xuw...@hisilicon.com for hisi_defconfig patch
 - rebase on https://github.com/jh80chung/dw-mmc.git 
 tags/dw-mmc-for-ulf-v4.2 for merging easily

 Changes in v4:
 - remove host-trans_mode and use host-use_dma to indicate
transfer mode.
 - remove all bt-bindings' changes since we don't need new properities.
 - check transfer mode at runtime by reading HCON reg
 - spilt defconfig changes for each sub-architecture
 - fix the title of cover letter
 - reuse some code for reducing code size

 Changes in v3:
 - choose transfer mode at runtime
 - remove all CONFIG_MMC_DW_IDMAC config option
 - add supports-idmac property for some platforms

 Changes in v2:
 - Fix typo of dev_info msg
 - remove unused dmach from declaration of dw_mci_dma_slave

   drivers/mmc/host/Kconfig|  11 +-
   drivers/mmc/host/dw_mmc-pltfm.c |   2 +
   drivers/mmc/host/dw_mmc.c   | 264 
 
   drivers/mmc/host/dw_mmc.h   |   5 +
   include/linux/mmc/dw_mmc.h  |  27 +++-
   5 files changed, 242 insertions(+), 67 deletions(-)

 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
 index 6a0f9c7..a86c0eb 100644
 --- a/drivers/mmc/host/Kconfig
 +++ b/drivers/mmc/host/Kconfig
 @@ -607,15 +607,7 @@ config MMC_DW
   help
 This selects support for the Synopsys DesignWare Mobile Storage IP
 block, this provides host support for SD and MMC interfaces, in both
 -  PIO and external DMA modes.
 -
 -config MMC_DW_IDMAC
 -bool Internal DMAC interface
 -depends on MMC_DW
 -help
 -  This selects support for the internal DMAC block within the Synopsys
 -  Designware Mobile Storage IP block. This disables the external DMA
 -  interface.
 +  PIO, internal DMA mode and external DMA modes.

   config MMC_DW_PLTFM
   tristate Synopsys Designware MCI Support as platform device
 @@ -644,7 +636,6 @@ config MMC_DW_K3
   tristate K3 specific extensions for Synopsys DW Memory Card 
 Interface
   depends on MMC_DW
   select MMC_DW_PLTFM
 -select MMC_DW_IDMAC
   help
 This selects support for Hisilicon K3 SoC specific extensions to the
 Synopsys DesignWare Memory Card Interface driver. Select this option
 diff --git a/drivers/mmc/host/dw_mmc-pltfm.c 
 b/drivers/mmc/host/dw_mmc-pltfm.c
 index ec6dbcd..7e1d13b 100644
 --- a/drivers/mmc/host/dw_mmc-pltfm.c
 +++ b/drivers/mmc/host/dw_mmc-pltfm.c
 @@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
   host-pdata = pdev-dev.platform_data;

   regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 +/* Get registers' physical base address */
 +host-phy_regs = (void *)(regs-start);
   host-regs = devm_ioremap_resource(pdev-dev, regs);
   if (IS_ERR(host-regs))
   return PTR_ERR(host-regs);

 Is this board specific code? If so, separate the patch.

 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index fcbf552..f943619 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -56,7 +56,6 @@
   #define DW_MCI_FREQ_MAX2/* unit: HZ */
   #define DW_MCI_FREQ_MIN40/* unit: HZ */

 -#ifdef CONFIG_MMC_DW_IDMAC
   #define IDMAC_INT_CLR(SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
 @@ -102,7 +101,6 @@ struct

Re: [RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

2015-08-21 Thread Jaehoon Chung
On 08/21/2015 04:27 PM, Shawn Lin wrote:
 On 2015/8/21 14:35, Jaehoon Chung wrote:
 On 08/21/2015 03:30 PM, Shawn Lin wrote:
 On 2015/8/21 14:27, Jaehoon Chung wrote:
 Hi, Shawn.

 Is this based on Ulf's repository?


 no, it's based on https://github.com/jh80chung/dw-mmc.git 
 tags/dw-mmc-for-ulf-v4.2 :)

 Oh..I will rebase to Ulf's next branch on this weekend.
 Then could you rebase this patch? And i added more comments at below.. :)

 
 Okay, I will rebase to Ulf's next.
 
 Best Regards,
 Jaehoon Chung


 
 [...]
 
 index ec6dbcd..7e1d13b 100644
 --- a/drivers/mmc/host/dw_mmc-pltfm.c
 +++ b/drivers/mmc/host/dw_mmc-pltfm.c
 @@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host-pdata = pdev-dev.platform_data;

regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 +/* Get registers' physical base address */
 +host-phy_regs = (void *)(regs-start);
host-regs = devm_ioremap_resource(pdev-dev, regs);
if (IS_ERR(host-regs))
return PTR_ERR(host-regs);

 Is this board specific code? If so, separate the patch.
 
 It's might not board specific code.
 dmaengine need dw_mmc's *physical* fifo address for data transfer, so I get 
 controller physical address  here in order to calculate physical fifo address.
 
 regs is from dt-bindings, for instance:
  dwmmc0@1220 {
  compatible = snps,dw-mshc;
   clocks = clock 351, clock 132;
  clock-names = biu, ciu;
  reg = 0x1220 0x1000;
  interrupts = 0 75 0;
  #address-cells = 1;
  #size-cells = 0;
  };
 
 so, host-phy_regs will be 0x1220 .
 
 [...]
 
 +static void dw_mci_dmac_complete_dma(void *arg)
{
 +struct dw_mci *host = arg;
struct mmc_data *data = host-data;

dev_vdbg(host-dev, DMA complete\n);

 +if (host-use_dma == TRANS_MODE_EDMAC)
 +if (data  (data-flags  MMC_DATA_READ))

 Combine one condition.
 
 okay.
 
 [...]
 
 +u32 fifo_offset = host-fifo_reg - host-regs;
 +int ret = 0;
 +
 +/* Set external dma config: burst size, burst width */
 +cfg.dst_addr = (dma_addr_t)(host-phy_regs + fifo_offset);

 host-phy_regs is not assigned?
 
 we got it at dw_mci_pltfm_register. See comments above. :)
 
 [...]
 
mmc-max_blk_count = mmc-max_req_size / 512;
 +} else if (host-use_dma == TRANS_MODE_EDMAC) {
 +mmc-max_segs = 64;
 +mmc-max_blk_size = 65536;
 +mmc-max_blk_count = 65535;
 +mmc-max_req_size =
 +mmc-max_blk_size * mmc-max_blk_count;
 +mmc-max_seg_size = mmc-max_req_size;

 Fix the indention
 
 Hmm..I check it attentively but can't find the indention . Might it's because 
 you apply it against Ulf's repo?
 

 
 [...]
 

 -/* Alloc memory for sg translation */
 -host-sg_cpu = dmam_alloc_coherent(host-dev, PAGE_SIZE,
 -  host-sg_dma, GFP_KERNEL);
 -if (!host-sg_cpu) {
 -dev_err(host-dev, %s: could not alloc DMA memory\n,
 -__func__);
 +/* Check tansfer mode */
 +trans_mode = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
 +if (trans_mode == 0) {
 +trans_mode = TRANS_MODE_IDMAC;
 +} else if (trans_mode == 1 || trans_mode == 2) {
 +trans_mode = TRANS_MODE_EDMAC;
 +} else {
 +trans_mode = TRANS_MODE_PIO;

 what are trans_mode 0, 1, 2?
 (00 - none) is NO-DMA interface, isn't? is it IDMAC mode?

 
 No, I guess the databook's ambiguous description confuse everybody.
 
 I got double comfirm from my ASCI team as well as Synoposys
 2b'00: NO-DMA interface --  It support IDMAC actually
 2b'01  2b'02: DW_DMA  GENERIC_DMA -- Support 2 types of external dma.
 2b'02: NON-DW-DMA -- only support PIO

Then Could you add the comment about this?
Use definition instead of 0, 1, 2. Developer don't know meaning that is 0, 1, 
2.

Best Regards,
Jaehoon Chung

 
 refer to the description below:
 Parameter Name: DMA_INTERFACE
 Legal Values: 0-3
 Default Value: 0
 Description:
  0- No DMA Interface
  1- DesignWare DMA Interface
  2- Generic DMA Interface
  3- Non DW DMA Interface
 In DesignWare DMA mode, request/acknowledge protocol meets DW_ahb_dmac
 controller protocol. In this mode, host data bus is also used for DMA 
 transfers.Generic DMA-type interface has simpler request/acknowledge 
 handshake and has dedicated read/write data bus for DMA transfers. Non DW 
 DMAC interface uses dw_dma_single interface in addition to the existing 
 interface and uses host data bus for DMA transfers. This is configurable only 
 if INTERNAL_DMAC=0.
 
goto no_dma;
}

 +dev_info(host-dev, Using external DMA controller.\n);
 +}

if (!host-dma_ops)
goto no_dma;
 @@ -2562,12 +2720,12 @@ static void dw_mci_init_dma(struct dw_mci *host)
goto no_dma;
}

 -host-use_dma = 1;
 +host-use_dma

Re: [RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

2015-08-21 Thread Jaehoon Chung
(host);
 -#endif
 + if (host-use_dma == TRANS_MODE_IDMAC)
 + /* It is also recommended that we reset and reprogram idmac */
 + dw_mci_idmac_reset(host);
  
   ret = true;
  
 @@ -2890,7 +3047,7 @@ int dw_mci_probe(struct dw_mci *host)
* Get the host data width - this assumes that HCON has been set with
* the correct values.
*/
 - i = (mci_readl(host, HCON)  7)  0x7;
 + i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));

This is not related with supporting external dma interface.
Separate this.

   if (!i) {
   host-push_data = dw_mci_push_data16;
   host-pull_data = dw_mci_pull_data16;
 @@ -2972,7 +3129,7 @@ int dw_mci_probe(struct dw_mci *host)
   if (host-pdata-num_slots)
   host-num_slots = host-pdata-num_slots;
   else
 - host-num_slots = ((mci_readl(host, HCON)  1)  0x1F) + 1;
 + host-num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));

Ditto. (with above.)

  
   /*
* Enable interrupts for command done, data over, data empty,
 @@ -3067,6 +3224,9 @@ EXPORT_SYMBOL(dw_mci_remove);
   */
  int dw_mci_suspend(struct dw_mci *host)
  {
 + if (host-use_dma  host-dma_ops-exit)
 + host-dma_ops-exit(host);
 +
   return 0;
  }
  EXPORT_SYMBOL(dw_mci_suspend);
 diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
 index 8ce4674..c453e94 100644
 --- a/drivers/mmc/host/dw_mmc.h
 +++ b/drivers/mmc/host/dw_mmc.h
 @@ -148,6 +148,11 @@
  #define SDMMC_SET_FIFOTH(m, r, t)(((m)  0x7)  28 | \
((r)  0xFFF)  16 | \
((t)  0xFFF))
 +/* HCON register defines */
 +#define SDMMC_GET_SLOT_NUM(x)x)1)  0x1F) + 1)
 +#define SDMMC_GET_HDATA_WIDTH(x) (((x)7)  0x7)
 +#define SDMMC_GET_TRANS_MODE(x)  (((x)16)  0x3)
 +#define SDMMC_GET_ADDR_CONFIG(x) (((x)27)  0x1)
  /* Internal DMAC interrupt defines */
  #define SDMMC_IDMAC_INT_AI   BIT(9)
  #define SDMMC_IDMAC_INT_NI   BIT(8)
 diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
 index c846f42..6a2b83c 100644
 --- a/include/linux/mmc/dw_mmc.h
 +++ b/include/linux/mmc/dw_mmc.h
 @@ -16,6 +16,7 @@
  
  #include linux/scatterlist.h
  #include linux/mmc/core.h
 +#include linux/dmaengine.h
  
  #define MAX_MCI_SLOTS2
  
 @@ -40,6 +41,17 @@ enum {
  
  struct mmc_data;
  
 +enum {
 + TRANS_MODE_PIO = 0,
 + TRANS_MODE_IDMAC,
 + TRANS_MODE_EDMAC
 +};
 +
 +struct dw_mci_dma_slave {
 + struct dma_chan *ch;
 + enum dma_transfer_direction direction;
 +};
 +
  /**
   * struct dw_mci - MMC controller state shared between all slots
   * @lock: Spinlock protecting the queue and associated data.
 @@ -154,11 +166,16 @@ struct dw_mci {
   dma_addr_t  sg_dma;
   void*sg_cpu;
   const struct dw_mci_dma_ops *dma_ops;
 -#ifdef CONFIG_MMC_DW_IDMAC
 + /* For idmac */
   unsigned intring_size;
 -#else
 +
 + /* For edmac */
 + struct dw_mci_dma_slave *dms;
 + /* Registers's physical base address */
 + void*phy_regs;
 +
   struct dw_mci_dma_data  *dma_data;
 -#endif
 +

On ulf's repository, this point should be conflicted.

Best Regards,
Jaehoon Chung

   u32 cmd_status;
   u32 data_status;
   u32 stop_cmdr;
 @@ -212,8 +229,8 @@ struct dw_mci {
  struct dw_mci_dma_ops {
   /* DMA Ops */
   int (*init)(struct dw_mci *host);
 - void (*start)(struct dw_mci *host, unsigned int sg_len);
 - void (*complete)(struct dw_mci *host);
 + int (*start)(struct dw_mci *host, unsigned int sg_len);
 + void (*complete)(void *host);
   void (*stop)(struct dw_mci *host);
   void (*cleanup)(struct dw_mci *host);
   void (*exit)(struct dw_mci *host);
 

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Re: [RFC PATCH v4 0/9]

2015-08-06 Thread Jaehoon Chung
Hi, Shawn.

I remembered that Krzysztof has mentioned Fix the title of cover letter.
Your cover letter's title is nothing.. [RFC PATCH v4 0/9]  ??
[RFC PATCH v4 0/9] your title...

Best Regards,
Jaehoon Chung

On 08/06/2015 03:44 PM, Shawn Lin wrote:
 Add external dma support for Synopsys MSHC
 
 Synopsys DesignWare mobile storage host controller supports three
 types of transfer mode: pio, internal dma and external dma. However,
 dw_mmc can only supports pio and internal dma now. Thus some platforms
 using dw-mshc integrated with generic dma can't work in dma mode. So we
 submit this patch to achieve it.
 
 And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
 (commit:f95f3850) for the first version of dw_mmc and never be touched since
 then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
 we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
 time. Nowadays, device-tree helps us to support a variety of boards with one
 kernel. That's why we need to remove it and decide the transfer mode by 
 reading
 dw_mmc's HCON reg at runtime.
 
 This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
 to make the running.
 
 Patch does the following things:
 - remove CONFIG_MMC_DW_IDMAC config option
 - add bindings for edmac used by synopsys-dw-mshc
   at runtime
 - add edmac support for synopsys-dw-mshc
 
 Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc
 
 
 Changes in v4:
 - remove host-trans_mode and use host-use_dma to indicate
   transfer mode.
 - remove all bt-bindings' changes since we don't need new properities.
 - check transfer mode at runtime by reading HCON reg
 - spilt defconfig changes for each sub-architecture
 - fix the title of cover letter
 - reuse some code for reducing code size
 
 Changes in v3:
 - choose transfer mode at runtime
 - remove all CONFIG_MMC_DW_IDMAC config option
 - add supports-idmac property for some platforms
 
 Changes in v2:
 - Fix typo of dev_info msg
 - remove unused dmach from declaration of dw_mci_dma_slave
 
 Shawn Lin (9):
   mmc: dw_mmc: Add external dma interface support
   Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
   mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
   arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC
 
  .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  25 ++
  arch/arc/configs/axs101_defconfig  |   1 -
  arch/arc/configs/axs103_defconfig  |   1 -
  arch/arc/configs/axs103_smp_defconfig  |   1 -
  arch/arm/configs/exynos_defconfig  |   1 -
  arch/arm/configs/hisi_defconfig|   1 -
  arch/arm/configs/lpc18xx_defconfig |   1 -
  arch/arm/configs/multi_v7_defconfig|   1 -
  arch/arm/configs/zx_defconfig  |   1 -
  arch/mips/configs/pistachio_defconfig  |   1 -
  drivers/mmc/host/Kconfig   |  11 +-
  drivers/mmc/host/dw_mmc-pltfm.c|   2 +
  drivers/mmc/host/dw_mmc.c  | 258 
 +
  include/linux/mmc/dw_mmc.h |  27 ++-
  14 files changed, 257 insertions(+), 75 deletions(-)
 

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Re: [RFC PATCH v4 0/9]

2015-08-06 Thread Jaehoon Chung
On 08/06/2015 04:31 PM, Shawn Lin wrote:
 在 2015/8/6 15:08, Jaehoon Chung 写道:
 Hi, Shawn.

 I remembered that Krzysztof has mentioned Fix the title of cover letter.
 Your cover letter's title is nothing.. [RFC PATCH v4 0/9]  ??
 [RFC PATCH v4 0/9] your title...
  Sorry, I forgot it, and will fix in next version...

No problem :) 
At next time,  add the title at your cover-letter, plz.

Best Regards,
Jaehoon Chung

 
 Best Regards,
 Jaehoon Chung

 On 08/06/2015 03:44 PM, Shawn Lin wrote:
 Add external dma support for Synopsys MSHC

 Synopsys DesignWare mobile storage host controller supports three
 types of transfer mode: pio, internal dma and external dma. However,
 dw_mmc can only supports pio and internal dma now. Thus some platforms
 using dw-mshc integrated with generic dma can't work in dma mode. So we
 submit this patch to achieve it.

 And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
 (commit:f95f3850) for the first version of dw_mmc and never be touched since
 then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
 we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
 time. Nowadays, device-tree helps us to support a variety of boards with one
 kernel. That's why we need to remove it and decide the transfer mode by 
 reading
 dw_mmc's HCON reg at runtime.

 This RFC patch needs lots of ACKs. I know it's hard, but it does need 
 someone
 to make the running.

 Patch does the following things:
 - remove CONFIG_MMC_DW_IDMAC config option
 - add bindings for edmac used by synopsys-dw-mshc
at runtime
 - add edmac support for synopsys-dw-mshc

 Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc


 Changes in v4:
 - remove host-trans_mode and use host-use_dma to indicate
transfer mode.
 - remove all bt-bindings' changes since we don't need new properities.
 - check transfer mode at runtime by reading HCON reg
 - spilt defconfig changes for each sub-architecture
 - fix the title of cover letter
 - reuse some code for reducing code size

 Changes in v3:
 - choose transfer mode at runtime
 - remove all CONFIG_MMC_DW_IDMAC config option
 - add supports-idmac property for some platforms

 Changes in v2:
 - Fix typo of dev_info msg
 - remove unused dmach from declaration of dw_mci_dma_slave

 Shawn Lin (9):
mmc: dw_mmc: Add external dma interface support
Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

   .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  25 ++
   arch/arc/configs/axs101_defconfig  |   1 -
   arch/arc/configs/axs103_defconfig  |   1 -
   arch/arc/configs/axs103_smp_defconfig  |   1 -
   arch/arm/configs/exynos_defconfig  |   1 -
   arch/arm/configs/hisi_defconfig|   1 -
   arch/arm/configs/lpc18xx_defconfig |   1 -
   arch/arm/configs/multi_v7_defconfig|   1 -
   arch/arm/configs/zx_defconfig  |   1 -
   arch/mips/configs/pistachio_defconfig  |   1 -
   drivers/mmc/host/Kconfig   |  11 +-
   drivers/mmc/host/dw_mmc-pltfm.c|   2 +
   drivers/mmc/host/dw_mmc.c  | 258 
 +
   include/linux/mmc/dw_mmc.h |  27 ++-
   14 files changed, 257 insertions(+), 75 deletions(-)




 
 

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Re: [PATCH 1/1] ARM: dts: Add HS400 support for exynos5422-odroidxu3

2015-04-07 Thread Jaehoon Chung
Hi, Markus.

I have also tested on Odroid-xu3 board.

Acked-by: Jaehoon Chung jh80.ch...@samsung.com

Best Regards,
Jaehoon Chung


On 04/08/2015 12:33 AM, Markus Reichl wrote:
 Hi,
 
 the base patch in [0] has been applied now.
 
 My patch was meanwhile
 
 Tested-by: Anand Moon linux.am...@gmail.com
 
 
 Am 31.03.2015 um 14:27 schrieb Markus Reichl:
 Am 30.03.2015 um 17:51 schrieb Markus Reichl:
 HS400 timing values are added for exynos5422-odroidxu3 board.
 ---
 This patch is analog to [0].
 This patch needs [0] for the pin-ctrl definition of sd0_rclk.

 [0]: 
 https://www.mail-archive.com/linux-samsung-soc%40vger.kernel.org/msg42902.html

 Signed-off-by: Markus Reichl m.rei...@fivetechno.de
 ---
  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

 diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts 
 b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 index a519c86..0408ec0 100644
 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 @@ -298,15 +298,20 @@
  
  mmc_0 {
 status = okay;
 +   num-slots = 1;
 broken-cd;
 card-detect-delay = 200;
 samsung,dw-mshc-ciu-div = 3;
 samsung,dw-mshc-sdr-timing = 0 4;
 samsung,dw-mshc-ddr-timing = 0 2;
 +   samsung,dw-mshc-hs400-timing = 0 2;
 +   samsung,read-strobe-delay = 90;
 pinctrl-names = default;
 -   pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 +   pinctrl-0 = sd0_clk sd0_cmd sd0_bus1 sd0_bus4 sd0_bus8 sd0_rclk;
 bus-width = 8;
 cap-mmc-highspeed;
 +   mmc-hs200-1_8v;
 +   mmc-hs400-1_8v;
  };
  
  mmc_2 {


 hdparm -t /dev/mmcblk0

 without this patch:
 /dev/mmcblk0:
  Timing buffered disk reads: 230 MB in  3.01 seconds =  76.30 MB/sec

 with this patch:
 /dev/mmcblk0:
  Timing buffered disk reads: 588 MB in  3.00 seconds = 195.92 MB/sec

 cat /sys/kernel/debug/mmc0/ios

 without patch:
 clock:  5200 Hz
 vdd:7 (1.65 - 1.95 V)
 bus mode:   2 (push-pull)
 chip select:0 (don't care)
 power mode: 2 (on)
 bus width:  3 (8 bits)
 timing spec:8 (mmc DDR52)
 signal voltage: 0 (1.80 V)

 with patch:
 clock:  2 Hz
 vdd:7 (1.65 - 1.95 V)
 bus mode:   2 (push-pull)
 chip select:0 (don't care)
 power mode: 2 (on)
 bus width:  3 (8 bits)
 timing spec:10 (mmc HS400)
 signal voltage: 0 (1.80 V)

 Best Regards

 
 

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Re: [PATCH ulf.hansson-mmc] mmc: dw_mmc: exynos: dw_mci_exynos_prepare_hs400_tuning() can be static

2015-03-05 Thread Jaehoon Chung
Hi,

Sorry for missing warning, and Thanks for pointing out.

Best Regards,
Jaehoon Chung


On 03/05/2015 07:02 PM, kbuild test robot wrote:
 
 Signed-off-by: Fengguang Wu fengguang...@intel.com
 ---
  dw_mmc-exynos.c |2 +-
  dw_mmc.c|2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 0a56d766..e761eb1 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -477,7 +477,7 @@ static int dw_mci_exynos_execute_tuning(struct 
 dw_mci_slot *slot)
   return ret;
  }
  
 -int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
 +static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
   struct mmc_ios *ios)
  {
   struct dw_mci_exynos_priv_data *priv = host-priv;
 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index f30ef69..a99fa1b 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -1324,7 +1324,7 @@ static int dw_mci_execute_tuning(struct mmc_host *mmc, 
 u32 opcode)
   return err;
  }
  
 -int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
 +static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios 
 *ios)
  {
   struct dw_mci_slot *slot = mmc_priv(mmc);
   struct dw_mci *host = slot-host;
 

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Re: [PATCH V5 1/2] mmc: dw_mmc: exynos: Support eMMC's HS400 mode

2015-02-24 Thread Jaehoon Chung
Hi, Alim.

Tested-by: Jaehoon Chung jh80.ch...@samsung.com
Acked-by: Jaehoon Chung jh80.ch...@samsung.com

I will include this patch into my tree, and i will request pull to Ulf.

Thanks!

Best Regards,
Jaehoon Chung

On 01/29/2015 11:41 AM, Alim Akhtar wrote:
 From: Seungwon Jeon tgih@samsung.com
 
 Implements HS400 mode support for exynos host driver.
 This also include some updates as new mode is added.
 
 Signed-off-by: Seungwon Jeon tgih@samsung.com
 Signed-off-by: Alim Akhtar alim.akh...@samsung.com
 [Alim: addressed review comments]
 ---
  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |7 +
  drivers/mmc/host/dw_mmc-exynos.c   |  185 
 
  drivers/mmc/host/dw_mmc-exynos.h   |   19 +-
  drivers/mmc/host/dw_mmc.c  |   16 +-
  drivers/mmc/host/dw_mmc.h  |2 +
  5 files changed, 195 insertions(+), 34 deletions(-)
 
 diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 index ee4fc05..aad9844 100644
 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 @@ -36,6 +36,8 @@ Required Properties:
in transmit mode and CIU clock phase shift value in receive mode for double
data rate mode operation. Refer notes below for the order of the cells and 
 the
valid values.
 +* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock 
 phase
 +  shift value for hs400 mode operation.
  
Notes for the sdr-timing and ddr-timing values:
  
 @@ -50,6 +52,9 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
  phase shift clocks should be 0.
  
 +* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
 +  (Latency value for delay line in Read path)
 +
  Required properties for a slot (Deprecated - Recommend to use one slot per 
 host):
  
  * gpios: specifies a list of gpios used for command, clock and data bus. The
 @@ -82,5 +87,7 @@ Example:
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 2 3;
   samsung,dw-mshc-ddr-timing = 1 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + samsung,read-strobe-delay = 90;
   bus-width = 8;
   };
 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index fe32948..0a56d76 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -40,7 +40,12 @@ struct dw_mci_exynos_priv_data {
   u8  ciu_div;
   u32 sdr_timing;
   u32 ddr_timing;
 + u32 hs400_timing;
 + u32 tuned_sample;
   u32 cur_speed;
 + u32 dqs_delay;
 + u32 saved_dqs_en;
 + u32 saved_strobe_ctrl;
  };
  
  static struct dw_mci_exynos_compatible {
 @@ -71,6 +76,21 @@ static struct dw_mci_exynos_compatible {
   },
  };
  
 +static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
 +{
 + struct dw_mci_exynos_priv_data *priv = host-priv;
 +
 + if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS4412)
 + return EXYNOS4412_FIXED_CIU_CLK_DIV;
 + else if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS4210)
 + return EXYNOS4210_FIXED_CIU_CLK_DIV;
 + else if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 + priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 + return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
 + else
 + return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
 +}
 +
  static int dw_mci_exynos_priv_init(struct dw_mci *host)
  {
   struct dw_mci_exynos_priv_data *priv = host-priv;
 @@ -85,6 +105,16 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
  SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
   }
  
 + if (priv-ctrl_type = DW_MCI_TYPE_EXYNOS5420) {
 + priv-saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
 + priv-saved_dqs_en = mci_readl(host, HS400_DQS_EN);
 + priv-saved_dqs_en |= AXI_NON_BLOCKING_WR;
 + mci_writel(host, HS400_DQS_EN, priv-saved_dqs_en);
 + if (!priv-dqs_delay)
 + priv-dqs_delay =
 + DQS_CTRL_GET_RD_DELAY(priv-saved_strobe_ctrl);
 + }
 +
   return 0;
  }
  
 @@ -97,6 +127,26 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
   return 0;
  }
  
 +static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
 +{
 + struct dw_mci_exynos_priv_data *priv = host-priv;
 + u32 clksel;
 +
 + if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7

Re: [PATCH V5 2/2] ARM: dts: Add HS400 support for exynos5420 and exynos5800

2015-02-24 Thread Jaehoon Chung
Hi, Alim.

Acked-by: Jaehoon Chung jh80.ch...@samsung.com

Best Regards,
Jaehoon Chung

On 01/29/2015 11:41 AM, Alim Akhtar wrote:
 From: Seungwon Jeon tgih@samsung.com
 
 HS400 timing values are added for SMDK5420, exynos5420-peach-pit
 and exynos5800-peach-pi boards.
 This also adds RCLK GPIO line, this gpio should be in pull-down
 state.
 This also enables HS400 on peach-pi and this updates the clock frequency
 to 800MHz to be set as input clock to controller.
 
 Signed-off-by: Seungwon Jeon tgih@samsung.com
 Signed-off-by: Alim Akhtar alim.akh...@samsung.com
 [Alim: addressed review comments]
 ---
  arch/arm/boot/dts/exynos5420-peach-pit.dts |4 +++-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi  |7 +++
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 +++-
  arch/arm/boot/dts/exynos5800-peach-pi.dts  |7 +--
  4 files changed, 18 insertions(+), 4 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts 
 b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 index 9a050e1..f7a44a4 100644
 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
 +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 @@ -569,8 +569,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + samsung,read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
  };
  
 diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi 
 b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 index ba686e4..8b15316 100644
 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 @@ -201,6 +201,13 @@
   samsung,pin-drv = 3;
   };
  
 + sd0_rclk: sd0-rclk {
 + samsung,pins = gpc0-7;
 + samsung,pin-function = 2;
 + samsung,pin-pud = 1;
 + samsung,pin-drv = 3;
 + };
 +
   sd1_cmd: sd1-cmd {
   samsung,pins = gpc1-1;
   samsung,pin-function = 2;
 diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
 b/arch/arm/boot/dts/exynos5420-smdk5420.dts
 index 8be3d7b..2078a1f 100644
 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
 +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
 @@ -80,8 +80,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + samsung,read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
   cap-mmc-highspeed;
   };
 diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts 
 b/arch/arm/boot/dts/exynos5800-peach-pi.dts
 index e8fdda8..96f0d61 100644
 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
 +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
 @@ -550,15 +550,18 @@
   num-slots = 1;
   broken-cd;
   mmc-hs200-1_8v;
 + mmc-hs400-1_8v;
   cap-mmc-highspeed;
   non-removable;
   card-detect-delay = 200;
 - clock-frequency = 4;
 + clock-frequency = 8;
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + samsung,read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
  };
  
 

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Re: [PATCH v5 0/2] mmc: dw_mmc: exynos: Add HS400 support

2015-02-05 Thread Jaehoon Chung
Hi, Vivek.

On 02/06/2015 02:52 PM, Vivek Gautam wrote:
 Hi Jaehoon,
 
 
 On Fri, Feb 6, 2015 at 6:48 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 Hi, Alim.

 On my board, this patch isn't working fine.
 So when i complete to test on my board(exynos5), i will reply with comments.
 Sorry for late testing.
 
 I tested this series on linux-next, on Exynos5800-peach-pi board, and HS400
 seems to be working fine.
 I can see the card getting detected as HS400, and then i ran iozone as well.
 The iozone numbers are also as required.
 
 On peach-pit board too, the HS200 mode seems to be working good.
 
 What are the observations you saw on your board ?

Thanks for testing on your board. I have exynos5422 and exynos5433.(One is 
eMMC5.0, other is eMMC5.1)
I want to see that it's working fine on my board.
I should miss something..so i will check more detail after complete my other 
job, or on this weekend.
(It failed for hs400 tuning sequence..I needs to check that it has the board 
dependency)

Best Regards,
Jaehoon Chung

 

 Best Regards,
 Jaehoon Chung

 On 01/29/2015 11:41 AM, Alim Akhtar wrote:
 This adds HS400 mode support for exynos dw_mmc host controller.

 Currently tested on Exynos5800-peach-pi and Exyons7 platform for HS400 mode.
 Tested HS200 mode with this series applied, HS200 still works.

 Appreciate testing on other exynos5/7 platform which supports emmc5.0

 Changes in V5:
   * Enable HS400 on Exynos5800-peach-pi boards
   * Addressed other review comments from Jaehoon Chung

 Changes in V4:
   * drop the idea of changing existing binding for ciu_div as per [1]
 * addressed comments from Jaehoon Chung [2]

 [1] http://www.spinics.net/lists/linux-samsung-soc/msg40923.html
 [2] http://www.spinics.net/lists/devicetree/msg64373.html

 Changes in V3:
   rebased on ulf's next (commit: 607b448 mmc: core: Make tuning block 
 patterns static)

 Seungwon Jeon (2):
   mmc: dw_mmc: exynos: Support eMMC's HS400 mode
   ARM: dts: Add HS400 support for exynos5420 and exynos5800

  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |7 +
  arch/arm/boot/dts/exynos5420-peach-pit.dts |4 +-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi  |7 +
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 +-
  arch/arm/boot/dts/exynos5800-peach-pi.dts  |7 +-
  drivers/mmc/host/dw_mmc-exynos.c   |  185 
 
  drivers/mmc/host/dw_mmc-exynos.h   |   19 +-
  drivers/mmc/host/dw_mmc.c  |   16 +-
  drivers/mmc/host/dw_mmc.h  |2 +
  9 files changed, 213 insertions(+), 38 deletions(-)


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Re: [PATCH v5 0/2] mmc: dw_mmc: exynos: Add HS400 support

2015-02-05 Thread Jaehoon Chung
Hi, Alim.

On my board, this patch isn't working fine.
So when i complete to test on my board(exynos5), i will reply with comments.
Sorry for late testing.

Best Regards,
Jaehoon Chung

On 01/29/2015 11:41 AM, Alim Akhtar wrote:
 This adds HS400 mode support for exynos dw_mmc host controller.
 
 Currently tested on Exynos5800-peach-pi and Exyons7 platform for HS400 mode.
 Tested HS200 mode with this series applied, HS200 still works.
 
 Appreciate testing on other exynos5/7 platform which supports emmc5.0
 
 Changes in V5:
   * Enable HS400 on Exynos5800-peach-pi boards
   * Addressed other review comments from Jaehoon Chung
 
 Changes in V4:
   * drop the idea of changing existing binding for ciu_div as per [1]
 * addressed comments from Jaehoon Chung [2]
 
 [1] http://www.spinics.net/lists/linux-samsung-soc/msg40923.html
 [2] http://www.spinics.net/lists/devicetree/msg64373.html
 
 Changes in V3:
   rebased on ulf's next (commit: 607b448 mmc: core: Make tuning block 
 patterns static)
 
 Seungwon Jeon (2):
   mmc: dw_mmc: exynos: Support eMMC's HS400 mode
   ARM: dts: Add HS400 support for exynos5420 and exynos5800
 
  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |7 +
  arch/arm/boot/dts/exynos5420-peach-pit.dts |4 +-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi  |7 +
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 +-
  arch/arm/boot/dts/exynos5800-peach-pi.dts  |7 +-
  drivers/mmc/host/dw_mmc-exynos.c   |  185 
 
  drivers/mmc/host/dw_mmc-exynos.h   |   19 +-
  drivers/mmc/host/dw_mmc.c  |   16 +-
  drivers/mmc/host/dw_mmc.h  |2 +
  9 files changed, 213 insertions(+), 38 deletions(-)
 

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Re: [PATCH 1/2] mmc: dw_mmc-exynos: add support for controlling emmc reset pin

2015-01-27 Thread Jaehoon Chung
Hi, Marek.

your patch should be conflicted with 
https://patchwork.kernel.org/patch/5698421/;

On 01/27/2015 05:11 PM, Marek Szyprowski wrote:
 There are boards (like Hardkernel's Odroid boards) on which eMMC card's
 reset line is connected to SoC GPIO line instead of the hardware reset
 logic. In case of such boards, before performing system reboot,
 additional reset of eMMC card is required to boot again properly.
 This patch adds code for handling such cases.

mmc core supported to hw_reset function.
So i think we can use it. It's called at only initial time to clear the 
previous status.
But i think it can be called at reboot time. (it needs to implement codes.)
how about?

Best Regards,
Jaehoon Chung

 
 Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
 ---
  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |  6 +++
  drivers/mmc/host/dw_mmc-exynos.c   | 43 
 +-
  2 files changed, 48 insertions(+), 1 deletion(-)
 
 diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 index ee4fc0576c7d..fc53d335e7db 100644
 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 @@ -50,6 +50,12 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
  phase shift clocks should be 0.
  
 +Optional properties:
 +
 +* dw-mshc-reset-gpios: optional property specifying gpio for the eMMC nreset
 +  line, it will be triggered on system reboot to properly reset eMMC card for
 +  next system boot.
 +
  Required properties for a slot (Deprecated - Recommend to use one slot per 
 host):
  
  * gpios: specifies a list of gpios used for command, clock and data bus. The
 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 509365cb22c6..2add5a93859d 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -12,12 +12,14 @@
  #include linux/module.h
  #include linux/platform_device.h
  #include linux/clk.h
 +#include linux/delay.h
  #include linux/mmc/host.h
  #include linux/mmc/dw_mmc.h
  #include linux/mmc/mmc.h
  #include linux/of.h
  #include linux/of_gpio.h
  #include linux/slab.h
 +#include linux/reboot.h
  
  #include dw_mmc.h
  #include dw_mmc-pltfm.h
 @@ -77,8 +79,23 @@ struct dw_mci_exynos_priv_data {
   u32 sdr_timing;
   u32 ddr_timing;
   u32 cur_speed;
 + struct gpio_desc*reset_gpio;
 + struct notifier_block   reset_nb;
  };
  
 +static int dw_mci_restart_handler(struct notifier_block *this,
 +   unsigned long mode, void *cmd)
 +{
 + struct dw_mci_exynos_priv_data *data;
 + data = container_of(this, struct dw_mci_exynos_priv_data, reset_nb);
 +
 + gpiod_direction_output(data-reset_gpio, 0);
 + mdelay(150);
 + gpiod_direction_output(data-reset_gpio, 1);
 +
 + return NOTIFY_DONE;
 +}
 +
  static struct dw_mci_exynos_compatible {
   char*compatible;
   enum dw_mci_exynos_type ctrl_type;
 @@ -295,7 +312,20 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
   return ret;
  
   priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 +
 + priv-reset_gpio = devm_gpiod_get_optional(host-dev,
 +samsung,dw-mshc-reset,
 +GPIOD_OUT_HIGH);
 + if (!IS_ERR_OR_NULL(priv-reset_gpio)) {
 + priv-reset_nb.notifier_call = dw_mci_restart_handler;
 + priv-reset_nb.priority = 255;
 + ret = register_restart_handler(priv-reset_nb);
 + if (ret)
 + dev_err(host-dev, cannot register restart handler\n);
 + }
 +
   host-priv = priv;
 +
   return 0;
  }
  
 @@ -490,6 +520,17 @@ static int dw_mci_exynos_probe(struct platform_device 
 *pdev)
   return dw_mci_pltfm_register(pdev, drv_data);
  }
  
 +static int dw_mci_exynos_remove(struct platform_device *pdev)
 +{
 + struct dw_mci *host = platform_get_drvdata(pdev);
 + struct dw_mci_exynos_priv_data *priv = host-priv;
 +
 + if (priv-reset_gpio)
 + unregister_restart_handler(priv-reset_nb);
 +
 + return dw_mci_pltfm_remove(pdev);
 +}
 +
  static const struct dev_pm_ops dw_mci_exynos_pmops = {
   SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
   .resume_noirq = dw_mci_exynos_resume_noirq,
 @@ -499,7 +540,7 @@ static const struct dev_pm_ops dw_mci_exynos_pmops = {
  
  static struct platform_driver dw_mci_exynos_pltfm_driver = {
   .probe  = dw_mci_exynos_probe,
 - .remove = __exit_p(dw_mci_pltfm_remove),
 + .remove = dw_mci_exynos_remove,
   .driver

Re: [PATCH] ARM: dts: Add sd0_rst pinctrl node to exynos5420

2015-01-25 Thread Jaehoon Chung
Hi,

On 01/24/2015 12:59 AM, Javier Martinez Canillas wrote:
 Hello Sjoerd,
 
 On Fri, Jan 23, 2015 at 4:47 PM, Sjoerd Simons
 sjoerd.sim...@collabora.co.uk wrote:

 If this pin is used by the Odroid XU3 board, shouldn't be defined in
 the exynos5422-odroidxu3.dts instead?

 It's not just used by the XU3 though, it's also hooked up on the peach
 pi chromebook for example and i would expect it to be hooked up on most
 board with an eMMC

 This change is consistent with most of the special purpose GPIO pins
 defined in that file, so i don't see the problem with including it in
 that pinctrl file
 
 In that case I completely agree that it should be defined in the .dtsi
 but that is not what the commit message said though :-)

I will resend the patch with obvious commit message.
Thanks for review.

Best Regards,
Jaehoon Chung

 
 Best regards,
 Javier
 

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[PATCH] ARM: dts: Add sd0_rst pinctrl node to exynos5420

2015-01-23 Thread Jaehoon Chung
Add sd0_rst node to exynos5420-pinctrl.dtsi.
(It's used on odroid-xu3 board)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
 arch/arm/boot/dts/exynos5420-pinctrl.dtsi |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi 
b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index ba686e4..315cad7 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -194,6 +194,11 @@
samsung,pin-drv = 3;
};
 
+   sd0_rst: sd0-rst {
+   samsung,pins = gpd1-0;
+   samsung,pin-function = 1;
+   };
+
sd1_clk: sd1-clk {
samsung,pins = gpc1-0;
samsung,pin-function = 2;
-- 
1.7.9.5

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Re: [PATCH v4 2/2] ARM: dts: Add HS400 support for exynos5420 and exynos5800

2015-01-21 Thread Jaehoon Chung
Hi.

On 01/21/2015 11:12 PM, Alim Akhtar wrote:
 Hi Jaehoon
 
 On Wed, Jan 21, 2015 at 4:32 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 Hi,

 If you want to enable the hs400 mode, need to add mmc-hs400-1_8v or 
 mmc-hs400-1_2v.
 But this patch didn't add them. do you have any other plan?

 Yes, right, plan is to send separate patch to enable hs400, as of now
 I am not sure if all the 5800-peach-pi boards are populated with
 emmc5.0 device or not. So I will enable HS400 after confirming this
 point.

I know if card is not support hs400, then it should be enabled to other bus 
mode.

Best Regards,
Jaehoon Chung

 On 01/14/2015 07:30 PM, Alim Akhtar wrote:
 From: Seungwon Jeon tgih@samsung.com

 HS400 timing values are added for SMDK5420, exynos5420-peach-pit
 and exynos5800-peach-pi boards.
 This also adds RCLK GPIO line, this gpio should be in pull-down
 state.

 Signed-off-by: Seungwon Jeon tgih@samsung.com
 Signed-off-by: Alim Akhtar alim.akh...@samsung.com
 [Alim: addressed review comments]
 ---
  arch/arm/boot/dts/exynos5420-peach-pit.dts |4 +++-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi  |7 +++
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 +++-
  arch/arm/boot/dts/exynos5800-peach-pi.dts  |4 +++-
  4 files changed, 16 insertions(+), 3 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts 
 b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 index 9a050e1..7ffaba8 100644
 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
 +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 @@ -569,8 +569,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
  };

 diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi 
 b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 index ba686e4..8b15316 100644
 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 @@ -201,6 +201,13 @@
   samsung,pin-drv = 3;
   };

 + sd0_rclk: sd0-rclk {

 I know it used to sd0_rdqs, not sd0_rclk.
 Change name.

 Ok, I will change as per UM of 5800/5420,
 
 Best Regards,
 Jaehoon Chung
 + samsung,pins = gpc0-7;
 + samsung,pin-function = 2;
 + samsung,pin-pud = 1;
 + samsung,pin-drv = 3;
 + };
 +
   sd1_cmd: sd1-cmd {
   samsung,pins = gpc1-1;
   samsung,pin-function = 2;
 diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
 b/arch/arm/boot/dts/exynos5420-smdk5420.dts
 index 8be3d7b..5290e79 100644
 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
 +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
 @@ -80,8 +80,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
   cap-mmc-highspeed;
   };
 diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts 
 b/arch/arm/boot/dts/exynos5800-peach-pi.dts
 index e8fdda8..fa1c858 100644
 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
 +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
 @@ -557,8 +557,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
  };



 
 
 

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Re: [PATCH v4 2/2] ARM: dts: Add HS400 support for exynos5420 and exynos5800

2015-01-20 Thread Jaehoon Chung
Hi,

If you want to enable the hs400 mode, need to add mmc-hs400-1_8v or 
mmc-hs400-1_2v.
But this patch didn't add them. do you have any other plan?

On 01/14/2015 07:30 PM, Alim Akhtar wrote:
 From: Seungwon Jeon tgih@samsung.com
 
 HS400 timing values are added for SMDK5420, exynos5420-peach-pit
 and exynos5800-peach-pi boards.
 This also adds RCLK GPIO line, this gpio should be in pull-down
 state.
 
 Signed-off-by: Seungwon Jeon tgih@samsung.com
 Signed-off-by: Alim Akhtar alim.akh...@samsung.com
 [Alim: addressed review comments]
 ---
  arch/arm/boot/dts/exynos5420-peach-pit.dts |4 +++-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi  |7 +++
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 +++-
  arch/arm/boot/dts/exynos5800-peach-pi.dts  |4 +++-
  4 files changed, 16 insertions(+), 3 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts 
 b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 index 9a050e1..7ffaba8 100644
 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
 +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
 @@ -569,8 +569,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
  };
  
 diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi 
 b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 index ba686e4..8b15316 100644
 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
 @@ -201,6 +201,13 @@
   samsung,pin-drv = 3;
   };
  
 + sd0_rclk: sd0-rclk {

I know it used to sd0_rdqs, not sd0_rclk.
Change name.

Best Regards,
Jaehoon Chung
 + samsung,pins = gpc0-7;
 + samsung,pin-function = 2;
 + samsung,pin-pud = 1;
 + samsung,pin-drv = 3;
 + };
 +
   sd1_cmd: sd1-cmd {
   samsung,pins = gpc1-1;
   samsung,pin-function = 2;
 diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
 b/arch/arm/boot/dts/exynos5420-smdk5420.dts
 index 8be3d7b..5290e79 100644
 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
 +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
 @@ -80,8 +80,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
   cap-mmc-highspeed;
   };
 diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts 
 b/arch/arm/boot/dts/exynos5800-peach-pi.dts
 index e8fdda8..fa1c858 100644
 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
 +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
 @@ -557,8 +557,10 @@
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 0 4;
   samsung,dw-mshc-ddr-timing = 0 2;
 + samsung,dw-mshc-hs400-timing = 0 2;
 + read-strobe-delay = 90;
   pinctrl-names = default;
 - pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 + pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8 sd0_rclk;
   bus-width = 8;
  };
  
 

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Re: [PATCH v4 1/2] mmc: dw_mmc: exynos: Support eMMC's HS400 mode

2015-01-20 Thread Jaehoon Chung
;
   }
 +
 + /* Set clock timing for the requested speed mode*/
 + dw_mci_exynos_set_clksel_timing(host, clksel);
 +
 + /* Configure setting for HS400 */
 + dw_mci_exynos_config_hs400(host, timing);
 +
 + /* Configure clock rate */
 + dw_mci_exynos_adjust_clock(host, wanted);
  }
  
  static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 @@ -260,6 +353,16 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
   return ret;
  
   priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 +
 + ret = of_property_read_u32_array(np,
 + samsung,dw-mshc-hs400-timing, timing, 2);
 + if (!ret  of_property_read_u32(np,
 + read-strobe-delay, priv-dqs_delay))
 + dev_info(host-dev,
 + read-strobe-delay is not found, assuming usage of 
 default value\n);

Need the message?

 +
 + priv-hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
 + HS400_FIXED_CIU_CLK_DIV);

Why useed the HS400_FIXED_CIU_CLK_DIV? always set to 1?

Best Regards,
Jaehoon Chung

   host-priv = priv;
   return 0;
  }
 @@ -285,7 +388,7 @@ static inline void dw_mci_exynos_set_clksmpl(struct 
 dw_mci *host, u8 sample)
   clksel = mci_readl(host, CLKSEL64);
   else
   clksel = mci_readl(host, CLKSEL);
 - clksel = (clksel  ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
 + clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
   if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
   priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
   mci_writel(host, CLKSEL64, clksel);
 @@ -304,13 +407,16 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct 
 dw_mci *host)
   clksel = mci_readl(host, CLKSEL64);
   else
   clksel = mci_readl(host, CLKSEL);
 +
   sample = (clksel + 1)  0x7;
 - clksel = (clksel  ~0x7) | sample;
 + clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 +
   if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
   priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
   mci_writel(host, CLKSEL64, clksel);
   else
   mci_writel(host, CLKSEL, clksel);
 +
   return sample;
  }
  
 @@ -343,6 +449,7 @@ out:
  static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
  {
   struct dw_mci *host = slot-host;
 + struct dw_mci_exynos_priv_data *priv = host-priv;
   struct mmc_host *mmc = slot-mmc;
   u8 start_smpl, smpl, candiates = 0;
   s8 found = -1;
 @@ -360,14 +467,27 @@ static int dw_mci_exynos_execute_tuning(struct 
 dw_mci_slot *slot)
   } while (start_smpl != smpl);
  
   found = dw_mci_exynos_get_best_clksmpl(candiates);
 - if (found = 0)
 + if (found = 0) {
   dw_mci_exynos_set_clksmpl(host, found);
 - else
 + priv-tuned_sample = found;
 + } else {
   ret = -EIO;
 + }
  
   return ret;
  }
  
 +int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
 + struct mmc_ios *ios)
 +{
 + struct dw_mci_exynos_priv_data *priv = host-priv;
 +
 + dw_mci_exynos_set_clksel_timing(host, priv-hs400_timing);
 + dw_mci_exynos_adjust_clock(host, (ios-clock)  1);
 +
 + return 0;
 +}
 +
  /* Common capabilities of Exynos4/Exynos5 SoC */
  static unsigned long exynos_dwmmc_caps[4] = {
   MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 @@ -384,6 +504,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
   .set_ios= dw_mci_exynos_set_ios,
   .parse_dt   = dw_mci_exynos_parse_dt,
   .execute_tuning = dw_mci_exynos_execute_tuning,
 + .prepare_hs400_tuning   = dw_mci_exynos_prepare_hs400_tuning,
  };
  
  static const struct of_device_id dw_mci_exynos_match[] = {
 diff --git a/drivers/mmc/host/dw_mmc-exynos.h 
 b/drivers/mmc/host/dw_mmc-exynos.h
 index 7872ce5..595c934 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.h
 +++ b/drivers/mmc/host/dw_mmc-exynos.h
 @@ -12,20 +12,36 @@
  #ifndef _DW_MMC_EXYNOS_H_
  #define _DW_MMC_EXYNOS_H_
  
 -/* Extended Register's Offset */
  #define SDMMC_CLKSEL 0x09C
  #define SDMMC_CLKSEL64   0x0A8
  
 +/* Extended Register's Offset */
 +#define SDMMC_HS400_DQS_EN   0x180
 +#define SDMMC_HS400_ASYNC_FIFO_CTRL  0x184
 +#define SDMMC_HS400_DLINE_CTRL   0x188
 +
  /* CLKSEL register defines */
  #define SDMMC_CLKSEL_CCLK_SAMPLE(x)  (((x)  7)  0)
  #define SDMMC_CLKSEL_CCLK_DRIVE(x)   (((x)  7)  16)
  #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x)  7)  24)
  #define SDMMC_CLKSEL_GET_DRV_WD3(x)  (((x)  16)  0x7)
 +#define SDMMC_CLKSEL_GET_DIV(x)  (((x)  24)  0x7)
 +#define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x)  ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
 +  SDMMC_CLKSEL_CCLK_SAMPLE(y))
  #define SDMMC_CLKSEL_TIMING(x, y, z

Re: [PATCH v4 0/2] mmc: dw_mmc: exynos: Add HS400 support

2015-01-14 Thread Jaehoon Chung
Hi, Alim.

On 01/14/2015 07:30 PM, Alim Akhtar wrote:
 This adds HS400 mode support for exynos dw_mmc host controller.
 
 Currently tested on Exynos5800-peach-pi platform for HS400 mode.
 Tested HS200 mode with this series applied, HS200 still works.
 
 Appreciate testing on other exynos5/7 platform which supports emmc5.0

I will test this patch on exynos5/7 board.

Best Regards,
Jaehoon Chung
 
 Changes in V4:
   * drop the idea of changing existing binding for ciu_div as per [1]
 * addressed comments from Jaehoon Chung [2]
 
 [1] http://www.spinics.net/lists/linux-samsung-soc/msg40923.html
 [2] http://www.spinics.net/lists/devicetree/msg64373.html
 
 Changes in V3:
   rebased on ulf's next (commit: 607b448 mmc: core: Make tuning block 
 patterns static)
 
 Seungwon Jeon (2):
   mmc: dw_mmc: exynos: Support eMMC's HS400 mode
   ARM: dts: Add HS400 support for exynos5420 and exynos5800
 
  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |7 +
  arch/arm/boot/dts/exynos5420-peach-pit.dts |4 +-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi  |7 +
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |4 +-
  arch/arm/boot/dts/exynos5800-peach-pi.dts  |4 +-
  drivers/mmc/host/dw_mmc-exynos.c   |  187 
 
  drivers/mmc/host/dw_mmc-exynos.h   |   19 +-
  drivers/mmc/host/dw_mmc.c  |   16 +-
  drivers/mmc/host/dw_mmc.h  |2 +
  9 files changed, 212 insertions(+), 38 deletions(-)
 

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Re: [PATCH v3 2/4] mmc: dw_mmc: exynos: support eMMC's HS400 mode

2015-01-07 Thread Jaehoon Chung
 = mci_readl(host, CLKSEL);
 - clksel = (clksel  ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
 +
 + clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 +
   if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
   priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
   mci_writel(host, CLKSEL64, clksel);
 @@ -339,13 +422,16 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct 
 dw_mci *host)
   clksel = mci_readl(host, CLKSEL64);
   else
   clksel = mci_readl(host, CLKSEL);
 +
   sample = (clksel + 1)  0x7;
 - clksel = (clksel  ~0x7) | sample;
 + clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 +
   if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
   priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
   mci_writel(host, CLKSEL64, clksel);
   else
   mci_writel(host, CLKSEL, clksel);
 +
   return sample;
  }
  
 @@ -378,6 +464,7 @@ out:
  static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
  {
   struct dw_mci *host = slot-host;
 + struct dw_mci_exynos_priv_data *priv = host-priv;
   struct mmc_host *mmc = slot-mmc;
   u8 start_smpl, smpl, candiates = 0;
   s8 found = -1;
 @@ -395,14 +482,27 @@ static int dw_mci_exynos_execute_tuning(struct 
 dw_mci_slot *slot)
   } while (start_smpl != smpl);
  
   found = dw_mci_exynos_get_best_clksmpl(candiates);
 - if (found = 0)
 + if (found = 0) {
   dw_mci_exynos_set_clksmpl(host, found);
 - else
 + priv-tuned_sample = found;
 + } else {
   ret = -EIO;
 + }
  
   return ret;
  }
  
 +int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
 + struct mmc_ios *ios)
 +{
 + struct dw_mci_exynos_priv_data *priv = host-priv;
 +
 + dw_mci_exynos_set_clksel_timing(host, priv-hs400_timing);
 + dw_mci_exynos_adjust_clock(host, (ios-clock)  1);
 +
 + return 0;
 +}
 +
  /* Common capabilities of Exynos4/Exynos5 SoC */
  static unsigned long exynos_dwmmc_caps[4] = {
   MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 @@ -419,6 +519,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
   .set_ios= dw_mci_exynos_set_ios,
   .parse_dt   = dw_mci_exynos_parse_dt,
   .execute_tuning = dw_mci_exynos_execute_tuning,
 + .prepare_hs400_tuning   = dw_mci_exynos_prepare_hs400_tuning,
  };
  
  static const struct of_device_id dw_mci_exynos_match[] = {
 diff --git a/drivers/mmc/host/dw_mmc-exynos.h 
 b/drivers/mmc/host/dw_mmc-exynos.h
 index c04ecef..e7faffe 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.h
 +++ b/drivers/mmc/host/dw_mmc-exynos.h
 @@ -12,21 +12,36 @@
  #ifndef _DW_MMC_EXYNOS_H_
  #define _DW_MMC_EXYNOS_H_
  
 -/* Extended Register's Offset */
  #define SDMMC_CLKSEL 0x09C
  #define SDMMC_CLKSEL64   0x0A8
  
 +/* Extended Register's Offset */
 +#define SDMMC_HS400_DQS_EN   0x180
 +#define SDMMC_HS400_ASYNC_FIFO_CTRL  0x184
 +#define SDMMC_HS400_DLINE_CTRL   0x188
 +
  /* CLKSEL register defines */
  #define SDMMC_CLKSEL_CCLK_SAMPLE(x)  (((x)  7)  0)
  #define SDMMC_CLKSEL_CCLK_DRIVE(x)   (((x)  7)  16)
  #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x)  7)  24)
  #define SDMMC_CLKSEL_GET_DRV_WD3(x)  (((x)  16)  0x7)
  #define SDMMC_CLKSEL_GET_DIV(x)  (((x)  24)  0x7)
 +#define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x)  ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
 +  SDMMC_CLKSEL_CCLK_SAMPLE(y))
  #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
SDMMC_CLKSEL_CCLK_DRIVE(y) |   \
SDMMC_CLKSEL_CCLK_DIVIDER(z))
 +#define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7)
  #define SDMMC_CLKSEL_WAKEUP_INT  BIT(11)
  
 +/* HS400 control defines */
 +#define DATA_STROBE_EN   BIT(0)
Add comment xxx register defines.

 +#define AXI_NON_BLOCKING_WR  BIT(7)

I can't find this bit and comment..where?

 +
 +/* Delay Line Control defines */
 +#define DQS_CTRL_RD_DELAY(x, y)  (((x)  ~0x3FF) | ((y)  0x3FF))

I'm not understanding this define... clear and set?

Best Regards,
Jaehoon Chung

 +#define DQS_CTRL_GET_RD_DELAY(x) ((x)  0x3FF)
 +
  /* Protector Register */
  #define SDMMC_EMMCP_BASE 0x1000
  #define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 2e8abc8..43a3a5b 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -1084,7 +1084,8 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
 mmc_ios *ios)
   regs = mci_readl(slot-host, UHS_REG);
  
   /* DDR mode set */
 - if (ios-timing == MMC_TIMING_MMC_DDR52)
 + if (ios-timing == MMC_TIMING_MMC_DDR52 ||
 + ios-timing == MMC_TIMING_MMC_HS400

Re: [PATCH] mmc: dw_mmc: exynos: Add support for exynos7

2014-11-11 Thread Jaehoon Chung
Hi, Alim.

I have also tested this patch with my board.
It's working fine. Looks good to me.

Dear, Ulf.

Could you merge this patch at your repository?

Acked-by: Jaehoon Chung jh80.ch...@samsung.com

Best Regards,
Jaehoon Chung

On 11/11/2014 11:14 PM, Alim Akhtar wrote:
 Hi Jaehoon,
 As 64bit dependent patch for dw_mmc is already merged.
 Do you have any comments on this patch?
 
 This patch still apply cleanly on ulf's next and v3.18-rc4 kernel.
 
 Regards,
 Alim
 
 On Tue, Oct 21, 2014 at 1:50 PM, Vivek Gautam gautam.vi...@samsung.com 
 wrote:
 On Tue, Oct 21, 2014 at 1:47 PM, Vivek Gautam gautam.vi...@samsung.com 
 wrote:

 Corrected Tomasz's mail id, as the earlier samsung one is not valid now.
 Also giving a Tested-by

 On Mon, Sep 1, 2014 at 11:14 AM, Abhilash Kesavan
 kesavan.abhil...@gmail.com wrote:
 Hi Jaehoon,

 +Prabu Thangamuthu

 On Fri, Aug 29, 2014 at 4:14 PM, Jaehoon Chung jh80.ch...@samsung.com 
 wrote:
 Hi, Abhilash.

 On 08/28/2014 10:18 PM, Yuvaraj Kumar C D wrote:
 From: Abhilash Kesavan a.kesa...@samsung.com

 The Exynos7 has a DWMMC controller (v2.70a) which is different from
 prior versions. This patch adds new compatible strings for exynos7.
 This patch also fixes the CLKSEL register offset on exynos7.

 If support the 64bit, dw-mmc.c need to modify.(according to v2.70, some 
 offset is changed for 64-bit address)
 But i didn't see any patches at mailing.
 Do you have the plan which send patch of dw-mmc.c?

 We are using a rebased version of
 http://www.spinics.net/lists/linux-mmc/msg21742.html to handle the
 dwmmc side changes. We should have mentioned this dependency as the
 patch is required for proper functioning of dwmmc on Exynos7.
 Stress tests are on-going with that patch and once it looks good, we
 will post our results so that the original patch may be taken forward.

 Regards,
 Abhilash

 Best Regards,
 Jaehoon Chung

 Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
 ---

 I have tested this patch following set of patches:

 On Exynos7 support side:
 1) dts, kbuild: Implement support for dtb vendor subdirs patchset
 http://comments.gmane.org/gmane.linux.kbuild.devel/12131
 2) arch: arm64: Enable support for Samsung Exynos7 SoC  (V5)
 http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
 3) Serial clean-up patches for Exynos7
 http://www.spinics.net/lists/arm-kernel/msg367348.html
 http://www.spinics.net/lists/arm-kernel/msg367349.html
 4) Add initial support for pinctrl on Exynos7  (V5)
 http://www.spinics.net/lists/linux-samsung-soc/msg37708.html

 On MMC side:
 1) mmc: dw_mmc: Add IDMAC 64-bit address mode support  (V7)
 https://lkml.org/lkml/2014/10/20/58
 2) mmc: dw_mmc: Reset DMA before enabling IDMAC  (V2)
 http://www.gossamer-threads.com/lists/linux/kernel/2028229

 eMMC and SD are running fine on Exynos7.

 Tested-by: Vivek Gautam gautam.vi...@samsung.com


 If this change looks good, then we can take it in.

  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 +
  drivers/mmc/host/dw_mmc-exynos.c   |   91 
 +---
  2 files changed, 82 insertions(+), 13 deletions(-)

 diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 index 6cd3525..ee4fc05 100644
 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 @@ -18,6 +18,10 @@ Required Properties:
 specific extensions.
   - samsung,exynos5420-dw-mshc: for controllers with Samsung 
 Exynos5420
 specific extensions.
 + - samsung,exynos7-dw-mshc: for controllers with Samsung Exynos7
 +   specific extensions.
 + - samsung,exynos7-dw-mshc-smu: for controllers with Samsung 
 Exynos7
 +   specific extensions having an SMU.

  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card 
 interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's 
 and
 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 0fbc53a..509365c 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -25,6 +25,7 @@
  #define NUM_PINS(x)  (x + 2)

  #define SDMMC_CLKSEL 0x09C
 +#define SDMMC_CLKSEL64   0x0A8
  #define SDMMC_CLKSEL_CCLK_SAMPLE(x)  (((x)  7)  0)
  #define SDMMC_CLKSEL_CCLK_DRIVE(x)   (((x)  7)  16)
  #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x)  7)  24)
 @@ -65,6 +66,8 @@ enum dw_mci_exynos_type {
   DW_MCI_TYPE_EXYNOS5250,
   DW_MCI_TYPE_EXYNOS5420,
   DW_MCI_TYPE_EXYNOS5420_SMU,
 + DW_MCI_TYPE_EXYNOS7,
 + DW_MCI_TYPE_EXYNOS7_SMU,
  };

  /* Exynos implementation specific driver private data */
 @@ -95,6 +98,12 @@ static struct dw_mci_exynos_compatible {
   }, {
   .compatible = samsung,exynos5420-dw-mshc-smu,
   .ctrl_type

Re: [PATCH] ARM: dts: fix MMC2 regulators for Exynos5420 Arndale Octa board

2014-10-07 Thread Jaehoon Chung
Hi,

On 10/07/2014 01:51 AM, Doug Anderson wrote:
 Bartlomiej,
 
 On Thu, Oct 2, 2014 at 10:24 AM, Bartlomiej Zolnierkiewicz
 b.zolnier...@samsung.com wrote:

 Hi,

 On Thursday, October 02, 2014 09:45:41 AM Doug Anderson wrote:
 Bartiomiej

 On Thu, Oct 2, 2014 at 9:39 AM, Bartlomiej Zolnierkiewicz
 b.zolnier...@samsung.com wrote:
 On Thursday, October 02, 2014 09:19:08 AM Doug Anderson wrote:
 Bartiomiej,

 On Thu, Oct 2, 2014 at 9:10 AM, Bartlomiej Zolnierkiewicz
 b.zolnier...@samsung.com wrote:
 Regulators for MMC2 (SD card) are PVDD_TFLASH_2V8 (LDO19) for vmmc
 and PVDD_APIO_MMCOFF_2V8 (LDO13) for vqmmc.  Currently the device
 tree entry for MMC2 uses PVDD_PRE_1V8 (LDO10) for vmmc and vqmmc is
 not specified.  Fix it.

 Without this patch:
 - mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators
   patch causes a SD card detection to fail
 - mmc: dw_mmc: Support voltage changes patch causes a boot hang

 This patch fixes both above problems.

 Suggested-by: Doug Anderson diand...@google.com
 Cc: Yuvaraj Kumar C D yuvaraj...@samsung.com
 Cc: Ulf Hansson ulf.hans...@linaro.org
 Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  arch/arm/boot/dts/exynos5420-arndale-octa.dts |3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

 Index: b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
 ===
 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts 2014-10-02 
 15:44:53.014826886 +0200
 +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts 2014-10-02 
 17:35:24.110600398 +0200
 @@ -74,7 +74,8 @@
 samsung,dw-mshc-ddr-timing = 1 2;
 pinctrl-names = default;
 pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
 -   vmmc-supply = ldo10_reg;
 +   vmmc-supply = ldo19_reg;
 +   vqmmc-supply = ldo13_reg;

 This looks right to me.  ...but I notice that ldo13 and ldo19 are not
 always-on in the DTS.  Are you sure card detect works for you if you
 eject your card and try to put it back in?

 ...eventually the always-on won't be needed, but for now I think it 
 is...

 Card detection works fine without always-on.

 That's weird.

 1. In the schematics I see XMMC2CDN has an external pullup to 
 PVDD_TFLASH_2V8.

 2. The internal pullup should (I think) be to VDDQ_MMC2 which is
 PVDD_APIO_MMCOFF_2V8.

 3. In (51da224 mmc: dw_mmc: use mmc_regulator_get_supply to handle
 regulators) we should be turning off both regulators in
 MMC_POWER_OFF.

 4. If I understand correctly MMC_POWER_OFF is called when the card is
 ejected, which means that both regulators should be off when the card
 is ejected.

 5. I don't think card detect can work if neither regulator is powered.


 One of the above points must be wrong.  Any idea which one?  Can you
 check to see if MMC_POWER_OFF is called for you when the card is
 ejected?  Can you check to see if these regulators are off?

 MMC_POWER_OFF is called on card removal and both regulators get disabled
 (I have verified that they are really off with regulator_is_enabled() which
 returns 1 before and 0 after disabling regulator).  It seems that 5. is
 wrong?
 
 This really doesn't make a lot of sense to me, so I'm still kinda
 confused.  If you want to call it good then that's your (and Ulf's)
 decision, but it's the kind of thing that would keep me up at night.
 How can this pin be high if all the regulators pulling it up are off?
 Is there a current leak somewhere and that's why it's working?
 
 How this is supposed to work (as I understand it):
 
 1. When no card is inserted then this pin is supposed to be pulled up
 to VDDQ_MMC2.  That could be either an internal or an external pullup.
 It should be pulled up to VDDQ_MMC2 (as opposed to any other voltage)
 since the exynos manual documents that this pin lives in the VDDQ_MMC2
 io domain.  Note that it could be pulled up externally to a different
 supply than the one going to VDDQ_MMC2, but for correctness it should
 be the same voltage.
 
 2. When a card is inserted, the pin will be grounded (AKA this is an
 open drain pin).
 
 
 With your patch, can you probe the pin and see if card detect is high
 when all the regulators are off?  Any idea how it gets high?  If you
 turn off the internal pullup is it still high?

I remembered that I and Doug were discussed for this problem with 
exynos5420-peach board(?), right?
Is arndale-octa board the same circuit with peach?
If it's same, I think Doug's comment is right.
But if card-detect pis is used with other power, we don't need to consider the 
VDDQ_MMC2 power domain.
It needs more information and checks its schematic.

Best Regards,
Jaehoon Chung

 
 
 -Doug
 

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Re: [PATCH V2 1/3] mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators

2014-09-29 Thread Jaehoon Chung
Hi

On 09/29/2014 09:31 PM, Bartlomiej Zolnierkiewicz wrote:
 
 Hi,
 
 On Friday, August 29, 2014 01:34:44 PM Ulf Hansson wrote:
 On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
 This patch makes use of mmc_regulator_get_supply() to handle
 the vmmc and vqmmc regulators.Also it moves the code handling
 the these regulators to dw_mci_set_ios().It turned on the vmmc
 and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
 during MMC_POWER_OFF.

 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com

 Thanks! Applied for next.
 
 Unfortunately this patch breaks mmc1 card (Kingston 32GB micro SDHC)
 detection on Exynos5420 Arndale Octa for me:
 
 [   10.797979] dwmmc_exynos 1222.mmc: no support for card's volts
 [   10.797998] mmc1: error -22 whilst initialising SD card

OCR value is not matched. Which values are supported about the mmc_host's value 
and card's value?
Could you share the value?

Best Regards,
Jaehoon Chung

 
 Without the patch:
 
 [   10.866926] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot req 
 5000Hz, actual 5000HZ div = 0)
 [   10.866977] mmc1: new high speed SDHC card at address 1234
 [   10.868730] mmcblk1: mmc1:1234 SA32G 29.3 GiB 
 [   10.915054]  mmcblk1: p1 p2 p3
 
 The config is attached (exynos_defconfig doesn't work correctly for
 this board yet).
 
 Best regards,
 --
 Bartlomiej Zolnierkiewicz
 Samsung RD Institute Poland
 Samsung Electronics
 
 Kind regards
 Uffe

 ---
 changes from v1:
 1.Used mmc_regulator_set_ocr() instead of regulator_enable() for 
 vmmc.
 2.Turned on vmmc and vqmmc during MMC_POWER_UP.
 3. Removed the flags DW_MMC_CARD_POWERED and DW_MMC_IO_POWERED which
added during the initial version of this patch.
 4. Added error message, if it failed to turn on regulator's.

  drivers/mmc/host/dw_mmc.c  |   72 
 +---
  include/linux/mmc/dw_mmc.h |2 +-
  2 files changed, 36 insertions(+), 38 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 7f227e9..aadb0d6 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -936,6 +936,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
 mmc_ios *ios)
 struct dw_mci_slot *slot = mmc_priv(mmc);
 const struct dw_mci_drv_data *drv_data = slot-host-drv_data;
 u32 regs;
 +   int ret;

 switch (ios-bus_width) {
 case MMC_BUS_WIDTH_4:
 @@ -974,12 +975,38 @@ static void dw_mci_set_ios(struct mmc_host *mmc, 
 struct mmc_ios *ios)

 switch (ios-power_mode) {
 case MMC_POWER_UP:
 +   if (!IS_ERR(mmc-supply.vmmc)) {
 +   ret = mmc_regulator_set_ocr(mmc, mmc-supply.vmmc,
 +   ios-vdd);
 +   if (ret) {
 +   dev_err(slot-host-dev,
 +   failed to enable vmmc 
 regulator\n);
 +   /*return, if failed turn on vmmc*/
 +   return;
 +   }
 +   }
 +   if (!IS_ERR(mmc-supply.vqmmc)  
 !slot-host-vqmmc_enabled) {
 +   ret = regulator_enable(mmc-supply.vqmmc);
 +   if (ret  0)
 +   dev_err(slot-host-dev,
 +   failed to enable vqmmc 
 regulator\n);
 +   else
 +   slot-host-vqmmc_enabled = true;
 +   }
 set_bit(DW_MMC_CARD_NEED_INIT, slot-flags);
 regs = mci_readl(slot-host, PWREN);
 regs |= (1  slot-id);
 mci_writel(slot-host, PWREN, regs);
 break;
 case MMC_POWER_OFF:
 +   if (!IS_ERR(mmc-supply.vmmc))
 +   mmc_regulator_set_ocr(mmc, mmc-supply.vmmc, 0);
 +
 +   if (!IS_ERR(mmc-supply.vqmmc)  
 slot-host-vqmmc_enabled) {
 +   regulator_disable(mmc-supply.vqmmc);
 +   slot-host-vqmmc_enabled = false;
 +   }
 +
 regs = mci_readl(slot-host, PWREN);
 regs = ~(1  slot-id);
 mci_writel(slot-host, PWREN, regs);
 @@ -2110,7 +2137,13 @@ static int dw_mci_init_slot(struct dw_mci *host, 
 unsigned int id)
 mmc-f_max = freq[1];
 }

 -   mmc-ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 +   /*if there are external regulators, get them*/
 +   ret = mmc_regulator_get_supply(mmc);
 +   if (ret == -EPROBE_DEFER)
 +   goto err_setup_bus;
 +
 +   if (!mmc-ocr_avail)
 +   mmc-ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;

 if (host-pdata-caps)
 mmc-caps = host-pdata-caps;
 @@ -2176,7 +2209,7 @@ static int dw_mci_init_slot(struct dw_mci *host, 
 unsigned int id)

  err_setup_bus

Re: [PATCH] mmc: dw_mmc: exynos: Add support for exynos7

2014-08-29 Thread Jaehoon Chung
Hi, Abhilash.

On 08/28/2014 10:18 PM, Yuvaraj Kumar C D wrote:
 From: Abhilash Kesavan a.kesa...@samsung.com
 
 The Exynos7 has a DWMMC controller (v2.70a) which is different from
 prior versions. This patch adds new compatible strings for exynos7.
 This patch also fixes the CLKSEL register offset on exynos7.

If support the 64bit, dw-mmc.c need to modify.(according to v2.70, some offset 
is changed for 64-bit address)
But i didn't see any patches at mailing. 
Do you have the plan which send patch of dw-mmc.c?

Best Regards,
Jaehoon Chung
 
 Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
 ---
  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 +
  drivers/mmc/host/dw_mmc-exynos.c   |   91 
 +---
  2 files changed, 82 insertions(+), 13 deletions(-)
 
 diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 index 6cd3525..ee4fc05 100644
 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 @@ -18,6 +18,10 @@ Required Properties:
 specific extensions.
   - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
 specific extensions.
 + - samsung,exynos7-dw-mshc: for controllers with Samsung Exynos7
 +   specific extensions.
 + - samsung,exynos7-dw-mshc-smu: for controllers with Samsung Exynos7
 +   specific extensions having an SMU.
  
  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 0fbc53a..509365c 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -25,6 +25,7 @@
  #define NUM_PINS(x)  (x + 2)
  
  #define SDMMC_CLKSEL 0x09C
 +#define SDMMC_CLKSEL64   0x0A8
  #define SDMMC_CLKSEL_CCLK_SAMPLE(x)  (((x)  7)  0)
  #define SDMMC_CLKSEL_CCLK_DRIVE(x)   (((x)  7)  16)
  #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x)  7)  24)
 @@ -65,6 +66,8 @@ enum dw_mci_exynos_type {
   DW_MCI_TYPE_EXYNOS5250,
   DW_MCI_TYPE_EXYNOS5420,
   DW_MCI_TYPE_EXYNOS5420_SMU,
 + DW_MCI_TYPE_EXYNOS7,
 + DW_MCI_TYPE_EXYNOS7_SMU,
  };
  
  /* Exynos implementation specific driver private data */
 @@ -95,6 +98,12 @@ static struct dw_mci_exynos_compatible {
   }, {
   .compatible = samsung,exynos5420-dw-mshc-smu,
   .ctrl_type  = DW_MCI_TYPE_EXYNOS5420_SMU,
 + }, {
 + .compatible = samsung,exynos7-dw-mshc,
 + .ctrl_type  = DW_MCI_TYPE_EXYNOS7,
 + }, {
 + .compatible = samsung,exynos7-dw-mshc-smu,
 + .ctrl_type  = DW_MCI_TYPE_EXYNOS7_SMU,
   },
  };
  
 @@ -102,7 +111,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
  {
   struct dw_mci_exynos_priv_data *priv = host-priv;
  
 - if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
 + if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
 + priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
   mci_writel(host, MPSBEGIN0, 0);
   mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
   mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
 @@ -153,11 +163,22 @@ static int dw_mci_exynos_resume(struct device *dev)
  static int dw_mci_exynos_resume_noirq(struct device *dev)
  {
   struct dw_mci *host = dev_get_drvdata(dev);
 + struct dw_mci_exynos_priv_data *priv = host-priv;
   u32 clksel;
  
 - clksel = mci_readl(host, CLKSEL);
 - if (clksel  SDMMC_CLKSEL_WAKEUP_INT)
 - mci_writel(host, CLKSEL, clksel);
 + if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 + priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 + clksel = mci_readl(host, CLKSEL64);
 + else
 + clksel = mci_readl(host, CLKSEL);
 +
 + if (clksel  SDMMC_CLKSEL_WAKEUP_INT) {
 + if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 + priv-ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 + mci_writel(host, CLKSEL64, clksel);
 + else
 + mci_writel(host, CLKSEL, clksel);
 + }
  
   return 0;
  }
 @@ -169,6 +190,7 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
  
  static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
  {
 + struct dw_mci_exynos_priv_data *priv = host-priv;
   /*
* Exynos4412 and Exynos5250 extends the use of CMD register with the
* use of bit 29 (which is reserved on standard MSHC controllers) for
 @@ -176,8 +198,14 @@ static void dw_mci_exynos_prepare_command(struct dw_mci 
 *host, u32 *cmdr)
* HOLD register should be bypassed in case there is no phase

Re: [PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

2014-08-28 Thread Jaehoon Chung
On 08/28/2014 12:49 AM, Doug Anderson wrote:
 Jaehoon,
 
 On Tue, Aug 26, 2014 at 9:47 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 Doug,

 On 08/27/2014 01:14 PM, Doug Anderson wrote:
 Jaehoon,

 On Tue, Aug 26, 2014 at 8:48 PM, Jaehoon Chung jh80.ch...@samsung.com 
 wrote:
 Hi, Doug,

 On 08/26/2014 12:25 AM, Doug Anderson wrote:
 Jaehoon,

 On Mon, Aug 25, 2014 at 1:50 AM, Jaehoon Chung jh80.ch...@samsung.com 
 wrote:
 On 08/25/2014 05:13 PM, Ulf Hansson wrote:
 On 22 August 2014 20:27, Sonny Rao sonny...@chromium.org wrote:
 On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson ulf.hans...@linaro.org 
 wrote:
 On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com 
 wrote:
 Exynos 5250 and 5420 based boards uses built-in CD# line for card
 detection.But unfortunately CD# line is on the same voltage rails
 as of I/O voltage rails. When we cut off vqmmc,the consequent card
 detection will break in these boards.

 I didn't know that use CD# line for card detect.
 And if CD# voltage rails and I/O voltage rail are same voltage, it 
 doesn't make sense.
 Which card is used with same voltages? (eMMC? SD? SDIO?)

 Well, I have checked Exynos5250 and 5420, but it looks like not same 
 rails.

 I'm not sure I totally understood what you said.  In my manual I have
 a table titled Table 2-1 Exynos 5420 Pin List.  Look in this table
 for XMMC2CDN and XMMC2DATA_0.  Look to the right of the table and
 you'll see the power domain.  For both it shows VDDQ_MMC2.  If that
 doesn't mean that the two are in the same voltage domain then I don't
 know what does.  Can you point to any examples where they have
 different voltage domains?
 I think you're mis-understanding for it.
 Right, It's described at exynos5420, but it's not connected.

 It's not connected.  What do you mean?  If I were to guess I'd say
 that on some particular board you're looking at they don't happen to
 use the CD pin for card detect.  If this is what you mean, it
 doesn't help me.  exynos5420-peach-pit does use the CD pin for card
 detect.  You can look at the DTS file and confirm it.

 I didn't know how exynos5420-peach-pit's circuit is configured.
 But i guess that almost all exynos5 boards are configured with the similar 
 circuit.

 At Almost all Exynos5 board, CD-pin is used, but not included in Same power 
 domain.
 (CD-pin is external card-detect pin. - like XEINT_# pin)
 You mentioned CD# and DATA# lines is used the same power domain, right?
 In Circuit (not exynos5420-peach-pit), DATA# line and CMD/CLK(vqmmc) is same 
 power supply, and vdd is used other power supply.
 Not use the CD# pin, used the XEINT_# pin.
 So i think we don't need to consider the CD#.
 If exynos5420-peach-pit board is used the CD#-pin, then our discussion can 
 be changed.
 
 Maybe on your board you have CD connected to a gpx line.  ...but not
 mine.  The guys who designed our hardware followed the SMDK5420
 reference schematics which connect the SD card slot card detect to
 gpc2_2, which is the card detect pin.
 
 See arch/arm/boot/dts/exynos5420-smdk5420.dts, specifically noting
 the lack of a GPIO card detect and the inclusion of sd2_cd
 
 mmc@1222 {
   status = okay;
   card-detect-delay = 200;
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 2 3;
   samsung,dw-mshc-ddr-timing = 1 2;
   pinctrl-names = default;
   pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
   bus-width = 4;
   cap-sd-highspeed;
 };
 
 See arch/arm/boot/dts/exynos5420-peach-pit.dts too:
 
 mmc_2 {
   status = okay;
   num-slots = 1;
   cap-sd-highspeed;
   card-detect-delay = 200;
   clock-frequency = 4;
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 2 3;
   samsung,dw-mshc-ddr-timing = 1 2;
   pinctrl-names = default;
   pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
   bus-width = 4;
 };
 
 
 Here, see this ASCII art that shows how some lines are hooked up on
 peach-pit.  You might need to paste this into something with a
 fixed-width font.
 
  +
  |Exynos 5420
  |
  |
 P2.8V_LOUT4 -|- VDDQ_MMC2 (AK7)
 ||
 ||
   +-+- 10K res -+|- XMMC2CDN (AK6)
   | ||
   | ||
   | ||
   |   Ext CD |
   |  |
   +-- 10K res-+--+---|- XMMC2CMD (AK8)
  |
  |
Ext CMD
 
 You can see from the above that the external card detect signal (that
 goes to the connector) named Ext CD is pulled up to the same voltage
 as the external CMD signal (that also goes to the connector).  This is
 vqmmc.  If we turn off vqmmc then the 10K resistor will (I think) act
 as a pull down, or in the best case it will be floating.
 
 Said another way: we can't read card detect when vqmmc is off.

If that's the case, it makes sense. But i wonder why designed like that.
Anyway, then we need to consider that controls the vqmmc

Re: [PATCHv10 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-08-26 Thread Jaehoon Chung
Hi,

On 08/26/2014 07:19 PM, Pavel Machek wrote:
 Hi!
 
 Would you elaborate?

 If I have a device like a phone, I may want to put one slot inside
 phone for basic system, and offer second slot for user expansion
 (initially empty).

 if multiple slot is supported, then a mmcqd should be processing for 
 multiple slots.
 It's too inefficient, and affect the whole performance reduction.
 Sorry, Discard this comment. it means dwmci, not mmcqd.
 
 Well, that's a Linux problem, and for many applications, not even
 problem at all.
 
 Device tree should describe hardware, and hardware can do multiple
 slots per controller, so device tree should describe multiple slots
 per controller.
 
 Now, the configuration may be uncommon, but you are moving from good
 hardware description to bad hardware description.

Well, i don't think it's bad hardware description. And this policy is suggested 
by other mmc developers and maintainers.
At first time, I had also suggested same opinion with yours.
Refer to below..

https://patchwork.kernel.org/patch/4276481/

Best Regards,
Jaehoon Chung
 
   Pavel
 

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Re: [PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

2014-08-26 Thread Jaehoon Chung
Hi, Doug,

On 08/26/2014 12:25 AM, Doug Anderson wrote:
 Jaehoon,
 
 On Mon, Aug 25, 2014 at 1:50 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 On 08/25/2014 05:13 PM, Ulf Hansson wrote:
 On 22 August 2014 20:27, Sonny Rao sonny...@chromium.org wrote:
 On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson ulf.hans...@linaro.org 
 wrote:
 On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
 Exynos 5250 and 5420 based boards uses built-in CD# line for card
 detection.But unfortunately CD# line is on the same voltage rails
 as of I/O voltage rails. When we cut off vqmmc,the consequent card
 detection will break in these boards.

 I didn't know that use CD# line for card detect.
 And if CD# voltage rails and I/O voltage rail are same voltage, it doesn't 
 make sense.
 Which card is used with same voltages? (eMMC? SD? SDIO?)

 Well, I have checked Exynos5250 and 5420, but it looks like not same rails.
 
 I'm not sure I totally understood what you said.  In my manual I have
 a table titled Table 2-1 Exynos 5420 Pin List.  Look in this table
 for XMMC2CDN and XMMC2DATA_0.  Look to the right of the table and
 you'll see the power domain.  For both it shows VDDQ_MMC2.  If that
 doesn't mean that the two are in the same voltage domain then I don't
 know what does.  Can you point to any examples where they have
 different voltage domains?
I think you're mis-understanding for it.
Right, It's described at exynos5420, but it's not connected.
Exynos4 series are also described, but we used the broken card detection scheme 
and power used one of always-on powers.
Because Card-detection rail need to enable as always-on.

We don't need to consider this. I checked the circuit, this patch didn't need.

exynos5 also used the gpio-pin for card-detection. And we can use the slot-gpio 
API.

Best Regards,
Jaehoon Chung

 
 I agree that what exynos does is not sensible, but that's what it is.
 
 
 I am not sure I follow here.

 Is the card detect mechanism handled internally by the dw_mmc controller?

 Yes

 What card detect mechanism?
 
 The dw_mmc controller has a way to read the card detect, right?
 That's internal to the controller.  The alternative would be to use a
 generic GPIO for card detect.
 

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Re: [PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

2014-08-26 Thread Jaehoon Chung
Hi.

On 08/26/2014 12:20 AM, Doug Anderson wrote:
 Ulf,
 
 On Mon, Aug 25, 2014 at 1:13 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
 On 22 August 2014 20:27, Sonny Rao sonny...@chromium.org wrote:
 On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
 On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
 Exynos 5250 and 5420 based boards uses built-in CD# line for card
 detection.But unfortunately CD# line is on the same voltage rails
 as of I/O voltage rails. When we cut off vqmmc,the consequent card
 detection will break in these boards.

 I am not sure I follow here.

 Is the card detect mechanism handled internally by the dw_mmc controller?

 Yes

 Just out of curiosity.

 Do you know how the power to the actual dw_mmc controller is handled?
 I expect it to be SoC specific and I am guessing power domain
 regulators may be involved!?
 
 You can likely read the dw_mmc registers when vqmmc is off.  Is that
 what you're asking?  Certainly if vqmmc is not powered then the lines
 themselves will be useless, won't they?  The vqmmc supply goes to
 the VDDQ_MMC2 pin on 5420.  In my 5420 user manual, I see that
 clk, cmd, cd, datN, wp and biuvr pins are all in this same
 voltage (VDDQ_MMC2) domain.  Can you really read a pin without
 powering that part of the SoC?

It's not correct.
At TRM, described as same voltage domain. But CD-pin is used with always-on 
power.
In circuit, CD# pin is disconnected.

 
 
 I thought HW engineers long time ago realized that this should be done
 separately on a GPIO line to be able to save power while waiting for a
 card to be inserted. But that's not case then?

 At least in my limited experience, this seems to be common among SoC
 vendors who are using dw_mmc, as we've seen this elsewhere as well and
 after seeing it here we know that we need to ignore the CD pin that's
 routed to dw_mmc and use a separately powered GPIO on the board, but
 still there are probably many SoCs/boards which are doing it this way.


 These hosts (obviously) need to keep vqmmc (and thus vmmc) on all the
 time, even when the mmc core tells them to power off. However, one
 problem is that these cards won't properly handle mmc_power_cycle().
 That's needed to handle error cases when trying to switch voltages
 (see 0797e5f mmc:core: Fixup signal voltage switch).

 This patch adds a new MMC_POWER_OFF_HARD mode when it's doing a power
 cycle.  This mode differs from the normal MMC_POWER_OFF mode in that
 the mmc core will promise to power the slot back on before it expects
 the host to detect card insertion or removal.

 This patch is based off of one that Doug wrote (sent privately to
 Yuvaraj) which just modifies the MMC core, and should be split into
 two patches.
 One that modifies the mmc core and one that implements this in dw_mmc.

 I looked at the mmc core parts, it seems like the wrong approach.

 I think you shall be able use MMC_CAP_NEEDS_POLL, to handle this
 broken card detect mechanism. We even have a DT binding for that,
 broken-cd.
 
 I don't think this is possible, but let me explain why I think so and
 you can correct me.

Exynos series is using the external gpio-cd concept. So it need not to use 
MMC_CAP_NEEDS_POLL.
Can use the slot-gpio API. In my exynos5 board, it's working fine with the 
slot-gpio API.

Best Regards,
Jaehoon Chung

 
 The voltage domain of the card detect pin on the SoC is vqmmc,
 right?  That means that you won't be able to read the pin without
 turning on vqmmc.  Even if you could read the pin without turning on
 vqmmc, the pullup on this line is connected to vqmmc too.  ...so if
 vqmmc is off then there's no pulup and you can't use card detect.
 
 Are you suggesting that we should flip the voltage of vqmmc (and thus
 vmmc to prevent damaging the card) during polling?  That seems ugly.
 
 
 One other thing to mention: we didn't find any power savings by
 actually turning off vmmc and vqmmc when there was no card inserted.
 There's no current running through the lines when there is no card
 inserted and apparently everything is efficient enough that there was
 no problem.
 
 -Doug
 

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Re: [PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

2014-08-26 Thread Jaehoon Chung
Doug,

On 08/27/2014 01:14 PM, Doug Anderson wrote:
 Jaehoon,
 
 On Tue, Aug 26, 2014 at 8:48 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 Hi, Doug,

 On 08/26/2014 12:25 AM, Doug Anderson wrote:
 Jaehoon,

 On Mon, Aug 25, 2014 at 1:50 AM, Jaehoon Chung jh80.ch...@samsung.com 
 wrote:
 On 08/25/2014 05:13 PM, Ulf Hansson wrote:
 On 22 August 2014 20:27, Sonny Rao sonny...@chromium.org wrote:
 On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson ulf.hans...@linaro.org 
 wrote:
 On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
 Exynos 5250 and 5420 based boards uses built-in CD# line for card
 detection.But unfortunately CD# line is on the same voltage rails
 as of I/O voltage rails. When we cut off vqmmc,the consequent card
 detection will break in these boards.

 I didn't know that use CD# line for card detect.
 And if CD# voltage rails and I/O voltage rail are same voltage, it doesn't 
 make sense.
 Which card is used with same voltages? (eMMC? SD? SDIO?)

 Well, I have checked Exynos5250 and 5420, but it looks like not same rails.

 I'm not sure I totally understood what you said.  In my manual I have
 a table titled Table 2-1 Exynos 5420 Pin List.  Look in this table
 for XMMC2CDN and XMMC2DATA_0.  Look to the right of the table and
 you'll see the power domain.  For both it shows VDDQ_MMC2.  If that
 doesn't mean that the two are in the same voltage domain then I don't
 know what does.  Can you point to any examples where they have
 different voltage domains?
 I think you're mis-understanding for it.
 Right, It's described at exynos5420, but it's not connected.
 
 It's not connected.  What do you mean?  If I were to guess I'd say
 that on some particular board you're looking at they don't happen to
 use the CD pin for card detect.  If this is what you mean, it
 doesn't help me.  exynos5420-peach-pit does use the CD pin for card
 detect.  You can look at the DTS file and confirm it.

I didn't know how exynos5420-peach-pit's circuit is configured.
But i guess that almost all exynos5 boards are configured with the similar 
circuit.

At Almost all Exynos5 board, CD-pin is used, but not included in Same power 
domain.
(CD-pin is external card-detect pin. - like XEINT_# pin)
You mentioned CD# and DATA# lines is used the same power domain, right?
In Circuit (not exynos5420-peach-pit), DATA# line and CMD/CLK(vqmmc) is same 
power supply, and vdd is used other power supply.
Not use the CD# pin, used the XEINT_# pin.
So i think we don't need to consider the CD#.
If exynos5420-peach-pit board is used the CD#-pin, then our discussion can be 
changed.
Your commit message looks like all exynos5250/5420 board are used CD# line.

 
 ...or are you saying that the CD pin somehow changes voltage domains
 when configured as a GPIO?  I find that very hard to believe.  What
 voltage domain does it go to?  If it goes to a 1.8V voltage domain
 then that would be bad when vqmmc was 3.3V.  If it goes to a 3.3V
 voltage domain then that would be bad when vqmmc was 1.8V.  Remember
 that externally we've got a pull up to vqmmc.

It is used with XEINT_# pin instead of CD# pin.
As i mentioned above, if exynos5420-peach-pit is used CD# line and not used 
XEINT_# pin,
my point is meaningless. :)

Is exynos5420-peach-pit board used with CD#pin, not XEINT_# pin?

Best Regards,
Jaehoon Chung
 
 Even if somehow magically we can read the card detect pin with vqmmc
 off, we have an external pullup on this line that goes directly to the
 vqmmc power rail.  If the vqmmc power rail is off then this external
 pull up would not work and would actually act as an external pull down
 if you could somehow configure the internal line to be a pullup.
 
 
 Exynos4 series are also described, but we used the broken card detection 
 scheme and power used one of always-on powers.
 Because Card-detection rail need to enable as always-on.

 We don't need to consider this. I checked the circuit, this patch didn't 
 need.

 exynos5 also used the gpio-pin for card-detection. And we can use the 
 slot-gpio API.
 
 When you say exynos5, what do you mean here?  Do you mean the smdk
 for 5250, or something else?
 

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Re: [PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

2014-08-25 Thread Jaehoon Chung
On 08/25/2014 05:13 PM, Ulf Hansson wrote:
 On 22 August 2014 20:27, Sonny Rao sonny...@chromium.org wrote:
 On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
 On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
 Exynos 5250 and 5420 based boards uses built-in CD# line for card
 detection.But unfortunately CD# line is on the same voltage rails
 as of I/O voltage rails. When we cut off vqmmc,the consequent card
 detection will break in these boards.

I didn't know that use CD# line for card detect.
And if CD# voltage rails and I/O voltage rail are same voltage, it doesn't make 
sense.
Which card is used with same voltages? (eMMC? SD? SDIO?)

Well, I have checked Exynos5250 and 5420, but it looks like not same rails.


 I am not sure I follow here.

 Is the card detect mechanism handled internally by the dw_mmc controller?

 Yes

What card detect mechanism?

 
 Just out of curiosity.
 
 Do you know how the power to the actual dw_mmc controller is handled?
 I expect it to be SoC specific and I am guessing power domain
 regulators may be involved!?
 


 I thought HW engineers long time ago realized that this should be done
 separately on a GPIO line to be able to save power while waiting for a
 card to be inserted. But that's not case then?

 At least in my limited experience, this seems to be common among SoC
 vendors who are using dw_mmc, as we've seen this elsewhere as well and
 after seeing it here we know that we need to ignore the CD pin that's
 routed to dw_mmc and use a separately powered GPIO on the board, but
 still there are probably many SoCs/boards which are doing it this way.


 These hosts (obviously) need to keep vqmmc (and thus vmmc) on all the
 time, even when the mmc core tells them to power off. However, one
 problem is that these cards won't properly handle mmc_power_cycle().
 That's needed to handle error cases when trying to switch voltages
 (see 0797e5f mmc:core: Fixup signal voltage switch).

 This patch adds a new MMC_POWER_OFF_HARD mode when it's doing a power
 cycle.  This mode differs from the normal MMC_POWER_OFF mode in that
 the mmc core will promise to power the slot back on before it expects
 the host to detect card insertion or removal.

 This patch is based off of one that Doug wrote (sent privately to
 Yuvaraj) which just modifies the MMC core, and should be split into
 two patches.
 One that modifies the mmc core and one that implements this in dw_mmc.
 
 I looked at the mmc core parts, it seems like the wrong approach.
 
 I think you shall be able use MMC_CAP_NEEDS_POLL, to handle this
 broken card detect mechanism. We even have a DT binding for that,
 broken-cd.

I agreed with Ulf's opinion.

Best Regards,
Jaehoon Chung

 
 Kind regards
 Uffe
 

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Re: [PATCHv10 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-08-25 Thread Jaehoon Chung
On 08/25/2014 08:21 PM, Pavel Machek wrote:
 On Thu 2014-08-07 16:37:57, Jaehoon Chung wrote:
 Since used the mmc_of_parse(), didn't parse the sub-node.
 So we can remove the sub-node, because almost SoC used the only one card per 
 a host.
 And supports-highspeed can be replaced with cap-mmc/sd-highspeed
 property.
 
 Would it be better to fix parsing of the device tree, and not to
 change all the device trees?
 
 Someone will want to do two slots sooner or later...
 

First, I had considered that controller can be supported the multiple slot.
But MMC maintainers and other people suggested that consider the only one card 
per a host.
Two slots or more don't have any benefit, (power or performance, etc).

Best Regards,
Jaehoon Chung

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Re: [PATCHv10 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-08-25 Thread Jaehoon Chung
On 08/25/2014 08:37 PM, Pavel Machek wrote:
 On Mon 2014-08-25 20:28:21, Jaehoon Chung wrote:
 On 08/25/2014 08:21 PM, Pavel Machek wrote:
 On Thu 2014-08-07 16:37:57, Jaehoon Chung wrote:
 Since used the mmc_of_parse(), didn't parse the sub-node.
 So we can remove the sub-node, because almost SoC used the only one card 
 per a host.
 And supports-highspeed can be replaced with cap-mmc/sd-highspeed
 property.

 Would it be better to fix parsing of the device tree, and not to
 change all the device trees?

 Someone will want to do two slots sooner or later...


 First, I had considered that controller can be supported the multiple slot.
 But MMC maintainers and other people suggested that consider the only one 
 card per a host.
 Two slots or more don't have any benefit, (power or performance, etc).
 
 Would you elaborate?
 
 If I have a device like a phone, I may want to put one slot inside
 phone for basic system, and offer second slot for user expansion
 (initially empty).

if multiple slot is supported, then a mmcqd should be processing for multiple 
slots.
It's too inefficient, and affect the whole performance reduction.

If want to offer the second slot for user expansion, add the host for expansion 
slot.
Almost All SoC didn't use the multiple slot per a host controller for 
eMMC/SD/SDIO.

If Some device(Phone) supports the SD-card and eMMC, then there are two Host IP.
One Host IP is used for eMMC, other is used for SD-card.

this is H/W design issue.

a) You means the below,

One Host IP  eMMC
|
 SD
|
 SDIO

b) We means the below
One Host IP  eMMC
One Host IP  SD
One Host IP  SDIO

In now, I knew every SoC have used like b) type. I didn't see a) type 
(especially, dwmmc's case).

If i missed something, let me know, plz.

Best Regards,
Jaehoon Chung

 
 Or I may want to have internal slot with a card to boot from and have
 external slot (initially empty) for system update for embedded system.
 
 I see quite an obvious benefit there.
   Pavel
 

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Re: [PATCHv10 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-08-25 Thread Jaehoon Chung
On 08/25/2014 09:09 PM, Jaehoon Chung wrote:
 On 08/25/2014 08:37 PM, Pavel Machek wrote:
 On Mon 2014-08-25 20:28:21, Jaehoon Chung wrote:
 On 08/25/2014 08:21 PM, Pavel Machek wrote:
 On Thu 2014-08-07 16:37:57, Jaehoon Chung wrote:
 Since used the mmc_of_parse(), didn't parse the sub-node.
 So we can remove the sub-node, because almost SoC used the only one card 
 per a host.
 And supports-highspeed can be replaced with cap-mmc/sd-highspeed
 property.

 Would it be better to fix parsing of the device tree, and not to
 change all the device trees?

 Someone will want to do two slots sooner or later...


 First, I had considered that controller can be supported the multiple slot.
 But MMC maintainers and other people suggested that consider the only one 
 card per a host.
 Two slots or more don't have any benefit, (power or performance, etc).

 Would you elaborate?

 If I have a device like a phone, I may want to put one slot inside
 phone for basic system, and offer second slot for user expansion
 (initially empty).
 
 if multiple slot is supported, then a mmcqd should be processing for multiple 
 slots.
 It's too inefficient, and affect the whole performance reduction.
Sorry, Discard this comment. it means dwmci, not mmcqd.

 
 If want to offer the second slot for user expansion, add the host for 
 expansion slot.
 Almost All SoC didn't use the multiple slot per a host controller for 
 eMMC/SD/SDIO.
 
 If Some device(Phone) supports the SD-card and eMMC, then there are two Host 
 IP.
 One Host IP is used for eMMC, other is used for SD-card.
 
 this is H/W design issue.
 
 a) You means the below,
 
 One Host IP  eMMC
   |
    SD
   |
    SDIO
 
 b) We means the below
 One Host IP  eMMC
 One Host IP  SD
 One Host IP  SDIO
 
 In now, I knew every SoC have used like b) type. I didn't see a) type 
 (especially, dwmmc's case).
 
 If i missed something, let me know, plz.
 
 Best Regards,
 Jaehoon Chung
 

 Or I may want to have internal slot with a card to boot from and have
 external slot (initially empty) for system update for embedded system.

 I see quite an obvious benefit there.
  Pavel

 

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Re: [PATCH V2 1/3] mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators

2014-08-25 Thread Jaehoon Chung
On 08/22/2014 10:47 PM, Yuvaraj Kumar C D wrote:
 This patch makes use of mmc_regulator_get_supply() to handle
 the vmmc and vqmmc regulators.Also it moves the code handling
 the these regulators to dw_mci_set_ios().It turned on the vmmc
 and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
 during MMC_POWER_OFF.
 
 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
 ---
 changes from v1:
   1.Used mmc_regulator_set_ocr() instead of regulator_enable() for vmmc.
   2.Turned on vmmc and vqmmc during MMC_POWER_UP.
   3. Removed the flags DW_MMC_CARD_POWERED and DW_MMC_IO_POWERED which
  added during the initial version of this patch.
   4. Added error message, if it failed to turn on regulator's.
 
  drivers/mmc/host/dw_mmc.c  |   72 
 +---
  include/linux/mmc/dw_mmc.h |2 +-
  2 files changed, 36 insertions(+), 38 deletions(-)
 
 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 7f227e9..aadb0d6 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -936,6 +936,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
 mmc_ios *ios)
   struct dw_mci_slot *slot = mmc_priv(mmc);
   const struct dw_mci_drv_data *drv_data = slot-host-drv_data;
   u32 regs;
 + int ret;
  
   switch (ios-bus_width) {
   case MMC_BUS_WIDTH_4:
 @@ -974,12 +975,38 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
 mmc_ios *ios)
  
   switch (ios-power_mode) {
   case MMC_POWER_UP:
 + if (!IS_ERR(mmc-supply.vmmc)) {
 + ret = mmc_regulator_set_ocr(mmc, mmc-supply.vmmc,
 + ios-vdd);
 + if (ret) {
 + dev_err(slot-host-dev,
 + failed to enable vmmc regulator\n);
 + /*return, if failed turn on vmmc*/
 + return;
 + }
 + }
 + if (!IS_ERR(mmc-supply.vqmmc)  !slot-host-vqmmc_enabled) {

Can't use the regulator_is_enabled() instead of slot-host-vqmmc_enabled?

Best Regards,
Jaehoon Chung
 + ret = regulator_enable(mmc-supply.vqmmc);
 + if (ret  0)
 + dev_err(slot-host-dev,
 + failed to enable vqmmc regulator\n);
 + else
 + slot-host-vqmmc_enabled = true;
 + }
   set_bit(DW_MMC_CARD_NEED_INIT, slot-flags);
   regs = mci_readl(slot-host, PWREN);
   regs |= (1  slot-id);
   mci_writel(slot-host, PWREN, regs);
   break;
   case MMC_POWER_OFF:
 + if (!IS_ERR(mmc-supply.vmmc))
 + mmc_regulator_set_ocr(mmc, mmc-supply.vmmc, 0);
 +
 + if (!IS_ERR(mmc-supply.vqmmc)  slot-host-vqmmc_enabled) {
 + regulator_disable(mmc-supply.vqmmc);
 + slot-host-vqmmc_enabled = false;
 + }
 +
   regs = mci_readl(slot-host, PWREN);
   regs = ~(1  slot-id);
   mci_writel(slot-host, PWREN, regs);
 @@ -2110,7 +2137,13 @@ static int dw_mci_init_slot(struct dw_mci *host, 
 unsigned int id)
   mmc-f_max = freq[1];
   }
  
 - mmc-ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 + /*if there are external regulators, get them*/
 + ret = mmc_regulator_get_supply(mmc);
 + if (ret == -EPROBE_DEFER)
 + goto err_setup_bus;
 +
 + if (!mmc-ocr_avail)
 + mmc-ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  
   if (host-pdata-caps)
   mmc-caps = host-pdata-caps;
 @@ -2176,7 +2209,7 @@ static int dw_mci_init_slot(struct dw_mci *host, 
 unsigned int id)
  
  err_setup_bus:
   mmc_free_host(mmc);
 - return -EINVAL;
 + return ret;
  }
  
  static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
 @@ -2469,24 +2502,6 @@ int dw_mci_probe(struct dw_mci *host)
   }
   }
  
 - host-vmmc = devm_regulator_get_optional(host-dev, vmmc);
 - if (IS_ERR(host-vmmc)) {
 - ret = PTR_ERR(host-vmmc);
 - if (ret == -EPROBE_DEFER)
 - goto err_clk_ciu;
 -
 - dev_info(host-dev, no vmmc regulator found: %d\n, ret);
 - host-vmmc = NULL;
 - } else {
 - ret = regulator_enable(host-vmmc);
 - if (ret) {
 - if (ret != -EPROBE_DEFER)
 - dev_err(host-dev,
 - regulator_enable fail: %d\n, ret);
 - goto err_clk_ciu;
 - }
 - }
 -
   host-quirks = host-pdata-quirks;
  
   spin_lock_init(host-lock);
 @@ -2630,8 +2645,6 @@ err_workqueue:
  err_dmaunmap:
   if (host-use_dma  host-dma_ops-exit)
   host

Re: [PATCHv10 3/5] ARM: dts: exynos: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-08-18 Thread Jaehoon Chung
Hi, Kukjin.

Socfpga and Rockchip were queued into each SoC tree.
I want to know whether this patch is queued or not into Samsung-Soc tree.
Do you have any other plan for this patch?

Best Regards,
Jaehoon Chung

On 08/07/2014 04:38 PM, Jaehoon Chung wrote:
 dw-mmc controller can support multiple slots.
 But, there are no use-cases anywhere. So we don't need to support the
 slot-node for dw-mmc controller.
 And supports-highspeed property in dw-mmc is deprecated.
 supports-highspeed property can be replaced with cap-sd/mmc-highspeed.
 
 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 Reviewed-by: Tushar Behera trbli...@gmail.com
 Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
 Tested-by: Sachin Kamat sachin.ka...@samsung.com
 ---
  arch/arm/boot/dts/exynos4412-odroid-common.dtsi |8 ++--
  arch/arm/boot/dts/exynos4412-origen.dts |8 ++--
  arch/arm/boot/dts/exynos4412-trats2.dts |8 ++--
  arch/arm/boot/dts/exynos5250-arndale.dts|   18 +---
  arch/arm/boot/dts/exynos5250-cros-common.dtsi   |   25 
 +++
  arch/arm/boot/dts/exynos5250-smdk5250.dts   |   18 +---
  arch/arm/boot/dts/exynos5250-snow.dts   |6 ++
  arch/arm/boot/dts/exynos5260-xyref5260.dts  |   18 +---
  arch/arm/boot/dts/exynos5410-smdk5410.dts   |   18 +---
  arch/arm/boot/dts/exynos5420-arndale-octa.dts   |   16 ---
  arch/arm/boot/dts/exynos5420-peach-pit.dts  |   16 ---
  arch/arm/boot/dts/exynos5420-smdk5420.dts   |   16 ---
  arch/arm/boot/dts/exynos5800-peach-pi.dts   |   16 ---
  13 files changed, 51 insertions(+), 140 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
 b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 index 6d6d23c..f5c0f81 100644
 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 @@ -54,17 +54,13 @@
   status = okay;
  
   num-slots = 1;
 - supports-highspeed;
   broken-cd;
   card-detect-delay = 200;
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 2 3;
   samsung,dw-mshc-ddr-timing = 1 2;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 8;
 - };
 + bus-width = 8;
 + cap-mmc-highspeed;
   };
  
   watchdog@1006 {
 diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
 b/arch/arm/boot/dts/exynos4412-origen.dts
 index e925c9f..de15114 100644
 --- a/arch/arm/boot/dts/exynos4412-origen.dts
 +++ b/arch/arm/boot/dts/exynos4412-origen.dts
 @@ -137,17 +137,13 @@
   status = okay;
  
   num-slots = 1;
 - supports-highspeed;
   broken-cd;
   card-detect-delay = 200;
   samsung,dw-mshc-ciu-div = 3;
   samsung,dw-mshc-sdr-timing = 2 3;
   samsung,dw-mshc-ddr-timing = 1 2;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 8;
 - };
 + bus-width = 8;
 + cap-mmc-highspeed;
   };
  
   codec@1340 {
 diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
 b/arch/arm/boot/dts/exynos4412-trats2.dts
 index 11967f4..5e066cd 100644
 --- a/arch/arm/boot/dts/exynos4412-trats2.dts
 +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
 @@ -520,7 +520,6 @@
  
   mmc@1255 {
   num-slots = 1;
 - supports-highspeed;
   broken-cd;
   non-removable;
   card-detect-delay = 200;
 @@ -532,11 +531,8 @@
   pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
   pinctrl-names = default;
   status = okay;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 8;
 - };
 + bus-width = 8;
 + cap-mmc-highspeed;
   };
  
   serial@1380 {
 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
 b/arch/arm/boot/dts/exynos5250-arndale.dts
 index d0de1f5..42a3590 100644
 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
 +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
 @@ -401,7 +401,6 @@
   mmc_0: mmc@1220 {
   status = okay;
   num-slots = 1;
 - supports-highspeed;
   broken-cd;
   card-detect-delay = 200;
   samsung,dw-mshc-ciu-div = 3;
 @@ -410,17 +409,13 @@
   vmmc-supply = mmc_reg;
   pinctrl-names = default;
   pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
 -
 - slot@0 {
 - reg = 0;
 - bus-width = 8;
 - };
 + bus-width = 8;
 + cap-mmc-highspeed;
   };
  
   mmc_2: mmc@1222 {
   status

Re: [PATCHv10 3/5] ARM: dts: exynos: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-08-18 Thread Jaehoon Chung
Hi, Kukjin

On 08/19/2014 01:54 AM, Kukjin Kim wrote:
 On 08/18/14 09:10, Andreas Färber wrote:
 Hi Jaehoon,

 Am 18.08.2014 14:23, schrieb Jaehoon Chung:
 Socfpga and Rockchip were queued into each SoC tree.
 I want to know whether this patch is queued or not into Samsung-Soc tree.
 Do you have any other plan for this patch?

 It isn't applied in his tree:

 http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/

 In fact Kukjin has not applied any patches for 3 weeks now, which likely
 means he's on vacation. I am hoping he will review this and the other
 pending conflicting patches to decide on a merge order and fix any
 trivial conflicts himself. ;)

 Oh, I thought it has been queued in previous merge window with my ack.
 
 OK, I've applied this in my tree for 3.18.

Thanks!

Best Regards,
Jaehoon Chung
 
 Thanks,
 Kukjin
 

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Re: [PATCH v2] mmc: dw_mmc: Make sure we don't get stuck when we get an error

2014-08-13 Thread Jaehoon Chung
On 08/13/2014 10:38 PM, Doug Anderson wrote:
 Hi,
 
 On Wed, May 21, 2014 at 2:08 AM, Seungwon Jeon tgih@samsung.com wrote:
 On Wed, May 21, 2014, Doug Anderson wrote:
 If we happened to get a data error at just the wrong time the dw_mmc
 driver could get into a state where it would never complete its
 request.  That would leave the caller just hanging there.

 We fix this two ways and both of the two fixes on their own appear to
 fix the problems we've seen:

 1. Fix a race in the tasklet where the interrupt setting the data
error happens _just after_ we check for it, then we get a
EVENT_XFER_COMPLETE.  We fix this by repeating a bit of code.
 2. Fix it so that if we detect that we've got an error in the data
busy state and we're not going to do anything else we end the
request and unblock anyone waiting.

 Signed-off-by: Doug Anderson diand...@chromium.org
 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@gmail.com

 It will be applied after mmc: dw_mmc: change to use recommended reset 
 procedure

 Acked-by: Seungwon Jeon tgih@samsung.com

 Thanks,
 Seungwon Jeon
 
 I saw that Ulf applied mmc: dw_mmc: change to use recommended reset
 procedure.  Could we apply this one now, too?  Do you want me to
 repost?
It's good that it will be merged with it.

Best Regards,
Jaehoon Chung

 
 -Doug
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[PATCHv10 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-08-07 Thread Jaehoon Chung
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a 
host.
And supports-highspeed can be replaced with cap-mmc/sd-highspeed property.

Changelog V10:
- Rebased for next.
- Remove conflict
Changelog V9:
- Fix typos.
- Relocated the warning message.
- Change patch's sequence.
Changelog V8:
- Add the warning message to notice that slot-node was removed.
(As Doug's suggestion)
Changelog V7:
- Fixed typo and modified the commit message.
Changelog V6:
- Fixed Wrong bit control for host's quirks and rename.
- Add Acked-by for each SoC maintainers.
Changelog V5:
- Rebased on v3.16-rc4.
- Add Acked-by.
Changelog V4:
- Fix the checkpatch error.
Changelog V3:
- Fix the wrong bus-width value.
- Use the slot-host-quirks instead of brq-quirks.
- Add tested-by and reviewd-by.
Changelog V2:
- Add the mmc: dw_mmc: replace disable-wp from slot's quirks to 
host's quirk

Jaehoon Chung (5):
  mmc: dw_mmc: Slot quirk disable-wp is deprecated.
  mmc: dw_mmc: modify the dt-binding for removing slot-node and
supports-highspeed
  ARM: dts: exynos: unuse the slot-node and deprecate the
supports-highspeed for dw-mmc
  ARM: dts: socfpga: unuse the slot-node and deprecate the
supports-highspeed for dw-mmc
  ARM: dts: rockchip: unuse the slot-node and deprecate the
supports-highspeed for dw-mmc

 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 -
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 --
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 --
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi|8 ++-
 arch/arm/boot/dts/exynos4412-origen.dts|8 ++-
 arch/arm/boot/dts/exynos4412-trats2.dts|8 ++-
 arch/arm/boot/dts/exynos5250-arndale.dts   |   18 --
 arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   25 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   18 --
 arch/arm/boot/dts/exynos5250-snow.dts  |6 ++---
 arch/arm/boot/dts/exynos5260-xyref5260.dts |   18 --
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |   18 --
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |   16 -
 arch/arm/boot/dts/exynos5420-peach-pit.dts |   16 -
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   16 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |   16 -
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   15 
 arch/arm/boot/dts/rk3188-radxarock.dts |7 ++
 arch/arm/boot/dts/socfpga_arria5.dtsi  |9 +++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi|9 +++
 arch/arm/boot/dts/socfpga_vt.dts   |9 +++
 drivers/mmc/host/dw_mmc.c  |   11 +++--
 include/linux/mmc/dw_mmc.h |2 ++
 23 files changed, 92 insertions(+), 202 deletions(-)

-- 
1.7.9.5

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[PATCHv10 1/5] mmc: dw_mmc: Slot quirk disable-wp is deprecated.

2014-08-07 Thread Jaehoon Chung
Slot quirks disable-wp is deprecated.
Instead, use the host quirk disable-wp.
(Because the slot-node is removed in dt-file.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
---
 drivers/mmc/host/dw_mmc.c  |   11 +--
 include/linux/mmc/dw_mmc.h |2 ++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..47b52cc 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -997,7 +997,8 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
int gpio_ro = mmc_gpio_get_ro(mmc);
 
/* Use platform get_ro function, else try on board write protect */
-   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
+   if ((slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
+   (slot-host-quirks  DW_MCI_QUIRK_NO_WRITE_PROTECT))
read_only = 0;
else if (!IS_ERR_VALUE(gpio_ro))
read_only = gpio_ro;
@@ -2021,8 +2022,11 @@ static int dw_mci_of_get_slot_quirks(struct device *dev, 
u8 slot)
 
/* get quirks */
for (idx = 0; idx  ARRAY_SIZE(of_slot_quirks); idx++)
-   if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
+   if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
+   dev_warn(dev, Slot quirk %s is deprecated\n,
+   of_slot_quirks[idx].quirk);
quirks |= of_slot_quirks[idx].id;
+   }
 
return quirks;
 }
@@ -2238,6 +2242,9 @@ static struct dw_mci_of_quirks {
{
.quirk  = broken-cd,
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   }, {
+   .quirk  = disable-wp,
+   .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
},
 };
 
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index babaea9..29ce014 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -213,6 +213,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
+/* No write protect */
+#define DW_MCI_QUIRK_NO_WRITE_PROTECT  BIT(4)
 
 /* Slot level quirks */
 /* This slot has no write protect */
-- 
1.7.9.5

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[PATCHv10 2/5] mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed

2014-08-07 Thread Jaehoon Chung
Almost all SoCs use one slot per host controller.
(Even if controller can support the multiple slot, Recommend to use one slot 
per host controller.)
Don't use the slot-node and deprecate the supports-highspeed property.
Instead, use the cap-mmc/sd-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 +
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 +---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 +---
 3 files changed, 15 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 532b1d4..6cd3525 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -46,13 +46,14 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
+Required properties for a slot (Deprecated - Recommend to use one slot per 
host):
 
 * gpios: specifies a list of gpios used for command, clock and data bus. The
   first gpio is the command line and the second gpio is the clock line. The
   rest of the gpios (depending on the bus-width property) are the data lines in
   no particular order. The format of the gpio specifier depends on the gpio
   controller.
+(Deprecated - Refer to 
Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
 
 Example:
 
@@ -69,21 +70,13 @@ Example:
 
dwmmc0@1220 {
num-slots = 1;
-   supports-highspeed;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
-   gpc1 0 2 3 3, gpc1 1 2 3 3,
-   gpc1 2 2 3 3, gpc1 3 2 3 3,
-   gpc0 3 2 3 3, gpc0 4 2 3 3,
-   gpc0 5 2 3 3, gpc0 6 2 3 3;
-   };
+   bus-width = 8;
};
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index e5bc49f..3b35449 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -34,13 +34,11 @@ Example:
num-slots = 1;
vmmc-supply = ldo12;
fifo-depth = 0x100;
-   supports-highspeed;
pinctrl-names = default;
pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   cd-gpios = gpio10 3 0;
-   };
+   bus-width = 4;
+   disable-wp;
+   cd-gpios = gpio10 3 0;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 2d4a725..346c609 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -67,7 +67,8 @@ Optional properties:
 * card-detect-delay: Delay in milli-seconds before detecting card after card
   insert event. The default value is 0.
 
-* supports-highspeed: Enables support for high speed cards (up to 50MHz)
+* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 
50MHz)
+  (use cap-mmc-highspeed or cap-sd-highspeed 
instead)
 
 * broken-cd: as documented in mmc core bindings.
 
@@ -98,14 +99,11 @@ board specific portions as listed below.
clock-frequency = 4;
clock-freq-min-max = 40 2;
num-slots = 1;
-   supports-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
vmmc-supply = buck8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
+   cap-sd-highspeed

[PATCHv10 4/5] ARM: dts: socfpga: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-08-07 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced with cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Dinh Nguyen dingu...@altera.com
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   |9 +++--
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |9 +++--
 arch/arm/boot/dts/socfpga_vt.dts|9 +++--
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi 
b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2c..468fc4c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,13 +29,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi 
b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf51182..1ee03c4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -30,13 +30,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b4..f9345e0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff70 {
-- 
1.7.9.5

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[PATCHv10 5/5] ARM: dts: rockchip: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-08-07 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced with cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Reviewed-by: Heiko Stuebner he...@sntech.de
Acked-by: Seungwon Jeon tgih@samsung.com
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   15 ---
 arch/arm/boot/dts/rk3188-radxarock.dts |7 ++-
 2 files changed, 6 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts 
b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 042f821d..665dd56 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -150,12 +150,8 @@
num-slots = 1;
status = okay;
vmmc-supply = vcc_sd0;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
 };
 
 mmc1 { /* wifi */
@@ -166,11 +162,8 @@
pinctrl-names = default;
pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
 
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
 };
 
 uart0 {
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts 
b/arch/arm/boot/dts/rk3188-radxarock.dts
index 171b610..ef72faf 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -181,11 +181,8 @@
status = okay;
vmmc-supply = vcc_sd0;
 
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
 };
 
 pinctrl {
-- 
1.7.9.5

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[PATCHv10 3/5] ARM: dts: exynos: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-08-07 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced with cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi |8 ++--
 arch/arm/boot/dts/exynos4412-origen.dts |8 ++--
 arch/arm/boot/dts/exynos4412-trats2.dts |8 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts|   18 +---
 arch/arm/boot/dts/exynos5250-cros-common.dtsi   |   25 +++
 arch/arm/boot/dts/exynos5250-smdk5250.dts   |   18 +---
 arch/arm/boot/dts/exynos5250-snow.dts   |6 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts  |   18 +---
 arch/arm/boot/dts/exynos5410-smdk5410.dts   |   18 +---
 arch/arm/boot/dts/exynos5420-arndale-octa.dts   |   16 ---
 arch/arm/boot/dts/exynos5420-peach-pit.dts  |   16 ---
 arch/arm/boot/dts/exynos5420-smdk5420.dts   |   16 ---
 arch/arm/boot/dts/exynos5800-peach-pi.dts   |   16 ---
 13 files changed, 51 insertions(+), 140 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 6d6d23c..f5c0f81 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -54,17 +54,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
watchdog@1006 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
codec@1340 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4..5e066cd 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
mmc@1255 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = 200;
@@ -532,11 +531,8 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
serial@1380 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..42a3590 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@1220 {
status = okay;
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
@@ -410,17 +409,13 @@
vmmc-supply = mmc_reg;
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
mmc_2: mmc@1222 {
status = okay;
num-slots = 1;
-   supports-highspeed;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -428,12 +423,9 @@
vmmc-supply

Re: [PATCH] mmc: dw_mmc: change to use recommended reset procedure

2014-08-07 Thread Jaehoon Chung
Hi, 

I remembered that this patch was pushed at Ulf's tree.

Since dw_mci_idmac_reset() is located into #if CONFIG_MMC_DW_IDMAC,
it occurred the compiler error.
And it seems that didn't need to use IS_ENABLED() at there.

Acked-by: Jaehoon Chung jh80.ch...@samsung.com

Best Regards,
Jaehoon Chung

On 08/05/2014 10:19 AM, Sonny Rao wrote:
 This patch changes the fifo reset code to follow the reset procedure
 outlined in the documentation of Synopsys Mobile storage host databook.
 
 Signed-off-by: Sonny Rao sonny...@chromium.org
 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
 Acked-by: Seungwon Jeon tgih@samsung.com
 Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
 [sonnyrao: fix compile for !CONFIG_MMC_DW_IDMAC case]
 ---
  drivers/mmc/host/dw_mmc.c | 87 
 ++-
  drivers/mmc/host/dw_mmc.h |  5 +++
  2 files changed, 69 insertions(+), 23 deletions(-)
 
 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 1ac227c..39cf54f 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -111,8 +111,7 @@ static const u8 tuning_blk_pattern_8bit[] = {
   0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  };
  
 -static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 -static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 +static bool dw_mci_reset(struct dw_mci *host);
  
  #if defined(CONFIG_DEBUG_FS)
  static int dw_mci_req_show(struct seq_file *s, void *v)
 @@ -1235,7 +1234,7 @@ static int dw_mci_data_complete(struct dw_mci *host, 
 struct mmc_data *data)
* After an error, there may be data lingering
* in the FIFO
*/
 - dw_mci_fifo_reset(host);
 + dw_mci_reset(host);
   } else {
   data-bytes_xfered = data-blocks * data-blksz;
   data-error = 0;
 @@ -1352,7 +1351,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
  
   /* CMD error in data command */
   if (mrq-cmd-error  mrq-data)
 - dw_mci_fifo_reset(host);
 + dw_mci_reset(host);
  
   host-cmd = NULL;
   host-data = NULL;
 @@ -1963,14 +1962,8 @@ static void dw_mci_work_routine_card(struct 
 work_struct *work)
   }
  
   /* Power down slot */
 - if (present == 0) {
 - /* Clear down the FIFO */
 - dw_mci_fifo_reset(host);
 -#ifdef CONFIG_MMC_DW_IDMAC
 - dw_mci_idmac_reset(host);
 -#endif
 -
 - }
 + if (present == 0)
 + dw_mci_reset(host);
  
   spin_unlock_bh(host-lock);
  
 @@ -2208,8 +2201,11 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 
 reset)
   return false;
  }
  
 -static inline bool dw_mci_fifo_reset(struct dw_mci *host)
 +static bool dw_mci_reset(struct dw_mci *host)
  {
 + u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
 + bool ret = false;
 +
   /*
* Reseting generates a block interrupt, hence setting
* the scatter-gather pointer to NULL.
 @@ -2219,15 +2215,60 @@ static inline bool dw_mci_fifo_reset(struct dw_mci 
 *host)
   host-sg = NULL;
   }
  
 - return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
 -}
 + if (host-use_dma)
 + flags |= SDMMC_CTRL_DMA_RESET;
  
 -static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
 -{
 - return dw_mci_ctrl_reset(host,
 -  SDMMC_CTRL_FIFO_RESET |
 -  SDMMC_CTRL_RESET |
 -  SDMMC_CTRL_DMA_RESET);
 + if (dw_mci_ctrl_reset(host, flags)) {
 + /*
 +  * In all cases we clear the RAWINTS register to clear any
 +  * interrupts.
 +  */
 + mci_writel(host, RINTSTS, 0x);
 +
 + /* if using dma we wait for dma_req to clear */
 + if (host-use_dma) {
 + unsigned long timeout = jiffies + msecs_to_jiffies(500);
 + u32 status;
 + do {
 + status = mci_readl(host, STATUS);
 + if (!(status  SDMMC_STATUS_DMA_REQ))
 + break;
 + cpu_relax();
 + } while (time_before(jiffies, timeout));
 +
 + if (status  SDMMC_STATUS_DMA_REQ) {
 + dev_err(host-dev,
 + %s: Timeout waiting for dma_req to 
 + clear during reset\n, __func__);
 + goto ciu_out;
 + }
 +
 + /* when using DMA next we reset the fifo again

Re: [PATCHv9 1/5] mmc: dw_mmc: Slot quirk disable-wp is deprecated.

2014-07-31 Thread Jaehoon Chung
Hi, All.

It seems too late that this patch-set is merged into linux-3.16.
Also there are some conflicts in device-tree. (I will remove the conflicts)
So if everybody is ok, I will rebase on linux-next after released linux-3.16.
At that time, i will send this patch-set to stable kernel, too.
how about?
And I want to know who can apply this patch-set(#3~#5).

Best Regards,
Jaehoon Chung

On 08/01/2014 03:36 AM, Kukjin Kim wrote:
 On 08/01/14 01:02, Doug Anderson wrote:
 Jaehoon

 On Wed, Jul 30, 2014 at 10:35 PM, Jaehoon Chungjh80.ch...@samsung.com  
 wrote:
 Slot quirks disable-wp is deprecated.
 Instead, use the host quirk disable-wp.
 (Because the slot-node is removed in dt-file.)

 Signed-off-by: Jaehoon Chungjh80.ch...@samsung.com
 Tested-by: Sachin Kamatsachin.ka...@samsung.com
 Acked-by: Seungwon Jeontgih@samsung.com
 ---
   drivers/mmc/host/dw_mmc.c  |   11 +--
   include/linux/mmc/dw_mmc.h |2 ++
   2 files changed, 11 insertions(+), 2 deletions(-)

 Thanks for taking my suggestion and making it backward compatible.
 This looks great to me.  It tested this in both the backward
 compatible way (with the warning) and the non-backward compatible way.
 I think we should land and patch #2 ASAP and then we can land the rest
 of the series as SoC maintainers see fit.

 Yes, right if we don't want to see useless merge conflicts...
 
 When I sent ack on exynos stuff, there was no conflict with my tree but 
 happens it now.
 
 - Kukjin
 
 
 Reviewed-by: Doug Andersondiand...@chromium.org
 Tested-by: Doug Andersondiand...@chromium.org
 

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[PATCHv8 2/5] ARM: dts: exynos: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-30 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts  |8 ++--
 arch/arm/boot/dts/exynos4412-origen.dts   |8 ++--
 arch/arm/boot/dts/exynos4412-trats2.dts   |8 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |   18 +
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |   26 +++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   18 +
 arch/arm/boot/dts/exynos5250-snow.dts |6 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts|   18 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   18 +
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |   16 ---
 arch/arm/boot/dts/exynos5420-peach-pit.dts|   16 ---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |   16 ---
 arch/arm/boot/dts/exynos5800-peach-pi.dts |   16 ---
 13 files changed, 51 insertions(+), 141 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..778aec6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -45,17 +45,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
regulator_p3v3 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
codec@1340 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..65ab885 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
mmc@1255 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = 200;
@@ -532,11 +531,8 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
serial@1380 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..42a3590 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@1220 {
status = okay;
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
@@ -410,17 +409,13 @@
vmmc-supply = mmc_reg;
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
mmc_2: mmc@1222 {
status = okay;
num-slots = 1;
-   supports-highspeed;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -428,12

[PATCHv8 3/5] ARM: dts: socfpga: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-30 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Dinh Nguyen dingu...@altera.com
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   |9 +++--
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |9 +++--
 arch/arm/boot/dts/socfpga_vt.dts|9 +++--
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi 
b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2c..468fc4c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,13 +29,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi 
b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf51182..1ee03c4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -30,13 +30,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b4..f9345e0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff70 {
-- 
1.7.9.5

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[PATCHv8 5/5] mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

2014-07-30 Thread Jaehoon Chung
Replaced the disable-wp into host's quirks.
(Because the slot-node is removed at dt-file.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 drivers/mmc/host/dw_mmc.c  |8 +++-
 include/linux/mmc/dw_mmc.h |2 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..8d9edc6 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -997,7 +997,10 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
int gpio_ro = mmc_gpio_get_ro(mmc);
 
/* Use platform get_ro function, else try on board write protect */
-   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
+   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) {
+   dev_warn(slot-host-dev, Recommend not to use 'disable-wp'
+   into slot-node. Change your dt-file!!);
+   } else if (slot-host-quirks  DW_MCI_QUIRK_NO_WRITE_PROTECT)
read_only = 0;
else if (!IS_ERR_VALUE(gpio_ro))
read_only = gpio_ro;
@@ -2238,6 +2241,9 @@ static struct dw_mci_of_quirks {
{
.quirk  = broken-cd,
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   }, {
+   .quirk  = disable-wp,
+   .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
},
 };
 
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index babaea9..29ce014 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -213,6 +213,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
+/* No write protect */
+#define DW_MCI_QUIRK_NO_WRITE_PROTECT  BIT(4)
 
 /* Slot level quirks */
 /* This slot has no write protect */
-- 
1.7.9.5

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[PATCHv8 4/5] ARM: dts: rockchip: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-30 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Reviewed-by: Heiko Stuebner he...@sntech.de
Acked-by: Seungwon Jeon tgih@samsung.com
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts 
b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb3273..ecea889 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -59,12 +59,8 @@
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
vmmc-supply = vcc_sd0;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
dwmmc@10218000 { /* wifi */
@@ -74,12 +70,8 @@
 
pinctrl-names = default;
pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
gpio-keys {
-- 
1.7.9.5

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[PATCHv8 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-07-30 Thread Jaehoon Chung
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a 
host.
And supports-highspeed can be replaced to cap-mmc/sd-highspeed property.

Changelog V8:
- Add the warning message to notice that slot-node was removed.
(As Doug's suggestion)
Changelog V7:
- Fixed typo and modified the commit message.
Changelog V6:
- Fixed Wrong bit control for host's quirks and rename.
- Add Acked-by for each SoC maintainers.
Changelog V5:
- Rebased on v3.16-rc4.
- Add Acked-by.
Changelog V4:
- Fix the checkpatch error.
Changelog V3:
- Fix the wrong bus-width value.
- Use the slot-host-quirks instead of brq-quirks.
- Add tested-by and reviewd-by.
Changelog V2:
- Add the mmc: dw_mmc: replace disable-wp from slot's quirks to 
host's quirk

Jaehoon Chung (5):
  mmc: dw_mmc: modify the dt-binding for removing slot-node and
supports-highspeed
  ARM: dts: exynos: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: socfpga: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: rockchip: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 -
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 -
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 -
 arch/arm/boot/dts/exynos4412-odroidx.dts   |8 ++
 arch/arm/boot/dts/exynos4412-origen.dts|8 ++
 arch/arm/boot/dts/exynos4412-trats2.dts|8 ++
 arch/arm/boot/dts/exynos5250-arndale.dts   |   18 --
 arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   26 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   18 --
 arch/arm/boot/dts/exynos5250-snow.dts  |6 ++---
 arch/arm/boot/dts/exynos5260-xyref5260.dts |   18 --
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |   18 --
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |   16 +++-
 arch/arm/boot/dts/exynos5420-peach-pit.dts |   16 +++-
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   16 +++-
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |   16 +++-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 +++-
 arch/arm/boot/dts/socfpga_arria5.dtsi  |9 +++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi|9 +++
 arch/arm/boot/dts/socfpga_vt.dts   |9 +++
 drivers/mmc/host/dw_mmc.c  |8 +-
 include/linux/mmc/dw_mmc.h |2 ++
 22 files changed, 88 insertions(+), 198 deletions(-)

-- 
1.7.9.5

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[PATCHv8 1/5] mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed

2014-07-30 Thread Jaehoon Chung
Almost SoCs use one slot per host controller.
(Even if controller can support the multiple slot, Recommend to use one slot 
per host controller.)
Don't use the slot-node and deprecate the supports-highspeed property.
Instead, use the cap-mmc/sd-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 +
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 +---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 +---
 3 files changed, 15 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 532b1d4..6cd3525 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -46,13 +46,14 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
+Required properties for a slot (Deprecated - Recommend to use one slot per 
host):
 
 * gpios: specifies a list of gpios used for command, clock and data bus. The
   first gpio is the command line and the second gpio is the clock line. The
   rest of the gpios (depending on the bus-width property) are the data lines in
   no particular order. The format of the gpio specifier depends on the gpio
   controller.
+(Deprecated - Refer to 
Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
 
 Example:
 
@@ -69,21 +70,13 @@ Example:
 
dwmmc0@1220 {
num-slots = 1;
-   supports-highspeed;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
-   gpc1 0 2 3 3, gpc1 1 2 3 3,
-   gpc1 2 2 3 3, gpc1 3 2 3 3,
-   gpc0 3 2 3 3, gpc0 4 2 3 3,
-   gpc0 5 2 3 3, gpc0 6 2 3 3;
-   };
+   bus-width = 8;
};
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index e5bc49f..3b35449 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -34,13 +34,11 @@ Example:
num-slots = 1;
vmmc-supply = ldo12;
fifo-depth = 0x100;
-   supports-highspeed;
pinctrl-names = default;
pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   cd-gpios = gpio10 3 0;
-   };
+   bus-width = 4;
+   disable-wp;
+   cd-gpios = gpio10 3 0;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 2d4a725..346c609 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -67,7 +67,8 @@ Optional properties:
 * card-detect-delay: Delay in milli-seconds before detecting card after card
   insert event. The default value is 0.
 
-* supports-highspeed: Enables support for high speed cards (up to 50MHz)
+* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 
50MHz)
+  (use cap-mmc-highspeed or cap-sd-highspeed 
instead)
 
 * broken-cd: as documented in mmc core bindings.
 
@@ -98,14 +99,11 @@ board specific portions as listed below.
clock-frequency = 4;
clock-freq-min-max = 40 2;
num-slots = 1;
-   supports-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
vmmc-supply = buck8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
-- 
1.7.9.5

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[PATCHv9 5/5] ARM: dts: rockchip: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-07-30 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced with cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Reviewed-by: Heiko Stuebner he...@sntech.de
Acked-by: Seungwon Jeon tgih@samsung.com
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts 
b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb3273..ecea889 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -59,12 +59,8 @@
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
vmmc-supply = vcc_sd0;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
dwmmc@10218000 { /* wifi */
@@ -74,12 +70,8 @@
 
pinctrl-names = default;
pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
gpio-keys {
-- 
1.7.9.5

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[PATCHv9 4/5] ARM: dts: socfpga: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-07-30 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced with cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Dinh Nguyen dingu...@altera.com
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   |9 +++--
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |9 +++--
 arch/arm/boot/dts/socfpga_vt.dts|9 +++--
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi 
b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2c..468fc4c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,13 +29,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi 
b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf51182..1ee03c4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -30,13 +30,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b4..f9345e0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff70 {
-- 
1.7.9.5

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[PATCHv9 3/5] ARM: dts: exynos: unuse the slot-node and deprecate the supports-highspeed for dw-mmc

2014-07-30 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced with cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts  |8 ++--
 arch/arm/boot/dts/exynos4412-origen.dts   |8 ++--
 arch/arm/boot/dts/exynos4412-trats2.dts   |8 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |   18 +
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |   26 +++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   18 +
 arch/arm/boot/dts/exynos5250-snow.dts |6 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts|   18 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   18 +
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |   16 ---
 arch/arm/boot/dts/exynos5420-peach-pit.dts|   16 ---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |   16 ---
 arch/arm/boot/dts/exynos5800-peach-pi.dts |   16 ---
 13 files changed, 51 insertions(+), 141 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..778aec6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -45,17 +45,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
regulator_p3v3 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
codec@1340 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..65ab885 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
mmc@1255 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = 200;
@@ -532,11 +531,8 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
serial@1380 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..42a3590 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@1220 {
status = okay;
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
@@ -410,17 +409,13 @@
vmmc-supply = mmc_reg;
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
mmc_2: mmc@1222 {
status = okay;
num-slots = 1;
-   supports-highspeed;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -428,12

[PATCHv9 2/5] mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed

2014-07-30 Thread Jaehoon Chung
Almost all SoCs use one slot per host controller.
(Even if controller can support the multiple slot, Recommend to use one slot 
per host controller.)
Don't use the slot-node and deprecate the supports-highspeed property.
Instead, use the cap-mmc/sd-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 +
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 +---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 +---
 3 files changed, 15 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 532b1d4..6cd3525 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -46,13 +46,14 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
+Required properties for a slot (Deprecated - Recommend to use one slot per 
host):
 
 * gpios: specifies a list of gpios used for command, clock and data bus. The
   first gpio is the command line and the second gpio is the clock line. The
   rest of the gpios (depending on the bus-width property) are the data lines in
   no particular order. The format of the gpio specifier depends on the gpio
   controller.
+(Deprecated - Refer to 
Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
 
 Example:
 
@@ -69,21 +70,13 @@ Example:
 
dwmmc0@1220 {
num-slots = 1;
-   supports-highspeed;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
-   gpc1 0 2 3 3, gpc1 1 2 3 3,
-   gpc1 2 2 3 3, gpc1 3 2 3 3,
-   gpc0 3 2 3 3, gpc0 4 2 3 3,
-   gpc0 5 2 3 3, gpc0 6 2 3 3;
-   };
+   bus-width = 8;
};
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index e5bc49f..3b35449 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -34,13 +34,11 @@ Example:
num-slots = 1;
vmmc-supply = ldo12;
fifo-depth = 0x100;
-   supports-highspeed;
pinctrl-names = default;
pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   cd-gpios = gpio10 3 0;
-   };
+   bus-width = 4;
+   disable-wp;
+   cd-gpios = gpio10 3 0;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 2d4a725..346c609 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -67,7 +67,8 @@ Optional properties:
 * card-detect-delay: Delay in milli-seconds before detecting card after card
   insert event. The default value is 0.
 
-* supports-highspeed: Enables support for high speed cards (up to 50MHz)
+* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 
50MHz)
+  (use cap-mmc-highspeed or cap-sd-highspeed 
instead)
 
 * broken-cd: as documented in mmc core bindings.
 
@@ -98,14 +99,11 @@ board specific portions as listed below.
clock-frequency = 4;
clock-freq-min-max = 40 2;
num-slots = 1;
-   supports-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
vmmc-supply = buck8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
+   cap-sd-highspeed

[PATCHv9 1/5] mmc: dw_mmc: Slot quirk disable-wp is deprecated.

2014-07-30 Thread Jaehoon Chung
Slot quirks disable-wp is deprecated.
Instead, use the host quirk disable-wp.
(Because the slot-node is removed in dt-file.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 drivers/mmc/host/dw_mmc.c  |   11 +--
 include/linux/mmc/dw_mmc.h |2 ++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..47b52cc 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -997,7 +997,8 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
int gpio_ro = mmc_gpio_get_ro(mmc);
 
/* Use platform get_ro function, else try on board write protect */
-   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
+   if ((slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
+   (slot-host-quirks  DW_MCI_QUIRK_NO_WRITE_PROTECT))
read_only = 0;
else if (!IS_ERR_VALUE(gpio_ro))
read_only = gpio_ro;
@@ -2021,8 +2022,11 @@ static int dw_mci_of_get_slot_quirks(struct device *dev, 
u8 slot)
 
/* get quirks */
for (idx = 0; idx  ARRAY_SIZE(of_slot_quirks); idx++)
-   if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
+   if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
+   dev_warn(dev, Slot quirk %s is deprecated\n,
+   of_slot_quirks[idx].quirk);
quirks |= of_slot_quirks[idx].id;
+   }
 
return quirks;
 }
@@ -2238,6 +2242,9 @@ static struct dw_mci_of_quirks {
{
.quirk  = broken-cd,
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   }, {
+   .quirk  = disable-wp,
+   .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
},
 };
 
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index babaea9..29ce014 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -213,6 +213,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
+/* No write protect */
+#define DW_MCI_QUIRK_NO_WRITE_PROTECT  BIT(4)
 
 /* Slot level quirks */
 /* This slot has no write protect */
-- 
1.7.9.5

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[PATCHv9 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-07-30 Thread Jaehoon Chung
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a 
host.
And supports-highspeed can be replaced with cap-mmc/sd-highspeed property.

Changelog V9:
- Fix typos.
- Relocated the warning message.
- Change patch's sequence.
Changelog V8:
- Add the warning message to notice that slot-node was removed.
(As Doug's suggestion)
Changelog V7:
- Fixed typo and modified the commit message.
Changelog V6:
- Fixed Wrong bit control for host's quirks and rename.
- Add Acked-by for each SoC maintainers.
Changelog V5:
- Rebased on v3.16-rc4.
- Add Acked-by.
Changelog V4:
- Fix the checkpatch error.
Changelog V3:
- Fix the wrong bus-width value.
- Use the slot-host-quirks instead of brq-quirks.
- Add tested-by and reviewd-by.
Changelog V2:
- Add the mmc: dw_mmc: replace disable-wp from slot's quirks to 
host's quirk


Jaehoon Chung (5):
  mmc: dw_mmc: Slot quirk disable-wp is deprecated.
  mmc: dw_mmc: modify the dt-binding for removing slot-node and
supports-highspeed
  ARM: dts: exynos: unuse the slot-node and deprecate the
supports-highspeed for dw-mmc
  ARM: dts: socfpga: unuse the slot-node and deprecate the
supports-highspeed for dw-mmc
  ARM: dts: rockchip: unuse the slot-node and deprecate the
supports-highspeed for dw-mmc

 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 -
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 -
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 -
 arch/arm/boot/dts/exynos4412-odroidx.dts   |8 ++
 arch/arm/boot/dts/exynos4412-origen.dts|8 ++
 arch/arm/boot/dts/exynos4412-trats2.dts|8 ++
 arch/arm/boot/dts/exynos5250-arndale.dts   |   18 --
 arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   26 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   18 --
 arch/arm/boot/dts/exynos5250-snow.dts  |6 ++---
 arch/arm/boot/dts/exynos5260-xyref5260.dts |   18 --
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |   18 --
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |   16 +++-
 arch/arm/boot/dts/exynos5420-peach-pit.dts |   16 +++-
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   16 +++-
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |   16 +++-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 +++-
 arch/arm/boot/dts/socfpga_arria5.dtsi  |9 +++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi|9 +++
 arch/arm/boot/dts/socfpga_vt.dts   |9 +++
 drivers/mmc/host/dw_mmc.c  |   11 +++--
 include/linux/mmc/dw_mmc.h |2 ++
 22 files changed, 90 insertions(+), 199 deletions(-)

-- 
1.7.9.5

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Re: [PATCHv7 5/5] mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

2014-07-29 Thread Jaehoon Chung
Hi, Doug.

Thanks for review.

On 07/30/2014 03:01 AM, Doug Anderson wrote:
 Jaehoon,
 
 On Sun, Jul 27, 2014 at 7:29 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 Replaced the disable-wp into host's quirks.
 (Because the slot-node is removed at dt-file.)

 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 Tested-by: Sachin Kamat sachin.ka...@samsung.com
 Acked-by: Seungwon Jeon tgih@samsung.com
 ---
  drivers/mmc/host/dw_mmc.c  |   12 +---
  include/linux/mmc/dw_mmc.h |6 ++
  2 files changed, 7 insertions(+), 11 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 1ac227c..4a4f66f 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -997,7 +997,7 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
 int gpio_ro = mmc_gpio_get_ro(mmc);

 /* Use platform get_ro function, else try on board write protect */
 -   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
 +   if (slot-host-quirks  DW_MCI_QUIRK_NO_WRITE_PROTECT)
 
 It doesn't seem like it would be hard to include support for the old
 binding (and just print a warning).  Then this could land ahead of the
 device tree changes.
 
 Generally I think we're supposed to keep support for old device trees
 if possible (except in extreme cases).
Ok, I see. I will add the Warning message like this. (Recommend not to use the 
slot-node...)
Then Developers can change the device-tree, right.

Today, i will send the patch. If you have any other comment, let me know, plz.
I want to merge this patch-set into 3.16.

Best Regards,
Jaehoon Chung
 
 -Doug
 

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Re: [PATCHv6 1/5] mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed

2014-07-27 Thread Jaehoon Chung
Hi, Andreas,

On 07/25/2014 09:11 PM, Andreas Färber wrote:
 Hi Jaehoon,
 
 Am 25.07.2014 03:11, schrieb Jaehoon Chung:
 Almost Soc is used the slot per a host.
 
 Something's very wrong with this sentence. What are you trying to say?
 Almost all SoCs use one slot only per host controller device?

If you are confusion for this sentence, sorry.
It means that we recommend only one slot per host controller.
Some controller can be supported the multiple slot per a host controller.
But i didn't find anywhere it used the multiple slot per a host controller.


Best Regards,
Jaehoon Chung
 
 Don't use the slot-node and deprecated the supports-highsped property.
 
 s/deprecated/deprecate/ ?
 s/highsped/highspeed/
 
 Instead, use the cap-mmc/sd-highspeed.

 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 Reviewed-by: Tushar Behera trbli...@gmail.com
 Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
 Tested-by: Sachin Kamat sachin.ka...@samsung.com
 Acked-by: Seungwon Jeon tgih@samsung.com
 ---
  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 +
  .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 +---
  .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 +---
  3 files changed, 15 insertions(+), 26 deletions(-)

 diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 index 532b1d4..9308325 100644
 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
 @@ -46,13 +46,14 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and 
 rx
  phase shift clocks should be 0.
  
 -Required properties for a slot:
 +Required properties for a slot (Deprecated - Recommend to use one slot per 
 a host):
 
 per host
 
  
  * gpios: specifies a list of gpios used for command, clock and data bus. The
first gpio is the command line and the second gpio is the clock line. The
rest of the gpios (depending on the bus-width property) are the data 
 lines in
no particular order. The format of the gpio specifier depends on the gpio
controller.
 + (Deprecated - Refer to 
 Documentaion/devicetree/binding/pinctrl/samsung-pinctrl.txt)
 
 Documentation/
 
 Nit: Is the indentation intentional? (parenthesis not aligned with text)
 
  
  Example:
  
 @@ -69,21 +70,13 @@ Example:
  
  dwmmc0@1220 {
  num-slots = 1;
 -supports-highspeed;
 +cap-mmc-highspeed;
 +cap-sd-highspeed;
  broken-cd;
  fifo-depth = 0x80;
  card-detect-delay = 200;
  samsung,dw-mshc-ciu-div = 3;
  samsung,dw-mshc-sdr-timing = 2 3;
  samsung,dw-mshc-ddr-timing = 1 2;
 -
 -slot@0 {
 -reg = 0;
 -bus-width = 8;
 -gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
 -gpc1 0 2 3 3, gpc1 1 2 3 3,
 -gpc1 2 2 3 3, gpc1 3 2 3 3,
 -gpc0 3 2 3 3, gpc0 4 2 3 3,
 -gpc0 5 2 3 3, gpc0 6 2 3 3;
 -};
 +bus-width = 8;
  };
 diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
 index e5bc49f..3b35449 100644
 --- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
 @@ -34,13 +34,11 @@ Example:
  num-slots = 1;
  vmmc-supply = ldo12;
  fifo-depth = 0x100;
 -supports-highspeed;
  pinctrl-names = default;
  pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
 -slot@0 {
 -reg = 0;
 -bus-width = 4;
 -disable-wp;
 -cd-gpios = gpio10 3 0;
 -};
 +bus-width = 4;
 +disable-wp;
 +cd-gpios = gpio10 3 0;
 +cap-mmc-highspeed;
 +cap-sd-highspeed;
  };
 diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
 b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
 index 2d4a725..346c609 100644
 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
 +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
 @@ -67,7 +67,8 @@ Optional properties:
  * card-detect-delay: Delay in milli-seconds before detecting card after card
insert event. The default value is 0.
  
 -* supports-highspeed: Enables support for high speed cards (up to 50MHz)
 +* supports-highspeed (DEPRECATED): Enables support for high speed cards (up 
 to 50MHz)
 +   (use cap-mmc-highspeed or cap-sd-highspeed 
 instead)
  
  * broken-cd: as documented in mmc core bindings.
  
 @@ -98,14 +99,11 @@ board specific portions as listed

[PATCHv7 3/5] ARM: dts: socfpga: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-27 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Dinh Nguyen dingu...@altera.com
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   |9 +++--
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |9 +++--
 arch/arm/boot/dts/socfpga_vt.dts|9 +++--
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi 
b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2c..468fc4c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,13 +29,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi 
b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf51182..1ee03c4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -30,13 +30,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b4..f9345e0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff70 {
-- 
1.7.9.5

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[PATCHv7 4/5] ARM: dts: rockchip: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-27 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Reviewed-by: Heiko Stuebner he...@sntech.de
Acked-by: Seungwon Jeon tgih@samsung.com
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts 
b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb3273..ecea889 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -59,12 +59,8 @@
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
vmmc-supply = vcc_sd0;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
dwmmc@10218000 { /* wifi */
@@ -74,12 +70,8 @@
 
pinctrl-names = default;
pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
gpio-keys {
-- 
1.7.9.5

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[PATCHv7 1/5] mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed

2014-07-27 Thread Jaehoon Chung
Almost SoCs use one slot per host controller.
(Even if controller can support the multiple slot, Recommend to use one slot 
per host controller.)
Don't use the slot-node and deprecate the supports-highspeed property.
Instead, use the cap-mmc/sd-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 +
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 +---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 +---
 3 files changed, 15 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 532b1d4..6cd3525 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -46,13 +46,14 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
+Required properties for a slot (Deprecated - Recommend to use one slot per 
host):
 
 * gpios: specifies a list of gpios used for command, clock and data bus. The
   first gpio is the command line and the second gpio is the clock line. The
   rest of the gpios (depending on the bus-width property) are the data lines in
   no particular order. The format of the gpio specifier depends on the gpio
   controller.
+(Deprecated - Refer to 
Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
 
 Example:
 
@@ -69,21 +70,13 @@ Example:
 
dwmmc0@1220 {
num-slots = 1;
-   supports-highspeed;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
-   gpc1 0 2 3 3, gpc1 1 2 3 3,
-   gpc1 2 2 3 3, gpc1 3 2 3 3,
-   gpc0 3 2 3 3, gpc0 4 2 3 3,
-   gpc0 5 2 3 3, gpc0 6 2 3 3;
-   };
+   bus-width = 8;
};
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index e5bc49f..3b35449 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -34,13 +34,11 @@ Example:
num-slots = 1;
vmmc-supply = ldo12;
fifo-depth = 0x100;
-   supports-highspeed;
pinctrl-names = default;
pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   cd-gpios = gpio10 3 0;
-   };
+   bus-width = 4;
+   disable-wp;
+   cd-gpios = gpio10 3 0;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 2d4a725..346c609 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -67,7 +67,8 @@ Optional properties:
 * card-detect-delay: Delay in milli-seconds before detecting card after card
   insert event. The default value is 0.
 
-* supports-highspeed: Enables support for high speed cards (up to 50MHz)
+* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 
50MHz)
+  (use cap-mmc-highspeed or cap-sd-highspeed 
instead)
 
 * broken-cd: as documented in mmc core bindings.
 
@@ -98,14 +99,11 @@ board specific portions as listed below.
clock-frequency = 4;
clock-freq-min-max = 40 2;
num-slots = 1;
-   supports-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
vmmc-supply = buck8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
-- 
1.7.9.5

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[PATCHv7 0/5] ARM: remove the sub-node and deprecate supports-highspeed property for dwmmc.

2014-07-27 Thread Jaehoon Chung
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a 
host.
And supports-highspeed can be replaced to cap-mmc/sd-highspeed property.

Chnagelog V7:
- Fixed typo and modified the commit message.
Changelog V6:
- Fixed Wrong bit control for host's quirks and rename.
- Add Acked-by for each SoC maintainers.
Changelog V5:
- Rebased on v3.16-rc4.
- Add Acked-by.
Changelog V4:
- Fix the checkpatch error.
Changelog V3:
- Fix the wrong bus-width value.
- Use the slot-host-quirks instead of brq-quirks.
- Add tested-by and reviewd-by.
Changelog V2:
- Add the mmc: dw_mmc: replace disable-wp from slot's quirks to 
host's quirk


Jaehoon Chung (5):
  mmc: dw_mmc: modify the dt-binding for removing slot-node and
supports-highspeed
  ARM: dts: exynos: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: socfpga: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: rockchip: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 -
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 -
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 -
 arch/arm/boot/dts/exynos4412-odroidx.dts   |8 ++
 arch/arm/boot/dts/exynos4412-origen.dts|8 ++
 arch/arm/boot/dts/exynos4412-trats2.dts|8 ++
 arch/arm/boot/dts/exynos5250-arndale.dts   |   18 --
 arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   26 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   18 --
 arch/arm/boot/dts/exynos5250-snow.dts  |6 ++---
 arch/arm/boot/dts/exynos5260-xyref5260.dts |   18 --
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |   18 --
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |   16 +++-
 arch/arm/boot/dts/exynos5420-peach-pit.dts |   16 +++-
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   16 +++-
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |   16 +++-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 +++-
 arch/arm/boot/dts/socfpga_arria5.dtsi  |9 +++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi|9 +++
 arch/arm/boot/dts/socfpga_vt.dts   |9 +++
 drivers/mmc/host/dw_mmc.c  |   12 -
 include/linux/mmc/dw_mmc.h |6 ++---
 22 files changed, 86 insertions(+), 208 deletions(-)

-- 
1.7.9.5

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[PATCHv7 2/5] ARM: dts: exynos: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-27 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts  |8 ++--
 arch/arm/boot/dts/exynos4412-origen.dts   |8 ++--
 arch/arm/boot/dts/exynos4412-trats2.dts   |8 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |   18 +
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |   26 +++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   18 +
 arch/arm/boot/dts/exynos5250-snow.dts |6 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts|   18 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   18 +
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |   16 ---
 arch/arm/boot/dts/exynos5420-peach-pit.dts|   16 ---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |   16 ---
 arch/arm/boot/dts/exynos5800-peach-pi.dts |   16 ---
 13 files changed, 51 insertions(+), 141 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..778aec6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -45,17 +45,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
regulator_p3v3 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
codec@1340 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..65ab885 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
mmc@1255 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = 200;
@@ -532,11 +531,8 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
serial@1380 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..42a3590 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@1220 {
status = okay;
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
@@ -410,17 +409,13 @@
vmmc-supply = mmc_reg;
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
mmc_2: mmc@1222 {
status = okay;
num-slots = 1;
-   supports-highspeed;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -428,12

[PATCHv7 5/5] mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

2014-07-27 Thread Jaehoon Chung
Replaced the disable-wp into host's quirks.
(Because the slot-node is removed at dt-file.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 drivers/mmc/host/dw_mmc.c  |   12 +---
 include/linux/mmc/dw_mmc.h |6 ++
 2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..4a4f66f 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -997,7 +997,7 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
int gpio_ro = mmc_gpio_get_ro(mmc);
 
/* Use platform get_ro function, else try on board write protect */
-   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
+   if (slot-host-quirks  DW_MCI_QUIRK_NO_WRITE_PROTECT)
read_only = 0;
else if (!IS_ERR_VALUE(gpio_ro))
read_only = gpio_ro;
@@ -2006,12 +2006,7 @@ static struct device_node 
*dw_mci_of_find_slot_node(struct device *dev, u8 slot)
 static struct dw_mci_of_slot_quirks {
char *quirk;
int id;
-} of_slot_quirks[] = {
-   {
-   .quirk  = disable-wp,
-   .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
-   },
-};
+} of_slot_quirks[] = {};
 
 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
 {
@@ -2238,6 +2233,9 @@ static struct dw_mci_of_quirks {
{
.quirk  = broken-cd,
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   }, {
+   .quirk  = disable-wp,
+   .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
},
 };
 
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index babaea9..8b4b2d8 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -213,10 +213,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
-
-/* Slot level quirks */
-/* This slot has no write protect */
-#define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
+/* No write protect */
+#define DW_MCI_QUIRK_NO_WRITE_PROTECT  BIT(4)
 
 struct dma_pdata;
 
-- 
1.7.9.5

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[PATCHv6 0/5] remove the sub-node and deprecated

2014-07-24 Thread Jaehoon Chung
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a 
host.
And supports-highspeed can be replaced to cap-mmc/sd-highspeed property.

Changelog V6:
- Fixed Wrong bit control for host's quirks and rename.
- Add Acked-by for each SoC maintainers.
Changelog V5:
- Rebased on v3.16-rc4.
- Add Acked-by.
Changelog V4:
- Fix the checkpatch error.
Changelog V3:
- Fix the wrong bus-width value.
- Use the slot-host-quirks instead of brq-quirks.
- Add tested-by and reviewd-by.
Changelog V2:
- Add the mmc: dw_mmc: replace disable-wp from slot's quirks to 
host's quirk

Jaehoon Chung (5):
  mmc: dw_mmc: modify the dt-binding for removing slot-node and
supports-highspeed
  ARM: dts: exynos: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: socfpga: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: rockchip: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 -
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 -
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 -
 arch/arm/boot/dts/exynos4412-odroidx.dts   |8 ++
 arch/arm/boot/dts/exynos4412-origen.dts|8 ++
 arch/arm/boot/dts/exynos4412-trats2.dts|8 ++
 arch/arm/boot/dts/exynos5250-arndale.dts   |   18 --
 arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   26 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   18 --
 arch/arm/boot/dts/exynos5250-snow.dts  |6 ++---
 arch/arm/boot/dts/exynos5260-xyref5260.dts |   18 --
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |   18 --
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |   16 +++-
 arch/arm/boot/dts/exynos5420-peach-pit.dts |   16 +++-
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   16 +++-
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |   16 +++-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 +++-
 arch/arm/boot/dts/socfpga_arria5.dtsi  |9 +++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi|9 +++
 arch/arm/boot/dts/socfpga_vt.dts   |9 +++
 drivers/mmc/host/dw_mmc.c  |   12 -
 include/linux/mmc/dw_mmc.h |6 ++---
 22 files changed, 86 insertions(+), 208 deletions(-)

-- 
1.7.9.5

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[PATCHv6 1/5] mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed

2014-07-24 Thread Jaehoon Chung
Almost Soc is used the slot per a host.
Don't use the slot-node and deprecated the supports-highsped property.
Instead, use the cap-mmc/sd-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 +
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 +---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 +---
 3 files changed, 15 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 532b1d4..9308325 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -46,13 +46,14 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
+Required properties for a slot (Deprecated - Recommend to use one slot per a 
host):
 
 * gpios: specifies a list of gpios used for command, clock and data bus. The
   first gpio is the command line and the second gpio is the clock line. The
   rest of the gpios (depending on the bus-width property) are the data lines in
   no particular order. The format of the gpio specifier depends on the gpio
   controller.
+ (Deprecated - Refer to 
Documentaion/devicetree/binding/pinctrl/samsung-pinctrl.txt)
 
 Example:
 
@@ -69,21 +70,13 @@ Example:
 
dwmmc0@1220 {
num-slots = 1;
-   supports-highspeed;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
-   gpc1 0 2 3 3, gpc1 1 2 3 3,
-   gpc1 2 2 3 3, gpc1 3 2 3 3,
-   gpc0 3 2 3 3, gpc0 4 2 3 3,
-   gpc0 5 2 3 3, gpc0 6 2 3 3;
-   };
+   bus-width = 8;
};
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index e5bc49f..3b35449 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -34,13 +34,11 @@ Example:
num-slots = 1;
vmmc-supply = ldo12;
fifo-depth = 0x100;
-   supports-highspeed;
pinctrl-names = default;
pinctrl-0 = sd_pmx_pins sd_cfg_func1 sd_cfg_func2;
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   cd-gpios = gpio10 3 0;
-   };
+   bus-width = 4;
+   disable-wp;
+   cd-gpios = gpio10 3 0;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 2d4a725..346c609 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -67,7 +67,8 @@ Optional properties:
 * card-detect-delay: Delay in milli-seconds before detecting card after card
   insert event. The default value is 0.
 
-* supports-highspeed: Enables support for high speed cards (up to 50MHz)
+* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 
50MHz)
+  (use cap-mmc-highspeed or cap-sd-highspeed 
instead)
 
 * broken-cd: as documented in mmc core bindings.
 
@@ -98,14 +99,11 @@ board specific portions as listed below.
clock-frequency = 4;
clock-freq-min-max = 40 2;
num-slots = 1;
-   supports-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
vmmc-supply = buck8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
-- 
1.7.9.5

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More

[PATCHv6 2/5] ARM: dts: exynos: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-24 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts  |8 ++--
 arch/arm/boot/dts/exynos4412-origen.dts   |8 ++--
 arch/arm/boot/dts/exynos4412-trats2.dts   |8 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |   18 +
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |   26 +++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   18 +
 arch/arm/boot/dts/exynos5250-snow.dts |6 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts|   18 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   18 +
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |   16 ---
 arch/arm/boot/dts/exynos5420-peach-pit.dts|   16 ---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |   16 ---
 arch/arm/boot/dts/exynos5800-peach-pi.dts |   16 ---
 13 files changed, 51 insertions(+), 141 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..778aec6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -45,17 +45,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
regulator_p3v3 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
codec@1340 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..65ab885 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
mmc@1255 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = 200;
@@ -532,11 +531,8 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
serial@1380 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..42a3590 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@1220 {
status = okay;
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
@@ -410,17 +409,13 @@
vmmc-supply = mmc_reg;
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
mmc_2: mmc@1222 {
status = okay;
num-slots = 1;
-   supports-highspeed;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -428,12

[PATCHv6 4/5] ARM: dts: rockchip: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-24 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Reviewed-by: Heiko Stuebner he...@sntech.de
Acked-by: Seungwon Jeon tgih@samsung.com
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts 
b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb3273..ecea889 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -59,12 +59,8 @@
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
vmmc-supply = vcc_sd0;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
dwmmc@10218000 { /* wifi */
@@ -74,12 +70,8 @@
 
pinctrl-names = default;
pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
gpio-keys {
-- 
1.7.9.5

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[PATCHv6 5/5] mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

2014-07-24 Thread Jaehoon Chung
Replaced the disable-wp into host's quirks.
(Because the slot-node is removed at dt-file.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Tested-by: Sachin Kamat sachin.ka...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
 drivers/mmc/host/dw_mmc.c  |   12 +---
 include/linux/mmc/dw_mmc.h |6 ++
 2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..4a4f66f 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -997,7 +997,7 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
int gpio_ro = mmc_gpio_get_ro(mmc);
 
/* Use platform get_ro function, else try on board write protect */
-   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
+   if (slot-host-quirks  DW_MCI_QUIRK_NO_WRITE_PROTECT)
read_only = 0;
else if (!IS_ERR_VALUE(gpio_ro))
read_only = gpio_ro;
@@ -2006,12 +2006,7 @@ static struct device_node 
*dw_mci_of_find_slot_node(struct device *dev, u8 slot)
 static struct dw_mci_of_slot_quirks {
char *quirk;
int id;
-} of_slot_quirks[] = {
-   {
-   .quirk  = disable-wp,
-   .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
-   },
-};
+} of_slot_quirks[] = {};
 
 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
 {
@@ -2238,6 +2233,9 @@ static struct dw_mci_of_quirks {
{
.quirk  = broken-cd,
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   }, {
+   .quirk  = disable-wp,
+   .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
},
 };
 
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index babaea9..8b4b2d8 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -213,10 +213,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
-
-/* Slot level quirks */
-/* This slot has no write protect */
-#define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
+/* No write protect */
+#define DW_MCI_QUIRK_NO_WRITE_PROTECT  BIT(4)
 
 struct dma_pdata;
 
-- 
1.7.9.5

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[PATCHv6 3/5] ARM: dts: socfpga: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-24 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Acked-by: Seungwon Jeon tgih@samsung.com
Acked-by: Dinh Nguyen dingu...@altera.com
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   |9 +++--
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |9 +++--
 arch/arm/boot/dts/socfpga_vt.dts|9 +++--
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi 
b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2c..468fc4c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,13 +29,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi 
b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf51182..1ee03c4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -30,13 +30,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b4..f9345e0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff70 {
-- 
1.7.9.5

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Re: sdhci_s3c_consider_clock scheduling while atomic - clk_round_rate

2014-07-15 Thread Jaehoon Chung
Hi,

It's also related with clock-gating.
Mainline kernel is using the clkgate-delay = 0 by default.
If we use this value, Every request time should be gated/ungated...
Then it may be faced the race-condition...In my experiment, it occasionally 
occurred the CRC error or other problem.
And it's also degraded the performance since add the overhead.
I'm using clkgate-delay = 3 ~ 10.

Anyway, we need to fix this. I will consider this.


Best Regards,
Jaehoon Chung

On 06/25/2014 12:52 AM, Tomasz Figa wrote:
 Hi Daniel,
 
 [adding Ulf, Chris and Mike to the discussion]
 
 On 24.06.2014 11:48, Daniel Drake wrote:
 sdhci_s3c_set_clock is called from sdhci_do_set_ios with interrupts
 disabled, and this calls into sdhci_s3c_consider_clock().

 The patch mmc: sdhci-s3c: Cache bus clock rates addressed some
 scheduling while atomic in this function, but there are more issues
 here, seen while testing 3.16-rc2 on exynos4412:

 BUG: sleeping function called from invalid context at 
 kernel/locking/mutex.c:103
 in_atomic(): 1, irqs_disabled(): 128, pid: 75, name: mmcqd/0
 Preemption disabled at:[  (null)]   (null)

 CPU: 0 PID: 75 Comm: mmcqd/0 Not tainted 3.16.0-rc2-00028-ge9fe7eb-dirty #77
 [c0016140] (unwind_backtrace) from [c0011e14] (show_stack+0x10/0x14)
 [c0011e14] (show_stack) from [c05ce8a8] (dump_stack+0x84/0xc4)
 [c05ce8a8] (dump_stack) from [c05d2de0] (mutex_lock+0x1c/0x3c)
 [c05d2de0] (mutex_lock) from [c046214c] (clk_prepare_lock+0x6c/0xf4)
 [c046214c] (clk_prepare_lock) from [c04625ac] (clk_round_rate+0x10/0x2c)
 [c04625ac] (clk_round_rate) from [c0447628] 
 (sdhci_s3c_set_clock+0x4c/0x1e8)
 [c0447628] (sdhci_s3c_set_clock) from [c0447818]
 (sdhci_cmu_set_clock+0x54/0x140)
 [c0447818] (sdhci_cmu_set_clock) from [c0443a38]
 (sdhci_do_set_ios+0x138/0x58c)
 [c0443a38] (sdhci_do_set_ios) from [c0443864] (sdhci_set_ios+0x28/0x34)

 clk_round_rate cannot be called here because it takes a mutex.

 sdhci_s3c_set_clock() also calls into clk_prepare_enable() which looks
 like it could trigger this problem too.
 
 Apparently this is related to generic sdhci code calling .set_clock()
 under spin_lock_irqsave(). For reference, see sdhci_do_set_ios() and
 sdhci_tasklet_finish().
 
 Chris, Ulf, any suggestions?
 
 Best regards,
 Tomasz
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Re: [PATCH 1/6] mmc: sdhci-s3c: Fix local I/O clock gating

2014-07-14 Thread Jaehoon Chung
Looks good to me.

Acked-by: Jaehoon Chung jh80.ch...@samsung.com

On 06/24/2014 10:57 PM, Tomasz Figa wrote:
 For internal card detection mechanism it is required that the local I/O
 clock is always running. However while current implementation accounts
 for this, it does so incorrectly leading to race conditions and warnings
 about unbalanced clock disables.
 
 This patch fixes it by inverting the logic, which now increases local
 I/O clock enable count when internal card detect is used, instead of
 decreasing it otherwise.
 
 Signed-off-by: Tomasz Figa t.f...@samsung.com
 Cc: Ben Dooks ben-li...@fluff.org
 Cc: Chris Ball ch...@printf.net
 Cc: Ulf Hansson ulf.hans...@linaro.org
 Cc: linux-...@vger.kernel.org
 ---
  drivers/mmc/host/sdhci-s3c.c | 17 ++---
  1 file changed, 10 insertions(+), 7 deletions(-)
 
 diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
 index fa5954a..1795e1f 100644
 --- a/drivers/mmc/host/sdhci-s3c.c
 +++ b/drivers/mmc/host/sdhci-s3c.c
 @@ -487,8 +487,13 @@ static int sdhci_s3c_probe(struct platform_device *pdev)
   goto err_pdata_io_clk;
   }
  
 - /* enable the local io clock and keep it running for the moment. */
 - clk_prepare_enable(sc-clk_io);
 + /*
 +  * Keep local I/O clock enabled for internal card detect pin
 +  * or runtime PM is disabled.
 +  */
 + if (pdata-cd_type == S3C_SDHCI_CD_INTERNAL
 + || !IS_ENABLED(CONFIG_PM_RUNTIME))
 + clk_prepare_enable(sc-clk_io);
  
   for (clks = 0, ptr = 0; ptr  MAX_BUS_CLK; ptr++) {
   char name[14];
 @@ -611,15 +616,13 @@ static int sdhci_s3c_probe(struct platform_device *pdev)
   goto err_req_regs;
   }
  
 -#ifdef CONFIG_PM_RUNTIME
 - if (pdata-cd_type != S3C_SDHCI_CD_INTERNAL)
 - clk_disable_unprepare(sc-clk_io);
 -#endif
   return 0;
  
   err_req_regs:
   err_no_busclks:
 - clk_disable_unprepare(sc-clk_io);
 + if (pdata-cd_type == S3C_SDHCI_CD_INTERNAL
 + || !IS_ENABLED(CONFIG_PM_RUNTIME))
 + clk_disable_unprepare(sc-clk_io);
  
   err_pdata_io_clk:
   sdhci_free_host(host);
 

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Re: [PATCHv5] mmc: dw_mmc: change to use recommended reset procedure

2014-07-13 Thread Jaehoon Chung
On 07/12/2014 05:53 AM, Sonny Rao wrote:
 This patch changes the fifo reset code to follow the reset procedure
 outlined in the documentation of Synopsys Mobile storage host databook.
 
 Signed-off-by: Sonny Rao sonny...@chromium.org
 Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
 ---
 v2: Add Generic DMA support
 per the documentation, move interrupt clear before wait
 make the test for DMA host-use_dma rather than host-using_dma
 add proper return values (although it appears no caller checks)
 v3: rename fifo reset function, and change callers
 use this combined reset function in dw_mci_resume()
 just one caller left (probe), so get rid of dw_mci_ctrl_all_reset()
 use DMA reset bit for all systems which use DMA
 remove extra IDMAC reset in dw_mci_work_routine_card()
 do CIU clock update in error path, if CIU reset cleared
 v4: remove comment about FIFO reset in dw_mci_work_routine_card()
 move down error message when control reset clears but others don't
  and clarify the error stating that we will still update clocks
 make flags for all reset bits a macro
 v5: don't use dw_mci_reset() in dw_mci_resume() and instead match what
 is done in dw_mci_probe() and don't force inline dw_mci_resume()
 ---
  drivers/mmc/host/dw_mmc.c | 86 
 ++-
  drivers/mmc/host/dw_mmc.h |  5 +++
  2 files changed, 68 insertions(+), 23 deletions(-)
 
 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 55cd110..db25494 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -111,8 +111,7 @@ static const u8 tuning_blk_pattern_8bit[] = {
   0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  };
  
 -static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 -static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 +static bool dw_mci_reset(struct dw_mci *host);
  
  #if defined(CONFIG_DEBUG_FS)
  static int dw_mci_req_show(struct seq_file *s, void *v)
 @@ -1254,7 +1253,7 @@ static int dw_mci_data_complete(struct dw_mci *host, 
 struct mmc_data *data)
* After an error, there may be data lingering
* in the FIFO
*/
 - dw_mci_fifo_reset(host);
 + dw_mci_reset(host);
   } else {
   data-bytes_xfered = data-blocks * data-blksz;
   data-error = 0;
 @@ -1371,7 +1370,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
  
   /* CMD error in data command */
   if (mrq-cmd-error  mrq-data)
 - dw_mci_fifo_reset(host);
 + dw_mci_reset(host);
  
   host-cmd = NULL;
   host-data = NULL;
 @@ -1982,14 +1981,8 @@ static void dw_mci_work_routine_card(struct 
 work_struct *work)
   }
  
   /* Power down slot */
 - if (present == 0) {
 - /* Clear down the FIFO */
 - dw_mci_fifo_reset(host);
 -#ifdef CONFIG_MMC_DW_IDMAC
 - dw_mci_idmac_reset(host);
 -#endif
 -
 - }
 + if (present == 0)
 + dw_mci_reset(host);
  
   spin_unlock_bh(host-lock);
  
 @@ -2323,8 +2316,11 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 
 reset)
   return false;
  }
  
 -static inline bool dw_mci_fifo_reset(struct dw_mci *host)
 +static bool dw_mci_reset(struct dw_mci *host)
  {
 + u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
 + bool ret = false;
 +
   /*
* Reseting generates a block interrupt, hence setting
* the scatter-gather pointer to NULL.
 @@ -2334,15 +2330,59 @@ static inline bool dw_mci_fifo_reset(struct dw_mci 
 *host)
   host-sg = NULL;
   }
  
 - return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
 -}
 + if (host-use_dma)
 + flags |= SDMMC_CTRL_DMA_RESET;
  
 -static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
 -{
 - return dw_mci_ctrl_reset(host,
 -  SDMMC_CTRL_FIFO_RESET |
 -  SDMMC_CTRL_RESET |
 -  SDMMC_CTRL_DMA_RESET);
 + if (dw_mci_ctrl_reset(host, flags)) {
 + /*
 +  * In all cases we clear the RAWINTS register to clear any
 +  * interrupts.
 +  */
 + mci_writel(host, RINTSTS, 0x);
 +
 + /* if using dma we wait for dma_req to clear */
 + if (host-use_dma) {
 + unsigned long timeout = jiffies + msecs_to_jiffies(500);
 + u32 status;
 + do {
 + status = mci_readl(host, STATUS);
 + if (!(status  SDMMC_STATUS_DMA_REQ))
 +

[PATCHv3 3/5] ARM: dts: socfpga: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-10 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   |9 +++--
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |9 +++--
 arch/arm/boot/dts/socfpga_vt.dts|9 +++--
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi 
b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2c..468fc4c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,13 +29,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi 
b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf51182..1ee03c4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -30,13 +30,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b4..f9345e0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
dwmmc0@ff704000 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   };
+   bus-width = 4;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
};
 
ethernet@ff70 {
-- 
1.7.9.5

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[PATCHv3 4/5] ARM: dts: rockchip: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-10 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Reviewed-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts 
b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb3273..ecea889 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -59,12 +59,8 @@
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_cd sd0_bus4;
vmmc-supply = vcc_sd0;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
dwmmc@10218000 { /* wifi */
@@ -74,12 +70,8 @@
 
pinctrl-names = default;
pinctrl-0 = sd1_clk sd1_cmd sd1_bus4;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 4;
-   disable-wp;
-   };
+   bus-width = 4;
+   disable-wp;
};
 
gpio-keys {
-- 
1.7.9.5

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[PATCHv3 2/5] ARM: dts: exynos: unuse the slot-node and deprecated the supports-highspeed for dw-mmc

2014-07-10 Thread Jaehoon Chung
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Sachin Kamat sachin.ka...@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts  |8 ++--
 arch/arm/boot/dts/exynos4412-origen.dts   |8 ++--
 arch/arm/boot/dts/exynos4412-trats2.dts   |8 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |   18 +
 arch/arm/boot/dts/exynos5250-cros-common.dtsi |   26 +++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   18 +
 arch/arm/boot/dts/exynos5250-snow.dts |6 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts|   18 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   18 +
 arch/arm/boot/dts/exynos5420-arndale-octa.dts |   16 ---
 arch/arm/boot/dts/exynos5420-peach-pit.dts|   16 ---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |   16 ---
 arch/arm/boot/dts/exynos5800-peach-pi.dts |   16 ---
 13 files changed, 51 insertions(+), 141 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a..778aec6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -45,17 +45,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
regulator_p3v3 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = okay;
 
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
codec@1340 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts 
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..65ab885 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
mmc@1255 {
num-slots = 1;
-   supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = 200;
@@ -532,11 +531,8 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
serial@1380 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..42a3590 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@1220 {
status = okay;
num-slots = 1;
-   supports-highspeed;
broken-cd;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
@@ -410,17 +409,13 @@
vmmc-supply = mmc_reg;
pinctrl-names = default;
pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
-
-   slot@0 {
-   reg = 0;
-   bus-width = 8;
-   };
+   bus-width = 8;
+   cap-mmc-highspeed;
};
 
mmc_2: mmc@1222 {
status = okay;
num-slots = 1;
-   supports-highspeed;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
samsung,dw-mshc-sdr-timing = 2 3;
@@ -428,12 +423,9 @@
vmmc-supply = mmc_reg;
pinctrl-names = default

[PATCHv3 5/5] mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

2014-07-10 Thread Jaehoon Chung
Replaced the disable-wp into host's quirks.
(Because the slot-node is removed at dt-file.)

Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
 drivers/mmc/host/dw_mmc.c |   12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..a3ccd07 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -997,7 +997,7 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
int gpio_ro = mmc_gpio_get_ro(mmc);
 
/* Use platform get_ro function, else try on board write protect */
-   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
+   if (slot-host-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
read_only = 0;
else if (!IS_ERR_VALUE(gpio_ro))
read_only = gpio_ro;
@@ -2006,12 +2006,7 @@ static struct device_node 
*dw_mci_of_find_slot_node(struct device *dev, u8 slot)
 static struct dw_mci_of_slot_quirks {
char *quirk;
int id;
-} of_slot_quirks[] = {
-   {
-   .quirk  = disable-wp,
-   .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
-   },
-};
+} of_slot_quirks[] = {};
 
 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
 {
@@ -2238,6 +2233,9 @@ static struct dw_mci_of_quirks {
{
.quirk  = broken-cd,
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   },{
+   .quirk  = disable-wp,
+   .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
},
 };
 
-- 
1.7.9.5

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[PATCHv3 0/5] ARM: remove the sub-node and deprecated supports-highspeed property for dwmmc.

2014-07-10 Thread Jaehoon Chung
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a 
host.
And supports-highspeed can be replaced to cap-mmc/sd-highspeed property.

Changelog V3:
- Fix the wrong bus-width value.
- Use the slot-host-quirks instead of brq-quirks.
- Add tested-by and reviewd-by.
Changelog V2:
- Add the mmc: dw_mmc: replace disable-wp from slot's quirks to 
host's quirk

Jaehoon Chung (5):
  mmc: dw_mmc: modify the dt-binding for removing slot-node and
supports-highspeed
  ARM: dts: exynos: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: socfpga: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  ARM: dts: rockchip: unuse the slot-node and deprecated the
supports-highspeed for dw-mmc
  mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   17 -
 .../devicetree/bindings/mmc/k3-dw-mshc.txt |   12 -
 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |   12 -
 arch/arm/boot/dts/exynos4412-odroidx.dts   |8 ++
 arch/arm/boot/dts/exynos4412-origen.dts|8 ++
 arch/arm/boot/dts/exynos4412-trats2.dts|8 ++
 arch/arm/boot/dts/exynos5250-arndale.dts   |   18 --
 arch/arm/boot/dts/exynos5250-cros-common.dtsi  |   26 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   18 --
 arch/arm/boot/dts/exynos5250-snow.dts  |6 ++---
 arch/arm/boot/dts/exynos5260-xyref5260.dts |   18 --
 arch/arm/boot/dts/exynos5410-smdk5410.dts  |   18 --
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |   16 +++-
 arch/arm/boot/dts/exynos5420-peach-pit.dts |   16 +++-
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   16 +++-
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |   16 +++-
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |   16 +++-
 arch/arm/boot/dts/socfpga_arria5.dtsi  |9 +++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi|9 +++
 arch/arm/boot/dts/socfpga_vt.dts   |9 +++
 drivers/mmc/host/dw_mmc.c  |   12 -
 21 files changed, 84 insertions(+), 204 deletions(-)

-- 
1.7.9.5

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Re: [PATCHv3 5/5] mmc: dw_mmc: replace disable-wp from slot's quirk to host's quirk

2014-07-10 Thread Jaehoon Chung
Hi, Ulf.

On 07/10/2014 06:15 PM, Ulf Hansson wrote:
 On 10 July 2014 09:08, Jaehoon Chung jh80.ch...@samsung.com wrote:
 Replaced the disable-wp into host's quirks.
 (Because the slot-node is removed at dt-file.)

 Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
 
 Hi Jaehoon,
 
 I plan to carry these patches through my mmc tree and I will share
 them through a PR from an immutable branch with the ARM SoC guys.
 Please tell me if you have any concern with this set up.
 
 Now, while I was applying this patch, I found it had checkpatch
 errors. Please run checkpatch and resend a new version.

Sorry for not checking the patch. I will resend a new version.
Thanks for pointing out.

Best Regards,
Jaehoon Chung

 
 Kind regards
 Uffe
 
 ---
  drivers/mmc/host/dw_mmc.c |   12 +---
  1 file changed, 5 insertions(+), 7 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
 index 1ac227c..a3ccd07 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -997,7 +997,7 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
 int gpio_ro = mmc_gpio_get_ro(mmc);

 /* Use platform get_ro function, else try on board write protect */
 -   if (slot-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
 +   if (slot-host-quirks  DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
 read_only = 0;
 else if (!IS_ERR_VALUE(gpio_ro))
 read_only = gpio_ro;
 @@ -2006,12 +2006,7 @@ static struct device_node 
 *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
  static struct dw_mci_of_slot_quirks {
 char *quirk;
 int id;
 -} of_slot_quirks[] = {
 -   {
 -   .quirk  = disable-wp,
 -   .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
 -   },
 -};
 +} of_slot_quirks[] = {};

  static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
  {
 @@ -2238,6 +2233,9 @@ static struct dw_mci_of_quirks {
 {
 .quirk  = broken-cd,
 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
 +   },{
 +   .quirk  = disable-wp,
 +   .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
 },
  };

 --
 1.7.9.5

 

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