Re: [PATCH] ARM: exynos: Fix wake-up interrupts for Exynos3250
On 27/04/15 01:53, Kukjin Kim wrote: Krzysztof Kozlowski wrote: 2015-04-23 2:40 GMT+09:00 Marc Zyngier marc.zyng...@arm.com: Commit 8b283c025443 (ARM: exynos4/5: convert pmu wakeup to stacked domains) changed the Exynos PMU code to use stacked domains. This has led to a number of interrupt numbers to be fixed. In the meantime, support for Exynos 3250 was added, missing the required change to this platform. This amounts to revert ace283a04a4a (ARM: EXYNOS: Fix wrong hwirq of RTC interrupt for Exynos3250 SoC), as the initial patch was right, just a bit early... Cc: Chanwoo Choi cw00.c...@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Cc: Krzysztof Kozlowski k.kozlow...@samsung.com Cc: Kukjin Kim kg...@kernel.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-exynos/suspend.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Acked-by: Krzysztof Kozlowski k.kozlow...@samsung.com Thanks and applied. Looks like this fix never made it to mainline. What happened? Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: exynos: Fix wake-up interrupts for Exynos3250
Commit 8b283c025443 (ARM: exynos4/5: convert pmu wakeup to
stacked domains) changed the Exynos PMU code to use stacked
domains. This has led to a number of interrupt numbers to be
fixed.
In the meantime, support for Exynos 3250 was added, missing
the required change to this platform. This amounts to revert
ace283a04a4a (ARM: EXYNOS: Fix wrong hwirq of RTC interrupt
for Exynos3250 SoC), as the initial patch was right, just a
bit early...
Cc: Chanwoo Choi cw00.c...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Kukjin Kim kg...@kernel.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-exynos/suspend.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 3e6aea7..40dce36 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -87,8 +87,8 @@ static unsigned int exynos_pmu_spare3;
static u32 exynos_irqwake_intmask = 0x;
static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
- { 105, BIT(1) }, /* RTC alarm */
- { 106, BIT(2) }, /* RTC tick */
+ { 73, BIT(1) }, /* RTC alarm */
+ { 74, BIT(2) }, /* RTC tick */
{ /* sentinel */ },
};
--
2.1.4
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[PATCH v6 2/2] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b2113..2d6356d 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -29,10 +29,27 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- #interrupt-cells: must be identical to the that of the parent interrupt
+ controller.
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v6 0/2] irqchip: Move Exynos PM to use stacked domains
This series is extracted from [4], which is trying to remove all traces of gic_arch_extn from the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially. This series addresses Exynos by converting its PM support to a stacked domain on top of the standard GIC. Based on 4.0-rc1. * From v5: [5] - Added a big fat warning when an old DT is detected (as requested by Jason) - Added support for Exynos3250 - Allow interrupt affinity to be changed * From v4: [4] - Extracted from the full series - Rebased on 4.0-rc1 * From v3 [3]: - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4] - Fixed more iMX6 DTs (Stephan) - Fixed Exynos4/5 DTs * From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan * From v1 [1]: - Rebased on 3.19-rc3 - Fixed a number of additional platforms - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth [5]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325368.html [4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html [3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html [2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html Marc Zyngier (2): ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding .../devicetree/bindings/arm/samsung/pmu.txt| 17 +++ arch/arm/boot/dts/exynos3250.dtsi | 6 +- arch/arm/boot/dts/exynos4.dtsi | 4 + arch/arm/boot/dts/exynos5250.dtsi | 4 + arch/arm/boot/dts/exynos5420.dtsi | 4 + arch/arm/mach-exynos/exynos.c | 15 +-- arch/arm/mach-exynos/suspend.c | 139 ++--- 7 files changed, 164 insertions(+), 25 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 1/2] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos3250.dtsi | 6 +-
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 15 ++--
arch/arm/mach-exynos/suspend.c| 139 ++
6 files changed, 147 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 277b48b..554e9be 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -130,6 +130,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos3250-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
mipi_phy: video-phy@10020710 {
@@ -183,7 +186,8 @@
rtc: rtc@1007 {
compatible = samsung,exynos3250-rtc;
reg = 0x1007 0x100;
- interrupts = 0 73 0, 0 74 0;
+ interrupts = 0 41 0, 0 42 0;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 76173ca..1d21f02 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -152,6 +152,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -264,6 +267,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 9bb1b0b..72fa2d1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -196,6 +196,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -232,6 +235,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9dc2e97..d11a6ab 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -327,6 +327,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -769,6 +770,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 9e9dfdf..f44c2e0 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -166,16 +166,14 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
- { .compatible
Re: [PATCH v5 0/2] irqchip: Move Exynos PM to use stacked domains
Hi Pakaj, On 24/02/15 10:09, Pankaj Dubey wrote: Hi Mark, On Monday 23 February 2015 11:15 PM, Marc Zyngier wrote: This series is extracted from [4], which is trying to remove all traces of gic_arch_extn from the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially. This series addresses Exynos by converting its PM support to a stacked domain on top of the standard GIC. Based on 4.0-rc1. * From v4: [4] - Extracted from the full series - Rebased on 4.0-rc1 * From v3 [3]: - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4] - Fixed more iMX6 DTs (Stephan) - Fixed Exynos4/5 DTs * From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan * From v1 [1]: - Rebased on 3.19-rc3 - Fixed a number of additional platforms - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth [4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html [3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html [2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html Marc Zyngier (2): ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding .../devicetree/bindings/arm/samsung/pmu.txt| 17 +++ arch/arm/boot/dts/exynos4.dtsi | 4 + arch/arm/boot/dts/exynos5250.dtsi | 4 + arch/arm/boot/dts/exynos5420.dtsi | 4 + arch/arm/mach-exynos/exynos.c | 14 +-- arch/arm/mach-exynos/suspend.c | 122 +++-- 6 files changed, 146 insertions(+), 19 deletions(-) I tested and verified S2R functionality on Exynos5250 based SMDK5250 board, and suspend-resume working fine. For testing on SMDK5250 you can add my tested-by. Tested-by: Pankaj Dubey pankaj.du...@samsung.com Thanks. Will you or Kukjin get that merged directly? M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/2] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 129 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 76173ca..1d21f02 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -152,6 +152,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -264,6 +267,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 9bb1b0b..72fa2d1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -196,6 +196,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -232,6 +235,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9dc2e97..d11a6ab 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -327,6 +327,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -769,6 +770,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 9e9dfdf..c623d39 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -166,16 +166,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -186,9 +185,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 52e2b1a..69ede2c 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
[PATCH v5 2/2] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b2113..2d6356d 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -29,10 +29,27 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- #interrupt-cells: must be identical to the that of the parent interrupt
+ controller.
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v5 0/2] irqchip: Move Exynos PM to use stacked domains
This series is extracted from [4], which is trying to remove all traces of gic_arch_extn from the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially. This series addresses Exynos by converting its PM support to a stacked domain on top of the standard GIC. Based on 4.0-rc1. * From v4: [4] - Extracted from the full series - Rebased on 4.0-rc1 * From v3 [3]: - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4] - Fixed more iMX6 DTs (Stephan) - Fixed Exynos4/5 DTs * From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan * From v1 [1]: - Rebased on 3.19-rc3 - Fixed a number of additional platforms - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth [4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html [3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html [2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html Marc Zyngier (2): ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding .../devicetree/bindings/arm/samsung/pmu.txt| 17 +++ arch/arm/boot/dts/exynos4.dtsi | 4 + arch/arm/boot/dts/exynos5250.dtsi | 4 + arch/arm/boot/dts/exynos5420.dtsi | 4 + arch/arm/mach-exynos/exynos.c | 14 +-- arch/arm/mach-exynos/suspend.c | 122 +++-- 6 files changed, 146 insertions(+), 19 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Hi Pankaj,
On 2015-01-20 07:42, Pankaj Dubey wrote:
Hi Marc,
On Monday 19 January 2015 03:14 PM, Marc Zyngier wrote:
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
I tested this patch series on SMDK5250 board.
With the addition of #interrupt-cells = 3;in PMU device node S2R
is working on Exynos5250 based SMDK board.
Thanks for letting me know. Can I add your Tested-by tag on this?
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122
++
5 files changed, 129 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi
b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..0e7d74e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +256,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..1dc5f6b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +233,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..35ecd36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c
b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend
using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
As I know Exynos3250, S2R support has been added in kgene/for-next
and should work as expected so we may need to do update
exynos_wkup_irq for exynos3250 and remove it from this list, so
that
it's S2R should not break. I am adding concern engineer (+cc: Chanwoo
Choi) in the loop.
That would have to be an additional patch, unless we decide to delay
this series.
Thanks,
M.
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[PATCH v4 01/21] ARM: tegra: irq: nuke leftovers from non-DT support
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Acked-by: Thierry Reding tred...@nvidia.com Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-tegra/irq.c | 8 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ab95f53..7f87a50 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -283,13 +283,5 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_set_wake = tegra_set_wake; gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; - /* -* Check if there is a devicetree present, since the GIC will be -* initialized elsewhere under DT. -*/ - if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - tegra114_gic_cpu_pm_registration(); } -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 05/21] DT: tegra: add binding for the legacy interrupt controller
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/nvidia,tegra-ictlr.txt| 43 ++
1 file changed, 43 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000..1099fe0
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,43 @@
+NVIDIA Legacy Interrupt Controller
+
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+referred to as ictlr, hence the name of the binding.
+
+The HW block exposes a number of interrupt controllers, each
+implementing a set of 32 interrupts.
+
+Required properties:
+
+- compatible : should be: nvidia,tegrachip-ictlr. The LIC on
+ subsequent SoCs remained backwards-compatible with Tegra30, so on
+ Tegra generations later than Tegra30 the compatible value should
+ include nvidia,tegra30-ictlr.
+- reg : Specifies base physical address and size of the registers.
+ Each controller must be described separately (Tegra20 has 4 of them,
+ whereas Tegra30 and later have 5
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+ are explicitly forbidden.
+
+Example:
+
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
--
2.1.4
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[PATCH v4 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.
The stacked IRQ domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-tegra.c | 368
2 files changed, 369 insertions(+)
create mode 100644 drivers/irqchip/irq-tegra.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..e1ac65e
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,368 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR 0x14
+#define ICTLR_CPU_IEP_FIR_SET 0x18
+#define ICTLR_CPU_IEP_FIR_CLR 0x1c
+
+#define ICTLR_CPU_IER 0x20
+#define ICTLR_CPU_IER_SET 0x24
+#define ICTLR_CPU_IER_CLR 0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER 0x30
+#define ICTLR_COP_IER_SET 0x34
+#define ICTLR_COP_IER_CLR 0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS 5
+
+static unsigned int num_ictlrs;
+
+struct tegra_ictlr_soc {
+ unsigned int num_ictlrs;
+};
+
+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
+ .num_ictlrs = 4,
+};
+
+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
+ .num_ictlrs = 5,
+};
+
+static const struct of_device_id ictlr_matches[] = {
+ { .compatible = nvidia,tegra30-ictlr, .data = tegra30_ictlr_soc },
+ { .compatible = nvidia,tegra20-ictlr, .data = tegra20_ictlr_soc },
+ { }
+};
+
+struct tegra_ictlr_info {
+ void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+ u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+ u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *lic;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long
reg)
+{
+ void __iomem *base = d-chip_data;
+ u32 mask;
+
+ mask = BIT(d-hwirq % 32);
+ writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+ irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+ irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+ irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+ return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+ u32 irq = d-hwirq;
+ u32 index, mask;
+
+ index = (irq / 32);
+ mask = BIT(irq % 32);
+ if (enable)
+ lic-ictlr_wake_mask[index] |= mask;
+ else
+ lic-ictlr_wake_mask[index] = ~mask
[PATCH v4 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f58a3d9 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
/ {
compatible = nvidia,tegra114;
- interrupt-parent = gic;
+ interrupt-parent = lic;
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
+ };
+
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra114-ictlr, nvidia,tegra30-ictlr;
+ reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50,
+ 0x60004400 0x50;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..db85695 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
/ {
compatible = nvidia,tegra124;
- interrupt-parent = gic;
+ interrupt-parent = lic;
#address-cells = 2;
#size-cells = 2;
@@ -173,6 +173,7 @@
0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra124-ictlr, nvidia,tegra30-ictlr;
+ reg = 0x0 0x60004000 0x0 0x100,
+ 0x0 0x60004100 0x0 0x100,
+ 0x0 0x60004200 0x0 0x100,
+ 0x0 0x60004300 0x0 0x100,
+ 0x0 0x60004400 0x0 0x100;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
+ };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..362bb21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
/ {
compatible = nvidia,tegra20;
- interrupt-parent = intc;
+ interrupt-parent = lic;
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+ interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+ interrupt-parent = intc;
};
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr;
+ reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..6bea674 100644
[PATCH v4 10/21] irqchip: GIC: get rid of routable domain
The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
}
static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
- gic_routable_irq_domain_ops-unmap(d, irq);
}
static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0]) {
- ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
- if (IS_ERR_VALUE(ret))
- return ret;
- }
+ if (!intspec[0])
+ *out_hwirq += 16;
*out_type = intspec[2] IRQ_TYPE_SENSE_MASK;
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
- return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
- struct device_node *controller,
- const u32 *intspec, unsigned int intsize,
- unsigned long *out_hwirq,
- unsigned int *out_type)
-{
- *out_hwirq += 16;
- return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
- .map = gic_routable_irq_domain_map,
- .unmap = gic_routable_irq_domain_unmap,
- .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
- gic_default_routable_irq_domain_ops;
-
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
- int nr_routable_irqs;
BUG_ON(gic_nr = MAX_GIC_NR);
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic-gic_irqs = gic_irqs;
if (node) { /* DT case */
- const struct irq_domain_ops *ops =
gic_irq_domain_hierarchy_ops;
-
- if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
- ops = gic_irq_domain_ops;
- gic_irqs = nr_routable_irqs;
- }
-
- gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+ gic-domain = irq_domain_add_linear(node, gic_irqs,
+
gic_irq_domain_hierarchy_ops,
+ gic);
} else {/* Non-DT case */
/*
* For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
void gic_migrate_target(unsigned int new_cpu_id);
unsigned long gic_get_sgir_physaddr(void);
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
- (const struct irq_domain_ops *ops)
-{
- gic_routable_irq_domain_ops = ops
[PATCH v4 06/21] ARM: tegra: remove old LIC support
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c | 201 +---
arch/arm/mach-tegra/irq.h | 6 --
3 files changed, 2 insertions(+), 220 deletions(-)
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
#define TEGRA_ARM_INT_DIST_BASE0x50041000
#define TEGRA_ARM_INT_DIST_SIZESZ_4K
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
-
#define TEGRA_TMR1_BASE0x60005000
#define TEGRA_TMR1_SIZESZ_8
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1593c4c..3b9098d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
#include board.h
#include iomap.h
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR 0x14
-#define ICTLR_CPU_IEP_FIR_SET 0x18
-#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-
-#define ICTLR_CPU_IER 0x20
-#define ICTLR_CPU_IER_SET 0x24
-#define ICTLR_CPU_IER_CLR 0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER 0x30
-#define ICTLR_COP_IER_SET 0x34
-#define ICTLR_COP_IER_CLR 0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS 5
-
#define SGI_MASK 0x
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
- IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
#ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
static void __iomem *tegra_gic_cpu_base;
#endif
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
}
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
- void __iomem *base;
- u32 mask;
-
- BUG_ON(irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
- base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
- __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return 0;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
- return 1;
-}
-
#ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
- u32 irq = d-hwirq;
- u32 index, mask;
-
- if (irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
- return -EINVAL;
-
- index = ((irq - FIRST_LEGACY_IRQ) / 32);
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
- if (enable)
- ictlr_wake_mask[index] |= mask;
- else
- ictlr_wake_mask[index] = ~mask;
-
- return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- /* Save interrupt state */
- cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
- cpu_iep[i
[PATCH v4 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have been merged into 3.19, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we're already breaking it for the WUGEN block, we might as well do it again for the crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2, omap4 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3 + the patch posted here [4]. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die I'm still targetting 3.20 for this, but obviously things are getting quite tight. I'd very much like to hear from the maintainers about their views concerning this series. Thanks, M. * From v4 [3]: - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4] - Fixed more iMX6 DTs (Stephan) - Fixed Exynos4/5 DTs * From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan * From v1 [1]: - Rebased on 3.19-rc3 - Fixed a number of additional platforms - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth [4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317286.html [3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html [2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html Marc Zyngier (21): ARM: tegra: irq: nuke leftovers from non-DT support irqchip: tegra: add DT-based support for legacy interrupt controller ARM: tegra: skip gic_arch_extn setup if DT has a LIC node ARM: tegra: update DTs to expose legacy interrupt controller DT: tegra: add binding for the legacy interrupt controller ARM: tegra: remove old LIC support genirq: Add irqchip_set_wake_parent irqchip: crossbar: convert dra7 crossbar to stacked domains DT: update ti,irq-crossbar binding irqchip: GIC: get rid of routable domain DT: arm,gic: kill arm,routable-irqs DT: omap4/5: add binding for the wake-up generator ARM: omap: convert wakeupgen to stacked domains ARM: imx6: convert GPC to stacked domains ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding irqchip: gic: add an entry point to set up irqchip flags ARM: shmobile: remove use
[PATCH v4 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +-
arch/arm/boot/dts/dra7-evm.dts | 2 +-
arch/arm/boot/dts/dra7.dtsi | 35 +++---
arch/arm/boot/dts/dra72-evm.dts | 1 -
arch/arm/boot/dts/dra72x.dtsi | 3 +-
arch/arm/boot/dts/dra74x.dtsi | 5 +-
arch/arm/mach-omap2/omap4-common.c | 4 -
drivers/irqchip/irq-crossbar.c | 207 ++--
include/linux/irqchip/irq-crossbar.h| 11 --
9 files changed, 146 insertions(+), 125 deletions(-)
delete mode 100644 include/linux/irqchip/irq-crossbar.h
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..c2241c2 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
- interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW; /* IRQ_SYS_1N */
pinctrl-names = default;
@@ -358,7 +357,7 @@
uart3 {
status = okay;
- interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x248;
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..6f90673 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
#include skeleton.dtsi
#define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
/ {
#address-cells = 1;
#size-cells = 1;
compatible = ti,dra7xx;
- interrupt-parent = gic;
+ interrupt-parent = crossbar_mpu;
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
- arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
0x48212000 0x1000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
0x4500 0x1000;
- interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
- interrupts-extended = gic GIC_SPI 68
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH
[PATCH v4 07/21] genirq: Add irqchip_set_wake_parent
This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
#endif
/* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
return -ENOSYS;
}
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data: Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+ data = data-parent_data;
+ if (data-chip-irq_set_wake)
+ return data-chip-irq_set_wake(data, on);
+
+ return -ENOSYS;
+}
#endif
/**
--
2.1.4
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[PATCH v4 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
- arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
0xfff10100 0x100;
};
--
2.1.4
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[PATCH v4 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 129 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..0e7d74e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +256,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..1dc5f6b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +233,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..35ecd36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..b325ecd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
[PATCH v4 21/21] irqchip: gic: Drop support for gic_arch_extn
Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 54 -
include/linux/irqchip/arm-gic.h | 2 --
2 files changed, 56 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
#define NR_GIC_CPU_IF 8
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
- .irq_eoi= NULL,
- .irq_mask = NULL,
- .irq_unmask = NULL,
- .irq_retrigger = NULL,
- .irq_set_type = NULL,
- .irq_set_wake = NULL,
-};
-
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1
#endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
(gic_irq(d) / 32) * 4);
- if (gic_arch_extn.irq_mask)
- gic_arch_extn.irq_mask(d);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
- if (gic_arch_extn.irq_unmask)
- gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET +
(gic_irq(d) / 32) * 4);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_eoi_irq(struct irq_data *d)
{
- if (gic_arch_extn.irq_eoi) {
- raw_spin_lock(irq_controller_lock);
- gic_arch_extn.irq_eoi(d);
- raw_spin_unlock(irq_controller_lock);
- }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int
type)
if (type != IRQ_TYPE_LEVEL_HIGH type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
- raw_spin_lock(irq_controller_lock);
-
- if (gic_arch_extn.irq_set_type)
- gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
- raw_spin_unlock(irq_controller_lock);
-
return 0;
}
static int gic_retrigger(struct irq_data *d)
{
- if (gic_arch_extn.irq_retrigger)
- return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
}
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const
struct cpumask *mask_val,
}
#endif
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
- int ret = -ENXIO;
-
- if (gic_arch_extn.irq_set_wake)
- ret = gic_arch_extn.irq_set_wake(d, on);
-
- return ret;
-}
-
-#else
-#define gic_set_wake NULL
-#endif
-
static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
- .irq_set_wake = gic_set_wake,
};
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
set_handle_irq(gic_handle_irq);
}
- gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
struct device_node;
-extern struct irq_chip gic_arch_extn;
-
void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
--
2.1.4
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[PATCH v4 12/21] DT: omap4/5: add binding for the wake-up generator
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+ ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+ are explicitly forbiden.
+
+Example:
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
--
2.1.4
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[PATCH v4 16/21] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v4 17/21] irqchip: gic: add an entry point to set up irqchip flags
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 5 +
include/linux/irqchip/arm-gic.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
+void gic_set_irqchip_flags(unsigned long flags)
+{
+ gic_chip.flags |= flags;
+}
+
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
extern struct irq_chip gic_arch_extn;
+void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
--
2.1.4
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[PATCH v4 09/21] DT: update ti,irq-crossbar binding
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
Required properties:
- compatible : Should be ti,irq-crossbar
- reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt
controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be
routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
- crossbar_mpu: @4a02 {
+ crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
- ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further
details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as
a
-quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
- device_y@0x4a033000 {
- /* Direct mapped GIC SPI 1 used */
- interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
- ...
- };
--
2.1.4
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[PATCH v4 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
static void __init zynq_irq_init(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
}
--
2.1.4
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[PATCH v4 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
*/
void __init ux500_init_irq(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
/*
--
2.1.4
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Re: [PATCH v4 14/21] ARM: imx6: convert GPC to stacked domains
On 19/01/15 10:47, Lucas Stach wrote:
Am Montag, den 19.01.2015, 09:44 + schrieb Marc Zyngier:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 ++-
arch/arm/boot/dts/imx6sl.dtsi | 6 +-
arch/arm/boot/dts/imx6sx.dtsi | 6 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 119 insertions(+), 31 deletions(-)
[...]
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -102,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
-void imx_gpc_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 5f3602e..838da3c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -22,6 +22,7 @@
#define GPC_PGC_CPU_PDN 0x2a0
#define IMR_NUM 4
+#define GPC_MAX_IRQS(IMR_NUM * 32)
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
@@ -56,17 +57,17 @@ void imx_gpc_post_resume(void)
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
-unsigned int idx = d-hwirq / 32 - 1;
+unsigned int idx = d-hwirq / 32;
u32 mask;
-/* Sanity check for SPI irq */
-if (d-hwirq 32)
-return -EINVAL;
-
mask = 1 d-hwirq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] ~mask;
+/*
+ * Do *not* call into the parent, as the GIC doesn't have any
+ * wake-up facility...
+ */
return 0;
}
@@ -96,7 +97,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
void __iomem *reg;
u32 val;
-reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val = ~(1 hwirq % 32);
writel_relaxed(val, reg);
@@ -107,7 +108,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
void __iomem *reg;
u32 val;
-reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val |= 1 (hwirq % 32);
writel_relaxed(val, reg);
@@ -115,37 +116,115 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
static void imx_gpc_irq_unmask(struct irq_data *d)
{
-/* Sanity check for SPI irq */
-if (d-hwirq 32)
-return;
-
imx_gpc_hwirq_unmask(d-hwirq);
+irq_chip_unmask_parent(d);
}
static void imx_gpc_irq_mask(struct irq_data *d)
{
-/* Sanity check for SPI irq */
-if (d-hwirq 32)
-return;
-
imx_gpc_hwirq_mask(d-hwirq);
+irq_chip_mask_parent(d);
+}
+
+static struct irq_chip imx_gpc_chip = {
+.name = GPC,
+.irq_eoi= irq_chip_eoi_parent,
+.irq_mask = imx_gpc_irq_mask,
+.irq_unmask = imx_gpc_irq_unmask,
+.irq_retrigger = irq_chip_retrigger_hierarchy,
+.irq_set_wake = imx_gpc_irq_set_wake,
+};
+
+static int imx_gpc_domain_xlate(struct irq_domain *domain,
+struct device_node *controller,
+const u32 *intspec,
+unsigned int intsize,
+unsigned long *out_hwirq,
+unsigned int *out_type)
+{
+if (domain-of_node != controller)
+return -EINVAL; /* Shouldn't happen, really... */
+if (intsize != 3)
+return -EINVAL; /* Not GIC compliant */
+if (intspec[0] != 0)
+return -EINVAL; /* No PPI should point to this domain */
+
+*out_hwirq = intspec[1];
+*out_type = intspec[2];
+return 0;
+}
+
+static int imx_gpc_domain_alloc(struct irq_domain *domain,
+ unsigned int irq,
+ unsigned int nr_irqs, void *data)
+{
+struct of_phandle_args *args = data;
+struct of_phandle_args parent_args
Re: [v3,15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Hi Pankaj, On 15/01/15 06:41, Pankaj Dubey wrote: +CC: Thomas Abraham thomas...@samsung.com Hi Mark, On Monday 12 January 2015 11:56 PM, Marc Zyngier wrote: Exynos has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the PMU block is actually the first interrupt controller in the chain for RTC, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs may not even boot. Also, I stronly suspect that there is more than two wake-up interrupts on these platforms, but I leave it to the maintainers to fix their mess. Signed-off-by: Marc Zyngier marc.zyng...@arm.com I tested this series on Exynos5250, using kgene/for-next and linux-next/next-20150114, but S2R failed on Exynos5250 based SMDK board. Following is the log I got on SMDK5250 board, (note I have added some debugging log to know what is happening) I can see is S3C-RTC's enable_irq_wake is failing with error -6. I also observed that even though we are adding pmu_domain_ops using irq_domain_add_hierarchy, but none of pmu_domain_ops are getting called. Please let me know if I am missing anything or do I need to modify anything to test S2R on Exynos SoC. Thanks for giving it a go. One think I noticed is that I forgot to add a #interrupt-cells = 3; to the pmu_system_controller node. Also, it would be interesting to know what is the hwirq associated with the irq_desc you've printed below. Thanks, M. - echo +10 /sys/class/rtc/rtc1/wakealarm; sleep 1; echo mem /sys/power/sta te [ 257.428163] PM: Syncing filesystems ... done. [ 257.431786] Freezing user space processes ... (elapsed 0.003 seconds) done. [ 257.439680] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 257.544451] wake enabled for irq 116 [ 257.546916] CPU: 0 PID: 1311 Comm: ash Not tainted 3.19.0-rc4-next-20150114-00023-g492ff37 #15 [ 257.555141] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 257.561231] [c0014430] (unwind_backtrace) from [c0011594] (show_stack+0x10/0x14) [ 257.568948] [c0011594] (show_stack) from [c0418b00] (dump_stack+0x84/0xc4) [ 257.576151] [c0418b00] (dump_stack) from [c005ce30] (set_irq_wake_real+0x58/0x8c) [ 257.583961] [c005ce30] (set_irq_wake_real) from [c005cef0] (irq_set_irq_wake+0x8c/0xf0) [ 257.592295] [c005cef0] (irq_set_irq_wake) from [c02e9d94] (s3c_rtc_suspend+0xb8/0xdc) [ 257.600456] [c02e9d94] (s3c_rtc_suspend) from [c0298c80] (dpm_run_callback.isra.13+0x1c/0x60) [ 257.609308] [c0298c80] (dpm_run_callback.isra.13) from [c02996a0] (__device_suspend+0x128/0x2d0) [ 257.618422] [c02996a0] (__device_suspend) from [c029a850] (dpm_suspend+0x64/0x22c) [ 257.626320] [c029a850] (dpm_suspend) from [c0058488] (suspend_devices_and_enter+0x88/0x3dc) [ 257.634999] [c0058488] (suspend_devices_and_enter) from [c00589c8] (pm_suspend+0x1ec/0x24c) [ 257.643680] [c00589c8] (pm_suspend) from [c00576e0] (state_store+0x68/0xb8) [ 257.650972] [c00576e0] (state_store) from [c012835c] (kernfs_fop_write+0xb8/0x19c) [ 257.658870] [c012835c] (kernfs_fop_write) from [c00cf620] (vfs_write+0xa0/0x1ac) [ 257.666595] [c00cf620] (vfs_write) from [c00cfc78] (SyS_write+0x44/0x9c) [ 257.673625] [c00cfc78] (SyS_write) from [c000e6e0] (ret_fast_syscall+0x0/0x30) [ 257.681176] genirq: PKD: irq_desc-name: (null): irq: 60 [ 257.686469] genirq: PKD: set_irq_wake_real: ret: -6 [ 257.691349] s3c-rtc 101e.rtc: enable_irq_wake failed: -6 [ 257.708926] PM: suspend of devices complete after 260.482 msecs [ 257.713362] BUCK9: No configuration [ 257.716840] BUCK8: No configuration [ 257.720309] BUCK7: No configuration [ 257.723776] BUCK6: No configuration [ 257.727254] P1.8V_BUCK_OUT5: No configuration [ 257.731597] LDO26: No configuration [ 257.735066] LDO25: No configuration [ 257.738532] LDO24: No configuration [ 257.742009] LDO23: No configuration [ 257.745481] LDO22: No configuration [ 257.748954] LDO21: No configuration [ 257.752419] LDO20: No configuration [ 257.755897] LDO19: No configuration [ 257.759370] LDO18: No configuration [ 257.762835] LDO17: No configuration [ 257.766314] P1.8V_LDO_OUT16: No configuration [ 257.770653] P1.0V_LDO_OUT15: No configuration [ 257.774994] P1.8V_LDO_OUT14: No configuration [ 257.779334] P1.8V_LDO_OUT13: No configuration [ 257.783668] P3.0V_LDO_OUT12: No configuration [ 257.788013] P1.8V_LDO_OUT11: No configuration [ 257.792353] P1.8V_LDO_OUT10: No configuration [ 257.796693] LDO9: No configuration [ 257.800079] P1.0V_LDO_OUT8: No configuration [ 257.804332] P1.1V_LDO_OUT7
Re: [PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains
On Thu, Jan 15 2015 at 2:40:16 pm GMT, Nishanth Menon n...@ti.com wrote: On 14:28-20150115, Marc Zyngier wrote: Assuming the workaround I posted earlier works, the OMAP/DRA7 part of this series is going to require some rework too (I need to know where these legacy interrupts are attached: crossbar, WUGEN, or GIC?). crossbar will never work with legacy static interrupts anyways - since there was never a static interrupt possible - I believe we had removed all the legacy hardcoded interrupt definitions for DRA7. ideally, they should all be dt only now. Yes, I guessed as much after looking at the DRA7XX hwmod. So only OMAP4/5 is b0rken at the moment. I can probably work around it as I did in this example patch, just by changing the compatible strings for the xlate callback. Very ugly. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains
On Wed, Jan 14 2015 at 10:28:14 pm GMT, Tony Lindgren t...@atomide.com wrote: * Marc Zyngier marc.zyng...@arm.com [150112 10:30]: OMAP4/5 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the WUGEN HW block, kernels with this patch applied won't have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. On a platform with this patch applied, the system looks like this: root@bacon-fat:~# cat /proc/interrupts CPU0 CPU1 16: 0 0 WUGEN 37 gp_timer 19: 233799 155916 GIC 27 arch_timer 23: 0 0 WUGEN 9 l3-dbg-irq 24: 1 0 WUGEN 10 l3-app-irq 27:282 0 WUGEN 13 omap-dma-engine 44: 0 0 4ae1.gpio 13 DMA FYI, the legacy irq numbers are now all wrong since commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain.). Started a separate thread Regression with legacy IRQ numbers caused by 9a1091ef0017 on it, will give these a try once that's sorted out. Assuming the workaround I posted earlier works, the OMAP/DRA7 part of this series is going to require some rework too (I need to know where these legacy interrupts are attached: crossbar, WUGEN, or GIC?). Thanks, M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains
On 13/01/15 06:09, Linus Walleij wrote: Hi Linus, On Mon, Jan 12, 2015 at 7:26 PM, Marc Zyngier marc.zyng...@arm.com wrote: IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: Stefan Agner ste...@agner.ch Acked-by: Stefan Agner ste...@agner.ch Signed-off-by: Marc Zyngier marc.zyng...@arm.com (...) +static int imx_gpc_domain_alloc(struct irq_domain *domain, + unsigned int virq, Nutcase nitpick on this nice patch series: every time I see virq my OCD triggers, as I think the v in virq stand for virtual. These irqs are no more virtual than any other Linux irq numbers, hwirq is more to the point. I just refer to these as irq (sans v) in any code I write. That's fair enough. I'll update that as I fix some other nits. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains
On 12/01/15 19:00, Stefan Agner wrote:
Hi Marc,
On 2015-01-12 19:26, Marc Zyngier wrote:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 ++-
arch/arm/boot/dts/imx6sl.dtsi | 5 +-
arch/arm/boot/dts/imx6sx.dtsi | 5 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 117 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..aff9ded 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+ interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
@@ -694,8 +696,11 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
GPC is in three base device trees, and missing in all of them. So the
first is fixed
this one...
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..c476e67 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -131,7 +132,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
pmu {
@@ -700,7 +701,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
... and this one is still missing.
Sorry I did not see that the first review.
I thought I had them fixed on Sunday, but it looks like I've dropped the
fixup
Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
On 12/01/15 14:14, Rob Herring wrote: On Wed, Jan 7, 2015 at 11:42 AM, Marc Zyngier marc.zyng...@arm.com wrote: The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have landed in -next, the time has come for gic_arch_extn to meet the Big Bit Bucket. [...] - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... Just to be clear, you need some agreement from the maintainers of those platforms before doing this. It doesn't appear there is disagreement, but I don't see any explicit agreement either. I'm not trying to go behind anyone's back, if that's your concern. I fully intend to obtain every maintainer's explicit acknowledgement before removing any feature from the kernel. The warning above is there to get the maintainers attention on the disrupting effect of this series. This seems to model the interrupts as chained, but at least for some cases aren't these auxiliary controllers in parallel to the GIC? In From looking at the various TRMs, they all look to be chained interrupt controllers (at least Tegra, OMAP and IMX6 show this). I have not been able to find a publicly available TRM for any of the Samsung platforms, so this one could be different (but I really doubt it somehow). other words, do the they require configuration for interrupts to work for the normal non-wakeup use? I'm not sure that the h/w is being modeled any more accurately if that is the case. However, we don't really have a way to describe an interrupt line is connected to 2 interrupt parents in DT, so I'm not sure what else you could do here. The main problem is that they are not general-purpose interrupt controllers. They all come first on the interrupt path, and somehow feed two signals into the GIC: the actual interrupt, and the bypass signal. None of that is representable in DT. I'm willing to take any idea though. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
- arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
0xfff10100 0x100;
};
--
2.1.4
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[PATCH v3 07/21] genirq: Add irqchip_set_wake_parent
This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
#endif
/* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
return -ENOSYS;
}
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data: Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+ data = data-parent_data;
+ if (data-chip-irq_set_wake)
+ return data-chip-irq_set_wake(data, on);
+
+ return -ENOSYS;
+}
#endif
/**
--
2.1.4
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[PATCH v3 12/21] DT: omap4/5: add binding for the wake-up generator
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+ ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+ are explicitly forbiden.
+
+Example:
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
--
2.1.4
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[PATCH v3 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f58a3d9 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
/ {
compatible = nvidia,tegra114;
- interrupt-parent = gic;
+ interrupt-parent = lic;
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
+ };
+
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra114-ictlr, nvidia,tegra30-ictlr;
+ reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50,
+ 0x60004400 0x50;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..db85695 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
/ {
compatible = nvidia,tegra124;
- interrupt-parent = gic;
+ interrupt-parent = lic;
#address-cells = 2;
#size-cells = 2;
@@ -173,6 +173,7 @@
0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra124-ictlr, nvidia,tegra30-ictlr;
+ reg = 0x0 0x60004000 0x0 0x100,
+ 0x0 0x60004100 0x0 0x100,
+ 0x0 0x60004200 0x0 0x100,
+ 0x0 0x60004300 0x0 0x100,
+ 0x0 0x60004400 0x0 0x100;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
+ };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..362bb21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
/ {
compatible = nvidia,tegra20;
- interrupt-parent = intc;
+ interrupt-parent = lic;
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+ interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+ interrupt-parent = intc;
};
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr;
+ reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..6bea674 100644
[PATCH v3 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have been merged into 3.19, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we're already breaking it for the WUGEN block, we might as well do it again for the crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die I'm still targetting 3.20 for this, but obviously things are getting quite tight. I'd very much like to hear from the maintainers about their views concerning this series. Thanks, M. From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan From v1 [1]: - Rebased on 3.19-rc3 - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth Marc Zyngier (21): ARM: tegra: irq: nuke leftovers from non-DT support irqchip: tegra: add DT-based support for legacy interrupt controller ARM: tegra: skip gic_arch_extn setup if DT has a LIC node ARM: tegra: update DTs to expose legacy interrupt controller DT: tegra: add binding for the legacy interrupt controller ARM: tegra: remove old LIC support genirq: Add irqchip_set_wake_parent irqchip: crossbar: convert dra7 crossbar to stacked domains DT: update ti,irq-crossbar binding irqchip: GIC: get rid of routable domain DT: arm,gic: kill arm,routable-irqs DT: omap4/5: add binding for the wake-up generator ARM: omap: convert wakeupgen to stacked domains ARM: imx6: convert GPC to stacked domains ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding irqchip: gic: add an entry point to set up irqchip flags ARM: shmobile: remove use of gic_arch_extn.irq_set_wake ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags irqchip: gic: Drop support for gic_arch_extn Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../devicetree/bindings/arm/samsung/pmu.txt| 13 + .../interrupt-controller/nvidia,tegra-ictlr.txt| 43 +++ .../interrupt-controller/ti,omap4-wugen-mpu| 33 ++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm
[PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like
this:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer
19: 233799 155916 GIC 27 arch_timer
23: 0 0 WUGEN 9 l3-dbg-irq
24: 1 0 WUGEN 10 l3-app-irq
27:282 0 WUGEN 13 omap-dma-engine
44: 0 0 4ae1.gpio 13 DMA
294: 0 0 WUGEN 20 gpmc
297:506 0 WUGEN 56 4807.i2c
298: 0 0 WUGEN 57 48072000.i2c
299: 0 0 WUGEN 61 4806.i2c
300: 0 0 WUGEN 62 4807a000.i2c
301: 8 0 WUGEN 60 4807c000.i2c
308: 2439 0 WUGEN 74 OMAP UART2
312:362 0 WUGEN 83 mmc2
313:502 0 WUGEN 86 mmc0
314: 13 0 WUGEN 94 mmc1
350: 0 0 PRCM pinctrl, pinctrl
406: 35155709 0 GIC 109 ehci_hcd:usb1
407: 0 0 WUGEN 7 palmas
409: 0 0 WUGEN 119 twl6040
410: 0 0 twl6040 5 twl6040_irq_ready
411: 0 0 twl6040 0 twl6040_irq_th
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 95334 902334 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4:479648 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am4372.dtsi | 11 ++-
arch/arm/boot/dts/am437x-gp-evm.dts | 1 -
arch/arm/boot/dts/am437x-sk-evm.dts | 1 -
arch/arm/boot/dts/am43x-epos-evm.dts | 1 -
arch/arm/boot/dts/dra7.dtsi | 12 ++-
arch/arm/boot/dts/dra72x.dtsi | 2 +-
arch/arm/boot/dts/dra74x.dtsi | 2 +-
arch/arm/boot/dts/omap4-duovero.dtsi | 2 -
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +-
arch/arm/boot/dts/omap4-sdp.dts | 8 +-
arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 -
arch/arm/boot/dts/omap4.dtsi | 18 -
arch/arm/boot/dts/omap5-cm-t54.dts| 1 -
arch/arm/boot/dts/omap5-uevm.dts | 2 -
arch/arm/boot/dts/omap5.dtsi | 26 ---
arch/arm/mach-omap2/omap-wakeupgen.c | 125 +++---
arch/arm/mach-omap2/omap-wakeupgen.h | 1 -
arch/arm/mach-omap2/omap4-common.c| 1 -
18 files changed, 154 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd..9d672a7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
/ {
compatible = ti,am4372, ti,am43;
- interrupt-parent = gic;
+ interrupt-parent = wakeupgen;
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
0x48240100 0x0100;
+ interrupt-parent = gic;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
};
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4c..69f2313 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
- interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc9..029bade 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
- interrupt-parent = gic;
interrupts = GIC_SPI 7
[PATCH v3 16/21] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v3 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 3 +
arch/arm/boot/dts/exynos5250.dtsi | 3 +
arch/arm/boot/dts/exynos5420.dtsi | 3 +
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 126 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..adc189f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,8 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +255,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..c31007c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +232,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..1946c76c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..b325ecd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
-#include linux/irqchip/arm-gic.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
[PATCH v3 09/21] DT: update ti,irq-crossbar binding
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
Required properties:
- compatible : Should be ti,irq-crossbar
- reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt
controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be
routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
- crossbar_mpu: @4a02 {
+ crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
- ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further
details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as
a
-quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
- device_y@0x4a033000 {
- /* Direct mapped GIC SPI 1 used */
- interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
- ...
- };
--
2.1.4
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[PATCH v3 06/21] ARM: tegra: remove old LIC support
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c | 201 +---
arch/arm/mach-tegra/irq.h | 6 --
3 files changed, 2 insertions(+), 220 deletions(-)
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
#define TEGRA_ARM_INT_DIST_BASE0x50041000
#define TEGRA_ARM_INT_DIST_SIZESZ_4K
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
-
#define TEGRA_TMR1_BASE0x60005000
#define TEGRA_TMR1_SIZESZ_8
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1593c4c..3b9098d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
#include board.h
#include iomap.h
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR 0x14
-#define ICTLR_CPU_IEP_FIR_SET 0x18
-#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-
-#define ICTLR_CPU_IER 0x20
-#define ICTLR_CPU_IER_SET 0x24
-#define ICTLR_CPU_IER_CLR 0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER 0x30
-#define ICTLR_COP_IER_SET 0x34
-#define ICTLR_COP_IER_CLR 0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS 5
-
#define SGI_MASK 0x
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
- IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
#ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
static void __iomem *tegra_gic_cpu_base;
#endif
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
}
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
- void __iomem *base;
- u32 mask;
-
- BUG_ON(irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
- base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
- __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return 0;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
- return 1;
-}
-
#ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
- u32 irq = d-hwirq;
- u32 index, mask;
-
- if (irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
- return -EINVAL;
-
- index = ((irq - FIRST_LEGACY_IRQ) / 32);
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
- if (enable)
- ictlr_wake_mask[index] |= mask;
- else
- ictlr_wake_mask[index] = ~mask;
-
- return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- /* Save interrupt state */
- cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
- cpu_iep[i
[PATCH v3 01/21] ARM: tegra: irq: nuke leftovers from non-DT support
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Acked-by: Thierry Reding tred...@nvidia.com Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-tegra/irq.c | 8 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ab95f53..7f87a50 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -283,13 +283,5 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_set_wake = tegra_set_wake; gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; - /* -* Check if there is a devicetree present, since the GIC will be -* initialized elsewhere under DT. -*/ - if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - tegra114_gic_cpu_pm_registration(); } -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node
If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.
This is only a temporary measure until that code is removed for good.
Acked-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/irq.c | 12
arch/arm/mach-tegra/tegra.c | 1 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7f87a50..1593c4c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -255,11 +255,22 @@ static void tegra114_gic_cpu_pm_registration(void)
static void tegra114_gic_cpu_pm_registration(void) { }
#endif
+static const struct of_device_id tegra_ictlr_match[] __initconst = {
+ { .compatible = nvidia,tegra20-ictlr },
+ { .compatible = nvidia,tegra30-ictlr },
+ { }
+};
+
void __init tegra_init_irq(void)
{
int i;
void __iomem *distbase;
+ if (of_find_matching_node(NULL, tegra_ictlr_match))
+ goto skip_extn_setup;
+
+ tegra_legacy_irq_syscore_init();
+
distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f;
@@ -283,5 +294,6 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+skip_extn_setup:
tegra114_gic_cpu_pm_registration();
}
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af..c33fba7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -82,7 +82,6 @@ static void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
irqchip_init();
- tegra_legacy_irq_syscore_init();
}
static void __init tegra_dt_init(void)
--
2.1.4
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[PATCH v3 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
*/
void __init ux500_init_irq(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
/*
--
2.1.4
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[PATCH v3 10/21] irqchip: GIC: get rid of routable domain
The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
}
static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
- gic_routable_irq_domain_ops-unmap(d, irq);
}
static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0]) {
- ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
- if (IS_ERR_VALUE(ret))
- return ret;
- }
+ if (!intspec[0])
+ *out_hwirq += 16;
*out_type = intspec[2] IRQ_TYPE_SENSE_MASK;
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
- return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
- struct device_node *controller,
- const u32 *intspec, unsigned int intsize,
- unsigned long *out_hwirq,
- unsigned int *out_type)
-{
- *out_hwirq += 16;
- return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
- .map = gic_routable_irq_domain_map,
- .unmap = gic_routable_irq_domain_unmap,
- .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
- gic_default_routable_irq_domain_ops;
-
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
- int nr_routable_irqs;
BUG_ON(gic_nr = MAX_GIC_NR);
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic-gic_irqs = gic_irqs;
if (node) { /* DT case */
- const struct irq_domain_ops *ops =
gic_irq_domain_hierarchy_ops;
-
- if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
- ops = gic_irq_domain_ops;
- gic_irqs = nr_routable_irqs;
- }
-
- gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+ gic-domain = irq_domain_add_linear(node, gic_irqs,
+
gic_irq_domain_hierarchy_ops,
+ gic);
} else {/* Non-DT case */
/*
* For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
void gic_migrate_target(unsigned int new_cpu_id);
unsigned long gic_get_sgir_physaddr(void);
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
- (const struct irq_domain_ops *ops)
-{
- gic_routable_irq_domain_ops = ops
[PATCH v3 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +-
arch/arm/boot/dts/dra7-evm.dts | 2 +-
arch/arm/boot/dts/dra7.dtsi | 35 +++---
arch/arm/boot/dts/dra72-evm.dts | 1 -
arch/arm/boot/dts/dra72x.dtsi | 3 +-
arch/arm/boot/dts/dra74x.dtsi | 5 +-
arch/arm/mach-omap2/omap4-common.c | 4 -
drivers/irqchip/irq-crossbar.c | 207 ++--
include/linux/irqchip/irq-crossbar.h| 11 --
9 files changed, 146 insertions(+), 125 deletions(-)
delete mode 100644 include/linux/irqchip/irq-crossbar.h
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..c2241c2 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
- interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW; /* IRQ_SYS_1N */
pinctrl-names = default;
@@ -358,7 +357,7 @@
uart3 {
status = okay;
- interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x248;
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..6f90673 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
#include skeleton.dtsi
#define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
/ {
#address-cells = 1;
#size-cells = 1;
compatible = ti,dra7xx;
- interrupt-parent = gic;
+ interrupt-parent = crossbar_mpu;
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
- arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
0x48212000 0x1000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
0x4500 0x1000;
- interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
- interrupts-extended = gic GIC_SPI 68
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH
[PATCH v3 18/21] ARM: shmobile: remove use of gic_arch_extn.irq_set_wake
shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.
It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags function.
Acked-by: Simon Horman horms+rene...@verge.net.au
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-shmobile/intc-sh73a0.c | 7 +--
arch/arm/mach-shmobile/setup-r8a7779.c | 7 +--
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c
b/arch/arm/mach-shmobile/intc-sh73a0.c
index 9e36180..fd63ae6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,11 +252,6 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
-{
- return 0; /* always allow wakeup */
-}
-
#define PINTER0_PHYS 0xe69000a0
#define PINTER1_PHYS 0xe69000a4
#define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -318,8 +313,8 @@ void __init sh73a0_init_irq(void)
void __iomem *gic_cpu_base = IOMEM(0xf100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
- gic_arch_extn.irq_set_wake = sh73a0_set_wake;
register_intc_controller(intcs_desc);
register_intc_controller(intc_pint0_desc);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c
b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d17..989de2d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -713,14 +713,9 @@ void __init r8a7779_init_late(void)
}
#ifdef CONFIG_USE_OF
-static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
-{
- return 0; /* always allow wakeup */
-}
-
void __init r8a7779_init_irq_dt(void)
{
- gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
irqchip_init();
--
2.1.4
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[PATCH v3 05/21] DT: tegra: add binding for the legacy interrupt controller
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/nvidia,tegra-ictlr.txt| 43 ++
1 file changed, 43 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000..1099fe0
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,43 @@
+NVIDIA Legacy Interrupt Controller
+
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+referred to as ictlr, hence the name of the binding.
+
+The HW block exposes a number of interrupt controllers, each
+implementing a set of 32 interrupts.
+
+Required properties:
+
+- compatible : should be: nvidia,tegrachip-ictlr. The LIC on
+ subsequent SoCs remained backwards-compatible with Tegra30, so on
+ Tegra generations later than Tegra30 the compatible value should
+ include nvidia,tegra30-ictlr.
+- reg : Specifies base physical address and size of the registers.
+ Each controller must be described separately (Tegra20 has 4 of them,
+ whereas Tegra30 and later have 5
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+ are explicitly forbidden.
+
+Example:
+
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
--
2.1.4
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[PATCH v3 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.
The stacked IRQ domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-tegra.c | 368
2 files changed, 369 insertions(+)
create mode 100644 drivers/irqchip/irq-tegra.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..e1ac65e
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,368 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR 0x14
+#define ICTLR_CPU_IEP_FIR_SET 0x18
+#define ICTLR_CPU_IEP_FIR_CLR 0x1c
+
+#define ICTLR_CPU_IER 0x20
+#define ICTLR_CPU_IER_SET 0x24
+#define ICTLR_CPU_IER_CLR 0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER 0x30
+#define ICTLR_COP_IER_SET 0x34
+#define ICTLR_COP_IER_CLR 0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS 5
+
+static unsigned int num_ictlrs;
+
+struct tegra_ictlr_soc {
+ unsigned int num_ictlrs;
+};
+
+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
+ .num_ictlrs = 4,
+};
+
+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
+ .num_ictlrs = 5,
+};
+
+static const struct of_device_id ictlr_matches[] = {
+ { .compatible = nvidia,tegra30-ictlr, .data = tegra30_ictlr_soc },
+ { .compatible = nvidia,tegra20-ictlr, .data = tegra20_ictlr_soc },
+ { }
+};
+
+struct tegra_ictlr_info {
+ void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+ u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+ u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *lic;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long
reg)
+{
+ void __iomem *base = d-chip_data;
+ u32 mask;
+
+ mask = BIT(d-hwirq % 32);
+ writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+ irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+ irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+ irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+ return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+ u32 irq = d-hwirq;
+ u32 index, mask;
+
+ index = (irq / 32);
+ mask = BIT(irq % 32);
+ if (enable)
+ lic-ictlr_wake_mask[index] |= mask;
+ else
+ lic-ictlr_wake_mask[index] = ~mask
[PATCH v3 17/21] irqchip: gic: add an entry point to set up irqchip flags
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 5 +
include/linux/irqchip/arm-gic.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
+void gic_set_irqchip_flags(unsigned long flags)
+{
+ gic_chip.flags |= flags;
+}
+
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
extern struct irq_chip gic_arch_extn;
+void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
--
2.1.4
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[PATCH v3 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
static void __init zynq_irq_init(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
}
--
2.1.4
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[PATCH v3 21/21] irqchip: gic: Drop support for gic_arch_extn
Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 54 -
include/linux/irqchip/arm-gic.h | 2 --
2 files changed, 56 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
#define NR_GIC_CPU_IF 8
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
- .irq_eoi= NULL,
- .irq_mask = NULL,
- .irq_unmask = NULL,
- .irq_retrigger = NULL,
- .irq_set_type = NULL,
- .irq_set_wake = NULL,
-};
-
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1
#endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
(gic_irq(d) / 32) * 4);
- if (gic_arch_extn.irq_mask)
- gic_arch_extn.irq_mask(d);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
- if (gic_arch_extn.irq_unmask)
- gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET +
(gic_irq(d) / 32) * 4);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_eoi_irq(struct irq_data *d)
{
- if (gic_arch_extn.irq_eoi) {
- raw_spin_lock(irq_controller_lock);
- gic_arch_extn.irq_eoi(d);
- raw_spin_unlock(irq_controller_lock);
- }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int
type)
if (type != IRQ_TYPE_LEVEL_HIGH type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
- raw_spin_lock(irq_controller_lock);
-
- if (gic_arch_extn.irq_set_type)
- gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
- raw_spin_unlock(irq_controller_lock);
-
return 0;
}
static int gic_retrigger(struct irq_data *d)
{
- if (gic_arch_extn.irq_retrigger)
- return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
}
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const
struct cpumask *mask_val,
}
#endif
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
- int ret = -ENXIO;
-
- if (gic_arch_extn.irq_set_wake)
- ret = gic_arch_extn.irq_set_wake(d, on);
-
- return ret;
-}
-
-#else
-#define gic_set_wake NULL
-#endif
-
static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
- .irq_set_wake = gic_set_wake,
};
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
set_handle_irq(gic_handle_irq);
}
- gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
struct device_node;
-extern struct irq_chip gic_arch_extn;
-
void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
--
2.1.4
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Re: [PATCH v2 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
On 2015-01-08 10:41, Thierry Reding wrote:
On Wed, Jan 07, 2015 at 05:42:39PM +, Marc Zyngier wrote:
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
I've updated the patch to reflect the requested changes. See below for
the few contentious points:
[...]
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
Is this allowed? It makes the GIC its own parent. I guess we need it
to
stop a loop from GIC - LIC - GIC, but it doesn't look quite right.
This seems to be the expected construct to override a parent interrupt
controller. Actually, this is already what happens when you have a
single interrupt-controller and a global interrupt-parent property.
[...]
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
Why does this get to have a non-default parent?
The per-cpu timers are using PPIs. As such,. they are not routed
through the LIC, but are wired to the GIC instead.
[...]
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
Why doesn't the Tegra timer get to keep the GIC as parent like for
Tegra114 and Tegra124? Instead I see that the Cortex-A9 TWD timer
gets
to keep the parent instead.
The Tegra timer is using SPI (and can probably be used as a wake-up
source). As such, it is connected to the LIC, not to the GIC.
Per-CPU timers (arch timer for A15 and TWD for A9) are all using PPIs,
and are directly wired to the GIC.
[...]
timer@60005000 {
compatible = nvidia,tegra30-timer, nvidia,tegra20-timer;
reg = 0x60005000 0x400;
Like for Tegra20, the Tegra timer is now switched to the LIC as
parent.
Which, in my understanding, is the right thing to do. Unless I missed
something obvious about this?
Thanks,
M.
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Re: [PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
On 2015-01-08 14:39, Nishanth Menon wrote:
On 17:42-20150107, Marc Zyngier wrote:
[..]
diff --git a/arch/arm/boot/dts/dra7-evm.dts
b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
^^ interrrupt-extended for uart1 here
[..]
diff --git a/arch/arm/boot/dts/dra7.dtsi
b/arch/arm/boot/dts/dra7.dtsi
[...]
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
^^ implies we will have both interrupts and interrupts-extended
properties for uart1 in dra7-evm.dtb
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
does not make it clear as to what the priority will be when both
properties are present.
Yup, good call. I don't think it matters (interrupts inherits the
implicit irq-parent, but consistency is good.
[...]
Also, for 3.19-rc3, Missing the following causing x15 to fail boot.
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c2241c2e5d9d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
- interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW; /* IRQ_SYS_1N */
pinctrl-names = default;
@@ -358,7 +357,7 @@
uart3 {
status = okay;
- interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 69
IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x248;
pinctrl-names = default;
Ah, thanks for the patch, I've folded this in.
Thanks,
M.
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Re: [PATCH v2 07/21] genirq: Add irqchip_set_wake_parent
On 2015-01-08 15:15, Nishanth Menon wrote: On 17:42-20150107, Marc Zyngier wrote: This proves to be usefull with stacked domains, when the current ^^ useful ? minor: +WARNING: 'usefull' may be misspelled - perhaps 'useful'? +#6: +This proves to be usefull with stacked domains, when the current +CHECK: extern prototypes should be avoided in .h files +#23: FILE: include/linux/irq.h:463: ++extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); Consistency trumps whatever checkpatch says, I'm afraid. Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
On 2015-01-08 15:06, Nishanth Menon wrote: On 17:42-20150107, Marc Zyngier wrote: Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked irq domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- Saw a few checkpatch warnings as below: all of them seem minors. @@ -0,0 +1,35 @@ +WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? I'll leave to the Tegra maintainers to update this file it they want to. +#36: +new file mode 100644 +WARNING: line over 80 characters +#169: FILE: drivers/irqchip/irq-tegra.c:129: ++ tegra_ictlr_info-cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER); As a matter of principle, I ignore what checkpatch says about the length of lines of code. I trust my eyes more than the tool. [...] +WARNING: Missing a blank line after declarations +#196: FILE: drivers/irqchip/irq-tegra.c:156: ++ void __iomem *ictlr = tegra_ictlr_info-ictlr_reg_base[i]; ++ writel_relaxed(tegra_ictlr_info-cpu_iep[i], Done. +WARNING: line over 80 characters +#284: FILE: drivers/irqchip/irq-tegra.c:244: ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, parent_args); +CHECK: Please don't use multiple blank lines +#287: FILE: drivers/irqchip/irq-tegra.c:247: ++ ++ +WARNING: Missing a blank line after declarations +#296: FILE: drivers/irqchip/irq-tegra.c:256: ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ` Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
On 2015-01-08 10:13, Thierry Reding wrote: On Wed, Jan 07, 2015 at 05:42:37PM +, Marc Zyngier wrote: Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked irq domain framework fits this pretty well, and allows Nit: s/irq/IRQ/ the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- drivers/irqchip/Makefile| 1 + drivers/irqchip/irq-tegra.c | 335 2 files changed, 336 insertions(+) create mode 100644 drivers/irqchip/irq-tegra.c This matches largely what I have in a local patch (modulo the stacked domains vs. gic_arch_extn). A few comments below. [snip] Thanks for the extensive review. I've implemented all of this, except for the hunk below: diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 9516a32..59f34be 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o obj-$(CONFIG_ARCH_MXS) += irq-mxs.o +obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o Should these be sorted alphabetically? Well, the left side is (up to S3C24xx, and then it all goes down the drain). Do you have a suggestion? Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
On 2015-01-07 17:42, Marc Zyngier wrote: The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have landed in -next, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we already broke it for the OMAP WUGEN block, we might as well do it again for the TI crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die I've updated this branch with the changes requested in this review cycle. I'll give it a test run on Monday with the platforms I have around (mainly Tegra20 and OMAP4/5). Unless anything major comes up, I'll post v3 with a view of getting this into 3.20. Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 06/21] ARM: tegra: remove old LIC support
On 2015-01-08 11:29, Thierry Reding wrote:
On Wed, Jan 07, 2015 at 05:42:41PM +, Marc Zyngier wrote:
[...]
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
[...]
void __init tegra_init_irq(void)
{
- int i;
- void __iomem *distbase;
-
- if (of_find_matching_node(NULL, tegra_ictlr_match))
- goto skip_extn_setup;
-
- tegra_legacy_irq_syscore_init();
-
- distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
- num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f;
-
- if (num_ictlrs ARRAY_SIZE(ictlr_reg_base)) {
- WARN(1, Too many (%d) interrupt controllers found. Maximum is
%d.,
- num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
- num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
- }
-
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- writel(~0, ictlr + ICTLR_CPU_IER_CLR);
- writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
- }
-
- gic_arch_extn.irq_ack = tegra_ack;
- gic_arch_extn.irq_eoi = tegra_eoi;
- gic_arch_extn.irq_mask = tegra_mask;
- gic_arch_extn.irq_unmask = tegra_unmask;
- gic_arch_extn.irq_retrigger = tegra_retrigger;
- gic_arch_extn.irq_set_wake = tegra_set_wake;
- gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+ if (!of_find_matching_node(NULL, tegra_ictlr_match))
+ pr_warn(Outdated DT detected, suspend/resume will NOT work\n);
I'm not very happy about the ABI breakage here, but I also realize
that
we need this change to properly describe the hardware. To make it
more
obvious that people really should update their DTBs, maybe turn this
into a WARN()?
Sure, done.
-skip_extn_setup:
tegra114_gic_cpu_pm_registration();
I'm not intimately familiar with the GIC, but is this really SoC
specific? Doesn't anybody else need this? Comparing to the GIC spec
the
write of 0x1e0 to the GIC_CPU_CTRL register (which I assume
corresponds
to GICC_CTLR in the spec), this simply disables the IRQ and FIQ
bypass
signals for both group 0 and group 1.
This seems to be a Tegra special, at least in mainline. But yes, I'd
very much like to be able to remove this from platform code and make it
part of the GIC driver if we can.
Something for a subsequent patch series, I guess.
Thanks,
M.
--
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Re: [PATCH v2 13/21] DT: omap4/5: add binding for the wake-up generator
On 2015-01-08 16:52, Nishanth Menon wrote: On 17:42-20150107, Marc Zyngier wrote: Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- .../interrupt-controller/ti,omap4-wugen-mpu| 32 ++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu new file mode 100644 index 000..16149d9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu @@ -0,0 +1,32 @@ +TI OMAP4 Wake-up Generator + +All TI OMAP4/5 (and their derivatives) an interrupt controllerthat controller that +routes interrupts to the GIC, and also serves as a wakeup source. It +is also refered to as WUGEN-MPU, hence the name of the binding. + +Reguired properties: + +- compatible : should contain at least ti,omap4-wugen-mpu Could we also document ti,omap5-wugen-mpu. In addition, if you could make this patch prior to patch #12, it helps the checkpatch at the very least ;) Sure. also saw a few checkpatch warnings: +WARNING: 'refered' may be misspelled - perhaps 'referred'? +#22: FILE: Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu:5: ++is also refered to as WUGEN-MPU, hence the name of the binding. +WARNING: 'explicitely' may be misspelled - perhaps 'explicitly'? +#39: FILE: Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu:22: ++ are explicitely forbiden. +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 3. +- interrupt-parent : a phandle to the GIC these interrupts are routed + to. + +Notes: + +- Because this HW ultimately routes interrupts to the GIC, the + interrupt specifier must be that of the GIC. +- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs I think you mean interrupt controller and not nvidia ictlr here.. :) -ECOPYPASTE... ;-) Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 12/21] ARM: omap: convert wakeupgen to stacked domains
On 2015-01-08 16:44, Nishanth Menon wrote:
On 17:42-20150107, Marc Zyngier wrote:
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like
this:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer
19: 233799 155916 GIC 27 arch_timer
23: 0 0 WUGEN 9 l3-dbg-irq
24: 1 0 WUGEN 10 l3-app-irq
27:282 0 WUGEN 13 omap-dma-engine
44: 0 0 4ae1.gpio 13 DMA
294: 0 0 WUGEN 20 gpmc
297:506 0 WUGEN 56 4807.i2c
298: 0 0 WUGEN 57 48072000.i2c
299: 0 0 WUGEN 61 4806.i2c
300: 0 0 WUGEN 62 4807a000.i2c
301: 8 0 WUGEN 60 4807c000.i2c
308: 2439 0 WUGEN 74 OMAP UART2
312:362 0 WUGEN 83 mmc2
313:502 0 WUGEN 86 mmc0
314: 13 0 WUGEN 94 mmc1
350: 0 0 PRCM pinctrl, pinctrl
406: 35155709 0 GIC 109 ehci_hcd:usb1
407: 0 0 WUGEN 7 palmas
409: 0 0 WUGEN 119 twl6040
410: 0 0 twl6040 5 twl6040_irq_ready
411: 0 0 twl6040 0 twl6040_irq_th
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 95334 902334 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4:479648 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am4372.dtsi | 11 ++-
arch/arm/boot/dts/dra7.dtsi | 12 ++-
arch/arm/boot/dts/dra72x.dtsi | 2 +-
arch/arm/boot/dts/dra74x.dtsi | 2 +-
arch/arm/boot/dts/omap4-duovero.dtsi | 2 -
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +-
arch/arm/boot/dts/omap4-sdp.dts | 8 +-
arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 -
arch/arm/boot/dts/omap4.dtsi | 18 -
arch/arm/boot/dts/omap5-cm-t54.dts| 1 -
arch/arm/boot/dts/omap5-uevm.dts | 2 -
arch/arm/boot/dts/omap5.dtsi | 24 --
arch/arm/mach-omap2/omap-wakeupgen.c | 125
+++---
arch/arm/mach-omap2/omap-wakeupgen.h | 1 -
arch/arm/mach-omap2/omap4-common.c| 1 -
15 files changed, 154 insertions(+), 65 deletions(-)
we may need the following changes as well:
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4cf9f89..69f2313a49d1 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
- interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc90b26a..029badefad3d 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
- interrupt-parent = gic;
interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 662261d6b2ca..2d26bc11bad6 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -333,7 +333,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
- interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c2241c2e5d9d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6
[PATCH v2 01/21] ARM: tegra: irq: nuke leftovers from non-DT support
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-tegra/irq.c | 8 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ab95f53..7f87a50 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -283,13 +283,5 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_set_wake = tegra_set_wake; gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; - /* -* Check if there is a devicetree present, since the GIC will be -* initialized elsewhere under DT. -*/ - if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - tegra114_gic_cpu_pm_registration(); } -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f70bed0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
/ {
compatible = nvidia,tegra114;
- interrupt-parent = gic;
+ interrupt-parent = ictlr;
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
+ };
+
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra114-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64,
+ 0x60004400 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..6ed6ca0 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
/ {
compatible = nvidia,tegra124;
- interrupt-parent = gic;
+ interrupt-parent = ictlr;
#address-cells = 2;
#size-cells = 2;
@@ -173,6 +173,7 @@
0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra124-ictlr, nvidia,tegra-ictlr;
+ reg = 0x0 0x60004000 0x0 0x40,
+ 0x0 0x60004100 0x0 0x40,
+ 0x0 0x60004200 0x0 0x40,
+ 0x0 0x60004300 0x0 0x40,
+ 0x0 0x60004400 0x0 0x40;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
+ };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..ab2f004 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
/ {
compatible = nvidia,tegra20;
- interrupt-parent = intc;
+ interrupt-parent = ictlr;
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+ interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+ interrupt-parent = intc;
};
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..c621e30
[PATCH v2 10/21] irqchip: GIC: get rid of routable domain
The only user of the so called routable domain functionnality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
}
static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
- gic_routable_irq_domain_ops-unmap(d, irq);
}
static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0]) {
- ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
- if (IS_ERR_VALUE(ret))
- return ret;
- }
+ if (!intspec[0])
+ *out_hwirq += 16;
*out_type = intspec[2] IRQ_TYPE_SENSE_MASK;
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
- return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
- struct device_node *controller,
- const u32 *intspec, unsigned int intsize,
- unsigned long *out_hwirq,
- unsigned int *out_type)
-{
- *out_hwirq += 16;
- return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
- .map = gic_routable_irq_domain_map,
- .unmap = gic_routable_irq_domain_unmap,
- .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
- gic_default_routable_irq_domain_ops;
-
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
- int nr_routable_irqs;
BUG_ON(gic_nr = MAX_GIC_NR);
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic-gic_irqs = gic_irqs;
if (node) { /* DT case */
- const struct irq_domain_ops *ops =
gic_irq_domain_hierarchy_ops;
-
- if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
- ops = gic_irq_domain_ops;
- gic_irqs = nr_routable_irqs;
- }
-
- gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+ gic-domain = irq_domain_add_linear(node, gic_irqs,
+
gic_irq_domain_hierarchy_ops,
+ gic);
} else {/* Non-DT case */
/*
* For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
void gic_migrate_target(unsigned int new_cpu_id);
unsigned long gic_get_sgir_physaddr(void);
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
- (const struct irq_domain_ops *ops)
-{
- gic_routable_irq_domain_ops = ops
[PATCH v2 09/21] DT: update ti,irq-crossbar binding
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
Required properties:
- compatible : Should be ti,irq-crossbar
- reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt
controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be
routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
- crossbar_mpu: @4a02 {
+ crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
- ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further
details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as
a
-quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
- device_y@0x4a033000 {
- /* Direct mapped GIC SPI 1 used */
- interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
- ...
- };
--
2.1.4
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[PATCH v2 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node
If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.
This is only a temporary measure until that code is removed for good.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/irq.c | 11 +++
arch/arm/mach-tegra/tegra.c | 1 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7f87a50..b37141d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -255,11 +255,21 @@ static void tegra114_gic_cpu_pm_registration(void)
static void tegra114_gic_cpu_pm_registration(void) { }
#endif
+static const struct of_device_id tegra_ictlr_match[] __initconst = {
+ { .compatible = nvidia,tegra-ictlr },
+ { }
+};
+
void __init tegra_init_irq(void)
{
int i;
void __iomem *distbase;
+ if (of_find_matching_node(NULL, tegra_ictlr_match))
+ goto skip_extn_setup;
+
+ tegra_legacy_irq_syscore_init();
+
distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f;
@@ -283,5 +293,6 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+skip_extn_setup:
tegra114_gic_cpu_pm_registration();
}
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af..c33fba7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -82,7 +82,6 @@ static void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
irqchip_init();
- tegra_legacy_irq_syscore_init();
}
static void __init tegra_dt_init(void)
--
2.1.4
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[PATCH v2 14/21] ARM: imx6: convert GPC to stacked domains
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 +-
arch/arm/boot/dts/imx6sl.dtsi | 5 +-
arch/arm/boot/dts/imx6sx.dtsi | 5 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 116 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..c16d428 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+ interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
@@ -694,8 +696,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..c476e67 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -131,7 +132,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
pmu {
@@ -700,7 +701,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
iomuxc: iomuxc@020e {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cfcdb62..7052302 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -102,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void
[PATCH v2 12/21] ARM: omap: convert wakeupgen to stacked domains
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like
this:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer
19: 233799 155916 GIC 27 arch_timer
23: 0 0 WUGEN 9 l3-dbg-irq
24: 1 0 WUGEN 10 l3-app-irq
27:282 0 WUGEN 13 omap-dma-engine
44: 0 0 4ae1.gpio 13 DMA
294: 0 0 WUGEN 20 gpmc
297:506 0 WUGEN 56 4807.i2c
298: 0 0 WUGEN 57 48072000.i2c
299: 0 0 WUGEN 61 4806.i2c
300: 0 0 WUGEN 62 4807a000.i2c
301: 8 0 WUGEN 60 4807c000.i2c
308: 2439 0 WUGEN 74 OMAP UART2
312:362 0 WUGEN 83 mmc2
313:502 0 WUGEN 86 mmc0
314: 13 0 WUGEN 94 mmc1
350: 0 0 PRCM pinctrl, pinctrl
406: 35155709 0 GIC 109 ehci_hcd:usb1
407: 0 0 WUGEN 7 palmas
409: 0 0 WUGEN 119 twl6040
410: 0 0 twl6040 5 twl6040_irq_ready
411: 0 0 twl6040 0 twl6040_irq_th
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 95334 902334 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4:479648 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am4372.dtsi | 11 ++-
arch/arm/boot/dts/dra7.dtsi | 12 ++-
arch/arm/boot/dts/dra72x.dtsi | 2 +-
arch/arm/boot/dts/dra74x.dtsi | 2 +-
arch/arm/boot/dts/omap4-duovero.dtsi | 2 -
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +-
arch/arm/boot/dts/omap4-sdp.dts | 8 +-
arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 -
arch/arm/boot/dts/omap4.dtsi | 18 -
arch/arm/boot/dts/omap5-cm-t54.dts| 1 -
arch/arm/boot/dts/omap5-uevm.dts | 2 -
arch/arm/boot/dts/omap5.dtsi | 24 --
arch/arm/mach-omap2/omap-wakeupgen.c | 125 +++---
arch/arm/mach-omap2/omap-wakeupgen.h | 1 -
arch/arm/mach-omap2/omap4-common.c| 1 -
15 files changed, 154 insertions(+), 65 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd..9d672a7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
/ {
compatible = ti,am4372, ti,am43;
- interrupt-parent = gic;
+ interrupt-parent = wakeupgen;
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
0x48240100 0x0100;
+ interrupt-parent = gic;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
};
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 59ec0e6..a5741ae 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -64,6 +64,14 @@
interrupt-parent = gic;
};
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@@ -92,7 +100,7 @@
reg = 0x4400 0x100,
0x4500 0x1000;
interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
- gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ wakeupgen GIC_SPI 10
[PATCH v2 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
- arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
0xfff10100 0x100;
};
--
2.1.4
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[PATCH v2 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
*/
void __init ux500_init_irq(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
/*
--
2.1.4
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[PATCH v2 13/21] DT: omap4/5: add binding for the wake-up generator
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/ti,omap4-wugen-mpu| 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..16149d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,32 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controllerthat
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also refered to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+ are explicitely forbiden.
+
+Example:
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
--
2.1.4
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[PATCH v2 21/21] irqchip: gic: Drop support for gic_arch_extn
Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 54 -
include/linux/irqchip/arm-gic.h | 2 --
2 files changed, 56 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
#define NR_GIC_CPU_IF 8
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
- .irq_eoi= NULL,
- .irq_mask = NULL,
- .irq_unmask = NULL,
- .irq_retrigger = NULL,
- .irq_set_type = NULL,
- .irq_set_wake = NULL,
-};
-
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1
#endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
(gic_irq(d) / 32) * 4);
- if (gic_arch_extn.irq_mask)
- gic_arch_extn.irq_mask(d);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
- if (gic_arch_extn.irq_unmask)
- gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET +
(gic_irq(d) / 32) * 4);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_eoi_irq(struct irq_data *d)
{
- if (gic_arch_extn.irq_eoi) {
- raw_spin_lock(irq_controller_lock);
- gic_arch_extn.irq_eoi(d);
- raw_spin_unlock(irq_controller_lock);
- }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int
type)
if (type != IRQ_TYPE_LEVEL_HIGH type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
- raw_spin_lock(irq_controller_lock);
-
- if (gic_arch_extn.irq_set_type)
- gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
- raw_spin_unlock(irq_controller_lock);
-
return 0;
}
static int gic_retrigger(struct irq_data *d)
{
- if (gic_arch_extn.irq_retrigger)
- return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
}
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const
struct cpumask *mask_val,
}
#endif
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
- int ret = -ENXIO;
-
- if (gic_arch_extn.irq_set_wake)
- ret = gic_arch_extn.irq_set_wake(d, on);
-
- return ret;
-}
-
-#else
-#define gic_set_wake NULL
-#endif
-
static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
- .irq_set_wake = gic_set_wake,
};
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
set_handle_irq(gic_handle_irq);
}
- gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
struct device_node;
-extern struct irq_chip gic_arch_extn;
-
void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
--
2.1.4
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[PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/dra7-evm.dts | 2 +-
arch/arm/boot/dts/dra7.dtsi | 35 +++---
arch/arm/boot/dts/dra72-evm.dts | 1 -
arch/arm/boot/dts/dra72x.dtsi| 3 +-
arch/arm/boot/dts/dra74x.dtsi| 5 +-
arch/arm/mach-omap2/omap4-common.c | 4 -
drivers/irqchip/irq-crossbar.c | 202 ---
include/linux/irqchip/irq-crossbar.h | 11 --
8 files changed, 141 insertions(+), 122 deletions(-)
delete mode 100644 include/linux/irqchip/irq-crossbar.h
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..59ec0e6 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
#include skeleton.dtsi
#define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
/ {
#address-cells = 1;
#size-cells = 1;
compatible = ti,dra7xx;
- interrupt-parent = gic;
+ interrupt-parent = crossbar_mpu;
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
- arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
0x48212000 0x1000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
0x4500 0x1000;
- interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
- interrupts-extended = gic GIC_SPI 68
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart2;
clock-frequency = 4800;
status = disabled;
@@ -366,7 +366,7 @@
uart3: serial@4802 {
compatible = ti,omap4-uart;
reg = 0x4802 0x100;
- interrupts-extended = gic GIC_SPI 69
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart3;
clock-frequency = 4800;
status = disabled;
@@ -377,7 +377,7 @@
uart4: serial@4806e000 {
compatible = ti,omap4-uart;
reg = 0x4806e000 0x100;
- interrupts-extended = gic GIC_SPI 65
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI
[PATCH v2 06/21] ARM: tegra: remove old LIC support
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c | 201 +---
arch/arm/mach-tegra/irq.h | 6 --
3 files changed, 2 insertions(+), 220 deletions(-)
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
#define TEGRA_ARM_INT_DIST_BASE0x50041000
#define TEGRA_ARM_INT_DIST_SIZESZ_4K
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
-
#define TEGRA_TMR1_BASE0x60005000
#define TEGRA_TMR1_SIZESZ_8
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index b37141d..a1befd3 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
#include board.h
#include iomap.h
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR 0x14
-#define ICTLR_CPU_IEP_FIR_SET 0x18
-#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-
-#define ICTLR_CPU_IER 0x20
-#define ICTLR_CPU_IER_SET 0x24
-#define ICTLR_CPU_IER_CLR 0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER 0x30
-#define ICTLR_COP_IER_SET 0x34
-#define ICTLR_COP_IER_CLR 0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS 5
-
#define SGI_MASK 0x
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
- IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
#ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
static void __iomem *tegra_gic_cpu_base;
#endif
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
}
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
- void __iomem *base;
- u32 mask;
-
- BUG_ON(irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
- base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
- __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return 0;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
- return 1;
-}
-
#ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
- u32 irq = d-hwirq;
- u32 index, mask;
-
- if (irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
- return -EINVAL;
-
- index = ((irq - FIRST_LEGACY_IRQ) / 32);
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
- if (enable)
- ictlr_wake_mask[index] |= mask;
- else
- ictlr_wake_mask[index] = ~mask;
-
- return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- /* Save interrupt state */
- cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
- cpu_iep[i
[PATCH v2 07/21] genirq: Add irqchip_set_wake_parent
This proves to be usefull with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
#endif
/* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
return -ENOSYS;
}
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data: Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+ data = data-parent_data;
+ if (data-chip-irq_set_wake)
+ return data-chip-irq_set_wake(data, on);
+
+ return -ENOSYS;
+}
#endif
/**
--
2.1.4
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[PATCH v2 17/21] irqchip: gic: add an entry point to set up irqchip flags
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 5 +
include/linux/irqchip/arm-gic.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
+void gic_set_irqchip_flags(unsigned long flags)
+{
+ gic_chip.flags |= flags;
+}
+
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
extern struct irq_chip gic_arch_extn;
+void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
--
2.1.4
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[PATCH v2 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
static void __init zynq_irq_init(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
}
--
2.1.4
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[PATCH v2 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 3 +
arch/arm/boot/dts/exynos5250.dtsi | 3 +
arch/arm/boot/dts/exynos5420.dtsi | 3 +
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 126 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..adc189f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,8 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +255,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..c31007c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +232,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..1946c76c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..24fc7f8 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
-#include linux/irqchip/arm-gic.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
[PATCH v2 16/21] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
--
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Re: [PATCH 16/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
On 27/11/14 07:35, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
+
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 523 +++
2 files changed, 1221 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
new file mode 100644
index 000..3d8b576
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
+ timer {
+ compatible = arm,armv8-timer;
+ interrupts = 1 13 0xff01,
+1 14 0xff01,
+1 11 0xff01,
+1 10 0xff01;
This is wrong. Timer interrupts for both A53 and A57 are level triggered.
+ clock-frequency = 2400;
Please go and fix your firmware. Really...
+ use-clocksource-only;
+ use-physical-timer;
+ };
Well, that's a total NAK. Neither of these properties are part of the
binding, and we've already established that none of that would never be
valid on arm64.
I suggest you finally do what we've been asking for years, which is to
fix your boot ROM by adding the 5 lines of assembly code that are needed
instead of repeatedly post the same bogus DT files.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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Re: Unable to boot mainline on snow chromebook since 3.15
On 05/09/14 14:46, Ajay kumar wrote: Hi Will, On Fri, Sep 5, 2014 at 5:52 PM, Will Deacon will.dea...@arm.com wrote: [Looks like it's not just Rutland that can't spell the address of the mailing list today. Fixed here, so please use this post in any replies]. On Fri, Sep 05, 2014 at 12:57:04PM +0100, Will Deacon wrote: Hi all, I'm one of the few, foolish people to try running mainline on my 5250-based Samsung Chromebook (snow). I can live without wireless, usb3 and video acceleration, so actually it makes a reasonable development platform for doing A15-based (micro)-architectural work. However, since 3.15 I've not been able to boot *any* mainline kernels on this board. I did mean to report this earlier, but I have other machines that can run mainline so this has fallen by the wayside. The problems started with 3.16, where simple-fb would fail to initialise and I lost my display. Note that I don't have a serial console on this machine (I looked at the PCB and there's no way I can solder one of those myself :) I bisected the issue at the time, and I could get my display back by removing some of the new regulator and hdmi properties from the DT. At that point, I could boot, but DMA didn't initialise for the MMC controller so I couldn't mount my root filesystem. http://www.spinics.net/lists/dri-devel/msg66740.html With 3.17-rc3, it seems a lot worse -- I don't get any output after nv-uboot (i.e. the nv-uboot screen just remains on the display, with the last line reading Stashed 20 records). I'd usually try to debug this a bit further, but without a console it's really painful to get anywhere. I've been working with 3.15, but now I'm having to backport patches when I want to test them, which is more effort than I can be bothered with. Is anybody else running mainline on this device and are these known/fixed problems? AFAIK, ARM chromebooks use DRM based display drivers and the required patches are still not merged: http://www.spinics.net/lists/dri-devel/msg66740.html Corresponding DT patches are also still not merged: http://www.spinics.net/lists/arm-kernel/msg358324.html http://www.spinics.net/lists/arm-kernel/msg358325.html There is a patch for configs as well: https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35828.html Try these patches(I hope they will apply directly on 3.17-rc3) and you should be able to use display on snow. As Will said, it used to work with simplefb, and it doesn't anymore. It means someone broke mainline. So before even considering merging these DRM patches, I'd really like to see simplefb on Snow restored to working conditions *in mainline*. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7
On 28/08/14 04:56, Olof Johansson wrote:
Hi,
On Wed, Aug 27, 2014 at 03:14:18PM +0530, Naveen Krishna Chatradhi wrote:
Add initial device tree nodes for EXYNOS7 SoC.
Also, includes the dt-binding definitions for clock ids.
Uh, no -- it just adds the dtsi.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/exynos7.dtsi | 553
++
1 file changed, 553 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/exynos7.dtsi
b/arch/arm64/boot/dts/exynos7.dtsi
new file mode 100644
index 000..6b9eaf4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7.dtsi
Let's not make the same mistake as on 32-bit, and go with a directory
hierarchy here from day one.
So, please create a exynos subdirectory for this file. You also need
a Makefile when you add a board dts.
@@ -0,0 +1,553 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS7 SoC device nodes are listed in this file.
+ * EXYNOS7 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+compatible = samsung,exynos7;
+interrupt-parent = gic;
+#address-cells = 1;
+#size-cells = 1;
You should probably use address-cells/size-cells 2/2 on a 64-bit platform.
+aliases {
+pinctrl0 = pinctrl_0;
+pinctrl1 = pinctrl_1;
+pinctrl2 = pinctrl_2;
+pinctrl3 = pinctrl_3;
+pinctrl4 = pinctrl_4;
+pinctrl5 = pinctrl_5;
+pinctrl6 = pinctrl_6;
+pinctrl7 = pinctrl_7;
+pinctrl8 = pinctrl_8;
+pinctrl9 = pinctrl_9;
+mshc0 = mmc_0;
+mshc2 = mmc_2;
+};
+
+chipid@1000 {
+compatible = samsung,exynos4210-chipid;
+reg = 0x1000 0x100;
+};
+
+cpus {
+#address-cells = 2;
+#size-cells = 0;
Why size-cells=2? Can you not fit a cpuid in 32 bits?
+cpu@0 {
+device_type = cpu;
+compatible = arm,cortex-a57, arm,armv8;
+reg = 0x0 0x0;
+};
+};
+
+fin_pll: xxti {
+compatible = fixed-clock;
+clock-frequency = 2400;
+clock-output-names = fin_pll;
+#clock-cells = 0;
+};
+
+gic: interrupt-controller@11001000 {
+compatible = arm,gic-400;
+#interrupt-cells = 3;
+#address-cells = 0;
+interrupt-controller;
+reg = 0x11001000 0x1000,
+0x11002000 0x1000,
+0x11004000 0x2000,
+0x11006000 0x2000;
+};
+
+hsi2c_0: hsi2c@1364 {
+compatible = samsung,exynos7-hsi2c;
Is the i2c controller here completely new?
Also, please use 'i2c' for node name on these nodes.
+reg = 0x1364 0x1000;
+interrupts = 0 441 0;
+#address-cells = 1;
+#size-cells = 0;
+pinctrl-names = default;
+pinctrl-0 = hs_i2c0_bus;
+clocks = clock_peric0 PCLK_HSI2C0;
+clock-names = hsi2c;
+status = disabled;
+};
+
+hsi2c_1: hsi2c@1365 {
+compatible = samsung,exynos7-hsi2c;
+reg = 0x1365 0x1000;
+interrupts = 0 442 0;
+#address-cells = 1;
+#size-cells = 0;
+pinctrl-names = default;
+pinctrl-0 = hs_i2c1_bus;
+clocks = clock_peric0 PCLK_HSI2C1;
+clock-names = hsi2c;
+status = disabled;
+};
+
+hsi2c_2: hsi2c@14E6 {
I much prefer lowercase hex in unit addresses (and reg entries) below. I
know 32-bit uses uppercase, but let's switch going forward here.
+mct@101C {
+compatible = samsung,exynos4210-mct;
Please just do away with MCT here, and use architected timers going
forward. There really shouldn't be a need to keep supporting MCT any
more -- it's a construct from before arch timers on Cortex-A9.
+mmc_0: mmc@1574 {
+compatible = samsung,exynos7-dw-mshc-smu;
Is this controller backwards compatible with exynos5 ones?
+/* The Clock nodes are ordered as per the usermanual. */
The clock
user manual
+timer {
+compatible = arm,armv8-timer;
+
Re: [PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7
On 28/08/14 18:03, Mark Rutland wrote: From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001 From: Mark Rutland mark.rutl...@arm.com Date: Thu, 28 Aug 2014 17:41:03 +0100 Subject: [PATCH] Doc: dt: arch_timer: discourage clock-frequency use The ARM Generic Timer (AKA the architected timer, arm_arch_timer) features a CPU register (CNTFRQ) which firmware is intended to initialize, and non-secure software can read to determine the frequency of the timer. On CPUs with secure state, this register cannot be written from non-secure states. The firmware of early SoCs featuring the timer did not correctly initialize CNTFRQ correctly on all CPUs, requiring the frequency to be described in DT as a workaround. This workaround is not complete however as CNTFRQ is exposed to all software in a privileged non-secure mode, including KVM guests. The firmware and DTs for recent SoCs have followed I believe Xen is also affected by this. the example set by these early SoCs. This patch updates the arch timer binding documentation to make it clearer that the use of the clock-frequency property is a poor work-around. The MMIO generic timer binding is similarly updated, though this is less of a concern as there is generally no need to expose the MMIO timers to guest OSs. Signed-off-by: Mark Rutland mark.rutl...@arm.com Cc: Marc Zyngier marc.zyng...@arm.com Short of more explicit threats: Acked-by: Marc Zyngier marc.zyng...@arm.com --- Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 37b2caf..5ca3f95 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -17,7 +17,10 @@ to deliver its interrupts via SPIs. - interrupts : Interrupt list for secure, non-secure, virtual and hypervisor timers, in that order. -- clock-frequency : The frequency of the main counter, in Hz. Optional. +- clock-frequency : The frequency of the main counter, in Hz. Should be present + only where necessary to work around BROKEN firmware which does not configure + CNTFRQ on all CPUs to a uniform correct value. Use of this property is + STRONGLY DISCOURAGED; fix your firmware unless absolutely impossible. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. @@ -38,7 +41,8 @@ Example: - compatible : Should at least contain arm,armv7-timer-mem. -- clock-frequency : The frequency of the main counter, in Hz. Optional. +- clock-frequency : The frequency of the main counter, in Hz. Should be present + only when firmware has not configured the MMIO CNTFRQ registers. - reg : The control frame base address. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7
On 28/08/14 18:30, Mark Rutland wrote: On Thu, Aug 28, 2014 at 06:27:04PM +0100, Marc Zyngier wrote: On 28/08/14 18:03, Mark Rutland wrote: From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001 From: Mark Rutland mark.rutl...@arm.com Date: Thu, 28 Aug 2014 17:41:03 +0100 Subject: [PATCH] Doc: dt: arch_timer: discourage clock-frequency use The ARM Generic Timer (AKA the architected timer, arm_arch_timer) features a CPU register (CNTFRQ) which firmware is intended to initialize, and non-secure software can read to determine the frequency of the timer. On CPUs with secure state, this register cannot be written from non-secure states. The firmware of early SoCs featuring the timer did not correctly initialize CNTFRQ correctly on all CPUs, requiring the frequency to be described in DT as a workaround. This workaround is not complete however as CNTFRQ is exposed to all software in a privileged non-secure mode, including KVM guests. The firmware and DTs for recent SoCs have followed I believe Xen is also affected by this. True. s/KVM/KVM\/Xen/, then? Yup. Or including guests running under a hypervisor, I expect this to be such a fundamental problem that all hypervisors will trip over on that one (Jailhouse definitely does). Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi | 2 +-
arch/arm/boot/dts/exynos5260.dtsi | 2 +-
arch/arm/boot/dts/exynos5410.dtsi | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/omap5.dtsi| 2 +-
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi| 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi| 2 +-
arch/arm/boot/dts/tegra114.dtsi | 2 +-
arch/arm/boot/dts/tegra124.dtsi | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
arch/arm64/boot/dts/apm-storm.dtsi | 2 +-
arch/arm64/boot/dts/foundation-v8.dts | 2 +-
arch/arm64/boot/dts/rtsm_ve-aemv8a.dts | 2 +-
21 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index ea288f0..40aacc9 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -62,7 +62,7 @@
#address-cells = 0;
interrupt-controller;
reg = 0x20 0x01001000 0 0x1000,
- 0x20 0x01002000 0 0x1000,
+ 0x20 0x01002000 0 0x2000,
0x20 0x01004000 0 0x2000,
0x20 0x01006000 0 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c29945e..65329ff 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -46,7 +46,7 @@
interrupt-controller;
#interrupt-cells = 3;
reg = 0x48211000 0x1000,
- 0x48212000 0x1000,
+ 0x48212000 0x2000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 2ccbb57f..c15e7e0 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -99,7 +99,7 @@
interrupt-controller;
interrupts = 1 9 0xf04;
reg = 0xfff11000 0x1000,
- 0xfff12000 0x1000,
+ 0xfff12000 0x2000,
0xfff14000 0x2000,
0xfff16000 0x2000;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 3e678fa..bbd177a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -173,7 +173,7 @@
#interrupt-cells = 3;
interrupt-controller;
reg = 0x10481000 0x1000,
- 0x10482000 0x1000,
+ 0x10482000 0x2000,
0x10484000 0x2000,
0x10486000 0x2000;
interrupts = 1 9 0xf04;
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..15fdc3b 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -44,7 +44,7 @@
#interrupt-cells = 3;
interrupt-controller;
reg = 0x10481000 0x1000,
- 0x10482000 0x1000,
+ 0x10482000 0x2000,
0x10484000 0x2000,
0x10486000 0x2000;
interrupts = 1 9 0xf04;
diff --git a/arch/arm/boot/dts/exynos5260.dtsi
b/arch/arm/boot/dts/exynos5260.dtsi
index 5398a60..c0e2341 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -161,7 +161,7 @@
#size-cells = 0;
interrupt-controller;
reg = 0x10481000 0x1000,
- 0x10482000 0x1000,
+ 0x10482000 0x2000,
0x10484000 0x2000,
0x10486000
Re: [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
On Wed, Jun 25 2014 at 01:21:17 PM, Rob Herring robherri...@gmail.com wrote:
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
What's your plan for making the kernel change? Updating the dts files
is good, but that doesn't immediately help you if you have old dtbs.
See at the end of https://lkml.org/lkml/2014/6/25/243
Basically, we stay with a GICv1 behaviour if we detect the mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
Acked-by: Rob Herring r...@kernel.org
Thanks,
M.
--
Jazz is not dead. It just smells funny.
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Re: [PATCH v2 7/7] arm64: KVM: Implement 4 levels of translation tables for HYP and stage2
On Wed, Apr 16 2014 at 5:33:31 am BST, Jungseok Lee jays@samsung.com
wrote:
This patch adds 4 levels of translation tables implementation for both
HYP and stage2. A combination of 4KB + 4 levels host and 4KB + 4 levels
guest can run on ARMv8 architecture as introducing this feature.
Just to be sure: have you tested it with asymetric configurations (4kB
host, 64kB guest, and the oposite configuration)?
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm/include/asm/kvm_mmu.h | 10 +
arch/arm/kvm/mmu.c | 88
+-
arch/arm64/include/asm/kvm_arm.h | 20 +
arch/arm64/include/asm/kvm_mmu.h | 10 +
4 files changed, 117 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 5c7aa3c..6f7906e 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -37,6 +37,11 @@
*/
#define TRAMPOLINE_VAUL(CONFIG_VECTORS_BASE)
+/*
+ * NUM_OBJS depends on the number of page table translation levels
+ */
+#define NUM_OBJS 2
I'm afraid this is way too generic. Use something along the lines of
MMU_CACHE_MIN_PAGES, that makes it obvious what we're talking about.
+
#ifndef __ASSEMBLY__
#include asm/cacheflush.h
@@ -94,6 +99,11 @@ static inline void kvm_clean_pgd(pgd_t *pgd)
clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
}
+static inline void kvm_clean_pmd(pmd_t *pmd)
+{
+ clean_dcache_area(pmd, PTRS_PER_PMD * sizeof(pmd_t));
+}
+
static inline void kvm_clean_pmd_entry(pmd_t *pmd)
{
clean_pmd_entry(pmd);
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 80bb1e6..7fc9e55 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -388,13 +388,44 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned
long start,
return 0;
}
+static int create_hyp_pud_mappings(pgd_t *pgd, unsigned long start,
+unsigned long end, unsigned long pfn,
+pgprot_t prot)
+{
+ pud_t *pud;
+ pmd_t *pmd;
+ unsigned long addr, next;
+
+ addr = start;
+ do {
+ pud = pud_offset(pgd, addr);
+
+ if (pud_none_or_clear_bad(pud)) {
+ pmd = pmd_alloc_one(NULL, addr);
+ if (!pmd) {
+ kvm_err(Cannot allocate Hyp pmd\n);
+ return -ENOMEM;
+ }
+ pud_populate(NULL, pud, pmd);
+ get_page(virt_to_page(pud));
+ kvm_flush_dcache_to_poc(pud, sizeof(*pud));
+ }
+
+ next = pud_addr_end(addr, end);
+
+ create_hyp_pmd_mappings(pud, addr, next, pfn, prot);
+ pfn += (next - addr) PAGE_SHIFT;
+ } while (addr = next, addr != end);
+
+ return 0;
+}
+
static int __create_hyp_mappings(pgd_t *pgdp,
unsigned long start, unsigned long end,
unsigned long pfn, pgprot_t prot)
{
pgd_t *pgd;
pud_t *pud;
- pmd_t *pmd;
unsigned long addr, next;
int err = 0;
@@ -403,22 +434,23 @@ static int __create_hyp_mappings(pgd_t *pgdp,
end = PAGE_ALIGN(end);
do {
pgd = pgdp + pgd_index(addr);
- pud = pud_offset(pgd, addr);
- if (pud_none_or_clear_bad(pud)) {
- pmd = pmd_alloc_one(NULL, addr);
- if (!pmd) {
- kvm_err(Cannot allocate Hyp pmd\n);
+ if (pgd_none(*pgd)) {
+ pud = pud_alloc_one(NULL, addr);
+ if (!pud) {
+ kvm_err(Cannot allocate Hyp pud\n);
err = -ENOMEM;
goto out;
}
- pud_populate(NULL, pud, pmd);
- get_page(virt_to_page(pud));
- kvm_flush_dcache_to_poc(pud, sizeof(*pud));
+ pgd_populate(NULL, pgd, pud);
+ get_page(virt_to_page(pgd));
+ kvm_flush_dcache_to_poc(pgd, sizeof(*pgd));
}
next = pgd_addr_end(addr, end);
- err = create_hyp_pmd_mappings(pud, addr, next, pfn, prot);
+
+ err = create_hyp_pud_mappings(pgd, addr, next, pfn, prot);
+
if (err)
goto out;
pfn += (next - addr) PAGE_SHIFT;
@@ -563,6 +595,24 @@ void kvm_free_stage2_pgd(struct kvm *kvm)
kvm-arch.pgd = NULL;
}
+static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache
*cache,
+ phys_addr_t addr)
+{
+ pgd_t *pgd;
Re: [PATCH 2/8] arm/arm64: KVM: Fix line length exceeding 80 characters
On 15/04/14 01:38, Jungseok Lee wrote: On Tuesday, April 15, 2014 1:19 AM, Marc Zyngier wrote: On 14/04/14 08:40, Jungseok Lee wrote: This patch deals with checkpatch complaint as fixing line length exceeding 80 characters. WARNING: line over 80 characters Signed-off-by: Jungseok Lee jays@samsung.com Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com --- arch/arm/kvm/mmu.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 80bb1e6..e0d4f24 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -563,8 +563,8 @@ void kvm_free_stage2_pgd(struct kvm *kvm) kvm-arch.pgd = NULL; } -static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, -phys_addr_t addr) +static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache +*cache, phys_addr_t addr) Please don't. This makes the code unreadable (and no, I don't care about checkpatch ;-). Okay. I will drop this patch from the next version. It would be good to change stage2_set_pmd_huge function for readability if you don't care about checkpatch. We usually don't change that kind of thing just for the sake of changing it. It feels like fairly pointless churn. *IF* someone happens to rework that code, then they're welcome to fix it. M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/8] arm/arm64: KVM: Fix line length exceeding 80 characters
On 14/04/14 08:40, Jungseok Lee wrote: This patch deals with checkpatch complaint as fixing line length exceeding 80 characters. WARNING: line over 80 characters Signed-off-by: Jungseok Lee jays@samsung.com Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com --- arch/arm/kvm/mmu.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 80bb1e6..e0d4f24 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -563,8 +563,8 @@ void kvm_free_stage2_pgd(struct kvm *kvm) kvm-arch.pgd = NULL; } -static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, - phys_addr_t addr) +static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache + *cache, phys_addr_t addr) Please don't. This makes the code unreadable (and no, I don't care about checkpatch ;-). M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: This patch declare coretex-a7's irqchip to initialze gic from dt with arm,cortex-a7-gic data. Cc: Thomas Gleixner t...@linutronix.de Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/irqchip/irq-gic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4300b66..8e906e4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, arm,cortex-a15-gic, gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, arm,cortex-a9-gic, gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, arm,cortex-a7-gic, gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, qcom,msm-8660-qgic, gic_of_init); IRQCHIP_DECLARE(msm_qgic2, qcom,msm-qgic2, gic_of_init); Frankly, this patch adds no value. Are we going to add arm,cortex-a12-gic, arm,cortex-a17-gic, arm,cortex-a53-gic, arm,cortex-a57-gic? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic arm,gic property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. Mark, what do you think? I think this has been discussed in the past already. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:09:02 am BST, armdev armdev@gmail.com wrote: On 10-Apr-2014, at 3:34 pm, Marc Zyngier marc.zyng...@arm.com wrote: On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: This patch declare coretex-a7's irqchip to initialze gic from dt with arm,cortex-a7-gic data. Cc: Thomas Gleixner t...@linutronix.de Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/irqchip/irq-gic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4300b66..8e906e4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, arm,cortex-a15-gic, gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, arm,cortex-a9-gic, gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, arm,cortex-a7-gic, gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, qcom,msm-8660-qgic, gic_of_init); IRQCHIP_DECLARE(msm_qgic2, qcom,msm-qgic2, gic_of_init); Frankly, this patch adds no value. Are we going to add arm,cortex-a12-gic, arm,cortex-a17-gic, arm,cortex-a53-gic, arm,cortex-a57-gic? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic arm,gic property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. How about keeping it simple and tied to arm gic versions arm,gicv1, arm,gicv2, arm,gicv2ve That's a variation on the same theme. As for GICv2, we don't need to distinguish between having the Virtualization Extentions, the binding already allows you to tell one from the other. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:30:41 am BST, armdev armdev@gmail.com wrote: On 10-Apr-2014, at 3:51 pm, Marc Zyngier marc.zyng...@arm.com wrote: On Thu, Apr 10 2014 at 11:09:02 am BST, armdev armdev@gmail.com wrote: On 10-Apr-2014, at 3:34 pm, Marc Zyngier marc.zyng...@arm.com wrote: On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: This patch declare coretex-a7's irqchip to initialze gic from dt with arm,cortex-a7-gic data. Cc: Thomas Gleixner t...@linutronix.de Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/irqchip/irq-gic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4300b66..8e906e4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, arm,cortex-a15-gic, gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, arm,cortex-a9-gic, gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, arm,cortex-a7-gic, gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, qcom,msm-8660-qgic, gic_of_init); IRQCHIP_DECLARE(msm_qgic2, qcom,msm-qgic2, gic_of_init); Frankly, this patch adds no value. Are we going to add arm,cortex-a12-gic, arm,cortex-a17-gic, arm,cortex-a53-gic, arm,cortex-a57-gic? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic arm,gic property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. How about keeping it simple and tied to arm gic versions arm,gicv1, arm,gicv2, arm,gicv2ve That's a variation on the same theme. As for GICv2, we don't need to distinguish between having the Virtualization Extentions, the binding already allows you to tell one from the other. So if there be just 2 types of gic, it would be simple. Not exactly. We just happen to support two revisions of the GIC architecture with the same binding. GICv3 has an entierely separate binding. gicv1 - 2 address sets (gicc and gicd) Yes. gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right? No. The presence of the GICV, GICH and maintenance interrupt are indicative of the support for the Virtualization Extentions. GICv2 itself can perfectly be built without it. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:37:12 am BST, Chanho Park chanho61.p...@samsung.com wrote: Hi, -Original Message- From: linux-arm-kernel [mailto:linux-arm-kernel- boun...@lists.infradead.org] On Behalf Of Marc Zyngier Sent: Thursday, April 10, 2014 7:05 PM To: Chanwoo Choi Cc: mark.rutl...@arm.com; linux-samsung-soc@vger.kernel.org; t.f...@samsung.com; hyunhee@samsung.com; sw0312@samsung.com; linux-ker...@vger.kernel.org; yj44@samsung.com; inki@samsung.com; kyungmin.p...@samsung.com; kgene@samsung.com; Thomas Gleixner; linux-arm-ker...@lists.infradead.org Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: This patch declare coretex-a7's irqchip to initialze gic from dt with arm,cortex-a7-gic data. Cc: Thomas Gleixner t...@linutronix.de Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/irqchip/irq-gic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4300b66..8e906e4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, arm,cortex-a15-gic, gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, arm,cortex-a9-gic, gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, arm,cortex-a7-gic, gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, qcom,msm-8660-qgic, gic_of_init); IRQCHIP_DECLARE(msm_qgic2, qcom,msm-qgic2, gic_of_init); Frankly, this patch adds no value. Are we going to add arm,cortex-a12-gic, arm,cortex-a17-gic, arm,cortex-a53-gic, arm,cortex-a57-gic? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic arm,gic property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. I prefer it would be arm,gicv2 instead arm-gic. If you prefer, fine by me. Consider spelling it arm,gic-v2, which seems to be the current convention for version numbers. In case of GICv3 of arm64, it can be arm,gicv3. GICv3 and arm64 are independent of each other, and the binding has already been specified as arm,gic-v3. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:42:56 am BST, armdev armdev@gmail.com wrote: On 10-Apr-2014, at 4:11 pm, Marc Zyngier marc.zyng...@arm.com wrote: On Thu, Apr 10 2014 at 11:30:41 am BST, armdev armdev@gmail.com wrote: On 10-Apr-2014, at 3:51 pm, Marc Zyngier marc.zyng...@arm.com wrote: On Thu, Apr 10 2014 at 11:09:02 am BST, armdev armdev@gmail.com wrote: On 10-Apr-2014, at 3:34 pm, Marc Zyngier marc.zyng...@arm.com wrote: On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: This patch declare coretex-a7's irqchip to initialze gic from dt with arm,cortex-a7-gic data. Cc: Thomas Gleixner t...@linutronix.de Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/irqchip/irq-gic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4300b66..8e906e4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, arm,cortex-a15-gic, gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, arm,cortex-a9-gic, gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, arm,cortex-a7-gic, gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, qcom,msm-8660-qgic, gic_of_init); IRQCHIP_DECLARE(msm_qgic2, qcom,msm-qgic2, gic_of_init); Frankly, this patch adds no value. Are we going to add arm,cortex-a12-gic, arm,cortex-a17-gic, arm,cortex-a53-gic, arm,cortex-a57-gic? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic arm,gic property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. How about keeping it simple and tied to arm gic versions arm,gicv1, arm,gicv2, arm,gicv2ve That's a variation on the same theme. As for GICv2, we don't need to distinguish between having the Virtualization Extentions, the binding already allows you to tell one from the other. So if there be just 2 types of gic, it would be simple. Not exactly. We just happen to support two revisions of the GIC architecture with the same binding. GICv3 has an entierely separate binding. gicv1 - 2 address sets (gicc and gicd) Yes. gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right? No. The presence of the GICV, GICH and maintenance interrupt are indicative of the support for the Virtualization Extentions. GICv2 itself can perfectly be built without it. then does gicv2-ve makes sense ? Read what I just wrote. You find the GICV region, you have the VE extensions. You don't find them, they are not present. No need for an overloaded compatible string, they both conform to the same *Architecture Spec*. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: On 04/10/2014 06:51 PM, Marc Zyngier wrote: On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi cw00.c...@samsung.com wrote: This patch decide proper lowpower mode of either a15 or a9 according to own ID from Main ID register. Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/hotplug.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 5eead53..36d3db6 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu) int primary_part = 0; /* -* we're ready for shutdown now, so do it. -* Exynos4 is A9 based while Exynos5 is A15; check the CPU part +* we're ready for shutdown now, so do it. Exynos4 is A9 based +* while Exynos5 is A15/Exynos7 is A7; check the CPU part * number by reading the Main ID register and then perform the * appropriate sequence for entering low power. */ asm(mrc p15, 0, %0, c0, c0, 0 : =r(primary_part) : : cc); While you're touching that code, how about using: primary_part = read_cpuid(CPUID_ID); Or, I suggest read_cpuid_part_number() instead of assembler directly. primary_part = read_cpuid_part_number(); Yup, even better. - if ((primary_part 0xfff0) == 0xc0f0) + + /* +* Main ID register of Cortex series +* - Cortex-a7 : 0x410F_C07x +* - Cortex-a15 : 0x410F_C0Fx +*/ + primary_part = primary_part 0xfff0; + if (primary_part == 0xc0f0 || primary_part == 0xc070) ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7 OK I'll use this defined constant as following: switch (primary_part) case ARM_CPU_PART_CORTEX_A7: case ARM_CPU_PART_CORTEX_A15: cpu_enter_lowpower_a15(); break; default: cpu_enter_lowpower_a9(); break; } Looks good. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
On 11/02/14 23:36, Olof Johansson wrote:
Hi,
Besides what Mark Rutland already commented on:
On Mon, Feb 10, 2014 at 10:29 PM, Kukjin Kim kgene@samsung.com wrote:
+/ {
+ model = SAMSUNG GH7;
+ compatible = samsung,gh7;
Model and compatible in the dtsi should probably always be overridden
by a dts that includes it, so there's little use in having it here.
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
+
+ cpu@000 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 0x0 0x000;
No need to zero-pad cpu numbers in unit address or reg.
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@001 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 0x0 0x001;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@002 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 0x0 0x002;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@003 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 0x0 0x003;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ };
+
+ gic: interrupt-controller@1C00 {
+ compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
This looks incorrect -- you should at the very least have a more
specific one than a15-gic? Marc?
arm,cortex-a9-gic is definitely wrong (the A9 GIC doesn't have the
virt extensions). This binding matches what the A15 GIC has, so
arm,cortex-a15-gic is probably fine. Main issue here is that the GICv2
driver has no compatible string for anything else.
Should we define something more generic (like arm,gic-v2)? Or carry on
adding more compatible strings?
M.
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x0 0x1C001000 0 0x1000,/* GIC Dist */
+ 0x0 0x1C002000 0 0x1000,/* GIC CPU */
+ 0x0 0x1C004000 0 0x2000,/* GIC VCPU Control
*/
+ 0x0 0x1C006000 0 0x2000;/* GIC VCPU */
+ interrupts = 1 9 0xf04; /* GIC Maintenence IRQ */
+ };
--
Jazz is not dead. It just smells funny...
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