[PATCH V2 3/3] clk: samsung: exynos7: add clocks for audio block
Add required clk support for I2S,PCM amd SPDIF
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|9 ++
drivers/clk/samsung/clk-exynos7.c | 143 +++-
include/dt-bindings/clock/exynos7-clk.h| 24 +++-
3 files changed, 171 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 9282f71..6bf1e74 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -35,6 +35,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-fsys0
- samsung,exynos7-clock-fsys1
- samsung,exynos7-clock-mscl
+ - samsung,exynos7-clock-aud
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -54,6 +55,7 @@ Input clocks for top0 clock controller:
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+ - dout_sclk_aud_pll
Input clocks for top1 clock controller:
- fin_pll
@@ -82,6 +84,9 @@ Input clocks for peric1 clock controller:
- sclk_spi2
- sclk_spi3
- sclk_spi4
+ - sclk_i2s1
+ - sclk_pcm1
+ - sclk_spdif
Input clocks for peris clock controller:
- fin_pll
@@ -97,3 +102,7 @@ Input clocks for fsys1 clock controller:
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+ - fin_pll
+ - fout_aud_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index d40c09d..03d36e8 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -46,6 +46,7 @@ static struct samsung_fixed_factor_clock
topc_fixed_factor_clks[] __initdata = {
};
/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_aud_pll_ctrl_p) = { fin_pll, fout_aud_pll };
PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
@@ -105,6 +106,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, mout_aud_pll_ctrl, mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -129,6 +131,13 @@ static struct samsung_div_clock topc_div_clks[] __initdata
= {
DIV_TOPC3, 12, 3),
DIV(DOUT_SCLK_MFC_PLL, dout_sclk_mfc_pll, mout_mfc_pll_ctrl,
DIV_TOPC3, 16, 3),
+ DIV(DOUT_SCLK_AUD_PLL, dout_sclk_aud_pll, mout_aud_pll_ctrl,
+ DIV_TOPC3, 28, 3),
+};
+
+static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
+ PLL_36XX_RATE(49152, 20, 1, 0, 31457),
+ {},
};
static struct samsung_gate_clock topc_gate_clks[] __initdata = {
@@ -145,8 +154,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata
= {
BUS1_DPLL_CON0, NULL),
PLL(pll_1452x, 0, fout_mfc_pll, fin_pll, MFC_PLL_LOCK,
MFC_PLL_CON0, NULL),
- PLL(pll_1460x, 0, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
- AUD_PLL_CON0, NULL),
+ PLL(pll_1460x, FOUT_AUD_PLL, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
+ AUD_PLL_CON0, pll1460x_24mhz_tbl),
};
static struct samsung_cmu_info topc_cmu_info __initdata = {
@@ -177,13 +186,16 @@ CLK_OF_DECLARE(exynos7_clk_topc,
samsung,exynos7-clock-topc,
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC00x0230
#define MUX_SEL_TOP0_PERIC10x0234
#define MUX_SEL_TOP0_PERIC20x0238
#define MUX_SEL_TOP0_PERIC30x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC00x0630
#define DIV_TOP0_PERIC10x0634
#define DIV_TOP0_PERIC20x0638
#define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC00x0A30
#define ENABLE_SCLK_TOP0_PERIC10x0A34
#define ENABLE_SCLK_TOP0_PERIC20x0A38
#define ENABLE_SCLK_TOP0_PERIC30x0A3C
@@ -193,6 +205,7 @@ PNAME(mout_bus0_pll_p) = { fin_pll,
dout_sclk_bus0_pll };
PNAME(mout_bus1_pll_p) = { fin_pll, dout_sclk_bus1_pll };
PNAME(mout_cc_pll_p) = { fin_pll, dout_sclk_cc_pll };
PNAME(mout_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll };
+PNAME(mout_aud_pll_p) = { fin_pll, dout_sclk_aud_pll };
PNAME(mout_top0_half_bus0_pll_p) = {mout_top0_bus0_pll,
ffac_top0_bus0_pll_div2};
@@ -206,24 +219,34 @@ PNAME
[PATCH V2 2/3] clk: samsung: exynos7: add clocks for SPI block
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|5 ++
drivers/clk/samsung/clk-exynos7.c | 73
include/dt-bindings/clock/exynos7-clk.h| 19 +-
3 files changed, 95 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index d0e048c..9282f71 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -77,6 +77,11 @@ Input clocks for peric1 clock controller:
- sclk_uart1
- sclk_uart2
- sclk_uart3
+ - sclk_spi0
+ - sclk_spi1
+ - sclk_spi2
+ - sclk_spi3
+ - sclk_spi4
Input clocks for peris clock controller:
- fin_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index d01d766..d40c09d 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -177,9 +177,15 @@ CLK_OF_DECLARE(exynos7_clk_topc,
samsung,exynos7-clock-topc,
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC10x0234
+#define MUX_SEL_TOP0_PERIC20x0238
#define MUX_SEL_TOP0_PERIC30x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC10x0634
+#define DIV_TOP0_PERIC20x0638
#define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC10x0A34
+#define ENABLE_SCLK_TOP0_PERIC20x0A38
#define ENABLE_SCLK_TOP0_PERIC30x0A3C
/* List of parent clocks for Muxes in CMU_TOP0 */
@@ -205,9 +211,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC1,
+ MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+ DIV_TOP0_PERIC1,
+ DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC1,
+ ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
@@ -229,10 +241,16 @@ static struct samsung_mux_clock top0_mux_clks[]
__initdata = {
MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+ MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+ MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+ MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+ MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+ MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
};
static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -241,13 +259,29 @@ static struct samsung_div_clock top0_div_clks[]
__initdata = {
DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
DIV_TOP03, 20, 6),
+ DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
+ DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
+
+ DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
+ DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
+ DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
};
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+ GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
+ ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
+ ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
+ ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
+ ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, sclk_uart2
[PATCH V2 0/3] Add clk support for PDMA, SPI and audio on Exynos7
Add PDMA0,PDMA1 gate clock, required clks for 5 SPI channels and for clks in audio block. This patchset is dependent on usb clk support from Vivek in below link. http://www.spinics.net/lists/linux-samsung-soc/msg39342.html Changes since V1: - Added documentation for source clks of peric1 block. - Changed the parent of sclk_i2s1_user,sclk_pcm1_user and sclk_spdif_user from divider clk to gate clk. - Removed unused clk IDs Padmavathi Venna (3): clk: samsung: exynos7: add gate clock for DMA block clk: samsung: exynos7: add clocks for SPI block clk: samsung: exynos7: add clocks for audio block .../devicetree/bindings/clock/exynos7-clock.txt| 14 ++ drivers/clk/samsung/clk-exynos7.c | 220 +++- include/dt-bindings/clock/exynos7-clk.h| 43 - 3 files changed, 271 insertions(+), 6 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] clk: samsung: exynos7: add gate clock for DMA block
Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c |4
include/dt-bindings/clock/exynos7-clk.h |4 +++-
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 945f41c..d01d766 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -722,6 +722,10 @@ static struct samsung_gate_clock fsys0_gate_clks[]
__initdata = {
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, aclk_axius_usbdrd30x_fsys0x,
mout_aclk_fsys0_200_user,
ENABLE_ACLK_FSYS00, 19, 0, 0),
+ GATE(ACLK_PDMA1, aclk_pdma1, mout_aclk_fsys0_200_user,
+ ENABLE_ACLK_FSYS00, 3, 0, 0),
+ GATE(ACLK_PDMA0, aclk_pdma0, mout_aclk_fsys0_200_user,
+ ENABLE_ACLK_FSYS00, 4, 0, 0),
GATE(ACLK_USBDRD300, aclk_usbdrd300, mout_aclk_fsys0_200_user,
ENABLE_ACLK_FSYS01, 29, 0, 0),
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index e33d0ca..05e2a47 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -91,7 +91,9 @@
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER7
#define OSCCLK_PHY_CLKOUT_USB30_PHY8
-#define FSYS0_NR_CLK 9
+#define ACLK_PDMA0 9
+#define ACLK_PDMA1 10
+#define FSYS0_NR_CLK 11
/* FSYS1 */
#define ACLK_MMC1 1
--
1.7.4.4
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[PATCH 0/2] Add pinctrl support for audio IPs on exynos7
Audio interface IPs I2S, PCM and SPDIF on Exynos7 requires GPIOs available on AUD and BUS0 pin controller blocks. So add support for all. This patchset is dependent on BUS1 pin control support from Vivek in the below link https://patchwork.kernel.org/patch/5467321/ Padmavathi Venna (2): pinctrl: exynos: Add AUDIO pin controller for exynos7 arm64: dts: Add pinctrl support for audio IPs on exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |1 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 56 arch/arm64/boot/dts/exynos/exynos7.dtsi|7 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 10 4 files changed, 74 insertions(+), 0 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] arm64: dts: Add pinctrl support for audio IPs on exynos7
Add pinctrl support for I2S,PCM,SPDIF
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 56 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi |7 +++
2 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index c367f0a..a5aeb07 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -333,6 +333,29 @@
samsung,pin-pud = 3;
samsung,pin-drv = 0;
};
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = gpd4-0, gpd4-1, gpd4-2,
+ gpd4-3, gpd4-4;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = gpd4-0, gpd4-2,
+ gpd4-3, gpd4-4;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = gpd4-3, gpd4-4;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
};
pinctrl_bus1 {
@@ -668,3 +691,36 @@
samsung,pin-drv = 2;
};
};
+
+pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = gpz0-0, gpz0-1, gpz0-2, gpz0-3,
+ gpz0-4;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = gpz1-0, gpz1-1, gpz1-2, gpz1-3;
+ samsung,pin-function = 5;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index e633b02..eeaa9b8d 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -27,6 +27,7 @@
pinctrl6 = pinctrl_fsys0;
pinctrl7 = pinctrl_fsys1;
pinctrl8 = pinctrl_bus1;
+ pinctrl9 = pinctrl_aud;
};
cpus {
@@ -285,6 +286,12 @@
interrupts = 0 203 0;
};
+ pinctrl_aud: pinctrl@114b {
+ compatible = samsung,exynos7-pinctrl;
+ reg = 0x114b 0x1000;
+ interrupts = 0 92 0;
+ };
+
hsi2c_0: hsi2c@1364 {
compatible = samsung,exynos7-hsi2c;
reg = 0x1364 0x1000;
--
1.7.4.4
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[PATCH 1/2] pinctrl: exynos: Add AUDIO pin controller for exynos7
Audio IPs on Exynos7 require gpios available in AUDIO
pin controller block. So adding the AUDIO pinctrl support.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 10 ++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index c88ba35..9d2a995 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -181,6 +181,7 @@ Aliases for controllers compatible with
samsung,exynos7-pinctrl:
- pinctrl6: pin controller of FSYS0 block,
- pinctrl7: pin controller of FSYS1 block,
- pinctrl8: pin controller of BUS1 block,
+- pinctrl9: pin controller of AUDIO block,
Example: A pin-controller node with pin banks:
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 2a85cb4..c8f83f9 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1314,6 +1314,11 @@ static const struct samsung_pin_bank_data
exynos7_pin_banks8[] __initconst = {
EXYNOS_PIN_BANK_EINTG(3, 0x140, gpv6, 0x24),
};
+static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 Alive data */
@@ -1361,5 +1366,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[]
__initconst = {
.pin_banks = exynos7_pin_banks8,
.nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
.eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 9 AUD data */
+ .pin_banks = exynos7_pin_banks9,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
+ .eint_gpio_init = exynos_eint_gpio_init,
},
};
--
1.7.4.4
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[PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7
Add PDMA0,PDMA1 gate clock and required clks for 5 SPI channels. Also enable the support for PDMA and 5 SPI channels in DT. This patchset is dependent on usb clk support from Vivek in below link. http://www.spinics.net/lists/linux-samsung-soc/msg39342.html Padmavathi Venna (4): clk: samsung: exynos7: add gate clock for DMA block clk: samsung: exynos7: add clocks for SPI block clk: samsung: exynos7: add clocks for audio block arm64: dts: Add PDMA and SPI device tree node for exynos7 .../devicetree/bindings/clock/exynos7-clock.txt|6 + arch/arm64/boot/dts/exynos/exynos7.dtsi| 113 ++ drivers/clk/samsung/clk-exynos7.c | 221 +++- include/dt-bindings/clock/exynos7-clk.h| 46 - 4 files changed, 380 insertions(+), 6 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 73 +++
include/dt-bindings/clock/exynos7-clk.h | 22 -
2 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 954f9a0..cf5e50e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc,
samsung,exynos7-clock-topc,
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC10x0234
+#define MUX_SEL_TOP0_PERIC20x0238
#define MUX_SEL_TOP0_PERIC30x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC10x0634
+#define DIV_TOP0_PERIC20x0638
#define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC10x0A34
+#define ENABLE_SCLK_TOP0_PERIC20x0A38
#define ENABLE_SCLK_TOP0_PERIC30x0A3C
/* List of parent clocks for Muxes in CMU_TOP0 */
@@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC1,
+ MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+ DIV_TOP0_PERIC1,
+ DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC1,
+ ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
@@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[]
__initdata = {
MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+ MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+ MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+ MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+ MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+ MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
};
static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[]
__initdata = {
DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
DIV_TOP03, 20, 6),
+ DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
+ DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
+
+ DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
+ DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
+ DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
};
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+ GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
+ ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
+ ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
+ ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
+ ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, sclk_uart2, dout_sclk_uart2,
@@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[]
__initdata = {
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
GATE(CLK_SCLK_UART0, sclk_uart0, dout_sclk_uart0,
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+ GATE(CLK_SCLK_SPI4, sclk_spi4, dout_sclk_spi4,
+ ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
};
static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata =
{
@@ -520,6 +556,7 @@ static void __init exynos7_clk_peric0_init(struct
device_node *np)
/* Register Offset definitions for CMU_PERIC1 (0x14C8) */
#define MUX_SEL_PERIC100x0200
#define
[PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
Add required clk support for I2S,PCM amd SPDIF
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 144 +++-
include/dt-bindings/clock/exynos7-clk.h| 24 +++-
3 files changed, 169 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f8..3b439ed 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-peris
- samsung,exynos7-clock-fsys0
- samsung,exynos7-clock-fsys1
+ - samsung,exynos7-clock-aud
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -53,6 +54,7 @@ Input clocks for top0 clock controller:
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+ - dout_sclk_aud_pll
Input clocks for top1 clock controller:
- fin_pll
@@ -91,3 +93,7 @@ Input clocks for fsys1 clock controller:
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+ - fin_pll
+ - fout_aud_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index cf5e50e..e4bc241 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -45,6 +45,7 @@ static struct samsung_fixed_factor_clock
topc_fixed_factor_clks[] __initdata = {
};
/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_aud_pll_ctrl_p) = { fin_pll, fout_aud_pll };
PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
@@ -104,6 +105,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, mout_aud_pll_ctrl, mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -125,6 +127,13 @@ static struct samsung_div_clock topc_div_clks[] __initdata
= {
DIV_TOPC3, 12, 3),
DIV(DOUT_SCLK_MFC_PLL, dout_sclk_mfc_pll, mout_mfc_pll_ctrl,
DIV_TOPC3, 16, 3),
+ DIV(DOUT_SCLK_AUD_PLL, dout_sclk_aud_pll, mout_aud_pll_ctrl,
+ DIV_TOPC3, 28, 3),
+};
+
+static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
+ PLL_36XX_RATE(49152, 20, 1, 0, 31457),
+ {},
};
static struct samsung_pll_clock topc_pll_clks[] __initdata = {
@@ -136,8 +145,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata
= {
BUS1_DPLL_CON0, NULL),
PLL(pll_1452x, 0, fout_mfc_pll, fin_pll, MFC_PLL_LOCK,
MFC_PLL_CON0, NULL),
- PLL(pll_1460x, 0, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
- AUD_PLL_CON0, NULL),
+ PLL(pll_1460x, FOUT_AUD_PLL, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
+ AUD_PLL_CON0, pll1460x_24mhz_tbl),
};
static struct samsung_cmu_info topc_cmu_info __initdata = {
@@ -166,13 +175,16 @@ CLK_OF_DECLARE(exynos7_clk_topc,
samsung,exynos7-clock-topc,
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC00x0230
#define MUX_SEL_TOP0_PERIC10x0234
#define MUX_SEL_TOP0_PERIC20x0238
#define MUX_SEL_TOP0_PERIC30x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC00x0630
#define DIV_TOP0_PERIC10x0634
#define DIV_TOP0_PERIC20x0638
#define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC00x0A30
#define ENABLE_SCLK_TOP0_PERIC10x0A34
#define ENABLE_SCLK_TOP0_PERIC20x0A38
#define ENABLE_SCLK_TOP0_PERIC30x0A3C
@@ -182,6 +194,8 @@ PNAME(mout_bus0_pll_p) = { fin_pll,
dout_sclk_bus0_pll };
PNAME(mout_bus1_pll_p) = { fin_pll, dout_sclk_bus1_pll };
PNAME(mout_cc_pll_p) = { fin_pll, dout_sclk_cc_pll };
PNAME(mout_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll };
+PNAME(mout_aud_pll_p) = { fin_pll, dout_sclk_aud_pll };
+
PNAME(mout_top0_half_bus0_pll_p) = {mout_top0_bus0_pll,
ffac_top0_bus0_pll_div2};
@@ -195,24 +209,34 @@ PNAME(mout_top0_half_mfc_pll_p) = {mout_top0_mfc_pll,
PNAME(mout_top0_group1) = {mout_top0_half_bus0_pll,
mout_top0_half_bus1_pll, mout_top0_half_cc_pll,
mout_top0_half_mfc_pll};
+PNAME(mout_top0_group3) = {ioclk_audiocdclk0
[PATCH 4/4] arm64: dts: Add PDMA and SPI device tree node for exynos7
Add PDMA0,PDMA1 and 5 SPI dt nodes for Exynos7.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 113 +++
1 files changed, 113 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index eeaa9b8d..db7058a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -28,6 +28,9 @@
pinctrl7 = pinctrl_fsys1;
pinctrl8 = pinctrl_bus1;
pinctrl9 = pinctrl_aud;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
};
cpus {
@@ -573,6 +576,116 @@
samsung,pmu-syscon = pmu_system_controller;
#phy-cells = 1;
};
+
+ amba {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = arm,amba-bus;
+ interrupt-parent = gic;
+ ranges;
+
+ pdma1: pdma1@10EB {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x10EB 0x1000;
+ interrupts = 0 226 0;
+ clocks = clock_fsys0 ACLK_PDMA1;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma0: pdma0@10E1 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x10E1 0x1000;
+ interrupts = 0 225 0;
+ clocks = clock_fsys0 ACLK_PDMA0;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+ };
+
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 464 0;
+ dmas = pdma0 7
+ pdma0 6;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI0, clock_peric1
SCLK_SPI0;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ status = disabled;
+ };
+
+ spi_1: spi@14d3 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d3 0x100;
+ interrupts = 0 465 0;
+ dmas = pdma0 9
+ pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI1, clock_peric1
SCLK_SPI1;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi1_bus;
+ status = disabled;
+ };
+
+ spi_2: spi@14d4 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d4 0x100;
+ interrupts = 0 466 0;
+ dmas = pdma0 11
+ pdma0 10;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI2, clock_peric1
SCLK_SPI2;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi2_bus;
+ status = disabled;
+ };
+
+ spi_3: spi@14d5 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d5 0x100;
+ interrupts = 0 467 0;
+ dmas = pdma0 13
+ pdma0 12;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI3, clock_peric1
SCLK_SPI3;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi3_bus;
+ status = disabled;
+ };
+
+ spi_4
[PATCH] clk: samsung: exynos7: Fix fsys NR_CLK
Fix typo in fsys0 and fsys1 NR_CLK assignment
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3128593..3a56875 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -742,7 +742,7 @@ static struct samsung_cmu_info fsys0_cmu_info __initdata = {
.nr_mux_clks= ARRAY_SIZE(fsys0_mux_clks),
.gate_clks = fsys0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
- .nr_clk_ids = TOP1_NR_CLK,
+ .nr_clk_ids = FSYS0_NR_CLK,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs= ARRAY_SIZE(fsys0_clk_regs),
};
@@ -793,7 +793,7 @@ static struct samsung_cmu_info fsys1_cmu_info __initdata = {
.nr_mux_clks= ARRAY_SIZE(fsys1_mux_clks),
.gate_clks = fsys1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
- .nr_clk_ids = TOP1_NR_CLK,
+ .nr_clk_ids = FSYS1_NR_CLK,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs= ARRAY_SIZE(fsys1_clk_regs),
};
--
1.7.4.4
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[PATCH] arm64: dts: exynos7: Fix wrong base address of i2c7 bus
I2C7 base address corrected.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7.dtsi |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index db7058a..84a57c8 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -386,9 +386,9 @@
status = disabled;
};
- hsi2c_7: hsi2c@13e1 {
+ hsi2c_7: hsi2c@14e1 {
compatible = samsung,exynos7-hsi2c;
- reg = 0x13e1 0x1000;
+ reg = 0x14e1 0x1000;
interrupts = 0 462 0;
#address-cells = 1;
#size-cells = 0;
--
1.7.4.4
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[PATCH] dmaengine: pl330: Set residue in tx_status callback
Fill txstate.residue with the amount of bytes remaining in the current
transfer if the transfer is not complete. This will be of particular
use to i2s DMA transfers, providing more accurate hw_ptr values to ASoC.
I had taken the code from Dylan Reid dgr...@chromium.org patch from the
below link and modified according to the current dmaengine framework.
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/23007
Cc: Dylan Reid dgr...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This patch has been tested for audio playback on exynos5420 peach-pit.
drivers/dma/pl330.c | 67 +-
1 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index b7493d2..db880ae 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2182,11 +2182,74 @@ static void pl330_free_chan_resources(struct dma_chan
*chan)
pm_runtime_put_autosuspend(pch-dmac-ddma.dev);
}
+static inline int
+pl330_src_addr_in_desc(struct dma_pl330_desc *desc, unsigned int sar)
+{
+ return ((desc-px.src_addr = sar)
+ (sar = (desc-px.src_addr + desc-px.bytes)));
+}
+
+static inline int
+pl330_dst_addr_in_desc(struct dma_pl330_desc *desc, unsigned int dar)
+{
+ return ((desc-px.dst_addr = dar)
+ (dar = (desc-px.dst_addr + desc-px.bytes)));
+}
+
static enum dma_status
pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
- return dma_cookie_status(chan, cookie, txstate);
+ dma_addr_t sar, dar;
+ struct dma_pl330_chan *pch = to_pchan(chan);
+ void __iomem *regs = pch-dmac-base;
+ struct pl330_thread *thrd = pch-thread;
+ struct dma_pl330_desc *desc;
+ unsigned int residue = 0;
+ unsigned long flags;
+ bool first = true;
+ dma_cookie_t first_c, current_c;
+ dma_cookie_t used;
+ enum dma_status ret;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+ list_for_each_entry(desc, pch-work_list, node) {
+ if (desc-status == BUSY) {
+ current_c = desc-txd.cookie;
+ if (first) {
+ first_c = desc-txd.cookie;
+ first = false;
+ }
+
+ if (first_c current_c)
+ residue += desc-px.bytes;
+ else {
+ if (desc-rqcfg.src_inc
pl330_src_addr_in_desc(desc, sar)) {
+ residue += desc-px.bytes;
+ residue -= sar - desc-px.src_addr;
+ } else if (desc-rqcfg.dst_inc
pl330_dst_addr_in_desc(desc, dar)) {
+ residue += desc-px.bytes;
+ residue -= dar - desc-px.dst_addr;
+ }
+ }
+ } else if (desc-status == PREP)
+ residue += desc-px.bytes;
+
+ if (desc-txd.cookie == used)
+ break;
+ }
+ spin_unlock_irqrestore(pch-lock, flags);
+ dma_set_residue(txstate, residue);
+ return ret;
}
static void pl330_issue_pending(struct dma_chan *chan)
@@ -2631,7 +2694,7 @@ static int pl330_dma_device_slave_caps(struct dma_chan
*dchan,
caps-directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
caps-cmd_pause = false;
caps-cmd_terminate = true;
- caps-residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ caps-residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
return 0;
}
--
1.7.4.4
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[PATCH] ASoC: samsung: In the i2s_set_sysclk() callback we are currently clearing all bits of the IISMOD register in i2s_set_sysclk. It's due to an incorrect mask used for the AND operation which is i
Cc: Sylwester Nawrocki s.nawro...@samsung.com Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com Signed-off-by: Padmavathi Venna padm...@samsung.com --- sound/soc/samsung/i2s.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index 0df6547..e1ace52 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c @@ -494,7 +494,7 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai, if (dir == SND_SOC_CLOCK_IN) mod |= 1 i2s_regs-cdclkcon_off; else - mod = 0 i2s_regs-cdclkcon_off; + mod = ~(1 i2s_regs-cdclkcon_off); i2s-rfs = rfs; break; @@ -551,10 +551,11 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai, } if (clk_id == 0) - mod = 0 i2s_regs-rclksrc_off; + mod = ~(1 i2s_regs-rclksrc_off); else mod |= 1 i2s_regs-rclksrc_off; + break; default: dev_err(i2s-pdev-dev, We don't serve that!\n); return -EINVAL; -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: samsung: ASoC: samsung: Fix IISMOD setting in i2s_set_sysclk()
In the i2s_set_sysclk() callback we are currently clearing all bits of the IISMOD register in i2s_set_sysclk. It's due to an incorrect mask used for the AND operation which is introduced in commit a5a56871f804edac93a53b5e871c0e9818fb9033 (ASoC: samsung: add support for exynos7 I2S controller) and also adds the missing break statement. Cc: Sylwester Nawrocki s.nawro...@samsung.com Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com Signed-off-by: Padmavathi Venna padm...@samsung.com --- sound/soc/samsung/i2s.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index 0df6547..e1ace52 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c @@ -494,7 +494,7 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai, if (dir == SND_SOC_CLOCK_IN) mod |= 1 i2s_regs-cdclkcon_off; else - mod = 0 i2s_regs-cdclkcon_off; + mod = ~(1 i2s_regs-cdclkcon_off); i2s-rfs = rfs; break; @@ -551,10 +551,11 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai, } if (clk_id == 0) - mod = 0 i2s_regs-rclksrc_off; + mod = ~(1 i2s_regs-rclksrc_off); else mod |= 1 i2s_regs-rclksrc_off; + break; default: dev_err(i2s-pdev-dev, We don't serve that!\n); return -EINVAL; -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] spi: s3c64xx: add support for exynos7 SPI controller
Exynos7 SPI controller supports only the auto Selection of
CS toggle mode and Exynos7 SoC includes six SPI controllers.
Add support for these changes in Exynos7 SPI controller driver.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/spi/spi-samsung.txt|2 +-
drivers/spi/Kconfig|2 +-
drivers/spi/spi-s3c64xx.c | 32 ---
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt
b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 1e8a857..6dbdeb3 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -9,7 +9,7 @@ Required SoC Specific Properties:
- samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
- samsung,s3c6410-spi: for s3c6410 platforms
- samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
-- samsung,exynos4210-spi: for exynos4 and exynos5 platforms
+- samsung,exynos7-spi: for exynos7 platforms
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 84e7c9e..de2d33d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -444,7 +444,7 @@ config SPI_S3C24XX_FIQ
config SPI_S3C64XX
tristate Samsung S3C64XX series type SPI
- depends on PLAT_SAMSUNG
+ depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
select S3C64XX_PL080 if ARCH_S3C64XX
help
SPI driver for Samsung S3C64XX and newer SoCs.
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 480133e..59e07cf 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -33,8 +33,9 @@
#include linux/platform_data/spi-s3c64xx.h
-#define MAX_SPI_PORTS 3
+#define MAX_SPI_PORTS 6
#define S3C64XX_SPI_QUIRK_POLL (1 0)
+#define S3C64XX_SPI_QUIRK_CS_AUTO (1 1)
/* Registers and bit-fields */
@@ -78,6 +79,7 @@
#define S3C64XX_SPI_SLAVE_AUTO (11)
#define S3C64XX_SPI_SLAVE_SIG_INACT(10)
+#define S3C64XX_SPI_SLAVE_NSC_CNT_2(24)
#define S3C64XX_SPI_INT_TRAILING_EN(16)
#define S3C64XX_SPI_INT_RX_OVERRUN_EN (15)
@@ -717,7 +719,12 @@ static int s3c64xx_spi_transfer_one(struct spi_master
*master,
enable_datapath(sdd, spi, xfer, use_dma);
/* Start the signals */
- writel(0, sdd-regs + S3C64XX_SPI_SLAVE_SEL);
+ if (!(sdd-port_conf-quirks S3C64XX_SPI_QUIRK_CS_AUTO))
+ writel(0, sdd-regs + S3C64XX_SPI_SLAVE_SEL);
+ else
+ writel(readl(sdd-regs + S3C64XX_SPI_SLAVE_SEL)
+ | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2,
+ sdd-regs + S3C64XX_SPI_SLAVE_SEL);
spin_unlock_irqrestore(sdd-lock, flags);
@@ -866,13 +873,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
}
pm_runtime_put(sdd-pdev-dev);
- writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd-regs + S3C64XX_SPI_SLAVE_SEL);
+ if (!(sdd-port_conf-quirks S3C64XX_SPI_QUIRK_CS_AUTO))
+ writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd-regs +
S3C64XX_SPI_SLAVE_SEL);
return 0;
setup_exit:
pm_runtime_put(sdd-pdev-dev);
/* setup() returns with device de-selected */
- writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd-regs + S3C64XX_SPI_SLAVE_SEL);
+ if (!(sdd-port_conf-quirks S3C64XX_SPI_QUIRK_CS_AUTO))
+ writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd-regs +
S3C64XX_SPI_SLAVE_SEL);
if (gpio_is_valid(spi-cs_gpio))
gpio_free(spi-cs_gpio);
@@ -946,7 +955,8 @@ static void s3c64xx_spi_hwinit(struct
s3c64xx_spi_driver_data *sdd, int channel)
sdd-cur_speed = 0;
- writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd-regs + S3C64XX_SPI_SLAVE_SEL);
+ if (!(sdd-port_conf-quirks S3C64XX_SPI_QUIRK_CS_AUTO))
+ writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd-regs +
S3C64XX_SPI_SLAVE_SEL);
/* Disable Interrupts - we use Polling if not DMA mode */
writel(0, regs + S3C64XX_SPI_INT_EN);
@@ -1341,6 +1351,15 @@ static struct s3c64xx_spi_port_config
exynos5440_spi_port_config = {
.quirks = S3C64XX_SPI_QUIRK_POLL,
};
+static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .high_speed = true,
+ .clk_from_cmu = true,
+ .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
+};
+
static struct platform_device_id s3c64xx_spi_driver_ids[] = {
{
.name = s3c2443-spi,
@@ -1374,6 +1393,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] =
{
{ .compatible = samsung,exynos5440-spi
[PATCH 0/2] add support for exynos7 I2S controller
I2S on exynos7 includes the below changes - has got support for lower root clock sampling frequencies like 64, 128, 96, 192fs. I2S on previous SoCs supports only 256,512,384 and 768. - supports 7.1CH TDM mode for recording. exynos5 has only 7.1CH TDM mode for playback. - secondary dai works with only external DMA. on previous SoCs secondary dai can work with either both or only internal DMA. - I2S1 controller upgraded to 5.1CH with slighlty modified bit offsets for supporting lower RFS and more no.of BFS values. As internal dma is not mandatory on all SoCs this patchset introduced a quirk for the same and added a structure to hold all the modified bit offsets across all SoCs. This patchset is made based on linux-next master branch and tested with exynos7 base support from the below link. http://www.spinics.net/lists/linux-samsung-soc/msg37047.html Padmavathi Venna (2): ASoC: Samsung: Add quirk for internal DMA ASoC: samsung: add support for exynos7 I2S controller .../devicetree/bindings/sound/samsung-i2s.txt | 15 +- include/linux/platform_data/asoc-s3c.h |1 + sound/soc/samsung/Kconfig |2 +- sound/soc/samsung/i2s-regs.h | 10 +- sound/soc/samsung/i2s.c| 228 ++-- 5 files changed, 180 insertions(+), 76 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ASoC: Samsung: Add quirk for internal DMA
Internal DMA is available only on some of Samsung platforms.
So added a quirk for the same and made it optional.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s.c| 12 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index a6591c6..5e0bc77 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -27,6 +27,7 @@ struct samsung_i2s {
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
#define QUIRK_SUPPORTS_TDM (1 4)
+#define QUIRK_SUPPORTS_IDMA(1 5)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 9d51347..38b9a52 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -987,7 +987,7 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
if (i2s-quirks QUIRK_NEED_RSTCLR)
writel(CON_RSTCLR, i2s-addr + I2SCON);
- if (i2s-quirks QUIRK_SEC_DAI)
+ if (i2s-quirks QUIRK_SUPPORTS_IDMA)
idma_reg_addr_init(i2s-addr,
i2s-sec_dai-idma_playback.dma_addr);
@@ -1199,10 +1199,9 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
quirks = i2s_dai_data-quirks;
if (of_property_read_u32(np, samsung,idma-addr,
idma_addr)) {
- if (quirks QUIRK_SEC_DAI) {
- dev_err(pdev-dev, idma address is not\
+ if (quirks QUIRK_SUPPORTS_IDMA) {
+ dev_info(pdev-dev, idma address is not\
specified);
- return -EINVAL;
}
}
}
@@ -1309,13 +1308,14 @@ static const struct samsung_i2s_dai_data i2sv3_dai_type
= {
static const struct samsung_i2s_dai_data i2sv5_dai_type = {
.dai_type = TYPE_PRI,
- .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
+ .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
+ QUIRK_SUPPORTS_IDMA,
};
static const struct samsung_i2s_dai_data i2sv6_dai_type = {
.dai_type = TYPE_PRI,
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
- QUIRK_SUPPORTS_TDM,
+ QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
};
static const struct samsung_i2s_dai_data samsung_dai_type_pri = {
--
1.7.4.4
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[PATCH 2/2] ASoC: samsung: add support for exynos7 I2S controller
Exynos7 I2S controller has no internal dma, supports more
no. of root clock sampling frequencies and has more no.of Rx
fifos to support 7.1CH recording in TDM mode. Due to more no.
of root clock frequency values some of the bit offsets got
shifted up by one. Also I2S1 on previous Samsung platforms
uses v3 dai type but on Exynos7 it is upgraded to v5 with
slightly modified register offsets for supporting more no.of
RFS values. Due to the above changes, the driver has to be
modified to handle all versions of I2S controller. For this
I introduced a new structure to hold modified bit offsets and
masks which is passed as dai data.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 15 +-
sound/soc/samsung/Kconfig |2 +-
sound/soc/samsung/i2s-regs.h | 10 +-
sound/soc/samsung/i2s.c| 218 ++--
4 files changed, 174 insertions(+), 71 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 7386d44..d188296 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -6,10 +6,17 @@ Required SoC Specific Properties:
- samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
secondary fifo, s/w reset control and internal mux for root clk src.
- - samsung,exynos5420-i2s: for 8/16/24bit multichannel(7.1) I2S with
- secondary fifo, s/w reset control, internal mux for root clk src and
- TDM support. TDM (Time division multiplexing) is to allow transfer of
- multiple channel audio data on single data line.
+ - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
+ playback, sterio channel capture, secondary fifo using internal
+ or external dma, s/w reset control, internal mux for root clk src
+ and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
+ is to allow transfer of multiple channel audio data on single data line.
+ - samsung,exynos7-i2s: with all the available features of exynos5 i2s,
+ exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo
+ with only external dma and more no.of root clk sampling frequencies.
+ - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
+ stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with
+ slightly modified bit offsets.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 55a3869..e0e737f 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,6 +1,6 @@
config SND_SOC_SAMSUNG
tristate ASoC support for Samsung
- depends on PLAT_SAMSUNG
+ depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
depends on S3C64XX_PL080 || !ARCH_S3C64XX
depends on S3C24XX_DMAC || !ARCH_S3C24XX
select SND_SOC_GENERIC_DMAENGINE_PCM
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index 821a502..9170c31 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -33,8 +33,9 @@
#define I2SLVL3ADDR0x3c
#define I2SSTR10x40
#define I2SVER 0x44
-#define I2SFIC20x48
+#define I2SFIC10x48
#define I2STDM 0x4c
+#define I2SFSTA0x50
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -93,8 +94,6 @@
#define MOD_BLC_24BIT (2 13)
#define MOD_BLC_MASK (3 13)
-#define MOD_IMS_SYSMUX (1 10)
-#define MOD_SLAVE (1 11)
#define MOD_TXONLY (0 8)
#define MOD_RXONLY (1 8)
#define MOD_TXRX (2 8)
@@ -132,7 +131,10 @@
#define EXYNOS5420_MOD_BCLK_256FS 8
#define EXYNOS5420_MOD_BCLK_MASK 0xf
-#define MOD_CDCLKCON (1 12)
+#define EXYNOS7_MOD_RCLK_64FS 4
+#define EXYNOS7_MOD_RCLK_128FS 5
+#define EXYNOS7_MOD_RCLK_96FS 6
+#define EXYNOS7_MOD_RCLK_192FS 7
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 38b9a52..947352d 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -36,9 +36,24 @@ enum samsung_dai_type {
TYPE_SEC,
};
+struct samsung_i2s_variant_regs {
+ unsigned intbfs_off;
+ unsigned intrfs_off;
+ unsigned intsdf_off;
+ unsigned inttxr_off;
+ unsigned intrclksrc_off;
+ unsigned intmss_off;
+ unsigned intcdclkcon_off;
+ unsigned intlrp_off;
+ unsigned intbfs_mask;
+ unsigned intrfs_mask;
+ unsigned intftx0cnt_off;
+};
+
struct samsung_i2s_dai_data {
int dai_type
[PATCH] ASoC: samsung: Initialize the dma_data for secondary dai
This patch initializes the dma_data for the secondary dai.
Without this patch there is crash due to NULL pointer
dereference during boot time on systems where secondary dai
is initialized.
Below is the crash log:
[1.63] smdk-audio-wm8894 sound.7: wm8994-aif1 - 383.i2s mapping
ok
[1.63] Unable to handle kernel NULL pointer dereference at virtual
address 0010
[1.63] pgd = c0004000
[1.63] [0010] *pgd=
[1.63] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
[1.63] Modules linked in:
...
...
[c0342d6c] (dmaengine_pcm_new+0x284/0x2ac) from [c0341ae8]
(soc_new_pcm+0x2fc/0x3f4)
[c0341ae8] (soc_new_pcm+0x2fc/0x3f4) from [c0338558]
(snd_soc_register_card+0x1898/0x18d8)
[c0338558] (snd_soc_register_card+0x1898/0x18d8) from [c034cc34]
(smdk_audio_probe+0xa8/0xe8)
[c034cc34] (smdk_audio_probe+0xa8/0xe8) from [c0252368]
(platform_drv_probe+0x18/0x1c)
[c0252368] (platform_drv_probe+0x18/0x1c) from [c02510a4]
(driver_probe_device+0xf4/0x204)
[c02510a4] (driver_probe_device+0xf4/0x204) from [c0251240]
(__driver_attach+0x8c/0x90)
[c0251240] (__driver_attach+0x8c/0x90) from [c024f70c]
(bus_for_each_dev+0x54/0x88)
[c024f70c] (bus_for_each_dev+0x54/0x88) from [c0250724]
(bus_add_driver+0xe0/0x2b8)
[c0250724] (bus_add_driver+0xe0/0x2b8) from [c0251868]
(driver_register+0x78/0xf4)
[c0251868] (driver_register+0x78/0xf4) from [c00086e8]
(do_one_initcall+0x34/0x150)
[c00086e8] (do_one_initcall+0x34/0x150) from [c0543c30]
(kernel_init_freeable+0x12c/0x1d0)
[c0543c30] (kernel_init_freeable+0x12c/0x1d0) from [c03ebf9c]
(kernel_init+0x8/0xe8)
[c03ebf9c] (kernel_init+0x8/0xe8) from [c000e978] (ret_from_fork+0x14/0x3c)
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This is made based on Mark Brown for-next branch of sound.git
This patch is based on Mark Brown below patches for
generic dma engine support for samsung audio IPs.
ASoC: samsung: Use ASoC dmaengine code where possible
ASoC: samsung: Provide helper for DMA init
sound/soc/samsung/dmaengine.c |3 ++-
sound/soc/samsung/i2s.c |5 -
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/sound/soc/samsung/dmaengine.c b/sound/soc/samsung/dmaengine.c
index ad0a371..3f60479 100644
--- a/sound/soc/samsung/dmaengine.c
+++ b/sound/soc/samsung/dmaengine.c
@@ -67,7 +67,8 @@ EXPORT_SYMBOL_GPL(samsung_asoc_init_dma_data);
int samsung_asoc_dma_platform_register(struct device *dev)
{
return snd_dmaengine_pcm_register(dev, samsung_dmaengine_pcm_config,
- SND_DMAENGINE_PCM_FLAG_COMPAT);
+ SND_DMAENGINE_PCM_FLAG_COMPAT |
+ SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME);
}
EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_register);
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 67d9fa9..0bcd7fb 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -946,8 +946,11 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
- if (other other-clk) /* If this is probe on secondary */
+ if (other other-clk) { /* If this is probe on secondary */
+ samsung_asoc_init_dma_data(dai, other-sec_dai-dma_playback,
+ NULL);
goto probe_exit;
+ }
i2s-addr = ioremap(i2s-base, 0x100);
if (i2s-addr == NULL) {
--
1.7.4.4
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[PATCH 0/3] Add pl330 residue support
This patch set adds support for finding the remaining number of bytes in the current transfer and fills txstate.residue with the amount of bytes remaining. Although Samsung specific dma operations will be removed in future, the residue specific patches are required. So when we add support for generic dma engine these patches have to be ported accordingly. Dylan Reid (3): dmaengine: pl330: Set residue in tx_status callback. ARM: SAMSUNG: Add residue DMA operation. ASoC: Update pointer to account for pending dma transfers. arch/arm/plat-samsung/dma-ops.c | 14 +++ arch/arm/plat-samsung/include/plat/dma-ops.h |1 + drivers/dma/pl330.c | 55 +- sound/soc/samsung/dma.c | 27 + 4 files changed, 88 insertions(+), 9 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: SAMSUNG: Add residue DMA operation.
From: Dylan Reid dgr...@chromium.org
Add a new dma op, residue. It returns the count of bytes left to be
transfered by the dma. This is useful for Audio, the Samsung dma ASoC
layer will use this to provide an accurate update to the hw_ptr that is
exported to user space. ASoC wants large transfers to reduce the amount
of wakeups, but needs to be able to know how much audio has been played
for latency estimates.
Signed-off-by: Dylan Reid dgr...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/plat-samsung/dma-ops.c | 14 ++
arch/arm/plat-samsung/include/plat/dma-ops.h |1 +
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index ec0d731..bfc6c1a 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -122,6 +122,19 @@ static inline int samsung_dmadev_flush(unsigned ch)
return dmaengine_terminate_all((struct dma_chan *)ch);
}
+static unsigned samsung_dmadev_residue(unsigned ch)
+{
+ struct dma_chan *chan = (struct dma_chan *)ch;
+ enum dma_status ret;
+ struct dma_tx_state state;
+
+ ret = chan-device-device_tx_status(chan, chan-cookie, state);
+ if (ret == DMA_SUCCESS) /* Transfer complete. */
+ return 0;
+
+ return state.residue;
+}
+
static struct samsung_dma_ops dmadev_ops = {
.request= samsung_dmadev_request,
.release= samsung_dmadev_release,
@@ -131,6 +144,7 @@ static struct samsung_dma_ops dmadev_ops = {
.started= NULL,
.flush = samsung_dmadev_flush,
.stop = samsung_dmadev_flush,
+ .residue= samsung_dmadev_residue,
};
void *samsung_dmadev_get_ops(void)
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h
b/arch/arm/plat-samsung/include/plat/dma-ops.h
index ce6d763..82eac53 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -47,6 +47,7 @@ struct samsung_dma_ops {
int (*started)(unsigned ch);
int (*flush)(unsigned ch);
int (*stop)(unsigned ch);
+ unsigned (*residue)(unsigned ch);
};
extern void *samsung_dmadev_get_ops(void);
--
1.7.4.4
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[PATCH 1/3] dmaengine: pl330: Set residue in tx_status callback.
From: Dylan Reid dgr...@chromium.org
Fill txstate.residue with the amount of bytes remaining in the current
transfer if the transfer is not complete. This will be of particular
use to i2s DMA transfers, providing more accurate hw_ptr values to ASoC.
Signed-off-by: Dylan Reid dgr...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/dma/pl330.c | 55 ++-
1 files changed, 54 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 593827b..7ab9136 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2476,11 +2476,64 @@ static void pl330_free_chan_resources(struct dma_chan
*chan)
spin_unlock_irqrestore(pch-lock, flags);
}
+static inline int
+pl330_src_addr_in_desc(struct dma_pl330_desc *desc, unsigned int sar)
+{
+ return ((desc-px.src_addr = sar)
+ (sar = (desc-px.src_addr + desc-px.bytes)));
+}
+
+static inline int
+pl330_dst_addr_in_desc(struct dma_pl330_desc *desc, unsigned int dar)
+{
+ return ((desc-px.dst_addr = dar)
+ (dar = (desc-px.dst_addr + desc-px.bytes)));
+}
+
+static unsigned int pl330_tx_residue(struct dma_chan *chan)
+{
+ struct dma_pl330_chan *pch = to_pchan(chan);
+ void __iomem *regs = pch-dmac-pif.base;
+ struct pl330_thread *thrd = pch-pl330_chid;
+ struct dma_pl330_desc *desc;
+ unsigned int sar, dar;
+ unsigned int residue = 0;
+ unsigned long flags;
+
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+ spin_lock_irqsave(pch-lock, flags);
+
+ /* Find the desc related to the current buffer. */
+ list_for_each_entry(desc, pch-work_list, node) {
+ if (desc-rqcfg.src_inc pl330_src_addr_in_desc(desc, sar)) {
+ residue = desc-px.bytes - (sar - desc-px.src_addr);
+ goto found_unlock;
+ }
+ if (desc-rqcfg.dst_inc pl330_dst_addr_in_desc(desc, dar)) {
+ residue = desc-px.bytes - (dar - desc-px.dst_addr);
+ goto found_unlock;
+ }
+ }
+
+found_unlock:
+ spin_unlock_irqrestore(pch-lock, flags);
+
+ return residue;
+}
+
static enum dma_status
pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
- return dma_cookie_status(chan, cookie, txstate);
+ enum dma_status ret;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret != DMA_SUCCESS) /* Not complete, check amount left. */
+ dma_set_residue(txstate, pl330_tx_residue(chan));
+
+ return ret;
}
static void pl330_issue_pending(struct dma_chan *chan)
--
1.7.4.4
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[PATCH 3/3] ASoC: Update pointer to account for pending dma transfers.
From: Dylan Reid dgr...@chromium.org
Make dma_pointer check how much of the current dma transfer has
completed. This improves the accuracy of the pointer operation, which
previously was only updated once a period. Before this change calling
snd_pcm_avail() right before a dma transfer completed would indicate
that the entire transfer was still pending, now it will indicate the
actual count of free frames.
If the dma being used doesn't support the residue operation to query a
pending transfer, then assume that no bytes have been transfered. This
leads to the same behavior as before the change.
Signed-off-by: Dylan Reid dgr...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
sound/soc/samsung/dma.c | 27 +++
1 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index 21b7926..6b2e55d 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -271,13 +271,24 @@ dma_pointer(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream-runtime;
struct runtime_data *prtd = runtime-private_data;
- unsigned long res;
+ unsigned long offset;
+ unsigned long xfd; /* Number of bytes transfered by current dma. */
+ unsigned int ret = 0;
pr_debug(Entered %s\n, __func__);
- res = prtd-dma_pos - prtd-dma_start;
+ /* If we can inspect how much of the transfer is left, use that for a
+* more accurate number. Otherwise, assume no bytes have been
+* transfered.
+*/
+ if (prtd-params-ops-residue)
+ ret = prtd-params-ops-residue(prtd-params-ch);
+
+ spin_lock(prtd-lock);
+ xfd = prtd-dma_period - ret;
- pr_debug(Pointer offset: %lu\n, res);
+ offset = prtd-dma_pos + xfd - prtd-dma_start;
+ spin_unlock(prtd-lock);
/* we seem to be getting the odd error from the pcm library due
* to out-of-bounds pointers. this is maybe due to the dma engine
@@ -285,12 +296,12 @@ dma_pointer(struct snd_pcm_substream *substream)
* called... (todo - fix )
*/
- if (res = snd_pcm_lib_buffer_bytes(substream)) {
- if (res == snd_pcm_lib_buffer_bytes(substream))
- res = 0;
- }
+ if (offset = snd_pcm_lib_buffer_bytes(substream))
+ offset = 0;
+
+ pr_debug(Pointer offset: %lu\n, offset);
- return bytes_to_frames(substream-runtime, res);
+ return bytes_to_frames(substream-runtime, offset);
}
static int dma_open(struct snd_pcm_substream *substream)
--
1.7.4.4
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[PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420
This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420 audio subsystem has a gate bit for ADMA controller and the some of the parent clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch adds provision for supporting both the platforms by determining the parent clk names based on compatible string. Changes since V1: - parent clocks are determined by using the compatible string and not passed via device tree as done in V1 because the probing order of the clock providers can't be guaranteed. Andrew Bresticker (3): clk: exynos-audss: add support for Exynos 5420 clk: exynos-audss: set correct parent clocks ARM: dts: exynos5420: add audio clock controller Padmavathi Venna (1): ARM: dts: Correct the /include entry on exynos5420 dtsi file .../devicetree/bindings/clock/clk-exynos-audss.txt |7 +-- arch/arm/boot/dts/exynos5420.dtsi | 11 ++- drivers/clk/samsung/clk-exynos-audss.c | 20 +++- include/dt-bindings/clk/exynos-audss-clk.h |3 ++- 4 files changed, 36 insertions(+), 5 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 2/4] clk: exynos-audss: set correct parent clocks
From: Andrew Bresticker abres...@chromium.org
Different Exynos SoCs have different names for certain input clocks
to the AudioSS block. Since the order in which clock providers are
probed is not guaranteed, we can't use the device-tree to pass the
correct input clocks. Instead, use the compatibility string to
determine what the correct parent clocks should be.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
drivers/clk/samsung/clk-exynos-audss.c | 12 +++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 86d2606..d81c5f8 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = {
/* list of all parent clock list */
static const char *mout_audss_p[] = { fin_pll, fout_epll };
static const char *mout_i2s_p[] = { mout_audss, cdclk0, sclk_audio0 };
+static const char *sclk_pcm_p = sclk_pcm0;
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
@@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np)
return;
}
+ /* fix up clock parent names based on SoC */
+ if (of_device_is_compatible(np, samsung,exynos5420-audss-clock)) {
+ mout_i2s_p[2] = sclk_maudio0;
+ sclk_pcm_p = sclk_maupcm0;
+ } else if (of_device_is_compatible(np,
+ samsung,exynos5250-audss-clock)) {
+ sclk_pcm_p = div_pcm0;
+ }
+
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
@@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np)
reg_base + ASS_CLK_GATE, 4, 0, lock);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, sclk_pcm,
- div_pcm0, CLK_SET_RATE_PARENT,
+ sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
if (of_device_is_compatible(np, samsung,exynos5420-audss-clock)) {
--
1.7.4.4
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[PATCH V2 3/4] ARM: dts: Correct the /include entry on exynos5420 dtsi file
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..334f7b7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -14,7 +14,7 @@
*/
#include exynos5.dtsi
-/include/ exynos5420-pinctrl.dtsi
+#include exynos5420-pinctrl.dtsi
/ {
compatible = samsung,exynos5420;
--
1.7.4.4
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[PATCH V1 1/4] clk: exynos-audss: add support for Exynos 5420
From: Andrew Bresticker abres...@chromium.org
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker abres...@chromium.org
seviewed-on: https://gerrit.chromium.org/gerrit/57711
Reviewed-by: Simon Glass s...@chromium.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt |7 +--
drivers/clk/samsung/clk-exynos-audss.c |8
include/dt-bindings/clk/exynos-audss-clk.h |3 ++-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a120180..3115930 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
- - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
-
+ - samsung,exynos5250-audss-clock - controller compatible with Exynos5250
+SoCs.
+ - samsung,exynos5420-audss-clock - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -34,6 +36,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd5..86d2606 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np)
div_pcm0, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
+ if (of_device_is_compatible(np, samsung,exynos5420-audss-clock)) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, adma,
+ dout_srp, CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, lock);
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(exynos_audss_clk_syscore_ops);
#endif
@@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk,
samsung,exynos4210-audss-clock,
exynos_audss_clk_init);
CLK_OF_DECLARE(exynos5250_audss_clk, samsung,exynos5250-audss-clock,
exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5420_audss_clk, samsung,exynos5420-audss-clock,
+ exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h
b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM9
+#define EXYNOS_ADMA10
-#define EXYNOS_AUDSS_MAX_CLKS 10
+#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
--
1.7.4.4
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[PATCH V2 4/4] ARM: dts: exynos5420: add audio clock controller
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Simon Glass s...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 334f7b7..dde4cc2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -15,6 +15,9 @@
#include exynos5.dtsi
#include exynos5420-pinctrl.dtsi
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5420;
@@ -65,6 +68,12 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5420-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
--
1.7.4.4
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[PATCH V5] ARM: dts: Change i2s compatible string on exynos5250
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V4:
- Mark Brown reverted the below two patches due to below build failure
with
exynos_defconfig.
ARM: dts: exynos5250: move common i2s properties to exynos5
dtsi
ARM: dts: Change i2s compatible string on exynos5250
build error:
DTC arch/arm/boot/dts/exynos5420-smdk5420.dtb
ERROR (phandle_references): Reference to non-existent node or label
pdma1
ERROR (phandle_references): Reference to non-existent node or label
pdma1
ERROR (phandle_references): Reference to non-existent node or label
pdma0
ERROR (phandle_references): Reference to non-existent node or label
pdma0
But with out ARM: dts: Change i2s compatible string on exynos5250 will break
the i2s
driver.
So posting this patch now and will take care of posting other patch later after
dependent
patches got merged.
arch/arm/boot/dts/exynos5250.dtsi |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index ef57277..376090f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -405,7 +405,7 @@
};
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
@@ -415,16 +415,13 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D6 0x100;
dmas = pdma1 12
pdma1 11;
@@ -436,7 +433,7 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D7 0x100;
dmas = pdma0 12
pdma0 11;
--
1.7.4.4
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[PATCH V2] ARM: dts: Add DMA controller node info on Exynos5420.
This patch adds dma controller node info on Exynos5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- In V1, dma node common stuff was added in common exynos5.dtsi file.
This was removed as per Kukjin comment and added in exynos5420.dtsi.
This patch is dependent on audss clk controller patches that were
posted in the below link.
http://www.spinics.net/lists/linux-samsung-soc/msg20253.html
arch/arm/boot/dts/exynos5420.dtsi | 63 +
1 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..23cfea4 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -126,6 +126,69 @@
interrupts = 0 47 0;
};
+ amba {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = arm,amba-bus;
+ interrupt-parent = gic;
+ ranges;
+
+ pdma0: pdma@121A {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121A 0x1000;
+ interrupts = 0 34 0;
+ clocks = clock 362;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@121B {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121B 0x1000;
+ interrupts = 0 35 0;
+ clocks = clock 363;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ mdma0: mdma@1080 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1080 0x1000;
+ interrupts = 0 33 0;
+ clocks = clock 473;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+
+ mdma1: mdma@11C1 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x11C1 0x1000;
+ interrupts = 0 124 0;
+ clocks = clock 442;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+
+ adma: adma@0388 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x0388 0x1000;
+ interrupts = 0 110 0;
+ clocks = clock_audss EXYNOS_ADMA;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 6;
+ #dma-requests = 16;
+ };
+ };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
--
1.7.4.4
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[PATCH V4 1/4] ASoC: Samsung: I2S: Add quirks as driver data in I2S
Samsung has different versions of I2S introduced in different
platforms. Each version has some new support added for multichannel,
secondary fifo, s/w reset control and internal mux for rclk src clk.
Each newly added change has a quirk. So this patch adds all the
required quirks as driver data and based on compatible string from
dtsi fetches the quirks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 18 ++
sound/soc/samsung/i2s.c| 62 +++
2 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 025e66b..25a0024 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -2,7 +2,11 @@
Required SoC Specific Properties:
-- compatible : samsung,i2s-v5
+- compatible : should be one of the following.
+ - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
+ - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
+ secondary fifo, s/w reset control and internal mux for root clk src.
+
- reg: physical base address of the controller and length of memory mapped
region.
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
@@ -21,13 +25,6 @@ Required SoC Specific Properties:
Optional SoC Specific Properties:
-- samsung,supports-6ch: If the I2S Primary sound source has 5.1 Channel
- support, this flag is enabled.
-- samsung,supports-rstclr: This flag should be set if I2S software reset bit
- control is required. When this flag is set I2S software reset bit will be
- enabled or disabled based on need.
-- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
- then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
@@ -36,7 +33,7 @@ Optional SoC Specific Properties:
Example:
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
@@ -46,9 +43,6 @@ i2s0: i2s@0383 {
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 47e08dd..1671d9b 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -40,6 +40,7 @@ enum samsung_dai_type {
struct samsung_i2s_dai_data {
int dai_type;
+ u32 quirks;
};
struct i2s_dai {
@@ -1032,18 +1033,18 @@ static struct i2s_dai *i2s_alloc_dai(struct
platform_device *pdev, bool sec)
static const struct of_device_id exynos_i2s_match[];
-static inline int samsung_i2s_get_driver_data(struct platform_device *pdev)
+static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
+ struct platform_device *pdev)
{
#ifdef CONFIG_OF
- struct samsung_i2s_dai_data *data;
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(exynos_i2s_match, pdev-dev.of_node);
- data = (struct samsung_i2s_dai_data *) match-data;
- return data-dai_type;
+ return match-data;
} else
#endif
- return platform_get_device_id(pdev)-driver_data;
+ return (struct samsung_i2s_dai_data *)
+ platform_get_device_id(pdev)-driver_data;
}
#ifdef CONFIG_PM_RUNTIME
@@ -1074,13 +1075,13 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
struct resource *res;
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
- enum samsung_dai_type samsung_dai_type;
+ const struct samsung_i2s_dai_data *i2s_dai_data;
int ret = 0;
/* Call during Seconday interface registration */
- samsung_dai_type = samsung_i2s_get_driver_data(pdev);
+ i2s_dai_data = samsung_i2s_get_driver_data(pdev);
- if (samsung_dai_type == TYPE_SEC) {
+ if (i2s_dai_data-dai_type == TYPE_SEC) {
sec_dai = dev_get_drvdata(pdev-dev);
if (!sec_dai) {
dev_err(pdev-dev, Unable to get drvdata\n);
@@ -1129,15 +1130,7 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
idma_addr = i2s_cfg-idma_addr;
}
} else {
- if (of_find_property(np, samsung
[PATCH V4 3/4] ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi
I2S nodes shares some properties across exynos5 SoCs (exynos5250
and exyno5420). Common code is moved to exynos5.dtsi which is
included in exyno5250 and exynos5420 SoC files.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 21 +
arch/arm/boot/dts/exynos5250.dtsi | 12
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..aae2fa1 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -108,4 +108,25 @@
interrupts = 0 42 0;
status = disabled;
};
+
+ i2s0: i2s@0383 {
+ reg = 0x0383 0x100;
+ samsung,idma-addr = 0x0300;
+ };
+
+ i2s1: i2s@12D6 {
+ compatible = samsung,i2s-v5;
+ reg = 0x12D6 0x100;
+ dmas = pdma1 12
+ pdma1 11;
+ dma-names = tx, rx;
+ };
+
+ i2s2: i2s@12D7 {
+ compatible = samsung,i2s-v5;
+ reg = 0x12D7 0x100;
+ dmas = pdma0 12
+ pdma0 11;
+ dma-names = tx, rx;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index ef57277..f941d52 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -406,7 +406,6 @@
i2s0: i2s@0383 {
compatible = samsung,i2s-v5;
- reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
@@ -418,17 +417,11 @@
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
- samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
- reg = 0x12D6 0x100;
- dmas = pdma1 12
- pdma1 11;
- dma-names = tx, rx;
clocks = clock 307, clock 157;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
@@ -436,11 +429,6 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
- reg = 0x12D7 0x100;
- dmas = pdma0 12
- pdma0 11;
- dma-names = tx, rx;
clocks = clock 308, clock 158;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
--
1.7.4.4
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[PATCH V4 0/4] Add i2s support on smdk5420
Samsung has different versions of I2S introduced in different platforms. Each version has some new support added for multichannel, secondary fifo, s/w reset control, internal mux for rclk src clk and tdm support. Each newly added change has a quirk. So this patch adds all the required quirks as driver data and based on compatible string from dtsi fetches the quirks. This also adds i2s support on exynos5420. Changes since V3: - Addressed review comments by Tomasz Figa related to const qualifier for samsung_i2s_dai_data - Removed passing quirks as driver data for non-dt platforms. - Separated out adding i2s nodes and enabling audio support on 5420 into different patch set as they are dependent on some of already posted but not yet merged i2c, dwmmc, dma and audss clock controller patches. Changes since V2: - Separated out driver side changes and dts changes in two patch sets. - Replaced samsung,s3c6410-i2s-v4 with samsung,s3c6410-i2s-multi for more clarity as suggested by Tomasz Figa. Changes since V1: - Pass quirks as driver data and fetch the quirks based on compatible string from dtsi file as suggested by Tomasz Figa and Mark Brown - Make the I2S driver more flexible with respect to register access as suggested by Tomasz Figa and Mark Brown - Add 5420 support in the driver. - Modify the dtsi files with the corresponding compatible strings and removed the i2s quirks from 5250 dtsi file. - Updated the i2s Documentation with relevent changes and i2s versioning info. - Add i2s nodes on exynos5420.dtsi - Enable sound support on smdk5420 This patch set is made based on Mark Brown for-next branch on sound.git. Padmavathi Venna (4): ASoC: Samsung: I2S: Add quirks as driver data in I2S ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420 ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi ARM: dts: Change i2s compatible string on exynos5250 .../devicetree/bindings/sound/samsung-i2s.txt | 22 ++-- arch/arm/boot/dts/exynos5.dtsi | 21 +++ arch/arm/boot/dts/exynos5250.dtsi | 17 +--- include/linux/platform_data/asoc-s3c.h |1 + sound/soc/samsung/i2s-regs.h | 15 ++ sound/soc/samsung/i2s.c| 143 +++- 6 files changed, 157 insertions(+), 62 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 2/4] ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |4 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 15
sound/soc/samsung/i2s.c| 81 ++--
4 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 25a0024..7386d44 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -6,6 +6,10 @@ Required SoC Specific Properties:
- samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
secondary fifo, s/w reset control and internal mux for root clk src.
+ - samsung,exynos5420-i2s: for 8/16/24bit multichannel(7.1) I2S with
+ secondary fifo, s/w reset control, internal mux for root clk src and
+ TDM support. TDM (Time division multiplexing) is to allow transfer of
+ multiple channel audio data on single data line.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index 30513b7..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR0x34
#define I2SLVL2ADDR0x38
#define I2SLVL3ADDR0x3c
+#define I2SSTR10x40
+#define I2SVER 0x44
+#define I2SFIC20x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -117,6 +121,17 @@
#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT 4
+#define EXYNOS5420_MOD_BCLK_SHIFT 0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS 6
+#define EXYNOS5420_MOD_BCLK_192FS 7
+#define EXYNOS5420_MOD_BCLK_256FS 8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 1671d9b..ce487c2 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -199,7 +199,12 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
+ u32 rfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
rfs = MOD_RCLK_MASK;
switch (rfs) {
@@ -214,8 +219,12 @@ static inline unsigned get_rfs(struct i2s_dai *i2s)
static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
{
u32 mod = readl(i2s-addr + I2SMOD);
- int rfs_shift = MOD_RCLK_SHIFT;
+ int rfs_shift;
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs_shift = EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs_shift = MOD_RCLK_SHIFT;
mod = ~(MOD_RCLK_MASK rfs_shift);
switch (rfs) {
@@ -239,10 +248,22 @@ static inline void set_rfs(struct i2s_dai *i2s, unsigned
rfs)
/* Read Bit-Clock of I2S (in multiples of LRCLK) */
static inline unsigned get_bfs(struct i2s_dai *i2s)
{
- u32 bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
- bfs = MOD_BCLK_MASK;
+ u32 bfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM) {
+ bfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_BCLK_SHIFT;
+ bfs = EXYNOS5420_MOD_BCLK_MASK;
+ } else {
+ bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
+ bfs = MOD_BCLK_MASK;
+ }
switch (bfs) {
+ case 8: return 256;
+ case 7
[PATCH V4 4/4] ARM: dts: Change i2s compatible string on exynos5250
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi|4 ++--
arch/arm/boot/dts/exynos5250.dtsi |5 +
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index aae2fa1..309894e 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -115,7 +115,7 @@
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D6 0x100;
dmas = pdma1 12
pdma1 11;
@@ -123,7 +123,7 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D7 0x100;
dmas = pdma0 12
pdma0 11;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index f941d52..ac5f5a1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -405,7 +405,7 @@
};
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
dmas = pdma0 10
pdma0 9
pdma0 8;
@@ -414,9 +414,6 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
--
1.7.4.4
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[PATCH V4 2/4] ARM: dts: Add i2c bus 1 and it's audio codec child node on smdk5420
This patch adds i2c bus 1 and wm8994 codec node on i2c bus1 and the
required regulator supplies and properties on smdk5420 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 62 +
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index d05de7a..1ef7e2e 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -68,4 +68,66 @@
bus-width = 4;
};
};
+
+ fixed-regulators {
+ compatible = simple-bus;
+
+ avdd2: fixed-regulator-0 {
+ compatible = regulator-fixed;
+ regulator-name = avdd2-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ cpvdd: fixed-regulator-1 {
+ compatible = regulator-fixed;
+ regulator-name = cpvdd-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ dbvdd: fixed-regulator-2 {
+ compatible = regulator-fixed;
+ regulator-name = dbvdd-supply;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ spkvdd: fixed-regulator-3 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+ };
+
+ i2c@12C7 {
+ status = okay;
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-max-bus-freq = 2;
+
+ eeprom@51 {
+ compatible = samsung,s524ad0xd1;
+ reg = 0x51;
+ };
+
+ wm8994: wm8994@1a {
+ compatible = wlf,wm8994;
+ reg = 0x1a;
+
+ gpio-controller;
+ #gpio-cells = 2;
+
+ AVDD2-supply = avdd2;
+ CPVDD-supply = cpvdd;
+ DBVDD-supply = dbvdd;
+ SPKVDD1-supply = spkvdd;
+ SPKVDD2-supply = spkvdd;
+ };
+ };
+
};
--
1.7.4.4
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[PATCH V4 4/4] ARM: dts: Enable sound support on smdk5420
This patch enables i2s0 and sound support on smdk5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index a898b3f..b1b745c 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -139,4 +139,14 @@
};
};
+ i2s0: i2s@0383 {
+ status = okay;
+ };
+
+ sound {
+ compatible = samsung,smdk-wm8994;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = wm8994;
+ };
};
--
1.7.4.4
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[PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the i2s controllers on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-on: https://gerrit.chromium.org/gerrit/57713
---
arch/arm/boot/dts/exynos5420.dtsi | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d2fdb87..8d57369 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -242,4 +242,36 @@
pinctrl-names = default;
pinctrl-0 = i2c3_bus;
};
+
+ i2s_0: i2s@0383 {
+ compatible = samsung,exynos5420-i2s;
+ dmas = adma 0
+ adma 2
+ adma 1;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
+ status = disabled;
+ };
+
+ i2s_1: i2s@12D6 {
+ clocks = clock 275, clock 138;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s1_bus;
+ status = disabled;
+ };
+
+ i2s_2: i2s@12D7 {
+ clocks = clock 276, clock 139;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s2_bus;
+ status = disabled;
+ };
+
};
--
1.7.4.4
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[PATCH V4 3/4] ARM: dts: Add osc clock node on smdk5420.
This patch adds 16MHz oscillator clock node required for audio
on smdk5420 and adds the phandle of the same in wm8994 clock info.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 1ef7e2e..a898b3f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,12 @@
};
};
+ osc3_clk16mhz: oscillator-0 {
+ compatible = fixed-clock;
+ #clock-cells = 0;
+ clock-frequency = 16934400;
+ };
+
dwmmc0@1220 {
status = okay;
num-slots = 1;
@@ -127,6 +133,9 @@
DBVDD-supply = dbvdd;
SPKVDD1-supply = spkvdd;
SPKVDD2-supply = spkvdd;
+
+ clocks = osc3_clk16mhz;
+ clock-names = mclk1;
};
};
--
1.7.4.4
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[PATCH V3 3/3] ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |4 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 15
sound/soc/samsung/i2s.c| 81 ++--
4 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index b3f6443..9b5c892 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -11,6 +11,10 @@ Required SoC Specific Properties:
with secondary fifo and s/w reset control.
- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
secondary fifo, s/w reset control and internal mux for root clk src.
+ - samsung,exynos5420-i2s: for 8/16/24bit multichannel(7.1) I2S with
+ secondary fifo, s/w reset control, internal mux for root clk src and
+ TDM support. TDM (Time division multiplexing) is to allow transfer of
+ multiple channel audio data on single data line.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index 30513b7..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR0x34
#define I2SLVL2ADDR0x38
#define I2SLVL3ADDR0x3c
+#define I2SSTR10x40
+#define I2SVER 0x44
+#define I2SFIC20x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -117,6 +121,17 @@
#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT 4
+#define EXYNOS5420_MOD_BCLK_SHIFT 0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS 6
+#define EXYNOS5420_MOD_BCLK_192FS 7
+#define EXYNOS5420_MOD_BCLK_256FS 8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 8a5504c..6964672 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -199,7 +199,12 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
+ u32 rfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
rfs = MOD_RCLK_MASK;
switch (rfs) {
@@ -214,8 +219,12 @@ static inline unsigned get_rfs(struct i2s_dai *i2s)
static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
{
u32 mod = readl(i2s-addr + I2SMOD);
- int rfs_shift = MOD_RCLK_SHIFT;
+ int rfs_shift;
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs_shift = EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs_shift = MOD_RCLK_SHIFT;
mod = ~(MOD_RCLK_MASK rfs_shift);
switch (rfs) {
@@ -239,10 +248,22 @@ static inline void set_rfs(struct i2s_dai *i2s, unsigned
rfs)
/* Read Bit-Clock of I2S (in multiples of LRCLK) */
static inline unsigned get_bfs(struct i2s_dai *i2s)
{
- u32 bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
- bfs = MOD_BCLK_MASK;
+ u32 bfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM) {
+ bfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_BCLK_SHIFT;
+ bfs = EXYNOS5420_MOD_BCLK_MASK;
+ } else {
+ bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
+ bfs = MOD_BCLK_MASK;
+ }
switch (bfs) {
+ case 8: return 256;
+ case 7: return 192;
+ case 6: return 128;
+ case
[PATCH V3 2/3] ASoC: Samsung: I2S: Add quirks as driver data in I2S
Samsung has different versions of I2S introduced in different
platforms. Each version has some new support added for multichannel,
secondary fifo, s/w reset control and internal mux for rclk src clk.
Each newly added change has a quirk. So this patch adds all the
required quirks as driver data and based on compatible string from
dtsi fetches the quirks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 21 +++---
sound/soc/samsung/i2s.c| 82 +---
2 files changed, 64 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 025e66b..b3f6443 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -2,7 +2,16 @@
Required SoC Specific Properties:
-- compatible : samsung,i2s-v5
+- compatible : should be one of the following.
+ - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. Previous versions
+ has only 8/16bit support.
+ - samsung,s3c6410-i2sv4: for 8/16/24bit multichannel(5.1 channel) I2S.
+ Introduced in s3c6410. This also applicable for s5p64x0 platforms.
+ - samsung,s5pc100-i2s: for 8/16/24bit multichannel(5.1 channel) I2S
+ with secondary fifo and s/w reset control.
+ - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
+ secondary fifo, s/w reset control and internal mux for root clk src.
+
- reg: physical base address of the controller and length of memory mapped
region.
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
@@ -21,13 +30,6 @@ Required SoC Specific Properties:
Optional SoC Specific Properties:
-- samsung,supports-6ch: If the I2S Primary sound source has 5.1 Channel
- support, this flag is enabled.
-- samsung,supports-rstclr: This flag should be set if I2S software reset bit
- control is required. When this flag is set I2S software reset bit will be
- enabled or disabled based on need.
-- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
- then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
@@ -46,9 +48,6 @@ i2s0: i2s@0383 {
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 47e08dd..8a5504c 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -40,6 +40,7 @@ enum samsung_dai_type {
struct samsung_i2s_dai_data {
int dai_type;
+ u32 quirks;
};
struct i2s_dai {
@@ -1032,18 +1033,18 @@ static struct i2s_dai *i2s_alloc_dai(struct
platform_device *pdev, bool sec)
static const struct of_device_id exynos_i2s_match[];
-static inline int samsung_i2s_get_driver_data(struct platform_device *pdev)
+static inline struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
+ struct platform_device *pdev)
{
#ifdef CONFIG_OF
- struct samsung_i2s_dai_data *data;
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(exynos_i2s_match, pdev-dev.of_node);
- data = (struct samsung_i2s_dai_data *) match-data;
- return data-dai_type;
+ return (struct samsung_i2s_dai_data *) match-data;
} else
#endif
- return platform_get_device_id(pdev)-driver_data;
+ return (struct samsung_i2s_dai_data *)
+ platform_get_device_id(pdev)-driver_data;
}
#ifdef CONFIG_PM_RUNTIME
@@ -1074,13 +1075,13 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
struct resource *res;
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
- enum samsung_dai_type samsung_dai_type;
+ struct samsung_i2s_dai_data *i2s_dai_data;
int ret = 0;
/* Call during Seconday interface registration */
- samsung_dai_type = samsung_i2s_get_driver_data(pdev);
+ i2s_dai_data = samsung_i2s_get_driver_data(pdev);
- if (samsung_dai_type == TYPE_SEC) {
+ if (i2s_dai_data-dai_type == TYPE_SEC) {
sec_dai = dev_get_drvdata(pdev-dev);
if (!sec_dai) {
dev_err(pdev-dev, Unable to get drvdata\n);
@@ -1129,15 +1130,7 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
idma_addr = i2s_cfg
[PATCH V3 0/3] Add audio support on smdk5420
Samsung has different versions of I2S introduced in different platforms. Each version has some new support added for multichannel, secondary fifo, s/w reset control, internal mux for rclk src clk and tdm support. Each newly added change has a quirk. So this patch adds all the required quirks as driver data and based on compatible string from dtsi fetches the quirks. This also adds i2s support on exynos5420. Changes since V2: - Seperated out driver side changes and dts changes in two patch sets. - Replaced samsung,s3c6410-i2s-v4 with samsung,s3c6410-i2s-multi for more clarity as suggested by Tomasz Figa. Changes since V1: - Pass quirks as driver data and fetch the quirks based on compatible string from dtsi file as suggested by Tomasz Figa and Mark Brown - Make the I2S driver more flexible with respect to register access as suggested by Tomasz Figa and Mark Brown - Add 5420 support in the driver. - Modify the dtsi files with the corresponding compatible strings and removed the i2s quirks from 5250 dtsi file. - Updated the i2s Documentation with relevent changes and i2s versioning info. - Add i2s nodes on exynos5420.dtsi - Enable sound support on smdk5420 This patch set is made based on Mark Brown for-next branch on sound.git. Padmavathi Venna (3): platform: Increase platform name size ASoC: Samsung: I2S: Add quirks as driver data in I2S ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420 .../devicetree/bindings/sound/samsung-i2s.txt | 25 ++-- include/linux/mod_devicetable.h|2 +- include/linux/platform_data/asoc-s3c.h |1 + sound/soc/samsung/i2s-regs.h | 15 ++ sound/soc/samsung/i2s.c| 163 +++- 5 files changed, 158 insertions(+), 48 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 1/3] platform: Increase platform name size
This patch increases the platform name size from 20 to 30 as one of
i2s platform_device name in this patchset crosses the limit.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
include/linux/mod_devicetable.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 45e9214..3a2c079 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -479,7 +479,7 @@ struct dmi_system_id {
#define DMI_MATCH(a, b){ .slot = a, .substr = b }
#define DMI_EXACT_MATCH(a, b) { .slot = a, .substr = b, .exact_match = 1 }
-#define PLATFORM_NAME_SIZE 20
+#define PLATFORM_NAME_SIZE 30
#define PLATFORM_MODULE_PREFIX platform:
struct platform_device_id {
--
1.7.4.4
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[PATCH 2/3] ARM: dts: Add osc clock node on smdk5420.
This patch adds 16MHz oscillator clock node required for audio
on smdk5420 and adds the phandle of the same in wm8994 clock info.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index b979405..a9eab45 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,13 @@
};
};
+ osc3_clk16mhz: clk16mhz {
+ compatible = osc3_clk16mhz;
+ #clock-cells = 0;
+ clock-frequency = 16934400;
+ clock-output-names = osc3_clk16mhz;
+ };
+
dwmmc0@1220 {
status = okay;
num-slots = 1;
@@ -123,6 +130,9 @@
DBVDD-supply = dbvdd;
SPKVDD1-supply = spkvdd;
SPKVDD2-supply = spkvdd;
+
+ clocks = osc3_clk16mhz;
+ clock-names = mclk1;
};
};
--
1.7.4.4
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[PATCH 1/3] ARM: dts: Enable sound support on smdk5420
This patch enables i2s0 and sound support on smdk5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index e86c1ae..b979405 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -126,4 +126,14 @@
};
};
+ i2s0: i2s@0383 {
+ status = okay;
+ };
+
+ sound {
+ compatible = samsung,smdk-wm8994;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = wm8994;
+ };
};
--
1.7.4.4
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[PATCH 2/7] ARM: dts: exynos5420: add i2s controllers
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the i2s controllers on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-on: https://gerrit.chromium.org/gerrit/57713
---
arch/arm/boot/dts/exynos5420.dtsi | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c2a2bd6..286354e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -242,4 +242,36 @@
pinctrl-names = default;
pinctrl-0 = i2c3_bus;
};
+
+ i2s_0: i2s@0383 {
+ compatible = samsung,exynos5420-i2s;
+ dmas = adma 0
+ adma 2
+ adma 1;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
+ status = disabled;
+ };
+
+ i2s_1: i2s@12D6 {
+ clocks = clock 275, clock 138;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s1_bus;
+ status = disabled;
+ };
+
+ i2s_2: i2s@12D7 {
+ clocks = clock 276, clock 139;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s2_bus;
+ status = disabled;
+ };
+
};
--
1.7.4.4
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[PATCH 4/7] ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi
I2S nodes shares some properties across exynos5 SoCs (exynos5250
and exyno5420). Common code is moved to exynos5.dtsi which is
included in exyno5250 and exynos5420 SoC files.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 21 +
arch/arm/boot/dts/exynos5250.dtsi | 12
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index ec384c9..c37b57d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -191,4 +191,25 @@
#size-cells = 0;
status = disabled;
};
+
+ i2s0: i2s@0383 {
+ reg = 0x0383 0x100;
+ samsung,idma-addr = 0x0300;
+ };
+
+ i2s1: i2s@12D6 {
+ compatible = samsung,s3c6410-i2s;
+ reg = 0x12D6 0x100;
+ dmas = pdma1 12
+ pdma1 11;
+ dma-names = tx, rx;
+ };
+
+ i2s2: i2s@12D7 {
+ compatible = samsung,s3c6410-i2s;
+ reg = 0x12D7 0x100;
+ dmas = pdma0 12
+ pdma0 11;
+ dma-names = tx, rx;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 5b36121..3873ff7 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -394,7 +394,6 @@
i2s0: i2s@0383 {
compatible = samsung,s5pv210-i2s;
- reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
@@ -403,17 +402,11 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,s3c6410-i2s;
- reg = 0x12D6 0x100;
- dmas = pdma1 12
- pdma1 11;
- dma-names = tx, rx;
clocks = clock 307, clock 157;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
@@ -421,11 +414,6 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,s3c6410-i2s;
- reg = 0x12D7 0x100;
- dmas = pdma0 12
- pdma0 11;
- dma-names = tx, rx;
clocks = clock 308, clock 158;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
--
1.7.4.4
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[PATCH V3 4/7] ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi
I2S nodes shares some properties across exynos5 SoCs (exynos5250
and exyno5420). Common code is moved to exynos5.dtsi which is
included in exyno5250 and exynos5420 SoC files.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 21 +
arch/arm/boot/dts/exynos5250.dtsi | 12
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index ec384c9..c37b57d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -191,4 +191,25 @@
#size-cells = 0;
status = disabled;
};
+
+ i2s0: i2s@0383 {
+ reg = 0x0383 0x100;
+ samsung,idma-addr = 0x0300;
+ };
+
+ i2s1: i2s@12D6 {
+ compatible = samsung,s3c6410-i2s;
+ reg = 0x12D6 0x100;
+ dmas = pdma1 12
+ pdma1 11;
+ dma-names = tx, rx;
+ };
+
+ i2s2: i2s@12D7 {
+ compatible = samsung,s3c6410-i2s;
+ reg = 0x12D7 0x100;
+ dmas = pdma0 12
+ pdma0 11;
+ dma-names = tx, rx;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 5b36121..3873ff7 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -394,7 +394,6 @@
i2s0: i2s@0383 {
compatible = samsung,s5pv210-i2s;
- reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
@@ -403,17 +402,11 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,s3c6410-i2s;
- reg = 0x12D6 0x100;
- dmas = pdma1 12
- pdma1 11;
- dma-names = tx, rx;
clocks = clock 307, clock 157;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
@@ -421,11 +414,6 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,s3c6410-i2s;
- reg = 0x12D7 0x100;
- dmas = pdma0 12
- pdma0 11;
- dma-names = tx, rx;
clocks = clock 308, clock 158;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
--
1.7.4.4
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[PATCH V3 3/7] ARM: dts: Add i2c bus 1 and it's audio codec child node on smdk5420
This patch adds i2c bus 1 and wm8994 codec node on i2c bus1 and the
required regulator supplies and properties on smdk5420 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 58 +
1 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index d05de7a..e86c1ae 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -68,4 +68,62 @@
bus-width = 4;
};
};
+
+ avdd2: fixed-regulator@0 {
+ compatible = regulator-fixed;
+ regulator-name = avdd2-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ cpvdd: fixed-regulator@1 {
+ compatible = regulator-fixed;
+ regulator-name = cpvdd-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ dbvdd: fixed-regulator@2 {
+ compatible = regulator-fixed;
+ regulator-name = dbvdd-supply;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ spkvdd: fixed-regulator@3 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+
+ i2c@12C7 {
+ status = okay;
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-max-bus-freq = 2;
+
+ eeprom@51 {
+ compatible = samsung,s524ad0xd1;
+ reg = 0x51;
+ };
+
+ wm8994: wm8994@1a {
+ compatible = wlf,wm8994;
+ reg = 0x1a;
+
+ gpio-controller;
+ #gpio-cells = 2;
+
+ AVDD2-supply = avdd2;
+ CPVDD-supply = cpvdd;
+ DBVDD-supply = dbvdd;
+ SPKVDD1-supply = spkvdd;
+ SPKVDD2-supply = spkvdd;
+ };
+ };
+
};
--
1.7.4.4
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[PATCH V3 7/7] ARM: dts: Enable sound support on smdk5420
This patch enables i2s0 and sound support on smdk5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 3c56a91..a9eab45 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -136,4 +136,14 @@
};
};
+ i2s0: i2s@0383 {
+ status = okay;
+ };
+
+ sound {
+ compatible = samsung,smdk-wm8994;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = wm8994;
+ };
};
--
1.7.4.4
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[PATCH V3 6/7] ASoC: Samsung: wm8994: Register the osc clock.
This patch registers the 16MHz oscillator clock as fixed clk.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
sound/soc/samsung/smdk_wm8994.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/sound/soc/samsung/smdk_wm8994.c b/sound/soc/samsung/smdk_wm8994.c
index 581ea4a..a6edded 100644
--- a/sound/soc/samsung/smdk_wm8994.c
+++ b/sound/soc/samsung/smdk_wm8994.c
@@ -9,6 +9,7 @@
#include ../codecs/wm8994.h
#include sound/pcm_params.h
+#include linux/clk-provider.h
#include linux/module.h
#include linux/of.h
@@ -37,6 +38,15 @@
/* SMDK has a 16.934MHZ crystal attached to WM8994 */
#define SMDK_WM8994_FREQ 16934000
+/* 16.9MHz fixed oscillator clock */
+static void init_osc_clock(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, osc3_clk16mhz);
+ of_fixed_clk_setup(np);
+}
+
static int smdk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
@@ -173,6 +183,8 @@ static int smdk_audio_probe(struct platform_device *pdev)
smdk_dai[0].platform_of_node = smdk_dai[0].cpu_of_node;
}
+ init_osc_clock();
+
ret = snd_soc_register_card(card);
if (ret)
--
1.7.4.4
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[PATCH V3 2/7] ARM: dts: exynos5420: add i2s controllers
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the i2s controllers on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-on: https://gerrit.chromium.org/gerrit/57713
---
arch/arm/boot/dts/exynos5420.dtsi | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c2a2bd6..286354e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -242,4 +242,36 @@
pinctrl-names = default;
pinctrl-0 = i2c3_bus;
};
+
+ i2s_0: i2s@0383 {
+ compatible = samsung,exynos5420-i2s;
+ dmas = adma 0
+ adma 2
+ adma 1;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
+ status = disabled;
+ };
+
+ i2s_1: i2s@12D6 {
+ clocks = clock 275, clock 138;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s1_bus;
+ status = disabled;
+ };
+
+ i2s_2: i2s@12D7 {
+ clocks = clock 276, clock 139;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s2_bus;
+ status = disabled;
+ };
+
};
--
1.7.4.4
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[PATCH V3 0/7] Add i2s nodes on Exynos5420 and enable sound support on sdmk5420
Changes since V2: - Seperated out driver side changes and dts changes in two patch sets - Added proper names for wm8994 regulators as commented by Mark - Moved common i2s nodes into the exynos5.dtsi - Added clock info in wm8994 node as requested by Mark. - Registered the 16.9MHz oscillator clock as fixed clock in the machine file. Right now no user of this clock but as Mark requested to add mclk info in wm8994 node, I added this part. This patch set is dependent on the following i2c, dma and audio subsystem clk controller patches. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20077 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20661 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20668 This patch set is made based on Kukjin Kim for-next branch. Andrew Bresticker (1): ARM: dts: exynos5420: add i2s controllers Padmavathi Venna (6): ARM: dts: Change i2s compatible string on exynos5250 ARM: dts: Add i2c bus 1 and it's audio codec child node on smdk5420 ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi ARM: dts: Add osc clock node on smdk5420. ASoC: Samsung: wm8994: Register the osc clock. ARM: dts: Enable sound support on smdk5420 arch/arm/boot/dts/exynos5.dtsi| 21 arch/arm/boot/dts/exynos5250.dtsi | 17 +-- arch/arm/boot/dts/exynos5420-smdk5420.dts | 78 + arch/arm/boot/dts/exynos5420.dtsi | 32 sound/soc/samsung/smdk_wm8994.c | 12 + 5 files changed, 144 insertions(+), 16 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 1/7] ARM: dts: Change i2s compatible string on exynos5250
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 48c0a88..5b36121 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -393,7 +393,7 @@
};
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
@@ -403,16 +403,13 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D6 0x100;
dmas = pdma1 12
pdma1 11;
@@ -424,7 +421,7 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D7 0x100;
dmas = pdma0 12
pdma0 11;
--
1.7.4.4
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[PATCH V3 5/7] ARM: dts: Add osc clock node on smdk5420.
This patch adds 16MHz oscillator clock node required for audio
on smdk5420 and adds the phandle of the same in wm8994 clock info.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index e86c1ae..3c56a91 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,13 @@
};
};
+ osc3_clk16mhz: clk16mhz {
+ compatible = osc3_clk16mhz;
+ #clock-cells = 0;
+ clock-frequency = 16934400;
+ clock-output-names = osc3_clk16mhz;
+ };
+
dwmmc0@1220 {
status = okay;
num-slots = 1;
@@ -123,6 +130,9 @@
DBVDD-supply = dbvdd;
SPKVDD1-supply = spkvdd;
SPKVDD2-supply = spkvdd;
+
+ clocks = osc3_clk16mhz;
+ clock-names = mclk1;
};
};
--
1.7.4.4
--
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[PATCH V2 1/8] platform: Increase platform name size
This patch increases the platform name size from 20 to 30.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
include/linux/mod_devicetable.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index b62d4af..f67b5d5 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -478,7 +478,7 @@ struct dmi_system_id {
#define DMI_MATCH(a, b){ .slot = a, .substr = b }
#define DMI_EXACT_MATCH(a, b) { .slot = a, .substr = b, .exact_match = 1 }
-#define PLATFORM_NAME_SIZE 20
+#define PLATFORM_NAME_SIZE 30
#define PLATFORM_MODULE_PREFIX platform:
struct platform_device_id {
--
1.7.4.4
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[PATCH V2 3/8] ARM: dts: Change i2s compatible string on exynos5250
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index db2ca8b..f7fbedd 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -385,7 +385,7 @@
};
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
@@ -395,16 +395,13 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D6 0x100;
dmas = pdma1 12
pdma1 11;
@@ -416,7 +413,7 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D7 0x100;
dmas = pdma0 12
pdma0 11;
--
1.7.4.4
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[PATCH V2 5/8] ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |4 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 15
sound/soc/samsung/i2s.c| 81 ++--
4 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index b3f6443..9b5c892 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -11,6 +11,10 @@ Required SoC Specific Properties:
with secondary fifo and s/w reset control.
- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
secondary fifo, s/w reset control and internal mux for root clk src.
+ - samsung,exynos5420-i2s: for 8/16/24bit multichannel(7.1) I2S with
+ secondary fifo, s/w reset control, internal mux for root clk src and
+ TDM support. TDM (Time division multiplexing) is to allow transfer of
+ multiple channel audio data on single data line.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index 30513b7..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR0x34
#define I2SLVL2ADDR0x38
#define I2SLVL3ADDR0x3c
+#define I2SSTR10x40
+#define I2SVER 0x44
+#define I2SFIC20x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -117,6 +121,17 @@
#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT 4
+#define EXYNOS5420_MOD_BCLK_SHIFT 0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS 6
+#define EXYNOS5420_MOD_BCLK_192FS 7
+#define EXYNOS5420_MOD_BCLK_256FS 8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 0b36b0a..bdbb65d 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -199,7 +199,12 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
+ u32 rfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
rfs = MOD_RCLK_MASK;
switch (rfs) {
@@ -214,8 +219,12 @@ static inline unsigned get_rfs(struct i2s_dai *i2s)
static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
{
u32 mod = readl(i2s-addr + I2SMOD);
- int rfs_shift = MOD_RCLK_SHIFT;
+ int rfs_shift;
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs_shift = EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs_shift = MOD_RCLK_SHIFT;
mod = ~(MOD_RCLK_MASK rfs_shift);
switch (rfs) {
@@ -239,10 +248,22 @@ static inline void set_rfs(struct i2s_dai *i2s, unsigned
rfs)
/* Read Bit-Clock of I2S (in multiples of LRCLK) */
static inline unsigned get_bfs(struct i2s_dai *i2s)
{
- u32 bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
- bfs = MOD_BCLK_MASK;
+ u32 bfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM) {
+ bfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_BCLK_SHIFT;
+ bfs = EXYNOS5420_MOD_BCLK_MASK;
+ } else {
+ bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
+ bfs = MOD_BCLK_MASK;
+ }
switch (bfs) {
+ case 8: return 256;
+ case 7: return 192;
+ case 6: return 128;
+ case
[PATCH V2 4/8] ASoC: Samsung: I2S: Modify driver to give more flexibility
This patch modifies the i2s driver to give flexibility towards register
handling. This is a pre requirement for enabling i2s support on Exynos5420.
This patch modifies only the required registers as a pre-requirement to
support on Exynos5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
sound/soc/samsung/i2s-regs.h | 36 ++---
sound/soc/samsung/i2s.c | 58 +
2 files changed, 55 insertions(+), 39 deletions(-)
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index c0e6d9a..30513b7 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -95,22 +95,26 @@
#define MOD_RXONLY (1 8)
#define MOD_TXRX (2 8)
#define MOD_MASK (3 8)
-#define MOD_LR_LLOW(0 7)
-#define MOD_LR_RLOW(1 7)
-#define MOD_SDF_IIS(0 5)
-#define MOD_SDF_MSB(1 5)
-#define MOD_SDF_LSB(2 5)
-#define MOD_SDF_MASK (3 5)
-#define MOD_RCLK_256FS (0 3)
-#define MOD_RCLK_512FS (1 3)
-#define MOD_RCLK_384FS (2 3)
-#define MOD_RCLK_768FS (3 3)
-#define MOD_RCLK_MASK (3 3)
-#define MOD_BCLK_32FS (0 1)
-#define MOD_BCLK_48FS (1 1)
-#define MOD_BCLK_16FS (2 1)
-#define MOD_BCLK_24FS (3 1)
-#define MOD_BCLK_MASK (3 1)
+#define MOD_LRP_SHIFT 7
+#define MOD_LR_LLOW0
+#define MOD_LR_RLOW1
+#define MOD_SDF_SHIFT 5
+#define MOD_SDF_IIS0
+#define MOD_SDF_MSB1
+#define MOD_SDF_LSB2
+#define MOD_SDF_MASK 3
+#define MOD_RCLK_SHIFT 3
+#define MOD_RCLK_256FS 0
+#define MOD_RCLK_512FS 1
+#define MOD_RCLK_384FS 2
+#define MOD_RCLK_768FS 3
+#define MOD_RCLK_MASK 3
+#define MOD_BCLK_SHIFT 1
+#define MOD_BCLK_32FS 0
+#define MOD_BCLK_48FS 1
+#define MOD_BCLK_16FS 2
+#define MOD_BCLK_24FS 3
+#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
#define MOD_CDCLKCON (1 12)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index f661a98..0b36b0a 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -199,7 +199,8 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) 3) 0x3;
+ u32 rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
+ rfs = MOD_RCLK_MASK;
switch (rfs) {
case 3: return 768;
@@ -213,21 +214,22 @@ static inline unsigned get_rfs(struct i2s_dai *i2s)
static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
{
u32 mod = readl(i2s-addr + I2SMOD);
+ int rfs_shift = MOD_RCLK_SHIFT;
- mod = ~MOD_RCLK_MASK;
+ mod = ~(MOD_RCLK_MASK rfs_shift);
switch (rfs) {
case 768:
- mod |= MOD_RCLK_768FS;
+ mod |= (MOD_RCLK_768FS rfs_shift);
break;
case 512:
- mod |= MOD_RCLK_512FS;
+ mod |= (MOD_RCLK_512FS rfs_shift);
break;
case 384:
- mod |= MOD_RCLK_384FS;
+ mod |= (MOD_RCLK_384FS rfs_shift);
break;
default:
- mod |= MOD_RCLK_256FS;
+ mod |= (MOD_RCLK_256FS rfs_shift);
break;
}
@@ -237,7 +239,8 @@ static inline void set_rfs(struct i2s_dai *i2s, unsigned
rfs)
/* Read Bit-Clock of I2S (in multiples of LRCLK) */
static inline unsigned get_bfs(struct i2s_dai *i2s)
{
- u32 bfs = (readl(i2s-addr + I2SMOD) 1) 0x3;
+ u32 bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
+ bfs = MOD_BCLK_MASK;
switch (bfs) {
case 3: return 24;
@@ -251,21 +254,22 @@ static inline unsigned get_bfs(struct i2s_dai *i2s)
static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
{
u32 mod = readl(i2s-addr + I2SMOD);
+ int bfs_shift = MOD_BCLK_SHIFT;
- mod = ~MOD_BCLK_MASK;
+ mod = ~(MOD_BCLK_MASK bfs_shift);
switch (bfs) {
case 48:
- mod |= MOD_BCLK_48FS;
+ mod |= (MOD_BCLK_48FS bfs_shift);
break;
case 32:
- mod |= MOD_BCLK_32FS;
+ mod |= (MOD_BCLK_32FS bfs_shift);
break;
case 24:
- mod |= MOD_BCLK_24FS;
+ mod |= (MOD_BCLK_24FS bfs_shift);
break;
case 16:
- mod |= MOD_BCLK_16FS;
+ mod |= (MOD_BCLK_16FS bfs_shift);
break;
default:
dev_err(i2s-pdev-dev, Wrong BCLK Divider!\n);
@@ -492,20 +496,25 @@ static int i2s_set_fmt(struct snd_soc_dai *dai,
{
struct i2s_dai *i2s = to_info
[PATCH V2 0/8] Add audio support on smdk5420
Samsung has different versions of I2S introduced in different platforms. Each version has some new support added for multichannel, secondary fifo, s/w reset control, internal mux for rclk src clk and tdm support. Each newly added change has a quirk. So this patch adds all the required quirks as driver data and based on compatible string from dtsi fetches the quirks. This also adds i2s support on exynos5420 and make relevent changes in the dtsi files. Changes since V1: - Pass quirks as driver data and fetch the quirks based on compatible string from dtsi file as suggested by Tomasz Figa and Mark Brown - Make the I2S driver more flexible with respect to register access as suggested by Tomasz Figa and Mark Brown - Add 5420 support in the driver. - Modify the dtsi files with the corresponding compatible strings and removed the i2s quirks from 5250 dtsi file. - Updated the i2s Documentation with relevent changes and i2s versioning info. - Add i2s nodes on exynos5420.dtsi - Enable sound support on smdk5420 This patch set is dependent on the following dma and audio subsystem clk controller patches. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20661 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20668 This patch set is made based on Kukjin Kim for-next branch. Andrew Bresticker (1): ARM: dts: exynos5420: add i2s controllers Padmavathi Venna (7): platform: Increase platform name size ASoC: Samsung: I2S: Add quirks as driver data in I2S ARM: dts: Change i2s compatible string on exynos5250 ASoC: Samsung: I2S: Modify driver to give more flexibility ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420 ARM: dts: wm8994: Add wm8994 support on smdk5420 ARM: dts: Enable sound support on smdk5420 .../devicetree/bindings/sound/samsung-i2s.txt | 25 ++- arch/arm/boot/dts/exynos5250.dtsi |9 +- arch/arm/boot/dts/exynos5420-smdk5420.dts | 60 ++ arch/arm/boot/dts/exynos5420.dtsi | 44 + include/linux/mod_devicetable.h|2 +- include/linux/platform_data/asoc-s3c.h |1 + sound/soc/samsung/i2s-regs.h | 51 -- sound/soc/samsung/i2s.c| 205 +++- 8 files changed, 312 insertions(+), 85 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 2/8] ASoC: Samsung: I2S: Add quirks as driver data in I2S
Samsung has different versions of I2S introduced in different
platforms. Each version has some new support added for multichannel,
secondary fifo, s/w reset control and internal mux for rclk src clk.
Each newly added change has a quirk. So this patch adds all the
required quirks as driver data and based on compatible string from
dtsi fetches the quirks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 21 +++---
sound/soc/samsung/i2s.c| 82 +---
2 files changed, 64 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 025e66b..b3f6443 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -2,7 +2,16 @@
Required SoC Specific Properties:
-- compatible : samsung,i2s-v5
+- compatible : should be one of the following.
+ - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. Previous versions
+ has only 8/16bit support.
+ - samsung,s3c6410-i2sv4: for 8/16/24bit multichannel(5.1 channel) I2S.
+ Introduced in s3c6410. This also applicable for s5p64x0 platforms.
+ - samsung,s5pc100-i2s: for 8/16/24bit multichannel(5.1 channel) I2S
+ with secondary fifo and s/w reset control.
+ - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
+ secondary fifo, s/w reset control and internal mux for root clk src.
+
- reg: physical base address of the controller and length of memory mapped
region.
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
@@ -21,13 +30,6 @@ Required SoC Specific Properties:
Optional SoC Specific Properties:
-- samsung,supports-6ch: If the I2S Primary sound source has 5.1 Channel
- support, this flag is enabled.
-- samsung,supports-rstclr: This flag should be set if I2S software reset bit
- control is required. When this flag is set I2S software reset bit will be
- enabled or disabled based on need.
-- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
- then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
@@ -46,9 +48,6 @@ i2s0: i2s@0383 {
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 959c702..f661a98 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -40,6 +40,7 @@ enum samsung_dai_type {
struct samsung_i2s_dai_data {
int dai_type;
+ u32 quirks;
};
struct i2s_dai {
@@ -1018,18 +1019,18 @@ static struct i2s_dai *i2s_alloc_dai(struct
platform_device *pdev, bool sec)
static const struct of_device_id exynos_i2s_match[];
-static inline int samsung_i2s_get_driver_data(struct platform_device *pdev)
+static inline struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
+ struct platform_device *pdev)
{
#ifdef CONFIG_OF
- struct samsung_i2s_dai_data *data;
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(exynos_i2s_match, pdev-dev.of_node);
- data = (struct samsung_i2s_dai_data *) match-data;
- return data-dai_type;
+ return (struct samsung_i2s_dai_data *) match-data;
} else
#endif
- return platform_get_device_id(pdev)-driver_data;
+ return (struct samsung_i2s_dai_data *)
+ platform_get_device_id(pdev)-driver_data;
}
#ifdef CONFIG_PM_RUNTIME
@@ -1060,13 +1061,13 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
struct resource *res;
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
- enum samsung_dai_type samsung_dai_type;
+ struct samsung_i2s_dai_data *i2s_dai_data;
int ret = 0;
/* Call during Seconday interface registration */
- samsung_dai_type = samsung_i2s_get_driver_data(pdev);
+ i2s_dai_data = samsung_i2s_get_driver_data(pdev);
- if (samsung_dai_type == TYPE_SEC) {
+ if (i2s_dai_data-dai_type == TYPE_SEC) {
sec_dai = dev_get_drvdata(pdev-dev);
if (!sec_dai) {
dev_err(pdev-dev, Unable to get drvdata\n);
@@ -1115,15 +1116,7 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
idma_addr = i2s_cfg
[PATCH] ASoC: Samsung: Set RFS and BFS in slave mode
As per the User Manual, the RFS and BFS should be set in slave mode
for correct operation.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit-int.chromium.org/37841
Reviewed-by: Simon Glass s...@google.com
---
sound/soc/samsung/i2s.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 82ebb1a..3fcf8d7 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -742,13 +742,13 @@ static int config_setup(struct i2s_dai *i2s)
return -EAGAIN;
}
- /* Don't bother RFS, BFS PSR in Slave mode */
- if (is_slave(i2s))
- return 0;
-
set_bfs(i2s, bfs);
set_rfs(i2s, rfs);
+ /* Don't bother with PSR in Slave mode */
+ if (is_slave(i2s))
+ return 0;
+
if (!(i2s-quirks QUIRK_NO_MUXPSR)) {
psr = i2s-rclk_srcrate / i2s-frmclk / rfs;
writel(((psr - 1) 8) | PSR_PSREN, i2s-addr + I2SPSR);
--
1.7.4.4
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[PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
[abrestic: style cleanup and documentation]
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit-int.chromium.org/37840
Reviewed-by: Simon Glass s...@google.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |2 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 51 ++---
sound/soc/samsung/i2s.c| 117
4 files changed, 132 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 025e66b..b8593d5 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -28,6 +28,8 @@ Optional SoC Specific Properties:
enabled or disabled based on need.
- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
then this flag is enabled.
+- samsung,supports-tdm: If the I2S controller supports TDM, then this flag
+ must be enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index c0e6d9a..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR0x34
#define I2SLVL2ADDR0x38
#define I2SLVL3ADDR0x3c
+#define I2SSTR10x40
+#define I2SVER 0x44
+#define I2SFIC20x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -95,24 +99,39 @@
#define MOD_RXONLY (1 8)
#define MOD_TXRX (2 8)
#define MOD_MASK (3 8)
-#define MOD_LR_LLOW(0 7)
-#define MOD_LR_RLOW(1 7)
-#define MOD_SDF_IIS(0 5)
-#define MOD_SDF_MSB(1 5)
-#define MOD_SDF_LSB(2 5)
-#define MOD_SDF_MASK (3 5)
-#define MOD_RCLK_256FS (0 3)
-#define MOD_RCLK_512FS (1 3)
-#define MOD_RCLK_384FS (2 3)
-#define MOD_RCLK_768FS (3 3)
-#define MOD_RCLK_MASK (3 3)
-#define MOD_BCLK_32FS (0 1)
-#define MOD_BCLK_48FS (1 1)
-#define MOD_BCLK_16FS (2 1)
-#define MOD_BCLK_24FS (3 1)
-#define MOD_BCLK_MASK (3 1)
+#define MOD_LRP_SHIFT 7
+#define MOD_LR_LLOW0
+#define MOD_LR_RLOW1
+#define MOD_SDF_SHIFT 5
+#define MOD_SDF_IIS0
+#define MOD_SDF_MSB1
+#define MOD_SDF_LSB2
+#define MOD_SDF_MASK 3
+#define MOD_RCLK_SHIFT 3
+#define MOD_RCLK_256FS 0
+#define MOD_RCLK_512FS 1
+#define MOD_RCLK_384FS 2
+#define MOD_RCLK_768FS 3
+#define MOD_RCLK_MASK 3
+#define MOD_BCLK_SHIFT 1
+#define MOD_BCLK_32FS 0
+#define MOD_BCLK_48FS 1
+#define MOD_BCLK_16FS 2
+#define MOD_BCLK_24FS 3
+#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT 4
+#define EXYNOS5420_MOD_BCLK_SHIFT 0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS 6
+#define EXYNOS5420_MOD_BCLK_192FS 7
+#define EXYNOS5420_MOD_BCLK_256FS 8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 3fcf8d7..398f8db 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -198,7 +198,13 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) 3) 0x3;
+ u32 rfs
[PATCH 3/4] ARM: dts: Correct the /include entry on exynos5420 dtsi file
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 8c54c4b..da55160 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -14,7 +14,7 @@
*/
#include exynos5.dtsi
-/include/ exynos5420-pinctrl.dtsi
+#include exynos5420-pinctrl.dtsi
/ {
compatible = samsung,exynos5420;
--
1.7.4.4
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[PATCH 2/4] clk: exynos-audss: allow input clocks to be specified in device tree
From: Andrew Bresticker abres...@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified
via device-tree bindings. Default names will be used when an input clock
is not given. This will be useful when adding support for the Exynos5420
where the audio bus clock is called sclk_maudio0 instead of sclk_audio0.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57833
Reviewed-by: Simon Glass s...@chromium.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 31 ++-
drivers/clk/samsung/clk-exynos-audss.c | 28 +++--
2 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 3115930..66d4662 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -16,6 +16,21 @@ Required Properties:
- #clock-cells: should be 1.
+Optional Properties:
+
+- clocks:
+ - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. fin_pll
+is used if not specified.
+ - pll_in: Input PLL to the AudioSS block, parent of mout_audss. fout_epll
+is used if not specified.
+ - cdclk: External i2s clock, parent of mout_i2s. cdclk0 is used if not
+specified.
+ - sclk_audio: Audio bus clock, parent of mout_i2s. sclk_audio0 is used if
+not specified.
+
+- clock-names: Aliases for the above clocks. They should be pll_ref,
+ pll_in, cdclk, and sclk_audio, respectively.
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -38,15 +53,27 @@ pcm_bus 8
sclk_pcm9
adma10 Exynos5420
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+ clock names is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: An example of a clock controller node with audio bus input clock
+ specified is listed below.
clock_audss: audss-clock-controller@381 {
compatible = samsung,exynos5250-audss-clock;
reg = 0x0381 0x0C;
#clock-cells = 1;
+ clocks = clock 148;
+ clock-names = sclk_audio;
};
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 86d2606..39d3383 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -32,10 +32,6 @@ static unsigned long reg_save[][2] = {
{ASS_CLK_GATE, 0},
};
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { fin_pll, fout_epll };
-static const char *mout_i2s_p[] = { mout_audss, cdclk0, sclk_audio0 };
-
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
@@ -64,6 +60,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
/* register exynos_audss clocks */
void __init exynos_audss_clk_init(struct device_node *np)
{
+ const char *mout_audss_p[] = {fin_pll, fout_epll};
+ const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio;
+
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err(%s: failed to map audss registers\n, __func__);
@@ -81,10 +81,30 @@ void __init exynos_audss_clk_init(struct device_node *np)
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+ pll_ref = of_clk_get_by_name(np, pll_ref);
+ pll_in = of_clk_get_by_name(np, pll_in);
+ if (!IS_ERR(pll_ref)) {
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ clk_put(pll_ref);
+ }
+ if (!IS_ERR(pll_in)) {
+ mout_audss_p[1] = __clk_get_name(pll_in);
+ clk_put(pll_in);
+ }
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
reg_base + ASS_CLK_SRC, 0, 1, 0, lock);
+ cdclk = of_clk_get_by_name(np, cdclk);
+ sclk_audio = of_clk_get_by_name(np, sclk_audio);
+ if (!IS_ERR(cdclk)) {
+ mout_i2s_p[1] = __clk_get_name(cdclk);
+
[PATCH 4/4] ARM: dts: exynos5420: add audio clock controller
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57712
Reviewed-by: Simon Glass s...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index da55160..a84f5f1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -15,6 +15,9 @@
#include exynos5.dtsi
#include exynos5420-pinctrl.dtsi
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5420;
@@ -65,6 +68,14 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5420-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ clocks = clock 148;
+ clock-names = sclk_audio;
+ };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
--
1.7.4.4
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[PATCH 1/4] clk: exynos-audss: add support for Exynos 5420
From: Andrew Bresticker abres...@chromium.org
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57711
Reviewed-by: Simon Glass s...@chromium.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt |7 +--
drivers/clk/samsung/clk-exynos-audss.c |8
include/dt-bindings/clk/exynos-audss-clk.h |3 ++-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a120180..3115930 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
- - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
-
+ - samsung,exynos5250-audss-clock - controller compatible with Exynos5250
+SoCs.
+ - samsung,exynos5420-audss-clock - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -34,6 +36,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd5..86d2606 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np)
div_pcm0, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
+ if (of_device_is_compatible(np, samsung,exynos5420-audss-clock)) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, adma,
+ dout_srp, CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, lock);
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(exynos_audss_clk_syscore_ops);
#endif
@@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk,
samsung,exynos4210-audss-clock,
exynos_audss_clk_init);
CLK_OF_DECLARE(exynos5250_audss_clk, samsung,exynos5250-audss-clock,
exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5420_audss_clk, samsung,exynos5420-audss-clock,
+ exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h
b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM9
+#define EXYNOS_ADMA10
-#define EXYNOS_AUDSS_MAX_CLKS 10
+#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
--
1.7.4.4
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[PATCH 0/2] Move comon DMA nodes to exynos5.dtsi and
Exynos5250 and Exynos5420 has 4 DMA controllers in common. So this patch set moved the common nodes to exynos.dtsi keeping the clk info seperate for both the platforms. Exynos5420 has a separate DMA controller for audio IPs. So this patch set also adds the ADMA node on Exynos5420. Padmavathi Venna (2): ARM: dts: Move the common DMA controller nodes to exynos5.dtsi ARM: dts: Add DMA controller node info on Exynos5420. arch/arm/boot/dts/exynos5.dtsi| 44 + arch/arm/boot/dts/exynos5250.dtsi | 30 - arch/arm/boot/dts/exynos5420.dtsi | 33 +++ 3 files changed, 77 insertions(+), 30 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: Move the common DMA controller nodes to exynos5.dtsi
exynos5250 and exynos5420 has 4 DMA controllers in common. So this patch
moves these nodes to common file keeping the dma controllers clk info in
the exynos5250 dtsi file.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 44 +
arch/arm/boot/dts/exynos5250.dtsi | 30 -
2 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..cac35c8 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,6 +50,50 @@
interrupts = 1 9 0xf04;
};
+ amba {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = arm,amba-bus;
+ interrupt-parent = gic;
+ ranges;
+
+ pdma0: pdma@121A {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121A 0x1000;
+ interrupts = 0 34 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@121B {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121B 0x1000;
+ interrupts = 0 35 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ mdma0: mdma@1080 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1080 0x1000;
+ interrupts = 0 33 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+
+ mdma1: mdma@11C1 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x11C1 0x1000;
+ interrupts = 0 124 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+ };
+
dwmmc_0: dwmmc0@1220 {
compatible = samsung,exynos5250-dw-mshc;
interrupts = 0 75 0;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 41cd625..3a474c4 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -511,54 +511,24 @@
};
amba {
- #address-cells = 1;
- #size-cells = 1;
- compatible = arm,amba-bus;
- interrupt-parent = gic;
- ranges;
-
pdma0: pdma@121A {
- compatible = arm,pl330, arm,primecell;
- reg = 0x121A 0x1000;
- interrupts = 0 34 0;
clocks = clock 275;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 32;
};
pdma1: pdma@121B {
- compatible = arm,pl330, arm,primecell;
- reg = 0x121B 0x1000;
- interrupts = 0 35 0;
clocks = clock 276;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 32;
};
mdma0: mdma@1080 {
- compatible = arm,pl330, arm,primecell;
- reg = 0x1080 0x1000;
- interrupts = 0 33 0;
clocks = clock 271;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 1;
};
mdma1: mdma@11C1 {
- compatible = arm,pl330, arm,primecell;
- reg = 0x11C1 0x1000;
- interrupts = 0 124 0;
clocks = clock 271;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 1;
};
};
--
1.7.4.4
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[PATCH 2/2] ARM: dts: Add DMA controller node info on Exynos5420.
Exynos5420 has one separate DMA controller for I2S0 and PCM0. This patch
adds the same node on exynos5420 dtsi and adds the DMA clk info for the
remaining DMA controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index a84f5f1..7035a4b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -137,6 +137,39 @@
interrupts = 0 47 0;
};
+ amba {
+ pdma0: pdma@121A {
+ clocks = clock 362;
+ clock-names = apb_pclk;
+ };
+
+ pdma1: pdma@121B {
+ clocks = clock 363;
+ clock-names = apb_pclk;
+ };
+
+ mdma0: mdma@1080 {
+ clocks = clock 473;
+ clock-names = apb_pclk;
+ };
+
+ mdma1: mdma@11C1 {
+ clocks = clock 442;
+ clock-names = apb_pclk;
+ };
+
+ adma: adma@0388 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x0388 0x1000;
+ interrupts = 0 110 0;
+ clocks = clock_audss EXYNOS_ADMA;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 6;
+ #dma-requests = 16;
+ };
+ };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
--
1.7.4.4
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[PATCH V6 4/6] ARM: dts: add clock provider information for i2s controllers in Exynos5250
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 84edf42..0aa9091 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
#include skeleton.dtsi
#include exynos5250-pinctrl.dtsi
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5250;
interrupt-parent = gic;
@@ -457,6 +459,10 @@
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@@ -471,6 +477,8 @@
dmas = pdma1 12
pdma1 11;
dma-names = tx, rx;
+ clocks = clock 307, clock 157;
+ clock-names = iis, i2s_opclk0;
pinctrl-names = default;
pinctrl-0 = i2s1_bus;
};
@@ -481,6 +489,8 @@
dmas = pdma0 12
pdma0 11;
dma-names = tx, rx;
+ clocks = clock 308, clock 158;
+ clock-names = iis, i2s_opclk0;
pinctrl-names = default;
pinctrl-0 = i2s2_bus;
};
--
1.7.4.4
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[PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework
Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem has a internal clock controller which controls i2s0 and pcm0 clocks. This patch series adds the Samsung audio subsytem clock to the common clock framework and provides the I2S controllers clock information in the dtsi file. This patch series is made based on Kukjin Kim for-next branch Changes since V5: - Added i2s_opclk0 entry for i2s1 and i2s2 nodes - Added Acked-by: Mike Turquette mturque...@linaro.org - Added Reviewed-by: Doug Anderson diand...@chromium.org Changes since V4: - Reworked on the nits given by Doug. - Removed mout_audss and mout_i2s from i2s nodes as we are not getting these clocks in the i2s driver. - Modified the I2S binding documentation for clocks and pinmux. Changes since V3: - Replaced samsung with exynos in the macro prefixes and function names as this driver supports mainly exynos and s5p family. - Added Reviewed-by:Sylwester Nawrocki s.nawro...@samsung.com Changes since V2: - Removed s5pv210 compatible name from driver as it is not yet supported which is different from Exynos series audio subsystem clock conroller. - Removed clkdev lookup support and added alias names in the i2s0 controller node. Changes since V1: - Reworked on all review comments by Sylwester Nawrocki - Added a header file for all clock indexes as requested by Sylwester - Added different compatible names for s5pv210, exynos4 and exynos5 - Registered the pcm clocks with common clock framework Padmavathi Venna (6): ARM: samsung: use #include for all device trees clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: add Exynos audio subsystem clock controller node ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: Update Samsung I2S documentation clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 .../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++ .../devicetree/bindings/sound/samsung-i2s.txt | 46 +++ arch/arm/boot/dts/exynos4.dtsi |2 +- arch/arm/boot/dts/exynos4210-origen.dts|2 +- arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +- arch/arm/boot/dts/exynos4210-trats.dts |2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts|2 +- arch/arm/boot/dts/exynos4210.dtsi |4 +- arch/arm/boot/dts/exynos4212.dtsi |2 +- arch/arm/boot/dts/exynos4412-odroidx.dts |2 +- arch/arm/boot/dts/exynos4412-origen.dts|2 +- arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +- arch/arm/boot/dts/exynos4412.dtsi |2 +- arch/arm/boot/dts/exynos4x12.dtsi |4 +- arch/arm/boot/dts/exynos5250-arndale.dts |2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- arch/arm/boot/dts/exynos5250-snow.dts |4 +- arch/arm/boot/dts/exynos5250.dtsi | 20 +++- arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +- arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +- arch/arm/boot/dts/exynos5440.dtsi |2 +- arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +- arch/arm/boot/dts/s3c2416.dtsi |4 +- arch/arm/boot/dts/s3c24xx.dtsi |2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos-audss.c | 133 drivers/clk/samsung/clk-exynos5250.c |5 +- include/dt-bindings/clk/exynos-audss-clk.h | 25 28 files changed, 288 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt create mode 100644 drivers/clk/samsung/clk-exynos-audss.c create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7c68850 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -87,6 +87,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+ div_i2s1, div_i2s2,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata =
{
DIV(none, div_pcm1, sclk_audio1, DIV_PERIC4, 4, 8),
DIV(none, div_audio2, mout_audio2, DIV_PERIC4, 16, 4),
DIV(none, div_pcm2, sclk_audio2, DIV_PERIC4, 20, 8),
- DIV(none, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
- DIV(none, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
+ DIV(div_i2s1, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
+ DIV(div_i2s2, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
DIV(sclk_pixel, div_hdmi_pixel, sclk_vpll, DIV_DISP1_0, 28, 4),
DIV_A(none, armclk, div_arm, DIV_CPU0, 28, 3, armclk),
DIV_F(none, div_mipi1_pre, div_mipi1,
--
1.7.4.4
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[PATCH V6 1/6] ARM: samsung: use #include for all device trees
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos4.dtsi |2 +-
arch/arm/boot/dts/exynos4210-origen.dts |2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4210-trats.dts |2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts |2 +-
arch/arm/boot/dts/exynos4210.dtsi |4 ++--
arch/arm/boot/dts/exynos4212.dtsi |2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts|2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +-
arch/arm/boot/dts/exynos4412.dtsi |2 +-
arch/arm/boot/dts/exynos4x12.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts|2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5250-snow.dts |4 ++--
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
arch/arm/boot/dts/exynos5440.dtsi |2 +-
arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +-
arch/arm/boot/dts/s3c2416.dtsi |4 ++--
arch/arm/boot/dts/s3c24xx.dtsi |2 +-
22 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
interrupt-parent = gic;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung smdkv310 evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Trats based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Universal C210 based on Exynos4210 rev0;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index d4f8067..b7f358a 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4.dtsi
-/include/ exynos4210-pinctrl.dtsi
+#include exynos4.dtsi
+#include exynos4210-pinctrl.dtsi
/ {
compatible = samsung,exynos4210;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include exynos4x12.dtsi
/ {
compatible = samsung,exynos4212;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 867d945..46c678e 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Hardkernel ODROID-X board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index ca73c42..7993641 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model
[PATCH V6 2/6] clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Acked-by: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos-audss.c | 133
include/dt-bindings/clk/exynos-audss-clk.h | 25
4 files changed, 223 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 000..a120180
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+ - samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
+ - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock ID SoC (if specific)
+---
+
+mout_audss 0
+mout_i2s1
+dout_srp2
+dout_aud_bus3
+dout_i2s4
+srp_clk 5
+i2s_bus 6
+sclk_i2s7
+pcm_bus 8
+sclk_pcm9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@0383 {
+ compatible = samsung,i2s-v5;
+ reg = 0x0383 0x100;
+ dmas = pdma0 10
+ pdma0 9
+ pdma0 8;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S,
+ clock_audss EXYNOS_MOUT_AUDSS,
+ clock_audss EXYNOS_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 000..9b1bbd5
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna padm...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/clk-provider.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0
[PATCH V6 3/6] ARM: dts: add Exynos audio subsystem clock controller node
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos5250.dtsi |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 5cfc5b7..84edf42 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ };
+
gic:interrupt-controller@10481000 {
compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
#interrupt-cells = 3;
--
1.7.4.4
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[PATCH V6 5/6] ARM: dts: Update Samsung I2S documentation
This patch updates the samsung i2s documentation for pinmux and
clock entries.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 46 ---
1 files changed, 19 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046..025e66b 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,16 @@ Required SoC Specific Properties:
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
- dma-names: identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: Handle to iis clock and RCLK source clk.
+- clock-names:
+ i2s0 uses some base clks from CMU and some are from audio subsystem internal
+ clock controller. The clock names for i2s0 should be iis, i2s_opclk0 and
+ i2s_opclk1 as shown in the example below.
+ i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
+ be iis and i2s_opclk0.
+ iis is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
+ clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
+ doesn't have any such mux.
Optional SoC Specific Properties:
@@ -20,44 +30,26 @@ Optional SoC Specific Properties:
then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
-
-Required Board Specific Properties:
-
-- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
- interface lines. The format of the gpio specifier depends on the gpio
- controller.
- The syntax of samsung gpio specifier is
- [phandle of the gpio controller node]
-[pin number within the gpio controller]
-[mux function]
-[flags and pull up/down]
-[drive strength]
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - default.
Example:
-- SoC Specific Portion:
-
-i2s@0383 {
+i2s0: i2s@0383 {
compatible = samsung,i2s-v5;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = 0x0300;
-};
-
-- Board Specific Portion:
-
-i2s@0383 {
- gpios = gpz 0 2 0 0, /* I2S_0_SCLK */
- gpz 1 2 0 0, /* I2S_0_CDCLK */
- gpz 2 2 0 0, /* I2S_0_LRCK */
- gpz 3 2 0 0, /* I2S_0_SDI */
- gpz 4 2 0 0, /* I2S_0_SDO[1] */
- gpz 5 2 0 0, /* I2S_0_SDO[2] */
- gpz 6 2 0 0; /* I2S_0_SDO[3] */
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
};
--
1.7.4.4
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[PATCH RESEND V2] ARM: dts: Correct the base address of pinctrl_3 on Exynos5250
This patch corrects the base address of pinctrl_3 on Exynos5250
platform.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Added platform name in the subject line.
arch/arm/boot/dts/exynos5250-pinctrl.dtsi |2 +-
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb..ded558b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -763,7 +763,7 @@
};
};
- pinctrl@0368 {
+ pinctrl@0386 {
gpz: gpz {
gpio-controller;
#gpio-cells = 2;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7154e3d..e9bfd13 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -169,9 +169,9 @@
interrupts = 0 50 0;
};
- pinctrl_3: pinctrl@0368 {
+ pinctrl_3: pinctrl@0386 {
compatible = samsung,exynos5250-pinctrl;
- reg = 0x0368000 0x1000;
+ reg = 0x0386 0x1000;
interrupts = 0 47 0;
};
--
1.7.4.4
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[PATCH RESEND V2] ARM: dts: wm8994: Add wm8994 regulator support on smdk5250.
This patch adds the required regulator supplies and properties
for wm8994 codec on smdk5250 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Clubbed the same supply regulators as suggested by Mark.
arch/arm/boot/dts/exynos5250-smdk5250.dts | 37 +++-
1 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f2a025e..dc2ec25 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -37,6 +37,30 @@
};
};
+ vdd:fixed-regulator@0 {
+ compatible = regulator-fixed;
+ regulator-name = vdd-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ dbvdd:fixed-regulator@1 {
+ compatible = regulator-fixed;
+ regulator-name = dbvdd-supply;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ spkvdd:fixed-regulator@2 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+
i2c@12C7 {
samsung,i2c-sda-delay = 100;
samsung,i2c-max-bus-freq = 2;
@@ -47,8 +71,17 @@
};
wm8994: wm8994@1a {
-compatible = wlf,wm8994;
-reg = 0x1a;
+ compatible = wlf,wm8994;
+ reg = 0x1a;
+
+ gpio-controller;
+ #gpio-cells = 2;
+
+ AVDD2-supply = vdd;
+ CPVDD-supply = vdd;
+ DBVDD-supply = dbvdd;
+ SPKVDD1-supply = spkvdd;
+ SPKVDD2-supply = spkvdd;
};
};
--
1.7.4.4
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[PATCH V5 0/5] clk: Samsung: audss: Register audio subsytem clocks using common clk framework
Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem has a internal clock controller which controls i2s0 and pcm0 clocks. This patch series adds the Samsung audio subsytem clock to the common clock framework and provides the I2S controllers clock information in the dtsi file. This patch series is made based on Kukjin Kim for-next branch Changes since V4: - Reworked on the nits given by Doug. - Removed mout_audss and mout_i2s from i2s nodes as we are not getting these clocks in the i2s driver. - Modified the I2S binding documentation for clocks and pinmux. Changes since V3: - Replaced samsung with exynos in the macro prefixes and function names as this driver supports mainly exynos and s5p family. - Added Reviewed-by:Sylwester Nawrocki s.nawro...@samsung.com Changes since V2: - Removed s5pv210 compatible name from driver as it is not yet supported which is different from Exynos series audio subsystem clock conroller. - Removed clkdev lookup support and added alias names in the i2s0 controller node. Changes since V1: - Reworked on all review comments by Sylwester Nawrocki - Added a header file for all clock indexes as requested by Sylwester - Added different compatible names for s5pv210, exynos4 and exynos5 - Registered the pcm clocks with common clock framework Padmavathi Venna (5): ARM: samsung: use #include for all device trees clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: add Exynos audio subsystem clock controller node ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: Update Samsung I2S documentation .../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++ .../devicetree/bindings/sound/samsung-i2s.txt | 40 ++ arch/arm/boot/dts/exynos4.dtsi |2 +- arch/arm/boot/dts/exynos4210-origen.dts|2 +- arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +- arch/arm/boot/dts/exynos4210-trats.dts |2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts|2 +- arch/arm/boot/dts/exynos4210.dtsi |4 +- arch/arm/boot/dts/exynos4212.dtsi |2 +- arch/arm/boot/dts/exynos4412-odroidx.dts |2 +- arch/arm/boot/dts/exynos4412-origen.dts|2 +- arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +- arch/arm/boot/dts/exynos4412.dtsi |2 +- arch/arm/boot/dts/exynos4x12.dtsi |4 +- arch/arm/boot/dts/exynos5250-arndale.dts |2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- arch/arm/boot/dts/exynos5250-snow.dts |4 +- arch/arm/boot/dts/exynos5250.dtsi | 20 +++- arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +- arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +- arch/arm/boot/dts/exynos5440.dtsi |2 +- arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +- arch/arm/boot/dts/s3c2416.dtsi |4 +- arch/arm/boot/dts/s3c24xx.dtsi |2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos-audss.c | 133 include/dt-bindings/clk/exynos-audss-clk.h | 25 27 files changed, 279 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt create mode 100644 drivers/clk/samsung/clk-exynos-audss.c create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 1/5] ARM: samsung: use #include for all device trees
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi |2 +-
arch/arm/boot/dts/exynos4210-origen.dts |2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4210-trats.dts |2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts |2 +-
arch/arm/boot/dts/exynos4210.dtsi |4 ++--
arch/arm/boot/dts/exynos4212.dtsi |2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts|2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +-
arch/arm/boot/dts/exynos4412.dtsi |2 +-
arch/arm/boot/dts/exynos4x12.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts|2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5250-snow.dts |4 ++--
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
arch/arm/boot/dts/exynos5440.dtsi |2 +-
arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +-
arch/arm/boot/dts/s3c2416.dtsi |4 ++--
arch/arm/boot/dts/s3c24xx.dtsi |2 +-
22 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
interrupt-parent = gic;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung smdkv310 evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Trats based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Universal C210 based on Exynos4210 rev0;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..75c2756 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4.dtsi
-/include/ exynos4210-pinctrl.dtsi
+#include exynos4.dtsi
+#include exynos4210-pinctrl.dtsi
/ {
compatible = samsung,exynos4210;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include exynos4x12.dtsi
/ {
compatible = samsung,exynos4212;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..7bb8d48 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Hardkernel ODROID-X board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..df097b5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4412
[PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos-audss.c | 133
include/dt-bindings/clk/exynos-audss-clk.h | 25
4 files changed, 223 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 000..a120180
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+ - samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
+ - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock ID SoC (if specific)
+---
+
+mout_audss 0
+mout_i2s1
+dout_srp2
+dout_aud_bus3
+dout_i2s4
+srp_clk 5
+i2s_bus 6
+sclk_i2s7
+pcm_bus 8
+sclk_pcm9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@0383 {
+ compatible = samsung,i2s-v5;
+ reg = 0x0383 0x100;
+ dmas = pdma0 10
+ pdma0 9
+ pdma0 8;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S,
+ clock_audss EXYNOS_MOUT_AUDSS,
+ clock_audss EXYNOS_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 000..9b1bbd5
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna padm...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/clk-provider.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { fin_pll
[PATCH V5 3/5] ARM: dts: add Exynos audio subsystem clock controller node
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index bccda67..388983e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ };
+
gic:interrupt-controller@10481000 {
compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
#interrupt-cells = 3;
--
1.7.4.4
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[PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 388983e..1e62ca9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
#include skeleton.dtsi
#include exynos5250-pinctrl.dtsi
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5250;
interrupt-parent = gic;
@@ -457,6 +459,10 @@
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@@ -471,6 +477,8 @@
dmas = pdma1 12
pdma1 11;
dma-names = tx, rx;
+ clocks = clock 307;
+ clock-names = iis;
pinctrl-names = default;
pinctrl-0 = i2s1_bus;
};
@@ -481,6 +489,8 @@
dmas = pdma0 12
pdma0 11;
dma-names = tx, rx;
+ clocks = clock 308;
+ clock-names = iis;
pinctrl-names = default;
pinctrl-0 = i2s2_bus;
};
--
1.7.4.4
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[PATCH V5 5/5] ARM: dts: Update Samsung I2S documentation
This patch updates the samsung i2s documentation for pinmux and
clock entries.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 40 ++-
1 files changed, 13 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046..6f9d29f 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,10 @@ Required SoC Specific Properties:
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
- dma-names: identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: from common clock binding. Handle to iis clock and RCLK src clk.
+- clock-names: from common clock binding: Should be iis,i2s_opclk0 and
+ i2s_opclk1. iis is the i2s bus clock and i2s_opclk selects the src of
+ RCLK which is a mux inside i2s controller.
Optional SoC Specific Properties:
@@ -20,44 +24,26 @@ Optional SoC Specific Properties:
then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
-
-Required Board Specific Properties:
-
-- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
- interface lines. The format of the gpio specifier depends on the gpio
- controller.
- The syntax of samsung gpio specifier is
- [phandle of the gpio controller node]
-[pin number within the gpio controller]
-[mux function]
-[flags and pull up/down]
-[drive strength]
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - default.
Example:
-- SoC Specific Portion:
-
-i2s@0383 {
+i2s0: i2s@0383 {
compatible = samsung,i2s-v5;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = 0x0300;
-};
-
-- Board Specific Portion:
-
-i2s@0383 {
- gpios = gpz 0 2 0 0, /* I2S_0_SCLK */
- gpz 1 2 0 0, /* I2S_0_CDCLK */
- gpz 2 2 0 0, /* I2S_0_LRCK */
- gpz 3 2 0 0, /* I2S_0_SDI */
- gpz 4 2 0 0, /* I2S_0_SDO[1] */
- gpz 5 2 0 0, /* I2S_0_SDO[2] */
- gpz 6 2 0 0; /* I2S_0_SDO[3] */
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
};
--
1.7.4.4
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[PATCH V4 1/4] ARM: samsung: use #include for all device trees
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi |2 +-
arch/arm/boot/dts/exynos4210-origen.dts |2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4210-trats.dts |2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts |2 +-
arch/arm/boot/dts/exynos4210.dtsi |4 ++--
arch/arm/boot/dts/exynos4212.dtsi |2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts|2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +-
arch/arm/boot/dts/exynos4412.dtsi |2 +-
arch/arm/boot/dts/exynos4x12.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts|2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5250-snow.dts |4 ++--
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
arch/arm/boot/dts/exynos5440.dtsi |2 +-
arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +-
arch/arm/boot/dts/s3c2416.dtsi |4 ++--
arch/arm/boot/dts/s3c24xx.dtsi |2 +-
22 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
interrupt-parent = gic;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung smdkv310 evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Trats based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Universal C210 based on Exynos4210 rev0;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..75c2756 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4.dtsi
-/include/ exynos4210-pinctrl.dtsi
+#include exynos4.dtsi
+#include exynos4210-pinctrl.dtsi
/ {
compatible = samsung,exynos4210;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include exynos4x12.dtsi
/ {
compatible = samsung,exynos4212;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..7bb8d48 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Hardkernel ODROID-X board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..df097b5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4412
[PATCH V4 0/4] clk: Samsung: audss: Register audio subsytem clocks using common clk framework
Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem has a internal clock controller which controls i2s0 and pcm0 clocks. This patch series adds the Samsung audio subsytem clock to the common clock framework and provides the I2S controllers clock information in the dtsi file. This patch series is made based on Kukjin Kim for-next branch Changes since V3: - Replaced samsung with exynos in the macro prefixes and function names as this driver supports mainly exynos and s5p family. - Added Reviewed-by:Sylwester Nawrocki s.nawro...@samsung.com Changes since V2: - Removed s5pv210 compatible name from driver as it is not yet supported which is different from Exynos series audio subsystem clock conroller. - Removed clkdev lookup support and added alias names in the i2s0 controller node. Changes since V1: - Reworked on all review comments by Sylwester Nawrocki - Added a header file for all clock indexes as requested by Sylwester - Added different compatible names for s5pv210, exynos4 and exynos5 - Registered the pcm clocks with common clock framework Padmavathi Venna (4): ARM: samsung: use #include for all device trees clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: add Exynos audio subsystem clock controller node ARM: dts: add clock provider information for i2s controllers in Exynos5250 .../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++ arch/arm/boot/dts/exynos4.dtsi |2 +- arch/arm/boot/dts/exynos4210-origen.dts|2 +- arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +- arch/arm/boot/dts/exynos4210-trats.dts |2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts|2 +- arch/arm/boot/dts/exynos4210.dtsi |4 +- arch/arm/boot/dts/exynos4212.dtsi |2 +- arch/arm/boot/dts/exynos4412-odroidx.dts |2 +- arch/arm/boot/dts/exynos4412-origen.dts|2 +- arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +- arch/arm/boot/dts/exynos4412.dtsi |2 +- arch/arm/boot/dts/exynos4x12.dtsi |4 +- arch/arm/boot/dts/exynos5250-arndale.dts |2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- arch/arm/boot/dts/exynos5250-snow.dts |4 +- arch/arm/boot/dts/exynos5250.dtsi | 23 +++- arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +- arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +- arch/arm/boot/dts/exynos5440.dtsi |2 +- arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +- arch/arm/boot/dts/s3c2416.dtsi |4 +- arch/arm/boot/dts/s3c24xx.dtsi |2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos-audss.c | 133 include/dt-bindings/clk/exynos-audss-clk.h | 25 26 files changed, 269 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt create mode 100644 drivers/clk/samsung/clk-exynos-audss.c create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 4/4] ARM: dts: add clock provider information for i2s controllers in Exynos5250
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 388983e..2b917ba 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
#include skeleton.dtsi
#include exynos5250-pinctrl.dtsi
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5250;
interrupt-parent = gic;
@@ -457,6 +459,13 @@
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S,
+ clock_audss EXYNOS_MOUT_AUDSS,
+ clock_audss EXYNOS_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@@ -471,6 +480,8 @@
dmas = pdma1 12
pdma1 11;
dma-names = tx, rx;
+ clocks = clock 307;
+ clock-names = iis;
pinctrl-names = default;
pinctrl-0 = i2s1_bus;
};
@@ -481,6 +492,8 @@
dmas = pdma0 12
pdma0 11;
dma-names = tx, rx;
+ clocks = clock 308;
+ clock-names = iis;
pinctrl-names = default;
pinctrl-0 = i2s2_bus;
};
--
1.7.4.4
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[PATCH V4 2/4] clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos-audss.c | 133
include/dt-bindings/clk/exynos-audss-clk.h | 25
4 files changed, 223 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 000..c401134
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+ - samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
+ - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock ID SoC (if specific)
+---
+
+mout_audss 0
+mout_i2s1
+dout_srp2
+dout_bus3
+dout_i2s4
+srp_clk 5
+i2s_bus 6
+sclk_i2s7
+pcm_bus 8
+sclk_pcm9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@0383 {
+ compatible = samsung,i2s-v5;
+ reg = 0x0383 0x100;
+ dmas = pdma0 10
+ pdma0 9
+ pdma0 8;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S,
+ clock_audss EXYNOS_MOUT_AUDSS,
+ clock_audss EXYNOS_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 000..8a77919
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna padm...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/clk-provider.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { fin_pll
[PATCH V4 3/4] ARM: dts: add Exynos audio subsystem clock controller node
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index bccda67..388983e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ };
+
gic:interrupt-controller@10481000 {
compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
#interrupt-cells = 3;
--
1.7.4.4
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[PATCH V2] ARM: dts: Correct the base address of pinctrl_3 on Exynos5250
This patch corrects the base address of pinctrl_3 on Exynos5250
platform.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Added platform name in the subject line.
arch/arm/boot/dts/exynos5250-pinctrl.dtsi |2 +-
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb..ded558b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -763,7 +763,7 @@
};
};
- pinctrl@0368 {
+ pinctrl@0386 {
gpz: gpz {
gpio-controller;
#gpio-cells = 2;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7154e3d..e9bfd13 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -169,9 +169,9 @@
interrupts = 0 50 0;
};
- pinctrl_3: pinctrl@0368 {
+ pinctrl_3: pinctrl@0386 {
compatible = samsung,exynos5250-pinctrl;
- reg = 0x0368000 0x1000;
+ reg = 0x0386 0x1000;
interrupts = 0 47 0;
};
--
1.7.4.4
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[PATCH V3 0/4] clk: Samsung: audss: Register audio subsytem clocks using common clk framework
Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem has a internal clock controller which controls i2s0 and pcm0 clocks. This patch series adds the Samsung audio subsytem clock to the common clock framework and provides the I2S controllers clock information in the dtsi file. This patch series is made based on Kukjin Kim for-next branch Changes since V2: - Removed s5pv210 compatible name from driver as it is not yet supported which is different from Exynos series audio subsystem clock conroller. - Removed clkdev lookup support and added alias names in the i2s0 controller node. Changes since V1: - Reworked on all review comments by Sylwester Nawrocki - Added a header file for all clock indexes as requested by Sylwester - Added different compatible names for s5pv210, exynos4 and exynos5 - Registered the pcm clocks with common clock framework Padmavathi Venna (4): ARM: samsung: use #include for all device trees clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: add Exynos audio subsystem clock controller node ARM: dts: add clock provider information for i2s controllers in Exynos5250 .../bindings/clock/clk-samsung-audss.txt | 64 ++ arch/arm/boot/dts/exynos4.dtsi |2 +- arch/arm/boot/dts/exynos4210-origen.dts|2 +- arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +- arch/arm/boot/dts/exynos4210-trats.dts |2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts|2 +- arch/arm/boot/dts/exynos4210.dtsi |4 +- arch/arm/boot/dts/exynos4212.dtsi |2 +- arch/arm/boot/dts/exynos4412-odroidx.dts |2 +- arch/arm/boot/dts/exynos4412-origen.dts|2 +- arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +- arch/arm/boot/dts/exynos4412.dtsi |2 +- arch/arm/boot/dts/exynos4x12.dtsi |4 +- arch/arm/boot/dts/exynos5250-arndale.dts |2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- arch/arm/boot/dts/exynos5250-snow.dts |4 +- arch/arm/boot/dts/exynos5250.dtsi | 23 +++- arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +- arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +- arch/arm/boot/dts/exynos5440.dtsi |2 +- arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +- arch/arm/boot/dts/s3c2416.dtsi |4 +- arch/arm/boot/dts/s3c24xx.dtsi |2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-samsung-audss.c| 133 include/dt-bindings/clk/samsung-audss-clk.h| 25 26 files changed, 269 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-samsung-audss.txt create mode 100644 drivers/clk/samsung/clk-samsung-audss.c create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 1/4] ARM: samsung: use #include for all device trees
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi |2 +-
arch/arm/boot/dts/exynos4210-origen.dts |2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4210-trats.dts |2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts |2 +-
arch/arm/boot/dts/exynos4210.dtsi |4 ++--
arch/arm/boot/dts/exynos4212.dtsi |2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts|2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +-
arch/arm/boot/dts/exynos4412.dtsi |2 +-
arch/arm/boot/dts/exynos4x12.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts|2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5250-snow.dts |4 ++--
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
arch/arm/boot/dts/exynos5440.dtsi |2 +-
arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +-
arch/arm/boot/dts/s3c2416.dtsi |4 ++--
arch/arm/boot/dts/s3c24xx.dtsi |2 +-
22 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
interrupt-parent = gic;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung smdkv310 evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Trats based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Universal C210 based on Exynos4210 rev0;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..75c2756 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4.dtsi
-/include/ exynos4210-pinctrl.dtsi
+#include exynos4.dtsi
+#include exynos4210-pinctrl.dtsi
/ {
compatible = samsung,exynos4210;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include exynos4x12.dtsi
/ {
compatible = samsung,exynos4212;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..7bb8d48 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Hardkernel ODROID-X board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..df097b5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
[PATCH V3 3/4] ARM: dts: add Exynos audio subsystem clock controller node
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index bccda67..388983e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ };
+
gic:interrupt-controller@10481000 {
compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
#interrupt-cells = 3;
--
1.7.4.4
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[PATCH V3 4/4] ARM: dts: add clock provider information for i2s controllers in Exynos5250
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 388983e..7154e3d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
#include skeleton.dtsi
#include exynos5250-pinctrl.dtsi
+#include dt-bindings/clk/samsung-audss-clk.h
+
/ {
compatible = samsung,exynos5250;
interrupt-parent = gic;
@@ -457,6 +459,13 @@
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss SAMSUNG_I2S_BUS,
+ clock_audss SAMSUNG_I2S_BUS,
+ clock_audss SAMSUNG_SCLK_I2S,
+ clock_audss SAMSUNG_MOUT_AUDSS,
+ clock_audss SAMSUNG_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@@ -471,6 +480,8 @@
dmas = pdma1 12
pdma1 11;
dma-names = tx, rx;
+ clocks = clock 307;
+ clock-names = iis;
pinctrl-names = default;
pinctrl-0 = i2s1_bus;
};
@@ -481,6 +492,8 @@
dmas = pdma0 12
pdma0 11;
dma-names = tx, rx;
+ clocks = clock 308;
+ clock-names = iis;
pinctrl-names = default;
pinctrl-0 = i2s2_bus;
};
--
1.7.4.4
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[PATCH V3 2/4] clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../bindings/clock/clk-samsung-audss.txt | 64 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-samsung-audss.c| 133
include/dt-bindings/clk/samsung-audss-clk.h| 25
4 files changed, 223 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
create mode 100644 drivers/clk/samsung/clk-samsung-audss.c
create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h
diff --git a/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
new file mode 100644
index 000..07a7ed4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+ - samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
+ - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock ID SoC (if specific)
+---
+
+mout_audss 0
+mout_i2s1
+dout_srp2
+dout_bus3
+dout_i2s4
+srp_clk 5
+i2s_bus 6
+sclk_i2s7
+pcm_bus 8
+sclk_pcm9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@0383 {
+ compatible = samsung,i2s-v5;
+ reg = 0x0383 0x100;
+ dmas = pdma0 10
+ pdma0 9
+ pdma0 8;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss SAMSUNG_I2S_BUS,
+ clock_audss SAMSUNG_I2S_BUS,
+ clock_audss SAMSUNG_SCLK_I2S,
+ clock_audss SAMSUNG_MOUT_AUDSS,
+ clock_audss SAMSUNG_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..5425fa8 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_PLAT_SAMSUNG) += clk-samsung-audss.o
diff --git a/drivers/clk/samsung/clk-samsung-audss.c
b/drivers/clk/samsung/clk-samsung-audss.c
new file mode 100644
index 000..534cdef
--- /dev/null
+++ b/drivers/clk/samsung/clk-samsung-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna padm...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/clk-provider.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clk/samsung-audss-clk.h
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { fin_pll, fout_epll };
+static const char *mout_i2s_p
[PATCH] ARM: dts: wm8994: Add wm8994 regulator support on smdk5250.
This patch adds the required regulator supplies and properties
for wm8994 codec on smdk5250 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 53 +++-
1 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f2a025e..42fc79e 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -37,6 +37,46 @@
};
};
+ avdd2:fixed-regulator@0 {
+ compatible = regulator-fixed;
+ regulator-name = avdd2-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ cpvdd:fixed-regulator@1 {
+ compatible = regulator-fixed;
+ regulator-name = cpvdd-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ dbvdd:fixed-regulator@2 {
+ compatible = regulator-fixed;
+ regulator-name = dbvdd-supply;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ spkvdd1:fixed-regulator@3 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd1-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+
+ spkvdd2:fixed-regulator@4 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd2-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+
i2c@12C7 {
samsung,i2c-sda-delay = 100;
samsung,i2c-max-bus-freq = 2;
@@ -47,8 +87,17 @@
};
wm8994: wm8994@1a {
-compatible = wlf,wm8994;
-reg = 0x1a;
+ compatible = wlf,wm8994;
+ reg = 0x1a;
+
+ gpio-controller;
+ #gpio-cells = 2;
+
+ AVDD2-supply = avdd2;
+ CPVDD-supply = cpvdd;
+ DBVDD-supply = dbvdd;
+ SPKVDD1-supply = spkvdd1;
+ SPKVDD2-supply = spkvdd2;
};
};
--
1.7.4.4
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[PATCH] ARM: samsung: use #include for all device trees
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This patch is dependent on below patches by Stephen Warren
http://www.spinics.net/lists/linux-kbuild/msg07616.html
arch/arm/boot/dts/exynos4.dtsi|2 +-
arch/arm/boot/dts/exynos4210-origen.dts |2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4210-trats.dts|2 +-
arch/arm/boot/dts/exynos4210.dtsi |4 ++--
arch/arm/boot/dts/exynos4212.dtsi |2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts |2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +-
arch/arm/boot/dts/exynos4412.dtsi |2 +-
arch/arm/boot/dts/exynos4x12.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts |2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5250-snow.dts |4 ++--
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts|2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
arch/arm/boot/dts/exynos5440.dtsi |2 +-
18 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index efd441a..e6f4261 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
interrupt-parent = gic;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 8b0a781..8d7a9e5 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung smdkv310 evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Trats based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 5d925ed..e9f878e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4.dtsi
-/include/ exynos4210-pinctrl.dtsi
+#include exynos4.dtsi
+#include exynos4210-pinctrl.dtsi
/ {
compatible = samsung,exynos4210;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index 36d4299..c7a9193 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include exynos4x12.dtsi
/ {
compatible = samsung,exynos4212;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 15dc0a3..9f7f467 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Hardkernel ODROID-X board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index 65e9c57..cfc6208 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index c52b01f..1e816fa 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Samsung SMDK evaluation board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index 7f42827..fae4f81 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include
