Re: [PATCH v3 07/16] clk: exynos5420: update clocks for PERIC block

2014-04-30 Thread Alim Akhtar 
HI shaik,

On Thu, Apr 24, 2014 at 6:33 PM, Shaik Ameer Basha
shaik.am...@samsung.com wrote:
 This patch includes,
 1] renaming of the HSI2C clocks
 2] renaming of spi clocks according to the datasheet
 3] fixes for child-parent relationships
 4] adding of more clocks related to PERIC block
You are also fixing the gate clock, GATE_BUS_PERIC - GATE_IP_PERIC
Please add them in your commit message.

 Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
 Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
 ---
  arch/arm/boot/dts/exynos5420.dtsi  |   14 +++---
  drivers/clk/samsung/clk-exynos5420.c   |   73 
 
  include/dt-bindings/clock/exynos5420.h |   14 +++---
  3 files changed, 50 insertions(+), 51 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
 b/arch/arm/boot/dts/exynos5420.dtsi
 index c3a9a66..67ba2c5 100644
 --- a/arch/arm/boot/dts/exynos5420.dtsi
 +++ b/arch/arm/boot/dts/exynos5420.dtsi
 @@ -549,7 +549,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c4_hs_bus;
 -   clocks = clock CLK_I2C4;
 +   clocks = clock CLK_USI0;
 clock-names = hsi2c;
 status = disabled;
 };
 @@ -562,7 +562,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c5_hs_bus;
 -   clocks = clock CLK_I2C5;
 +   clocks = clock CLK_USI1;
 clock-names = hsi2c;
 status = disabled;
 };
 @@ -575,7 +575,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c6_hs_bus;
 -   clocks = clock CLK_I2C6;
 +   clocks = clock CLK_USI2;
 clock-names = hsi2c;
 status = disabled;
 };
 @@ -588,7 +588,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c7_hs_bus;
 -   clocks = clock CLK_I2C7;
 +   clocks = clock CLK_USI3;
 clock-names = hsi2c;
 status = disabled;
 };
 @@ -601,7 +601,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c8_hs_bus;
 -   clocks = clock CLK_I2C8;
 +   clocks = clock CLK_USI4;
 clock-names = hsi2c;
 status = disabled;
 };
 @@ -614,7 +614,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c9_hs_bus;
 -   clocks = clock CLK_I2C9;
 +   clocks = clock CLK_USI5;
 clock-names = hsi2c;
 status = disabled;
 };
 @@ -627,7 +627,7 @@
 #size-cells = 0;
 pinctrl-names = default;
 pinctrl-0 = i2c10_hs_bus;
 -   clocks = clock CLK_I2C10;
 +   clocks = clock CLK_USI6;
 clock-names = hsi2c;
 status = disabled;
 };
 diff --git a/drivers/clk/samsung/clk-exynos5420.c 
 b/drivers/clk/samsung/clk-exynos5420.c
 index cd75661..b4cf4c1 100755
 --- a/drivers/clk/samsung/clk-exynos5420.c
 +++ b/drivers/clk/samsung/clk-exynos5420.c
 @@ -95,6 +95,7 @@
  #define GATE_IP_DISP1  0x10928
  #define GATE_IP_G3D0x10930
  #define GATE_IP_GEN0x10934
 +#define GATE_IP_PERIC  0x10950
  #define GATE_IP_MSCL   0x10970
  #define GATE_TOP_SCLK_GSCL 0x10820
  #define GATE_TOP_SCLK_DISP10x10828
 @@ -183,6 +184,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
 GATE_IP_DISP1,
 GATE_IP_G3D,
 GATE_IP_GEN,
 +   GATE_IP_PERIC,
 GATE_IP_MSCL,
 GATE_TOP_SCLK_GSCL,
 GATE_TOP_SCLK_DISP1,
 @@ -588,9 +590,9 @@ static struct samsung_div_clock exynos5420_div_clks[] 
 __initdata = {
 DIV(0, dout_audio2, mout_audio2, DIV_PERIC3, 28, 4),

 /* SPI Pre-Ratio */
 -   DIV(0, dout_pre_spi0, dout_spi0, DIV_PERIC4, 8, 8),
 -   DIV(0, dout_pre_spi1, dout_spi1, DIV_PERIC4, 16, 8),
 -   DIV(0, dout_pre_spi2, dout_spi2, DIV_PERIC4, 24, 8),
 +   DIV(0, dout_spi0_pre, dout_spi0, DIV_PERIC4, 8, 8),
 +   DIV(0, dout_spi1_pre, dout_spi1, DIV_PERIC4, 16, 8),
 +   DIV(0, dout_spi2_pre, dout_spi2, DIV_PERIC4, 24, 8),

 /* GSCL Block */
 DIV(0, dout_gscl_blk_300, mout_user_aclk300_gscl,
 @@ -641,8 +643,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] 
 __initdata = {
 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
 GATE(0, aclk66_psgen, mout_aclk66_psgen,
 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
 -   GATE(0, aclk66_peric, mout_aclk66_peric,
 -   GATE_BUS_TOP, 11, 0, 0),
 +   GATE(0, aclk66_peric, mout_user_aclk66_peric,
 +

[PATCH v3 07/16] clk: exynos5420: update clocks for PERIC block

2014-04-24 Thread Shaik Ameer Basha 
This patch includes,
1] renaming of the HSI2C clocks
2] renaming of spi clocks according to the datasheet
3] fixes for child-parent relationships
4] adding of more clocks related to PERIC block

Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
 arch/arm/boot/dts/exynos5420.dtsi  |   14 +++---
 drivers/clk/samsung/clk-exynos5420.c   |   73 
 include/dt-bindings/clock/exynos5420.h |   14 +++---
 3 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66..67ba2c5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -549,7 +549,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c4_hs_bus;
-   clocks = clock CLK_I2C4;
+   clocks = clock CLK_USI0;
clock-names = hsi2c;
status = disabled;
};
@@ -562,7 +562,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c5_hs_bus;
-   clocks = clock CLK_I2C5;
+   clocks = clock CLK_USI1;
clock-names = hsi2c;
status = disabled;
};
@@ -575,7 +575,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c6_hs_bus;
-   clocks = clock CLK_I2C6;
+   clocks = clock CLK_USI2;
clock-names = hsi2c;
status = disabled;
};
@@ -588,7 +588,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c7_hs_bus;
-   clocks = clock CLK_I2C7;
+   clocks = clock CLK_USI3;
clock-names = hsi2c;
status = disabled;
};
@@ -601,7 +601,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c8_hs_bus;
-   clocks = clock CLK_I2C8;
+   clocks = clock CLK_USI4;
clock-names = hsi2c;
status = disabled;
};
@@ -614,7 +614,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c9_hs_bus;
-   clocks = clock CLK_I2C9;
+   clocks = clock CLK_USI5;
clock-names = hsi2c;
status = disabled;
};
@@ -627,7 +627,7 @@
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = i2c10_hs_bus;
-   clocks = clock CLK_I2C10;
+   clocks = clock CLK_USI6;
clock-names = hsi2c;
status = disabled;
};
diff --git a/drivers/clk/samsung/clk-exynos5420.c 
b/drivers/clk/samsung/clk-exynos5420.c
index cd75661..b4cf4c1 100755
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -95,6 +95,7 @@
 #define GATE_IP_DISP1  0x10928
 #define GATE_IP_G3D0x10930
 #define GATE_IP_GEN0x10934
+#define GATE_IP_PERIC  0x10950
 #define GATE_IP_MSCL   0x10970
 #define GATE_TOP_SCLK_GSCL 0x10820
 #define GATE_TOP_SCLK_DISP10x10828
@@ -183,6 +184,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
GATE_IP_DISP1,
GATE_IP_G3D,
GATE_IP_GEN,
+   GATE_IP_PERIC,
GATE_IP_MSCL,
GATE_TOP_SCLK_GSCL,
GATE_TOP_SCLK_DISP1,
@@ -588,9 +590,9 @@ static struct samsung_div_clock exynos5420_div_clks[] 
__initdata = {
DIV(0, dout_audio2, mout_audio2, DIV_PERIC3, 28, 4),
 
/* SPI Pre-Ratio */
-   DIV(0, dout_pre_spi0, dout_spi0, DIV_PERIC4, 8, 8),
-   DIV(0, dout_pre_spi1, dout_spi1, DIV_PERIC4, 16, 8),
-   DIV(0, dout_pre_spi2, dout_spi2, DIV_PERIC4, 24, 8),
+   DIV(0, dout_spi0_pre, dout_spi0, DIV_PERIC4, 8, 8),
+   DIV(0, dout_spi1_pre, dout_spi1, DIV_PERIC4, 16, 8),
+   DIV(0, dout_spi2_pre, dout_spi2, DIV_PERIC4, 24, 8),
 
/* GSCL Block */
DIV(0, dout_gscl_blk_300, mout_user_aclk300_gscl,
@@ -641,8 +643,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] 
__initdata = {
GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
GATE(0, aclk66_psgen, mout_aclk66_psgen,
GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
-   GATE(0, aclk66_peric, mout_aclk66_peric,
-   GATE_BUS_TOP, 11, 0, 0),
+   GATE(0, aclk66_peric, mout_user_aclk66_peric,
+   GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
GATE(0, aclk166, mout_user_aclk166,
GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
GATE(0, aclk333, mout_aclk333,
@@ -657,11 +659,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] 
__initdata = {
GATE_TOP_SCLK_PERIC,