Re: [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

2012-08-13 Thread Catalin Marinas
On Mon, Aug 13, 2012 at 08:21:14AM +0100, shiraz hashim wrote: On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas catalin.mari...@arm.com wrote: On Wed, 2010-11-17 at 06:55 +, Kukjin Kim wrote: --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -168,7 +168,7 @@

[PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

2010-11-16 Thread Kukjin Kim
From: Changhwan Youn chaos.y...@samsung.com This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register). Actually, S5PV310 has same cache controller(PL310). Following is from