Re: [PATCH] ARM: dts: Specify default clocks for Exynos4 camera devices

2014-11-22 Thread Kukjin Kim 
On 11/21/14 01:14, Sylwester Nawrocki wrote:
 Specify the default mux and divider clocks in device tree
 to ensure the FIMC devices on Trats, Trats2, Universal_c210
 and Odroid X2/U3 boards are clocked from recommended clock
 source and with maximum supported frequency.
 For Trats2 also the MIPI-CSIS and the camera sensor clocks
 are configured, the 'clock-frequency' property is deprecated
 in favour of 'assigned-clock-rates' property.
 
 Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
 ---
  arch/arm/boot/dts/exynos4210-trats.dts  |   16 
  arch/arm/boot/dts/exynos4210-universal_c210.dts |   16 
  arch/arm/boot/dts/exynos4412-odroid-common.dtsi |   16 
  arch/arm/boot/dts/exynos4412-trats2.dts |   32 
 ---
  4 files changed, 77 insertions(+), 3 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos4210-trats.dts 
 b/arch/arm/boot/dts/exynos4210-trats.dts
 index f516da9..7208362 100644
 --- a/arch/arm/boot/dts/exynos4210-trats.dts
 +++ b/arch/arm/boot/dts/exynos4210-trats.dts
 @@ -431,18 +431,34 @@
  
   fimc_0: fimc@1180 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC0,
 + clock CLK_SCLK_FIMC0;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
  
   fimc_1: fimc@1181 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC1,
 + clock CLK_SCLK_FIMC1;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
  
   fimc_2: fimc@1182 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC2,
 + clock CLK_SCLK_FIMC2;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
  
   fimc_3: fimc@1183 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC3,
 + clock CLK_SCLK_FIMC3;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
   };
  };
 diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts 
 b/arch/arm/boot/dts/exynos4210-universal_c210.dts
 index d50eb3a..aaf0cae 100644
 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
 +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
 @@ -473,18 +473,34 @@
  
   fimc_0: fimc@1180 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC0,
 + clock CLK_SCLK_FIMC0;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
  
   fimc_1: fimc@1181 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC1,
 + clock CLK_SCLK_FIMC1;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
  
   fimc_2: fimc@1182 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC2,
 + clock CLK_SCLK_FIMC2;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
  
   fimc_3: fimc@1183 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC3,
 + clock CLK_SCLK_FIMC3;
 + assigned-clock-parents = clock CLK_SCLK_MPLL;
 + assigned-clock-rates = 0, 16000;
   };
   };
  };
 diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
 b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 index c697ff0..adf1331 100644
 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
 @@ -82,18 +82,34 @@
  
   fimc_0: fimc@1180 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC0,
 + clock CLK_SCLK_FIMC0;
 + assigned-clock-parents = clock CLK_MOUT_MPLL_USER_T;
 + assigned-clock-rates = 0, 17600;
   };
  
   fimc_1: fimc@1181 {
   status = okay;
 + assigned-clocks = clock CLK_MOUT_FIMC1,
 +

[PATCH] ARM: dts: Specify default clocks for Exynos4 camera devices

2014-11-20 Thread Sylwester Nawrocki 
Specify the default mux and divider clocks in device tree
to ensure the FIMC devices on Trats, Trats2, Universal_c210
and Odroid X2/U3 boards are clocked from recommended clock
source and with maximum supported frequency.
For Trats2 also the MIPI-CSIS and the camera sensor clocks
are configured, the 'clock-frequency' property is deprecated
in favour of 'assigned-clock-rates' property.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 arch/arm/boot/dts/exynos4210-trats.dts  |   16 
 arch/arm/boot/dts/exynos4210-universal_c210.dts |   16 
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi |   16 
 arch/arm/boot/dts/exynos4412-trats2.dts |   32 ---
 4 files changed, 77 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210-trats.dts 
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..7208362 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -431,18 +431,34 @@
 
fimc_0: fimc@1180 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC0,
+   clock CLK_SCLK_FIMC0;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
 
fimc_1: fimc@1181 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC1,
+   clock CLK_SCLK_FIMC1;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
 
fimc_2: fimc@1182 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC2,
+   clock CLK_SCLK_FIMC2;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
 
fimc_3: fimc@1183 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC3,
+   clock CLK_SCLK_FIMC3;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
};
 };
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts 
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..aaf0cae 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -473,18 +473,34 @@
 
fimc_0: fimc@1180 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC0,
+   clock CLK_SCLK_FIMC0;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
 
fimc_1: fimc@1181 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC1,
+   clock CLK_SCLK_FIMC1;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
 
fimc_2: fimc@1182 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC2,
+   clock CLK_SCLK_FIMC2;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
 
fimc_3: fimc@1183 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC3,
+   clock CLK_SCLK_FIMC3;
+   assigned-clock-parents = clock CLK_SCLK_MPLL;
+   assigned-clock-rates = 0, 16000;
};
};
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index c697ff0..adf1331 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -82,18 +82,34 @@
 
fimc_0: fimc@1180 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC0,
+   clock CLK_SCLK_FIMC0;
+   assigned-clock-parents = clock CLK_MOUT_MPLL_USER_T;
+   assigned-clock-rates = 0, 17600;
};
 
fimc_1: fimc@1181 {
status = okay;
+   assigned-clocks = clock CLK_MOUT_FIMC1,
+