Add intial PMU settings for exynos7. This is required for
future suspend-to-ram and cpuidle support.
Signed-off-by: Eunseok Choi es10.c...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
This patch has been tested on an Exynos7 espresso board and is based
on Kgene's tree (for-next branch).
Following are the dependencies:
1) Support 64bit Cortex A57 based Exynos7 SoC
http://www.spinics.net/lists/arm-kernel/msg357380.html
2) mfd: syscon: Decouple syscon interface from syscon devices
http://www.spinics.net/lists/linux-samsung-soc/msg35906.html
3) ARM: EXYNOS: Add platform driver support for Exynos PMU
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275675.html
4) ARM: EXYNOS: Move PMU specific definitions from common.h
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/270655.html
5) ARM: EXYNOS: Move pmu specific header files under linux/mfd/samsung
https://lkml.org/lkml/2014/4/28/217
6) drivers: mfd: Add support for Exynos PMU driver
https://lkml.org/lkml/2014/4/28/332
NOTE: The above dependencies are not final yet, especially the
movement of exynos pmu driver to the mfd directory. I will re-work
this patch when the final location for exynos PMU driver is decided.
.../devicetree/bindings/arm/samsung/pmu.txt|1 +
arch/arm64/boot/dts/exynos7.dtsi |5 +
drivers/mfd/exynos-pmu.c | 285
include/linux/mfd/samsung/exynos-regs-pmu.h| 212 +++
4 files changed, 503 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- samsung,exynos5260-pmu - for Exynos5260 SoC.
- samsung,exynos5410-pmu - for Exynos5410 SoC,
- samsung,exynos5420-pmu - for Exynos5420 SoC.
+ - samsung,exynos7-pmu - for Exynos7 SoC.
second value must be always syscon.
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos7.dtsi b/arch/arm64/boot/dts/exynos7.dtsi
index 6b9eaf4..e2f9f85 100644
--- a/arch/arm64/boot/dts/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos7.dtsi
@@ -361,6 +361,11 @@
status = disabled;
};
+ pmu: pmu-controller@105c {
+ compatible = samsung,exynos7-pmu;
+ reg = 0x105c 0x5000;
+ };
+
rtc@1059 {
compatible = samsung,s3c6410-rtc;
reg = 0x1059 0x100;
diff --git a/drivers/mfd/exynos-pmu.c b/drivers/mfd/exynos-pmu.c
index bfdadbf..9af3b53 100644
--- a/drivers/mfd/exynos-pmu.c
+++ b/drivers/mfd/exynos-pmu.c
@@ -11,6 +11,7 @@
#include linux/io.h
#include linux/of.h
+#include linux/of_address.h
#include linux/platform_device.h
#include linux/regmap.h
#include linux/mfd/syscon.h
@@ -348,6 +349,185 @@ static const struct exynos_pmu_conf
exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
+static const struct exynos_pmu_conf exynos7_pmu_config[] = {
+ /* { .addr = address, .val = { AFTR, LPA, SLEEP } } */
+ { EXYNOS7_ATLAS_CPU0_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU0_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_ATLAS_CPU1_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU1_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_ATLAS_CPU2_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU2_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_ATLAS_CPU3_SYS_PWR_REG, { 0x0, 0x0, 0x8
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_DIS_IRQ_ATLAS_CPU3_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_ATLAS_NONCPU_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_ATLAS_DBG_SYS_PWR_REG,{ 0x0, 0x0, 0x0
} },
+ { EXYNOS7_ATLAS_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0
} },
+ { EXYNOS7_CLKSTOP_CMU_TOP_SYS_PWR_REG,
