Re: [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
nit: %s/fo/of
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590 +
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
[snip]
static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata
= {
MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
};
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p) = { mout_mfc_pll, dout_mfc_pll, };
+PNAME(mout_bus_pll_div2_p) = { mout_bus_pll, dout_bus_pll, };
+PNAME(mout_mem1_pll_div2_p)= { mout_mem1_pll, dout_mem1_pll, };
+PNAME(mout_mem0_pll_div2_p)= { mout_mem0_pll, dout_mem0_pll, };
+PNAME(mout_mfc_pll_p) = { fin_pll, fout_mfc_pll, };
+PNAME(mout_bus_pll_p) = { fin_pll, fout_bus_pll, };
+PNAME(mout_mem1_pll_p) = { fin_pll, fout_mem1_pll, };
+PNAME(mout_mem0_pll_p) = { fin_pll, fout_mem0_pll, };
+
+PNAME(mout_clk2x_phy_c_p) = { mout_mem0_pll_div2, mout_clkm_phy_b, };
+PNAME(mout_clk2x_phy_b_p) = { mout_bus_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clk2x_phy_a_p) = { mout_bus_pll_div2, mout_mfc_pll_div2, };
+PNAME(mout_clkm_phy_c_p) = { mout_mem0_pll_div2, mout_clkm_phy_b, };
As mout_clk2x_phy_c_p and mout_clkm_phy_c_p both has same parent list
one of them can be dropped.
+PNAME(mout_clkm_phy_b_p) = { mout_mem1_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clkm_phy_a_p) = { mout_bus_pll_div2, mout_mfc_pll_div2, };
As mout_clk2x_phy_a_p and mout_clkm_phy_a_p both has same parent list
one of them can be dropped.
+
+PNAME(mout_aclk_mifnm_200_p) = { mout_mem0_pll_div2, div_mif_pre, };
+PNAME(mout_aclk_mifnm_400_p) = { mout_mem1_pll_div2, mout_bus_pll_div2,};
+
+PNAME(mout_aclk_disp_333_b_p) = { mout_aclk_disp_333_a,
+ mout_bus_pll_div2, };
+PNAME(mout_aclk_disp_333_a_p) = { mout_mfc_pll_div2, sclk_mphy_pll, };
+
+PNAME(mout_sclk_decon_vclk_c_p)= { mout_sclk_decon_vclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_vclk_b_p)= { mout_sclk_decon_vclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_vclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_decon_eclk_c_p)= { mout_sclk_decon_eclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_eclk_b_p)= { mout_sclk_decon_eclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_eclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { mout_sclk_decon_tv_eclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { mout_sclk_decon_tv_eclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_eclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_c_p) = { mout_sclk_dsd_b, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_b_p) = { mout_sclk_dsd_a, sclk_mphy_pll, };
+PNAME(mout_sclk_dsd_a_p) = { fin_pll, mout_mfc_pll_div2, };
+
+PNAME(mout_sclk_dsim0_c_p) = { mout_sclk_dsim0_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim0_b_p) = { mout_sclk_dsim0_a, mout_mfc_pll_div2 };
+PNAME(mout_sclk_dsim0_a_p) = { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { mout_sclk_decon_tv_vclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { mout_sclk_decon_tv_vclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_vclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsim1_c_p) = { mout_sclk_dsim1_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim1_b_p) = { mout_sclk_dsim1_a, mout_mfc_pll_div2,};
+PNAME(mout_sclk_dsim1_a_p) = { fin_pll, mout_bus_pll_div2, };
+
Same way I can see {fin_pll, mout_bus_pll_div2, } this combination
of parents is repeated six times above in different PNAME, which can be
replaced by one PNAME list with some common name, thus saving of 5 lines.
+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
+ /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+ FFACTOR(CLK_DOUT_MFC_PLL, dout_mfc_pll, mout_mfc_pll, 1, 1, 0),
+ FFACTOR(CLK_DOUT_BUS_PLL, dout_bus_pll, mout_bus_pll,
Re: [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
Hi Pankaj,
On 12/08/2014 08:37 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
nit: %s/fo/of
I'll fix it.
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent
Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590
+
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
[snip]
static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[]
__initdata = {
MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
};
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p)= { mout_mfc_pll, dout_mfc_pll, };
+PNAME(mout_bus_pll_div2_p)= { mout_bus_pll, dout_bus_pll, };
+PNAME(mout_mem1_pll_div2_p)= { mout_mem1_pll, dout_mem1_pll, };
+PNAME(mout_mem0_pll_div2_p)= { mout_mem0_pll, dout_mem0_pll, };
+PNAME(mout_mfc_pll_p)= { fin_pll, fout_mfc_pll, };
+PNAME(mout_bus_pll_p)= { fin_pll, fout_bus_pll, };
+PNAME(mout_mem1_pll_p)= { fin_pll, fout_mem1_pll, };
+PNAME(mout_mem0_pll_p)= { fin_pll, fout_mem0_pll, };
+
+PNAME(mout_clk2x_phy_c_p)= { mout_mem0_pll_div2, mout_clkm_phy_b, };
+PNAME(mout_clk2x_phy_b_p)= { mout_bus_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clk2x_phy_a_p)= { mout_bus_pll_div2, mout_mfc_pll_div2,
};
+PNAME(mout_clkm_phy_c_p)= { mout_mem0_pll_div2, mout_clkm_phy_b, };
As mout_clk2x_phy_c_p and mout_clkm_phy_c_p both has same parent list one of
them can be dropped.
OK, I'll use common parent to remove duplicat code.
+PNAME(mout_clkm_phy_b_p)= { mout_mem1_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clkm_phy_a_p)= { mout_bus_pll_div2, mout_mfc_pll_div2, };
As mout_clk2x_phy_a_p and mout_clkm_phy_a_p both has same parent list one of
them can be dropped.
OK.
+
+PNAME(mout_aclk_mifnm_200_p)= { mout_mem0_pll_div2, div_mif_pre, };
+PNAME(mout_aclk_mifnm_400_p)= { mout_mem1_pll_div2,
mout_bus_pll_div2,};
+
+PNAME(mout_aclk_disp_333_b_p)= { mout_aclk_disp_333_a,
+mout_bus_pll_div2, };
+PNAME(mout_aclk_disp_333_a_p)= { mout_mfc_pll_div2, sclk_mphy_pll,
};
+
+PNAME(mout_sclk_decon_vclk_c_p)= { mout_sclk_decon_vclk_b,
+sclk_mphy_pll, };
+PNAME(mout_sclk_decon_vclk_b_p)= { mout_sclk_decon_vclk_a,
+mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_vclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_decon_eclk_c_p)= { mout_sclk_decon_eclk_b,
+sclk_mphy_pll, };
+PNAME(mout_sclk_decon_eclk_b_p)= { mout_sclk_decon_eclk_a,
+mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_eclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { mout_sclk_decon_tv_eclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { mout_sclk_decon_tv_eclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_eclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_c_p)= { mout_sclk_dsd_b, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_b_p)= { mout_sclk_dsd_a, sclk_mphy_pll, };
+PNAME(mout_sclk_dsd_a_p)= { fin_pll, mout_mfc_pll_div2, };
+
+PNAME(mout_sclk_dsim0_c_p)= { mout_sclk_dsim0_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim0_b_p)= { mout_sclk_dsim0_a, mout_mfc_pll_div2
};
+PNAME(mout_sclk_dsim0_a_p)= { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { mout_sclk_decon_tv_vclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { mout_sclk_decon_tv_vclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_vclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsim1_c_p)= { mout_sclk_dsim1_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim1_b_p)= { mout_sclk_dsim1_a,
mout_mfc_pll_div2,};
+PNAME(mout_sclk_dsim1_a_p)= { fin_pll, mout_bus_pll_div2, };
+
Same way I can see {fin_pll, mout_bus_pll_div2, } this combination of
parents is repeated six times above in different PNAME, which can be replaced
by one PNAME list with some common name, thus saving of 5 lines.
OK.
+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata
= {
+/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+FFACTOR(CLK_DOUT_MFC_PLL, dout_mfc_pll, mout_mfc_pll, 1, 1, 0),
+
[PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590 +
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 4dec9fc..10197a1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -737,6 +737,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif,
samsung,exynos5433-cmu-cpif,
#define MFC_PLL_CON0 0x0130
#define MFC_PLL_CON1 0x0134
#define MFC_PLL_FREQ_DET 0x013c
+#define MUX_SEL_MIF0 0x0200
+#define MUX_SEL_MIF1 0x0204
+#define MUX_SEL_MIF2 0x0208
+#define MUX_SEL_MIF3 0x020c
+#define MUX_SEL_MIF4 0x0210
+#define MUX_SEL_MIF5 0x0214
+#define MUX_SEL_MIF6 0x0218
+#define MUX_SEL_MIF7 0x021c
+#define MUX_ENABLE_MIF00x0300
+#define MUX_ENABLE_MIF10x0304
+#define MUX_ENABLE_MIF20x0308
+#define MUX_ENABLE_MIF30x030c
+#define MUX_ENABLE_MIF40x0310
+#define MUX_ENABLE_MIF50x0314
+#define MUX_ENABLE_MIF60x0318
+#define MUX_ENABLE_MIF70x031c
+#define MUX_STAT_MIF0 0x0400
+#define MUX_STAT_MIF1 0x0404
+#define MUX_STAT_MIF2 0x0408
+#define MUX_STAT_MIF3 0x040c
+#define MUX_STAT_MIF4 0x0410
+#define MUX_STAT_MIF5 0x0414
+#define MUX_STAT_MIF6 0x0418
+#define MUX_STAT_MIF7 0x041c
+#define DIV_MIF1 0x0604
+#define DIV_MIF2 0x0608
+#define DIV_MIF3 0x060c
+#define DIV_MIF4 0x0610
+#define DIV_MIF5 0x0614
+#define DIV_MIF_PLL_FREQ_DET 0x0618
+#define DIV_STAT_MIF1 0x0704
+#define DIV_STAT_MIF2 0x0708
+#define DIV_STAT_MIF3 0x070c
+#define DIV_STAT_MIF4 0x0710
+#define DIV_STAT_MIF5 0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
+#define ENABLE_ACLK_MIF0 0x0800
+#define ENABLE_ACLK_MIF1 0x0804
+#define ENABLE_ACLK_MIF2 0x0808
+#define ENABLE_ACLK_MIF3 0x080c
+#define ENABLE_PCLK_MIF0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
+#define ENABLE_SCLK_MIF0x0a00
+#define ENABLE_IP_MIF0 0x0b00
+#define ENABLE_IP_MIF1 0x0b04
+#define ENABLE_IP_MIF2 0x0b08
+#define ENABLE_IP_MIF3 0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
+#define CLKOUT_CMU_MIF 0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT0x0c04
+#define DREX_FREQ_CTRL00x1000
+#define DREX_FREQ_CTRL10x1004
+#define PAUSE 0x1008
+#define DDRPHY_LOCK_CTRL 0x100c
static unsigned long mif_clk_regs[] __initdata = {
MEM0_PLL_LOCK,
@@ -755,6 +815,66 @@ static unsigned long mif_clk_regs[] __initdata = {
MFC_PLL_CON0,
MFC_PLL_CON1,
MFC_PLL_FREQ_DET,
+ MUX_SEL_MIF0,
+ MUX_SEL_MIF1,
+ MUX_SEL_MIF2,
+ MUX_SEL_MIF3,
+ MUX_SEL_MIF4,
+ MUX_SEL_MIF5,
+ MUX_SEL_MIF6,
+ MUX_SEL_MIF7,
+ MUX_ENABLE_MIF0,
+ MUX_ENABLE_MIF1,
+ MUX_ENABLE_MIF2,
+ MUX_ENABLE_MIF3,
+ MUX_ENABLE_MIF4,
+ MUX_ENABLE_MIF5,
+ MUX_ENABLE_MIF6,
+ MUX_ENABLE_MIF7,
+ MUX_STAT_MIF0,
+ MUX_STAT_MIF1,
+ MUX_STAT_MIF2,
+ MUX_STAT_MIF3,
+ MUX_STAT_MIF4,
+ MUX_STAT_MIF5,
+ MUX_STAT_MIF6,
+ MUX_STAT_MIF7,
+ DIV_MIF1,
+ DIV_MIF2,
+ DIV_MIF3,
+ DIV_MIF4,
+ DIV_MIF5,
+ DIV_MIF_PLL_FREQ_DET,
+ DIV_STAT_MIF1,
+ DIV_STAT_MIF2,
+ DIV_STAT_MIF3,
