Re: [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 -
include/dt-bindings/clock/exynos5433.h | 114 -
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
+which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_disp: clock-controller@0x13b9 {
+ compatible = samsung,exynos5433-cmu-disp;
+ reg = 0x13b9 0x0c04;
+ #clock-cells = 1;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 10197a1..ec23e97 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1,
fin_pll,
PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
mout_aud_pll_user_t,};
+PNAME(mout_sclk_hdmi_spdif_p) = { sclk_audio1, ioclk_spdif_extclk, };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata =
{
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
@@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, mout_sclk_audio0, mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, mout_sclk_hdmi_spdif,
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, aclk_bus2_400, div_aclk_bus2_400,
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, aclk_disp_333, div_aclk_disp_333,
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, aclk_cpif_200, div_aclk_cpif_200,
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, sclk_dsim1_disp, div_sclk_dsim1,
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, sclk_decon_tv_vclk_disp,
- div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF, 14, 0, 0),
+ div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, sclk_dsim0_disp, div_sclk_dsim0,
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, sclk_dsd_disp, div_sclk_dsd,
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, sclk_decon_tv_eclk_disp,
-
[PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 -
include/dt-bindings/clock/exynos5433.h | 114 -
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
+which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_disp: clock-controller@0x13b9 {
+ compatible = samsung,exynos5433-cmu-disp;
+ reg = 0x13b9 0x0c04;
+ #clock-cells = 1;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 10197a1..ec23e97 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1,
fin_pll,
PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
mout_aud_pll_user_t,};
+PNAME(mout_sclk_hdmi_spdif_p) = { sclk_audio1, ioclk_spdif_extclk, };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
@@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, mout_sclk_audio0, mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, mout_sclk_hdmi_spdif,
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, aclk_bus2_400, div_aclk_bus2_400,
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, aclk_disp_333, div_aclk_disp_333,
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, aclk_cpif_200, div_aclk_cpif_200,
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, sclk_dsim1_disp, div_sclk_dsim1,
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, sclk_decon_tv_vclk_disp,
- div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF, 14, 0, 0),
+ div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, sclk_dsim0_disp, div_sclk_dsim0,
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, sclk_dsd_disp, div_sclk_dsd,
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, sclk_decon_tv_eclk_disp,
- div_sclk_decon_tv_eclk, ENABLE_SCLK_MIF, 7, 0, 0),
+
