Re: [PATCH 1/3] ARM: EXYNOS: Add support for clock handling in power domain

2014-05-23 Thread Tomasz Figa 
Hi,

On 23.05.2014 07:08, Arun Kumar K wrote:
 From: Prathyush K prathyus...@samsung.com
 
 While powering on/off a local powerdomain in exynos5 chipsets, the input
 clocks to each device gets modified. This behaviour is based on the
 SYSCLK_SYS_PWR_REG registers.
 E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
  (aclk333) gets modified to oscclk
   = 0x1, no change in clocks.
 The recommended value of SYSCLK_SYS_PWR_REG before power gating any
 domain is 0x0. So we must also restore the clocks while powering on a
 domain everytime.
 
 This patch adds the framework for getting the required mux and parent clocks
 through a power domain device node. With this patch, while powering off
 a domain, parent is set to oscclk and while powering back on, its re-set
 to the correct parent which is as per the recommended pd on/off
 sequence.
 
 Signed-off-by: Prathyush K prathyus...@samsung.com
 Signed-off-by: Andrew Bresticker abres...@chromium.org
 Signed-off-by: Arun Kumar K arun...@samsung.com
 ---
  .../bindings/arm/exynos/power_domain.txt   |   18 +++
  arch/arm/mach-exynos/pm_domains.c  |   56 
 +++-
  2 files changed, 73 insertions(+), 1 deletion(-)
 
 diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
 b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 index 5216b41..168a191 100644
 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 @@ -9,6 +9,16 @@ Required Properties:
  - reg: physical base address of the controller and length of memory mapped
  region.
  
 +Optional Properties:
 +- clocks: List of clock handles. The parent clocks of the input clocks to the
 +  devices in this power domain are set to oscclk before power gating and
 +  restored back after powering on a domain. This is required for all domains
 +  which are powered on and off and not required for unused domains.

I'd keep it required to all domains that exhibit this behavior, as
device tree should expose complete information about the hardware
whenever possible.

 +  The following clocks can be specified:
 +  - oscclk: oscillator clock.
 +  - clk(n): input clock to the devices in this power domain

s/clk(n)/clkN/

 +  - pclk(n): parent clock of input clock to the devices in this power domain

s/pclk(n)/pclkN/

The meaning of N should be described and the relation between clkN and
pclkN with the same value of N.

Also shouldn't this rather be a description of clock-names property?

 +
  Node of a device using power domains must have a samsung,power-domain 
 property
  defined with a phandle to respective power domain.
  
 @@ -19,6 +29,14 @@ Example:
   reg = 0x10023C00 0x10;
   };
  
 + mfc_pd: power-domain@10044060 {
 + compatible = samsung,exynos4210-pd;
 + reg = 0x10044060 0x20;
 + clocks = clock CLK_FIN_PLL, clock CLK_MOUT_SW_ACLK333,
 + clock CLK_MOUT_USER_ACLK333;
 + clock-names = oscclk, pclk0, clk0;
 + };
 +
  Example of the node using power domain:
  
   node {
 diff --git a/arch/arm/mach-exynos/pm_domains.c 
 b/arch/arm/mach-exynos/pm_domains.c
 index fe6570e..e5fe76d 100644
 --- a/arch/arm/mach-exynos/pm_domains.c
 +++ b/arch/arm/mach-exynos/pm_domains.c
 @@ -17,6 +17,7 @@
  #include linux/err.h
  #include linux/slab.h
  #include linux/pm_domain.h
 +#include linux/clk.h
  #include linux/delay.h
  #include linux/of_address.h
  #include linux/of_platform.h
 @@ -24,6 +25,8 @@
  
  #include regs-pmu.h
  
 +#define MAX_CLK_PER_DOMAIN   4
 +
  /*
   * Exynos specific wrapper around the generic power domain
   */
 @@ -32,6 +35,9 @@ struct exynos_pm_domain {
   char const *name;
   bool is_off;
   struct generic_pm_domain pd;
 + struct clk *oscclk;
 + struct clk *clk[MAX_CLK_PER_DOMAIN];
 + struct clk *pclk[MAX_CLK_PER_DOMAIN];
  };
  
  static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 @@ -44,6 +50,18 @@ static int exynos_pd_power(struct generic_pm_domain 
 *domain, bool power_on)
   pd = container_of(domain, struct exynos_pm_domain, pd);
   base = pd-base;
  
 + /* Set oscclk before powering off a domain*/
 + if (!power_on) {
 + int i;
 + for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
 + if (!pd-clk[i])
 + break;

Clock handles should be checked for validity using IS_ERR() macro (as
most of opaque handles, which should not be considered pointers, even if
they have a pointer type).

 + if (clk_set_parent(pd-clk[i], pd-oscclk))
 + pr_info(%s: error setting oscclk as parent to 
 clock %d\n,
 + pd-name, i);

pr_err()?

 + }
 + }
 +
   pwr =

[PATCH 1/3] ARM: EXYNOS: Add support for clock handling in power domain

2014-05-22 Thread Arun Kumar K 
From: Prathyush K prathyus...@samsung.com

While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
   (aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on a
domain everytime.

This patch adds the framework for getting the required mux and parent clocks
through a power domain device node. With this patch, while powering off
a domain, parent is set to oscclk and while powering back on, its re-set
to the correct parent which is as per the recommended pd on/off
sequence.

Signed-off-by: Prathyush K prathyus...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
 .../bindings/arm/exynos/power_domain.txt   |   18 +++
 arch/arm/mach-exynos/pm_domains.c  |   56 +++-
 2 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b41..168a191 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,16 @@ Required Properties:
 - reg: physical base address of the controller and length of memory mapped
 region.
 
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+  devices in this power domain are set to oscclk before power gating and
+  restored back after powering on a domain. This is required for all domains
+  which are powered on and off and not required for unused domains.
+  The following clocks can be specified:
+  - oscclk: oscillator clock.
+  - clk(n): input clock to the devices in this power domain
+  - pclk(n): parent clock of input clock to the devices in this power domain
+
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
@@ -19,6 +29,14 @@ Example:
reg = 0x10023C00 0x10;
};
 
+   mfc_pd: power-domain@10044060 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044060 0x20;
+   clocks = clock CLK_FIN_PLL, clock CLK_MOUT_SW_ACLK333,
+   clock CLK_MOUT_USER_ACLK333;
+   clock-names = oscclk, pclk0, clk0;
+   };
+
 Example of the node using power domain:
 
node {
diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index fe6570e..e5fe76d 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -17,6 +17,7 @@
 #include linux/err.h
 #include linux/slab.h
 #include linux/pm_domain.h
+#include linux/clk.h
 #include linux/delay.h
 #include linux/of_address.h
 #include linux/of_platform.h
@@ -24,6 +25,8 @@
 
 #include regs-pmu.h
 
+#define MAX_CLK_PER_DOMAIN 4
+
 /*
  * Exynos specific wrapper around the generic power domain
  */
@@ -32,6 +35,9 @@ struct exynos_pm_domain {
char const *name;
bool is_off;
struct generic_pm_domain pd;
+   struct clk *oscclk;
+   struct clk *clk[MAX_CLK_PER_DOMAIN];
+   struct clk *pclk[MAX_CLK_PER_DOMAIN];
 };
 
 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -44,6 +50,18 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
pd = container_of(domain, struct exynos_pm_domain, pd);
base = pd-base;
 
+   /* Set oscclk before powering off a domain*/
+   if (!power_on) {
+   int i;
+   for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
+   if (!pd-clk[i])
+   break;
+   if (clk_set_parent(pd-clk[i], pd-oscclk))
+   pr_info(%s: error setting oscclk as parent to 
clock %d\n,
+   pd-name, i);
+   }
+   }
+
pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
__raw_writel(pwr, base);
 
@@ -60,6 +78,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
cpu_relax();
usleep_range(80, 100);
}
+
+   /* Restore clocks after powering on a domain*/
+   if (power_on) {
+   int i;
+   for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
+   if (!pd-clk[i])
+   break;
+   if (clk_set_parent(pd-clk[i], pd-pclk[i]))
+   pr_info(%s: error setting parent to clock%d\n,
+