[PATCH 1/3] ARM: SAMSUNG: Add support for EXYNOS SS USB 3.0 DRD controller
Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com Adds DRD global register definitions and related platform data. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- .../include/plat/regs-usb3-exynos-drd.h| 305 arch/arm/plat-samsung/include/plat/udc-ss.h| 21 ++ arch/arm/plat-samsung/include/plat/usb-phy.h |1 + 3 files changed, 327 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h create mode 100644 arch/arm/plat-samsung/include/plat/udc-ss.h diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h new file mode 100644 index 000..7006dc4 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h @@ -0,0 +1,305 @@ +/* arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h + * + * Copyright (c) 2011 Samsung Electronics Co. Ltd + * Author: Anton Tikhomirov av.tikhomi...@samsung.com + * + * Exynos SuperSpeed USB 3.0 DRD Controller Global registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H +#define __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H __FILE__ + +#define EXYNOS_USB3_REG(x) (x) + +#define EXYNOS_USB3_GSBUSCFG0 EXYNOS_USB3_REG(0xC100) +#define EXYNOS_USB3_GSBUSCFG0_SBusStoreAndForward (1 12) +#define EXYNOS_USB3_GSBUSCFG0_DatBigEnd(1 11) +#define EXYNOS_USB3_GSBUSCFG0_INCR256BrstEna (1 7) +#define EXYNOS_USB3_GSBUSCFG0_INCR128BrstEna (1 6) +#define EXYNOS_USB3_GSBUSCFG0_INCR64BrstEna(1 5) +#define EXYNOS_USB3_GSBUSCFG0_INCR32BrstEna(1 4) +#define EXYNOS_USB3_GSBUSCFG0_INCR16BrstEna(1 3) +#define EXYNOS_USB3_GSBUSCFG0_INCR8BrstEna (1 2) +#define EXYNOS_USB3_GSBUSCFG0_INCR4BrstEna (1 1) +#define EXYNOS_USB3_GSBUSCFG0_INCRBrstEna (1 0) + +#define EXYNOS_USB3_GSBUSCFG1 EXYNOS_USB3_REG(0xC104) +#define EXYNOS_USB3_GSBUSCFG1_EN1KPAGE (1 12) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_MASK (0xf 8) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_SHIFT 8 +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT(_x)((_x) 8) + + +#define EXYNOS_USB3_GTXTHRCFG EXYNOS_USB3_REG(0xC108) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCntSel (1 29) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_SHIFT24 +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_MASK (0xff 16) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_SHIFT 16 +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize(_x)((_x) 16) + + +#define EXYNOS_USB3_GRXTHRCFG EXYNOS_USB3_REG(0xC10C) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCntSel (1 29) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_SHIFT24 +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_MASK (0x1f 19) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_SHIFT 19 +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize(_x)((_x) 19) + + +#define EXYNOS_USB3_GCTL EXYNOS_USB3_REG(0xC110) +#define EXYNOS_USB3_GCTL_PwrDnScale_MASK (0x1fff 19) +#define EXYNOS_USB3_GCTL_PwrDnScale_SHIFT 19 +#define EXYNOS_USB3_GCTL_PwrDnScale(_x)((_x) 19) +#define EXYNOS_USB3_GCTL_U2RSTECN (1 16) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_MASK(0x3 14) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_SHIFT 14 +#define EXYNOS_USB3_GCTL_FRMSCLDWN(_x) ((_x) 14) +#define EXYNOS_USB3_GCTL_PrtCapDir_MASK(0x3 12) +#define EXYNOS_USB3_GCTL_PrtCapDir_SHIFT 12 +#define EXYNOS_USB3_GCTL_PrtCapDir(_x) ((_x) 12) +#define EXYNOS_USB3_GCTL_CoreSoftReset (1 11) +#define EXYNOS_USB3_GCTL_LocalLpBkEn (1 10) +#define EXYNOS_USB3_GCTL_LpbkEn(1 9) +#define EXYNOS_USB3_GCTL_DebugAttach (1 8) +#define EXYNOS_USB3_GCTL_RAMClkSel_MASK(0x3 6) +#define EXYNOS_USB3_GCTL_RAMClkSel_SHIFT 6 +#define EXYNOS_USB3_GCTL_RAMClkSel(_x) ((_x) 6) +#define EXYNOS_USB3_GCTL_ScaleDown_MASK(0x3 4) +#define EXYNOS_USB3_GCTL_ScaleDown_SHIFT 4 +#define EXYNOS_USB3_GCTL_ScaleDown(_x) ((_x) 4) +#define EXYNOS_USB3_GCTL_DisScramble
Re: [PATCH 1/3] ARM: SAMSUNG: Add support for EXYNOS SS USB 3.0 DRD controller
On Mon, Feb 6, 2012 at 5:11 PM, Anton Tikhomirov av.tikhomi...@samsung.com wrote: Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com Adds DRD global register definitions and related platform data. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com Hi, --- .../include/plat/regs-usb3-exynos-drd.h | 305 If special reason, please move to the proper drivers/usb. Thank you, Kyungmin Park arch/arm/plat-samsung/include/plat/udc-ss.h | 21 ++ arch/arm/plat-samsung/include/plat/usb-phy.h | 1 + 3 files changed, 327 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h create mode 100644 arch/arm/plat-samsung/include/plat/udc-ss.h diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h new file mode 100644 index 000..7006dc4 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h @@ -0,0 +1,305 @@ +/* arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h + * + * Copyright (c) 2011 Samsung Electronics Co. Ltd + * Author: Anton Tikhomirov av.tikhomi...@samsung.com + * + * Exynos SuperSpeed USB 3.0 DRD Controller Global registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H +#define __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H __FILE__ + +#define EXYNOS_USB3_REG(x) (x) + +#define EXYNOS_USB3_GSBUSCFG0 EXYNOS_USB3_REG(0xC100) +#define EXYNOS_USB3_GSBUSCFG0_SBusStoreAndForward (1 12) +#define EXYNOS_USB3_GSBUSCFG0_DatBigEnd (1 11) +#define EXYNOS_USB3_GSBUSCFG0_INCR256BrstEna (1 7) +#define EXYNOS_USB3_GSBUSCFG0_INCR128BrstEna (1 6) +#define EXYNOS_USB3_GSBUSCFG0_INCR64BrstEna (1 5) +#define EXYNOS_USB3_GSBUSCFG0_INCR32BrstEna (1 4) +#define EXYNOS_USB3_GSBUSCFG0_INCR16BrstEna (1 3) +#define EXYNOS_USB3_GSBUSCFG0_INCR8BrstEna (1 2) +#define EXYNOS_USB3_GSBUSCFG0_INCR4BrstEna (1 1) +#define EXYNOS_USB3_GSBUSCFG0_INCRBrstEna (1 0) + +#define EXYNOS_USB3_GSBUSCFG1 EXYNOS_USB3_REG(0xC104) +#define EXYNOS_USB3_GSBUSCFG1_EN1KPAGE (1 12) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_MASK (0xf 8) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_SHIFT 8 +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT(_x) ((_x) 8) + + +#define EXYNOS_USB3_GTXTHRCFG EXYNOS_USB3_REG(0xC108) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCntSel (1 29) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_SHIFT 24 +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_MASK (0xff 16) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_SHIFT 16 +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize(_x) ((_x) 16) + + +#define EXYNOS_USB3_GRXTHRCFG EXYNOS_USB3_REG(0xC10C) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCntSel (1 29) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_SHIFT 24 +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_MASK (0x1f 19) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_SHIFT 19 +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize(_x) ((_x) 19) + + +#define EXYNOS_USB3_GCTL EXYNOS_USB3_REG(0xC110) +#define EXYNOS_USB3_GCTL_PwrDnScale_MASK (0x1fff 19) +#define EXYNOS_USB3_GCTL_PwrDnScale_SHIFT 19 +#define EXYNOS_USB3_GCTL_PwrDnScale(_x) ((_x) 19) +#define EXYNOS_USB3_GCTL_U2RSTECN (1 16) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_MASK (0x3 14) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_SHIFT 14 +#define EXYNOS_USB3_GCTL_FRMSCLDWN(_x) ((_x) 14) +#define EXYNOS_USB3_GCTL_PrtCapDir_MASK (0x3 12) +#define EXYNOS_USB3_GCTL_PrtCapDir_SHIFT 12 +#define EXYNOS_USB3_GCTL_PrtCapDir(_x) ((_x) 12) +#define EXYNOS_USB3_GCTL_CoreSoftReset (1 11) +#define EXYNOS_USB3_GCTL_LocalLpBkEn (1 10) +#define EXYNOS_USB3_GCTL_LpbkEn (1 9) +#define EXYNOS_USB3_GCTL_DebugAttach (1 8) +#define EXYNOS_USB3_GCTL_RAMClkSel_MASK (0x3 6) +#define EXYNOS_USB3_GCTL_RAMClkSel_SHIFT 6 +#define EXYNOS_USB3_GCTL_RAMClkSel(_x)
