Re: [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain

2014-12-08 Thread Pankaj Dubey 

Hi Chanwoo,

On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:

This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.

Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
  drivers/clk/samsung/clk-exynos5433.c   | 286 +
  include/dt-bindings/clock/exynos5433.h |  82 +-
  2 files changed, 365 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c 
b/drivers/clk/samsung/clk-exynos5433.c
index 5b4ec83..e2b7ea6 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata 
= {
DIV(CLK_DIV_SCLK_MMC2_A, div_sclk_mmc2_a, mout_sclk_mmc2_b,
DIV_TOP_FSYS1, 0, 4),

+   /* DIV_TOP_FSYS2 */
+   DIV(CLK_DIV_SCLK_PCIE_100, div_sclk_pcie_100, mout_sclk_pcie_100,
+   DIV_TOP_FSYS2, 12, 3),
+   DIV(CLK_DIV_SCLK_USBHOST30, div_sclk_usbhost30,
+   mout_sclk_usbhost30, DIV_TOP_FSYS2, 8, 4),
+   DIV(CLK_DIV_SCLK_UFSUNIPRO, div_sclk_ufsunipro,
+   mout_sclk_ufsunipro, DIV_TOP_FSYS2, 4, 4),
+   DIV(CLK_DIV_SCLK_USBDRD30, div_sclk_usbdrd30, mout_sclk_usbdrd30,
+   DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, div_sclk_spi1_b, div_sclk_spi1_a,
DIV_TOP_PERIC0, 16, 8),
@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[] 
__initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),

/* ENABLE_SCLK_TOP_FSYS */
+   GATE(CLK_SCLK_PCIE_100_FSYS, sclk_pcie_100_fsys, div_sclk_pcie_100,
+   ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, sclk_mmc1_fsys, div_sclk_mmc1_b,
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, sclk_mmc0_fsys, div_sclk_mmc0_b,
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+   GATE(CLK_SCLK_UFSUNIPRO_FSYS, sclk_ufsunipro_fsys,
+   div_sclk_ufsunipro, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),


bit_index for sclk_ufsunipro_fsys is '3'.


+   GATE(CLK_SCLK_USBHOST30_FSYS, sclk_usbhost30_fsys,
+   div_sclk_usbhost30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),


bit_index for sclk_usbhost30_fsys is '1'.


+   GATE(CLK_SCLK_USBDRD30_FSYS, sclk_usbdrd30_fsys,
+   div_sclk_usbdrd30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),


bit_index for sclk_usbdrd30_fsys is '0'.



/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, sclk_spi4_peric, div_sclk_spi4_b,
@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, 
samsung,exynos5433-cmu-peris,
  #define ENABLE_IP_FSYS1   0x0b04

  /* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p)   = { fin_pll, sclk_ufs_mphy, };
  PNAME(mout_aclk_fsys_200_user_p)  = { fin_pll, aclk_fsys_200, };
+PNAME(mout_sclk_pcie_100_user_p)   = { fin_pll, sclk_ufsunipro_fsys,};


This parent list looks wrong.
As per UM, it should be: { fin_pll, sclk_pcie_100_fsys,};


+PNAME(mout_sclk_ufsunipro_user_p)  = { fin_pll, sclk_ufsunipro_fsys,};
  PNAME(mout_sclk_mmc2_user_p)  = { fin_pll, sclk_mmc2_fsys, };
  PNAME(mout_sclk_mmc1_user_p)  = { fin_pll, sclk_mmc1_fsys, };
  PNAME(mout_sclk_mmc0_user_p)  = { fin_pll, sclk_mmc0_fsys, };
+PNAME(mout_sclk_usbhost30_user_p)  = { fin_pll, sclk_usbhost30_fsys,};
+PNAME(mout_sclk_usbdrd30_user_p)   = { fin_pll, sclk_usbdrd30_fsys, };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+   = { fin_pll, phyclk_usbhost20_phy_hsic1_phy, };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+   = { fin_pll, phyclk_usbhost20_phy_clk48mohci_phy, };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+   = { fin_pll, phyclk_usbhost20_phy_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+   = { fin_pll, phyclk_usbhost20_phy_freeclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };


Here second parent should be 'phyclk_usbdrd30_udrd30_pipe_pclk_phy'.


+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };


Here second

[PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain

2014-12-02 Thread Chanwoo Choi 
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.

Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
 drivers/clk/samsung/clk-exynos5433.c   | 286 +
 include/dt-bindings/clock/exynos5433.h |  82 +-
 2 files changed, 365 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c 
b/drivers/clk/samsung/clk-exynos5433.c
index 5b4ec83..e2b7ea6 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata 
= {
DIV(CLK_DIV_SCLK_MMC2_A, div_sclk_mmc2_a, mout_sclk_mmc2_b,
DIV_TOP_FSYS1, 0, 4),
 
+   /* DIV_TOP_FSYS2 */
+   DIV(CLK_DIV_SCLK_PCIE_100, div_sclk_pcie_100, mout_sclk_pcie_100,
+   DIV_TOP_FSYS2, 12, 3),
+   DIV(CLK_DIV_SCLK_USBHOST30, div_sclk_usbhost30,
+   mout_sclk_usbhost30, DIV_TOP_FSYS2, 8, 4),
+   DIV(CLK_DIV_SCLK_UFSUNIPRO, div_sclk_ufsunipro,
+   mout_sclk_ufsunipro, DIV_TOP_FSYS2, 4, 4),
+   DIV(CLK_DIV_SCLK_USBDRD30, div_sclk_usbdrd30, mout_sclk_usbdrd30,
+   DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, div_sclk_spi1_b, div_sclk_spi1_a,
DIV_TOP_PERIC0, 16, 8),
@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[] 
__initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
 
/* ENABLE_SCLK_TOP_FSYS */
+   GATE(CLK_SCLK_PCIE_100_FSYS, sclk_pcie_100_fsys, div_sclk_pcie_100,
+   ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, sclk_mmc1_fsys, div_sclk_mmc1_b,
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, sclk_mmc0_fsys, div_sclk_mmc0_b,
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+   GATE(CLK_SCLK_UFSUNIPRO_FSYS, sclk_ufsunipro_fsys,
+   div_sclk_ufsunipro, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+   GATE(CLK_SCLK_USBHOST30_FSYS, sclk_usbhost30_fsys,
+   div_sclk_usbhost30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+   GATE(CLK_SCLK_USBDRD30_FSYS, sclk_usbdrd30_fsys,
+   div_sclk_usbdrd30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
 
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, sclk_spi4_peric, div_sclk_spi4_b,
@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, 
samsung,exynos5433-cmu-peris,
 #define ENABLE_IP_FSYS10x0b04
 
 /* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p)   = { fin_pll, sclk_ufs_mphy, };
 PNAME(mout_aclk_fsys_200_user_p)   = { fin_pll, aclk_fsys_200, };
+PNAME(mout_sclk_pcie_100_user_p)   = { fin_pll, sclk_ufsunipro_fsys,};
+PNAME(mout_sclk_ufsunipro_user_p)  = { fin_pll, sclk_ufsunipro_fsys,};
 PNAME(mout_sclk_mmc2_user_p)   = { fin_pll, sclk_mmc2_fsys, };
 PNAME(mout_sclk_mmc1_user_p)   = { fin_pll, sclk_mmc1_fsys, };
 PNAME(mout_sclk_mmc0_user_p)   = { fin_pll, sclk_mmc0_fsys, };
+PNAME(mout_sclk_usbhost30_user_p)  = { fin_pll, sclk_usbhost30_fsys,};
+PNAME(mout_sclk_usbdrd30_user_p)   = { fin_pll, sclk_usbdrd30_fsys, };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+   = { fin_pll, phyclk_usbhost20_phy_hsic1_phy, };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+   = { fin_pll, phyclk_usbhost20_phy_clk48mohci_phy, };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+   = { fin_pll, phyclk_usbhost20_phy_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+   = { fin_pll, phyclk_usbhost20_phy_freeclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+   = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+   = { fin_pll, phyclk_ufs_rx1_symbol_phy, };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+   = { fin_pll, phyclk_ufs_rx0_symbol_phy, };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+   = { fin_pll, phyclk_ufs_tx1_symbol_phy, };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+   = { fin_pll,