Simplify HW_TRIP level setting in exynos_tmu_initialize() (don't
pretend that the current code is hardware and configuration
independent and just do SoC type check explicitly). Then remove
no longer needed reg->threshold_[th2,th3_l0_shift] abstractions
(only assigned for Exynos5440 in exynos5440_tmu_registers) and
EXYNOS_MAX_TRIGGER_PER_REG define.
There should be no functional changes caused by this patch.
Cc: Naveen Krishna Chatradhi <ch.nav...@samsung.com>
Cc: Amit Daniel Kachhap <amit.dan...@samsung.com>
Cc: Lukasz Majewski <l.majew...@samsung.com>
Cc: Eduardo Valentin <edubez...@gmail.com>
Cc: Zhang Rui <rui.zh...@intel.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnier...@samsung.com>
Acked-by: Kyungmin Park <kyungmin.p...@samsung.com>
---
drivers/thermal/samsung/exynos_tmu.c | 10 +++++-----
drivers/thermal/samsung/exynos_tmu.h | 4 ----
drivers/thermal/samsung/exynos_tmu_data.c | 2 --
drivers/thermal/samsung/exynos_tmu_data.h | 2 --
4 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index f009a04..f02e65d 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -237,18 +237,18 @@ static int exynos_tmu_initialize(struct platform_device
*pdev)
(pdata->trigger_type[i] == HW_TRIP)) {
threshold_code = temp_to_code(data,
pdata->trigger_levels[i]);
- if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
+ if (data->soc != SOC_ARCH_EXYNOS5440) {
/* 1-4 level to be assigned in th0 reg */
rising_threshold &= ~(0xff << 8 * i);
rising_threshold |= threshold_code << 8 * i;
writel(rising_threshold,
- data->base + reg->threshold_th0);
- } else if (i == EXYNOS_MAX_TRIGGER_PER_REG) {
+ data->base + EXYNOS_THD_TEMP_RISE);
+ } else {
/* 5th level to be assigned in th2 reg */
rising_threshold =
- threshold_code << reg->threshold_th3_l0_shift;
+ threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
writel(rising_threshold,
- data->base + reg->threshold_th2);
+ data->base + EXYNOS5440_TMU_S0_7_TH2);
}
con = readl(data->base + reg->tmu_ctrl);
con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
diff --git a/drivers/thermal/samsung/exynos_tmu.h
b/drivers/thermal/samsung/exynos_tmu.h
index 7098e37..3430852 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -80,8 +80,6 @@ enum soc_type {
* @tmu_cur_temp: register containing the current temperature of the TMU.
* @threshold_th0: Register containing first set of rising levels.
* @threshold_th1: Register containing second set of rising levels.
- * @threshold_th2: Register containing third set of rising levels.
- * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
* @tmu_inten: register containing the different threshold interrupt
enable bits.
* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
@@ -104,8 +102,6 @@ struct exynos_tmu_registers {
u32 threshold_th0;
u32 threshold_th1;
- u32 threshold_th2;
- u32 threshold_th3_l0_shift;
u32 tmu_inten;
u32 inten_rise0_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c
b/drivers/thermal/samsung/exynos_tmu_data.c
index 23beb70..a63d945 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -408,8 +408,6 @@ static const struct exynos_tmu_registers
exynos5440_tmu_registers = {
.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
- .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
- .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h
b/drivers/thermal/samsung/exynos_tmu_data.h
index 96cf369..3ae42cd 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -80,8 +80,6 @@
#define EXYNOS_EMUL_DATA_MASK 0xFF
#define EXYNOS_EMUL_ENABLE 0x1
-#define EXYNOS_MAX_TRIGGER_PER_REG 4
-
/* Exynos5260 specific */
#define EXYNOS5260_TMU_REG_INTEN 0xC0
#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
--
1.8.2.3
--
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