[PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000..81fe925
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = gpz0-0, gpz0-1, gpz0-2, gpz0-3,
+ gpz0-4, gpz0-5, gpz0-6;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = gpz1-0, gpz1-1, gpz1-2, gpz1-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+};
+
+pinctrl_cpif {
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_ese {
+ gpj2: gpj2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_finger {
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = gpd5-0, gpd5-2, gpd5-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus {
+ samsung,pins = gpd5-3, gpd5-2;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+};
+
+pinctrl_fsys {
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpr4: gpr4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
+
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu0: cpu@100 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x100;
+ };
+
+ cpu1: cpu@101 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x101;
+ };
+
+ cpu2: cpu@102 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x0 0x102;
+ };
+
+ cpu3: cpu@103 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x103;
+ };
+
+ cpu4: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu5: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu6: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu7: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
Where the final cell is a sufficiently large value to cover all
addresses in the soc node.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
[...]
+ pinctrl_alive: pinctrl@1058 {
+ compatible = samsung,exynos5433-pinctrl;
+ reg = 0x1058 0x1000;
+
+ wakeup-interrupt-controller {
+ compatible = samsung,exynos7-wakeup-eint;
+ interrupts = 0 16 0;
+ };
+ };
How exactly does the wakeup interrupt controller interact with the GIC?
Surely the relationship between the two should be described?
Is it a subcomponent of the
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Dear Mark,
On 12/02/2014 08:09 PM, Mark Rutland wrote:
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433
supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
+
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu0: cpu@100 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x100;
+ };
+
+ cpu1: cpu@101 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x101;
+ };
+
+ cpu2: cpu@102 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x0 0x102;
+ };
+
+ cpu3: cpu@103 {
+ device_type = cpu;
+ compatible = arm,cortex-a53, arm,armv8;
+ enable-method = psci;
+ reg = 0x103;
+ };
+
+ cpu4: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu5: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu6: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu7: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
At current version,
CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of
CPU_OFF fail.
(I got CPU_ON of Exynos5433 all cores.)
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
I'll fix it after checking correct spec.
Where the final cell is a sufficiently large value to cover all
addresses in the soc node.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = 0x11001000 0x1000,
0x11002000 0x2000,- I changed the the range of
GICC.
0x11004000 0x2000,
0x11006000 0x2000;
[...]
+
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
At current version,
CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of
CPU_OFF fail.
(I got CPU_ON of Exynos5433 all cores.)
CPU_OFF should not be described in the DT unless it works.
[...]
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
I'll fix it after checking correct spec.
Thanks.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = 0x11001000 0x1000,
0x11002000 0x2000,- I changed the the range of
GICC.
0x11004000 0x2000,
0x11006000 0x2000;
Yes.
[...]
+ pinctrl_alive: pinctrl@1058 {
+ compatible = samsung,exynos5433-pinctrl;
+ reg = 0x1058 0x1000;
+
+ wakeup-interrupt-controller {
+ compatible = samsung,exynos7-wakeup-eint;
+ interrupts = 0 16 0;
+ };
+ };
How exactly does the wakeup interrupt controller interact with the GIC?
Surely the relationship between the two should be described?
The pinctrl_alive contains the alive part of GPIO PAD (gpa0~gpa3).
The each GPA0/GPA1 of pinctrl_alive pad did map to unique SPI number of GIC
amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
gpa0-0 - SPI[0]
gpa0-1 - SPI[1]
gpa0-2 - SPI[2]
gpa0-3 - SPI[3]
gpa0-4 - SPI[4]
gpa0-5 - SPI[5]
gpa0-6 - SPI[6]
gpa0-7 - SPI[7]
gpa1-0 - SPI[8]
gpa1-1 - SPI[9]
gpa1-2 - SPI[10]
gpa1-3 - SPI[11]
gpa1-4 - SPI[12]
gpa1-5 - SPI[13]
gpa1-6 - SPI[14]
gpa1-7 - SPI[15]
GPA2/GPA3 use only one interrupt (SPI[16]).
The pinctrl-exynos.c driver initialized external wakeup interrupt
(e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) in exynos_eint_wkup_init() function.
Following patch[1] adds the control for Exynos5433 wakeup irq.The
exynos5433_pin_ctrl structure
includes '.eint_wkup_init = exynos_eint_wkup_init;' fields to handle wakeup
interrupt of Exynos SoC.
[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = exynos5433-gpio-ctrl0,
+ }, {
And,
'struct exynos_irq_chip
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Dear Mark,
On Tue, Dec 2, 2014 at 9:13 PM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs (including CPU0)?
At current version,
CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of
CPU_OFF fail.
(I got CPU_ON of Exynos5433 all cores.)
CPU_OFF should not be described in the DT unless it works.
OK, I'll drop 'cpu_off property on next patchset. After fixing it,
I'll re-send separate patch.
[...]
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
Is that valid when changing the number of cells? The address spaces
aren't strictly identical in that case, and I'd expect a translation
something like:
ranges = 0x0 0x0 0x0 0xff00;
I'll fix it after checking correct spec.
Thanks.
[...]
+ gic:interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ interrupts = 1 9 0xf04;
+ };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at
0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = 0x11001000 0x1000,
0x11002000 0x2000,- I changed the the range
of GICC.
0x11004000 0x2000,
0x11006000 0x2000;
Yes.
OK. I'll fix it.
[...]
+ pinctrl_alive: pinctrl@1058 {
+ compatible = samsung,exynos5433-pinctrl;
+ reg = 0x1058 0x1000;
+
+ wakeup-interrupt-controller {
+ compatible =
samsung,exynos7-wakeup-eint;
+ interrupts = 0 16 0;
+ };
+ };
How exactly does the wakeup interrupt controller interact with the GIC?
Surely the relationship between the two should be described?
The pinctrl_alive contains the alive part of GPIO PAD (gpa0~gpa3).
The each GPA0/GPA1 of pinctrl_alive pad did map to unique SPI number of GIC
amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ #interrupt-cells = 2;
+ };
gpa0-0 - SPI[0]
gpa0-1 - SPI[1]
gpa0-2 - SPI[2]
gpa0-3 - SPI[3]
gpa0-4 - SPI[4]
gpa0-5 - SPI[5]
gpa0-6 - SPI[6]
gpa0-7 - SPI[7]
gpa1-0 - SPI[8]
gpa1-1 - SPI[9]
gpa1-2 - SPI[10]
gpa1-3 - SPI[11]
gpa1-4 - SPI[12]
gpa1-5 - SPI[13]
gpa1-6 - SPI[14]
gpa1-7 - SPI[15]
GPA2/GPA3 use only one interrupt (SPI[16]).
The pinctrl-exynos.c driver initialized external wakeup interrupt
(e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) in exynos_eint_wkup_init()
function.
Following patch[1] adds the control for Exynos5433 wakeup irq.The
exynos5433_pin_ctrl structure
includes '.eint_wkup_init = exynos_eint_wkup_init;' fields to handle wakeup
interrupt of Exynos SoC.
[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend=
