Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block

2015-01-12 Thread Padma Venkat 
Hi ViVek,

On 1/9/15, Vivek Gautam gautamvivek1...@gmail.com wrote:
 On Fri, Jan 9, 2015 at 5:18 PM, Vivek Gautam gautamvivek1...@gmail.com
 wrote:
 Hi Padma,


 On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com
 wrote:
 Add clock support for 5 SPI channels.

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---

[snip]

 Same here for SCLK_SPI5, unused in the patch.

ok.


 [snip]

 The rest all looks good in this patch. I have also verified from the
 Exynos7 UM.

 missed it earlier. You may also want to add update documentation for
 clock sources
 of peric1 block.

I will add the required source clks.
Thanks for the review.

Padma


 --
 Best Regards
 Vivek Gautam
 Samsung RD Institute, Bangalore
 India
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Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block

2015-01-09 Thread Vivek Gautam 
Hi Padma,


On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com wrote:
 Add clock support for 5 SPI channels.

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  drivers/clk/samsung/clk-exynos7.c   |   73 
 +++
  include/dt-bindings/clock/exynos7-clk.h |   22 -
  2 files changed, 93 insertions(+), 2 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos7.c 
 b/drivers/clk/samsung/clk-exynos7.c
 index 954f9a0..cf5e50e 100644
 --- a/drivers/clk/samsung/clk-exynos7.c
 +++ b/drivers/clk/samsung/clk-exynos7.c
 @@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, 
 samsung,exynos7-clock-topc,
  #define MUX_SEL_TOP00  0x0200
  #define MUX_SEL_TOP01  0x0204
  #define MUX_SEL_TOP03  0x020C
 +#define MUX_SEL_TOP0_PERIC10x0234
 +#define MUX_SEL_TOP0_PERIC20x0238
  #define MUX_SEL_TOP0_PERIC30x023C
  #define DIV_TOP03  0x060C
 +#define DIV_TOP0_PERIC10x0634
 +#define DIV_TOP0_PERIC20x0638
  #define DIV_TOP0_PERIC30x063C
 +#define ENABLE_SCLK_TOP0_PERIC10x0A34
 +#define ENABLE_SCLK_TOP0_PERIC20x0A38
  #define ENABLE_SCLK_TOP0_PERIC30x0A3C

  /* List of parent clocks for Muxes in CMU_TOP0 */
 @@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
 MUX_SEL_TOP00,
 MUX_SEL_TOP01,
 MUX_SEL_TOP03,
 +   MUX_SEL_TOP0_PERIC1,
 +   MUX_SEL_TOP0_PERIC2,
 MUX_SEL_TOP0_PERIC3,
 DIV_TOP03,
 +   DIV_TOP0_PERIC1,
 +   DIV_TOP0_PERIC2,
 DIV_TOP0_PERIC3,
 +   ENABLE_SCLK_TOP0_PERIC1,
 +   ENABLE_SCLK_TOP0_PERIC2,
 ENABLE_SCLK_TOP0_PERIC3,
  };

 @@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[] 
 __initdata = {
 MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 2),
 MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 2),

 +   MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
 +   MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 
 2),
 +
 +   MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
 +   MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 
 2),
 MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 
 2),
 MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 
 2),
 MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 
 2),
 MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 
 2),
 +   MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 
 2),
  };

  static struct samsung_div_clock top0_div_clks[] __initdata = {
 @@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[] 
 __initdata = {
 DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
 DIV_TOP03, 20, 6),

 +   DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
 +   DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
 +
 +   DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
 +   DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
 +
 DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
 DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
 DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
 DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
 +   DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
  };

  static struct samsung_gate_clock top0_gate_clks[] __initdata = {
 +   GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
 +   ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
 +   GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
 +   ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
 +
 +   GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
 +   ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
 +   GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
 +   ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
 GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
 GATE(CLK_SCLK_UART2, sclk_uart2, dout_sclk_uart2,
 @@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[] 
 __initdata = {
 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
 GATE(CLK_SCLK_UART0, sclk_uart0, dout_sclk_uart0,
 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
 +   GATE(CLK_SCLK_SPI4, sclk_spi4, dout_sclk_spi4,
 +   ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
  };

  static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata 
 = {
 @@ -520,6 +556,7 @@ static

Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block

2015-01-09 Thread Vivek Gautam 
On Fri, Jan 9, 2015 at 5:18 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
 Hi Padma,


 On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com wrote:
 Add clock support for 5 SPI channels.

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  drivers/clk/samsung/clk-exynos7.c   |   73 
 +++
  include/dt-bindings/clock/exynos7-clk.h |   22 -
  2 files changed, 93 insertions(+), 2 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos7.c 
 b/drivers/clk/samsung/clk-exynos7.c
 index 954f9a0..cf5e50e 100644
 --- a/drivers/clk/samsung/clk-exynos7.c
 +++ b/drivers/clk/samsung/clk-exynos7.c
 @@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, 
 samsung,exynos7-clock-topc,
  #define MUX_SEL_TOP00  0x0200
  #define MUX_SEL_TOP01  0x0204
  #define MUX_SEL_TOP03  0x020C
 +#define MUX_SEL_TOP0_PERIC10x0234
 +#define MUX_SEL_TOP0_PERIC20x0238
  #define MUX_SEL_TOP0_PERIC30x023C
  #define DIV_TOP03  0x060C
 +#define DIV_TOP0_PERIC10x0634
 +#define DIV_TOP0_PERIC20x0638
  #define DIV_TOP0_PERIC30x063C
 +#define ENABLE_SCLK_TOP0_PERIC10x0A34
 +#define ENABLE_SCLK_TOP0_PERIC20x0A38
  #define ENABLE_SCLK_TOP0_PERIC30x0A3C

  /* List of parent clocks for Muxes in CMU_TOP0 */
 @@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
 MUX_SEL_TOP00,
 MUX_SEL_TOP01,
 MUX_SEL_TOP03,
 +   MUX_SEL_TOP0_PERIC1,
 +   MUX_SEL_TOP0_PERIC2,
 MUX_SEL_TOP0_PERIC3,
 DIV_TOP03,
 +   DIV_TOP0_PERIC1,
 +   DIV_TOP0_PERIC2,
 DIV_TOP0_PERIC3,
 +   ENABLE_SCLK_TOP0_PERIC1,
 +   ENABLE_SCLK_TOP0_PERIC2,
 ENABLE_SCLK_TOP0_PERIC3,
  };

 @@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[] 
 __initdata = {
 MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 
 2),
 MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 
 2),

 +   MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 
 2),
 +   MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 
 2),
 +
 +   MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 
 2),
 +   MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 
 2),
 MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 
 2),
 MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 
 2),
 MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 
 2),
 MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 
 2),
 +   MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 
 2),
  };

  static struct samsung_div_clock top0_div_clks[] __initdata = {
 @@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[] 
 __initdata = {
 DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
 DIV_TOP03, 20, 6),

 +   DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
 +   DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
 +
 +   DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
 +   DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
 +
 DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
 DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
 DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
 DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
 +   DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
  };

  static struct samsung_gate_clock top0_gate_clks[] __initdata = {
 +   GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
 +   ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
 +   GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
 +   ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
 +
 +   GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
 +   ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
 +   GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
 +   ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
 GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
 GATE(CLK_SCLK_UART2, sclk_uart2, dout_sclk_uart2,
 @@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[] 
 __initdata = {
 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
 GATE(CLK_SCLK_UART0, sclk_uart0, dout_sclk_uart0,
 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
 +   GATE(CLK_SCLK_SPI4, sclk_spi4, dout_sclk_spi4,
 +   ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
  };

  static struct

[PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block

2014-12-19 Thread Padmavathi Venna 
Add clock support for 5 SPI channels.

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 drivers/clk/samsung/clk-exynos7.c   |   73 +++
 include/dt-bindings/clock/exynos7-clk.h |   22 -
 2 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c 
b/drivers/clk/samsung/clk-exynos7.c
index 954f9a0..cf5e50e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, 
samsung,exynos7-clock-topc,
 #define MUX_SEL_TOP00  0x0200
 #define MUX_SEL_TOP01  0x0204
 #define MUX_SEL_TOP03  0x020C
+#define MUX_SEL_TOP0_PERIC10x0234
+#define MUX_SEL_TOP0_PERIC20x0238
 #define MUX_SEL_TOP0_PERIC30x023C
 #define DIV_TOP03  0x060C
+#define DIV_TOP0_PERIC10x0634
+#define DIV_TOP0_PERIC20x0638
 #define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC10x0A34
+#define ENABLE_SCLK_TOP0_PERIC20x0A38
 #define ENABLE_SCLK_TOP0_PERIC30x0A3C
 
 /* List of parent clocks for Muxes in CMU_TOP0 */
@@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+   MUX_SEL_TOP0_PERIC1,
+   MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+   DIV_TOP0_PERIC1,
+   DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+   ENABLE_SCLK_TOP0_PERIC1,
+   ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
 };
 
@@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[] 
__initdata = {
MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 2),
 
+   MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+   MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+   MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+   MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+   MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
 };
 
 static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[] 
__initdata = {
DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
DIV_TOP03, 20, 6),
 
+   DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
+   DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
+
+   DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
+   DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
+   DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
 };
 
 static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+   GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
+   ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+   GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
+   ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+   GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
+   ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+   GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
+   ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, sclk_uart2, dout_sclk_uart2,
@@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[] 
__initdata = {
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
GATE(CLK_SCLK_UART0, sclk_uart0, dout_sclk_uart0,
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+   GATE(CLK_SCLK_SPI4, sclk_spi4, dout_sclk_spi4,
+   ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = 
{
@@ -520,6 +556,7 @@ static void __init exynos7_clk_peric0_init(struct 
device_node *np)
 /* Register Offset definitions for CMU_PERIC1 (0x14C8) */
 #define MUX_SEL_PERIC100x0200
 #define