RE: [PATCH v3] clk: exynos5420: Add 5800 specific clocks

2014-05-19 Thread Kukjin Kim 
Tomasz Figa wrote:
> 
> Hi,
> 
Hi,

> On 19.05.2014 10:32, Arun Kumar K wrote:
> > Hi Tomasz,
> >
> > Can this patch be taken for the 3.16 merge?
> >
> > Regards
> > Arun
> >
> > On Thu, May 15, 2014 at 11:26 AM, Arun Kumar K 
> wrote:
> >> From: Alim Akhtar 
> >>
> >> Exynos5800 clock structure is mostly similar to 5420 with only
> >> a small delta changes. So the 5420 clock file is re-used for
> >> 5800 also. The common clocks for both are seggreagated and few
> >> clocks which are different for both are separately initialized.
> >>
> >> Signed-off-by: Alim Akhtar 
> >> Signed-off-by: Arun Kumar K 
> >> ---
> >> Changes from v2
> >> - Rebased on Tomasz's samsung-clk-next branch of
> >>   samsung-clk [1] tree.
> >>   [1] git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-
> clk.git
> >> Changes from v1
> >> - Rebased on Shaik's clock consolidation for 5420
> >> - Addressed review comments from Tomasz
> 
> Looks good.
> 
> Acked-by: Tomasz Figa 
> 
> Kukjin, since this is just one patch, could you still pick it up
> directly? It should apply anywhere above your v3.16-next/clk-samsung
> branch.
> 
OK, I will with your ack.

Thanks,
Kukjin

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Re: [PATCH v3] clk: exynos5420: Add 5800 specific clocks

2014-05-19 Thread Tomasz Figa 
Hi,

On 19.05.2014 10:32, Arun Kumar K wrote:
> Hi Tomasz,
> 
> Can this patch be taken for the 3.16 merge?
> 
> Regards
> Arun
> 
> On Thu, May 15, 2014 at 11:26 AM, Arun Kumar K  wrote:
>> From: Alim Akhtar 
>>
>> Exynos5800 clock structure is mostly similar to 5420 with only
>> a small delta changes. So the 5420 clock file is re-used for
>> 5800 also. The common clocks for both are seggreagated and few
>> clocks which are different for both are separately initialized.
>>
>> Signed-off-by: Alim Akhtar 
>> Signed-off-by: Arun Kumar K 
>> ---
>> Changes from v2
>> - Rebased on Tomasz's samsung-clk-next branch of
>>   samsung-clk [1] tree.
>>   [1] git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
>> Changes from v1
>> - Rebased on Shaik's clock consolidation for 5420
>> - Addressed review comments from Tomasz

Looks good.

Acked-by: Tomasz Figa 

Kukjin, since this is just one patch, could you still pick it up
directly? It should apply anywhere above your v3.16-next/clk-samsung branch.

Best regards,
Tomasz

>> ---
>>  .../devicetree/bindings/clock/exynos5420-clock.txt |3 +-
>>  drivers/clk/samsung/clk-exynos5420.c   |  309 
>> 
>>  include/dt-bindings/clock/exynos5420.h |4 +
>>  3 files changed, 259 insertions(+), 57 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt 
>> b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>> index ca88c97..d54f42c 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>> @@ -1,12 +1,13 @@
>>  * Samsung Exynos5420 Clock Controller
>>
>>  The Exynos5420 clock controller generates and supplies clock to various
>> -controllers within the Exynos5420 SoC.
>> +controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
>>
>>  Required Properties:
>>
>>  - compatible: should be one of the following.
>>- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
>> +  - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
>>
>>  - reg: physical base address of the controller and length of memory mapped
>>region.
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c 
>> b/drivers/clk/samsung/clk-exynos5420.c
>> index 1c3674e..9d7d7ee 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -57,15 +57,19 @@
>>  #define SRC_TOP5   0x10214
>>  #define SRC_TOP6   0x10218
>>  #define SRC_TOP7   0x1021c
>> +#define SRC_TOP8   0x10220 /* 5800 specific */
>> +#define SRC_TOP9   0x10224 /* 5800 specific */
>>  #define SRC_DISP10 0x1022c
>>  #define SRC_MAU0x10240
>>  #define SRC_FSYS   0x10244
>>  #define SRC_PERIC0 0x10250
>>  #define SRC_PERIC1 0x10254
>>  #define SRC_ISP0x10270
>> +#define SRC_CAM0x10274 /* 5800 specific */
>>  #define SRC_TOP10  0x10280
>>  #define SRC_TOP11  0x10284
>>  #define SRC_TOP12  0x10288
>> +#define SRC_TOP13  0x1028c /* 5800 specific */
>>  #define SRC_MASK_TOP2  0x10308
>>  #define SRC_MASK_TOP7  0x1031c
>>  #define SRC_MASK_DISP100x1032c
>> @@ -76,6 +80,8 @@
>>  #define DIV_TOP0   0x10500
>>  #define DIV_TOP1   0x10504
>>  #define DIV_TOP2   0x10508
>> +#define DIV_TOP8   0x10520 /* 5800 specific */
>> +#define DIV_TOP9   0x10524 /* 5800 specific */
>>  #define DIV_DISP10 0x1052c
>>  #define DIV_MAU0x10544
>>  #define DIV_FSYS0  0x10548
>> @@ -86,6 +92,7 @@
>>  #define DIV_PERIC2 0x10560
>>  #define DIV_PERIC3 0x10564
>>  #define DIV_PERIC4 0x10568
>> +#define DIV_CAM0x10574 /* 5800 specific */
>>  #define SCLK_DIV_ISP0  0x10580
>>  #define SCLK_DIV_ISP1  0x10584
>>  #define DIV2_RATIO00x10590
>> @@ -102,6 +109,7 @@
>>  #define GATE_TOP_SCLK_ISP  0x10870
>>  #define GATE_IP_GSCL0  0x10910
>>  #define GATE_IP_GSCL1  0x10920
>> +#define GATE_IP_CAM0x10924 /* 5800 specific */
>>  #define GATE_IP_MFC0x1092c
>>  #define GATE_IP_DISP1  0x10928
>>  #define GATE_IP_G3D0x10930
>> @@ -123,23 +131,31 @@
>>  #define SRC_KFC0x28200
>>  #define DIV_KFC0   0x28500
>>
>> +/* Exynos5x SoC type */
>> +enum exynos5x_soc {
>> +   EXYNOS5420,
>> +   EXYNOS5800,
>> +};
>> +
>>  /* list of PLLs */
>> -enum exynos5420_plls {
>> +enum exynos5x_plls {
>> apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
>> bpll, kpll,
>> nr_plls /* number of PLLs */
>>  };
>>
>>  static void __iomem *

Re: [PATCH v3] clk: exynos5420: Add 5800 specific clocks

2014-05-19 Thread Arun Kumar K 
Hi Tomasz,

Can this patch be taken for the 3.16 merge?

Regards
Arun

On Thu, May 15, 2014 at 11:26 AM, Arun Kumar K  wrote:
> From: Alim Akhtar 
>
> Exynos5800 clock structure is mostly similar to 5420 with only
> a small delta changes. So the 5420 clock file is re-used for
> 5800 also. The common clocks for both are seggreagated and few
> clocks which are different for both are separately initialized.
>
> Signed-off-by: Alim Akhtar 
> Signed-off-by: Arun Kumar K 
> ---
> Changes from v2
> - Rebased on Tomasz's samsung-clk-next branch of
>   samsung-clk [1] tree.
>   [1] git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
> Changes from v1
> - Rebased on Shaik's clock consolidation for 5420
> - Addressed review comments from Tomasz
> ---
>  .../devicetree/bindings/clock/exynos5420-clock.txt |3 +-
>  drivers/clk/samsung/clk-exynos5420.c   |  309 
> 
>  include/dt-bindings/clock/exynos5420.h |4 +
>  3 files changed, 259 insertions(+), 57 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt 
> b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> index ca88c97..d54f42c 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> @@ -1,12 +1,13 @@
>  * Samsung Exynos5420 Clock Controller
>
>  The Exynos5420 clock controller generates and supplies clock to various
> -controllers within the Exynos5420 SoC.
> +controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
>
>  Required Properties:
>
>  - compatible: should be one of the following.
>- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
> +  - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
>
>  - reg: physical base address of the controller and length of memory mapped
>region.
> diff --git a/drivers/clk/samsung/clk-exynos5420.c 
> b/drivers/clk/samsung/clk-exynos5420.c
> index 1c3674e..9d7d7ee 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -57,15 +57,19 @@
>  #define SRC_TOP5   0x10214
>  #define SRC_TOP6   0x10218
>  #define SRC_TOP7   0x1021c
> +#define SRC_TOP8   0x10220 /* 5800 specific */
> +#define SRC_TOP9   0x10224 /* 5800 specific */
>  #define SRC_DISP10 0x1022c
>  #define SRC_MAU0x10240
>  #define SRC_FSYS   0x10244
>  #define SRC_PERIC0 0x10250
>  #define SRC_PERIC1 0x10254
>  #define SRC_ISP0x10270
> +#define SRC_CAM0x10274 /* 5800 specific */
>  #define SRC_TOP10  0x10280
>  #define SRC_TOP11  0x10284
>  #define SRC_TOP12  0x10288
> +#define SRC_TOP13  0x1028c /* 5800 specific */
>  #define SRC_MASK_TOP2  0x10308
>  #define SRC_MASK_TOP7  0x1031c
>  #define SRC_MASK_DISP100x1032c
> @@ -76,6 +80,8 @@
>  #define DIV_TOP0   0x10500
>  #define DIV_TOP1   0x10504
>  #define DIV_TOP2   0x10508
> +#define DIV_TOP8   0x10520 /* 5800 specific */
> +#define DIV_TOP9   0x10524 /* 5800 specific */
>  #define DIV_DISP10 0x1052c
>  #define DIV_MAU0x10544
>  #define DIV_FSYS0  0x10548
> @@ -86,6 +92,7 @@
>  #define DIV_PERIC2 0x10560
>  #define DIV_PERIC3 0x10564
>  #define DIV_PERIC4 0x10568
> +#define DIV_CAM0x10574 /* 5800 specific */
>  #define SCLK_DIV_ISP0  0x10580
>  #define SCLK_DIV_ISP1  0x10584
>  #define DIV2_RATIO00x10590
> @@ -102,6 +109,7 @@
>  #define GATE_TOP_SCLK_ISP  0x10870
>  #define GATE_IP_GSCL0  0x10910
>  #define GATE_IP_GSCL1  0x10920
> +#define GATE_IP_CAM0x10924 /* 5800 specific */
>  #define GATE_IP_MFC0x1092c
>  #define GATE_IP_DISP1  0x10928
>  #define GATE_IP_G3D0x10930
> @@ -123,23 +131,31 @@
>  #define SRC_KFC0x28200
>  #define DIV_KFC0   0x28500
>
> +/* Exynos5x SoC type */
> +enum exynos5x_soc {
> +   EXYNOS5420,
> +   EXYNOS5800,
> +};
> +
>  /* list of PLLs */
> -enum exynos5420_plls {
> +enum exynos5x_plls {
> apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
> bpll, kpll,
> nr_plls /* number of PLLs */
>  };
>
>  static void __iomem *reg_base;
> +static enum exynos5x_soc exynos5x_soc;
>
>  #ifdef CONFIG_PM_SLEEP
> -static struct samsung_clk_reg_dump *exynos5420_save;
> +static struct samsung_clk_reg_dump *exynos5x_save;
> +static struct samsung_clk_reg_dump *exynos5800_save;
>
>  /*
>   * list of controller registers to be saved and restored during a
>   * suspend/resume cycle.
>   */
> -static unsigned l

[PATCH v3] clk: exynos5420: Add 5800 specific clocks

2014-05-14 Thread Arun Kumar K 
From: Alim Akhtar 

Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.

Signed-off-by: Alim Akhtar 
Signed-off-by: Arun Kumar K 
---
Changes from v2
- Rebased on Tomasz's samsung-clk-next branch of
  samsung-clk [1] tree.
  [1] git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
Changes from v1
- Rebased on Shaik's clock consolidation for 5420
- Addressed review comments from Tomasz
---
 .../devicetree/bindings/clock/exynos5420-clock.txt |3 +-
 drivers/clk/samsung/clk-exynos5420.c   |  309 
 include/dt-bindings/clock/exynos5420.h |4 +
 3 files changed, 259 insertions(+), 57 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index ca88c97..d54f42c 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -1,12 +1,13 @@
 * Samsung Exynos5420 Clock Controller
 
 The Exynos5420 clock controller generates and supplies clock to various
-controllers within the Exynos5420 SoC.
+controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
 
 Required Properties:
 
 - compatible: should be one of the following.
   - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
+  - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
 
 - reg: physical base address of the controller and length of memory mapped
   region.
diff --git a/drivers/clk/samsung/clk-exynos5420.c 
b/drivers/clk/samsung/clk-exynos5420.c
index 1c3674e..9d7d7ee 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -57,15 +57,19 @@
 #define SRC_TOP5   0x10214
 #define SRC_TOP6   0x10218
 #define SRC_TOP7   0x1021c
+#define SRC_TOP8   0x10220 /* 5800 specific */
+#define SRC_TOP9   0x10224 /* 5800 specific */
 #define SRC_DISP10 0x1022c
 #define SRC_MAU0x10240
 #define SRC_FSYS   0x10244
 #define SRC_PERIC0 0x10250
 #define SRC_PERIC1 0x10254
 #define SRC_ISP0x10270
+#define SRC_CAM0x10274 /* 5800 specific */
 #define SRC_TOP10  0x10280
 #define SRC_TOP11  0x10284
 #define SRC_TOP12  0x10288
+#define SRC_TOP13  0x1028c /* 5800 specific */
 #define SRC_MASK_TOP2  0x10308
 #define SRC_MASK_TOP7  0x1031c
 #define SRC_MASK_DISP100x1032c
@@ -76,6 +80,8 @@
 #define DIV_TOP0   0x10500
 #define DIV_TOP1   0x10504
 #define DIV_TOP2   0x10508
+#define DIV_TOP8   0x10520 /* 5800 specific */
+#define DIV_TOP9   0x10524 /* 5800 specific */
 #define DIV_DISP10 0x1052c
 #define DIV_MAU0x10544
 #define DIV_FSYS0  0x10548
@@ -86,6 +92,7 @@
 #define DIV_PERIC2 0x10560
 #define DIV_PERIC3 0x10564
 #define DIV_PERIC4 0x10568
+#define DIV_CAM0x10574 /* 5800 specific */
 #define SCLK_DIV_ISP0  0x10580
 #define SCLK_DIV_ISP1  0x10584
 #define DIV2_RATIO00x10590
@@ -102,6 +109,7 @@
 #define GATE_TOP_SCLK_ISP  0x10870
 #define GATE_IP_GSCL0  0x10910
 #define GATE_IP_GSCL1  0x10920
+#define GATE_IP_CAM0x10924 /* 5800 specific */
 #define GATE_IP_MFC0x1092c
 #define GATE_IP_DISP1  0x10928
 #define GATE_IP_G3D0x10930
@@ -123,23 +131,31 @@
 #define SRC_KFC0x28200
 #define DIV_KFC0   0x28500
 
+/* Exynos5x SoC type */
+enum exynos5x_soc {
+   EXYNOS5420,
+   EXYNOS5800,
+};
+
 /* list of PLLs */
-enum exynos5420_plls {
+enum exynos5x_plls {
apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
bpll, kpll,
nr_plls /* number of PLLs */
 };
 
 static void __iomem *reg_base;
+static enum exynos5x_soc exynos5x_soc;
 
 #ifdef CONFIG_PM_SLEEP
-static struct samsung_clk_reg_dump *exynos5420_save;
+static struct samsung_clk_reg_dump *exynos5x_save;
+static struct samsung_clk_reg_dump *exynos5800_save;
 
 /*
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
-static unsigned long exynos5420_clk_regs[] __initdata = {
+static unsigned long exynos5x_clk_regs[] __initdata = {
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
@@ -222,18 +238,37 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
DIV_KFC0,
 };
 
+static unsigned long exynos5800_clk_regs[] __initdata = {
+   SRC_TOP8,
+   SRC_TOP9,
+