On Sun, Apr 27, 2014 at 12:37:35PM +0900, Jungseok Lee wrote:
On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
[ ... ]
This is overly complicated. For 4 levels we set x0 to be:
ttbr1 + 2*PAGE_SIZE. For 4-levels, we
On Monday, April 28, 2014 10:24 PM, Steve Capper wrote:
On Sun, Apr 27, 2014 at 12:37:35PM +0900, Jungseok Lee wrote:
On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
[ ... ]
This is overly complicated. For 4
On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
[ ... ]
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index
0fd5650..f313a7a 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels of
page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due to the
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels
of page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due to the following issue.
It is a restriction that kernel logical
This patch implements 4 levels of translation tables since 3 levels
of page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due to the following issue.
It is a restriction that kernel logical memory map with 4KB + 3 levels
