Re: [PATCH v4 3/7] ARM: Exynos: add device tree support for MCT controller driver
On 01/21/2013 03:02 AM, Thomas Abraham wrote: > Allow the MCT controller base address and interrupts to be obtained from > device tree and remove unused static definitions of these. The non-dt support > for Exynos5250 is removed but retained for Exynos4210 based platforms. Patches 3 and later in this series, fairly quickly, Reviewed-by: Stephen Warren Sorry for the slow review. I'm not 100% sure if I like Mark's #global-interrupts suggestion or not, but I'd be fine with the binding either way, so choose as you see fit. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/7] ARM: Exynos: add device tree support for MCT controller driver
Hi Marc,
On 21 January 2013 05:46, Mark Rutland wrote:
> On Mon, Jan 21, 2013 at 10:02:18AM +, Thomas Abraham wrote:
>> Allow the MCT controller base address and interrupts to be obtained from
>> device tree and remove unused static definitions of these. The non-dt support
>> for Exynos5250 is removed but retained for Exynos4210 based platforms.
>>
>> Cc: Changhwan Youn
>> Signed-off-by: Thomas Abraham
>> ---
>> .../bindings/timer/samsung,exynos4210-mct.txt | 68
>>
>> arch/arm/mach-exynos/include/mach/irqs.h |6 --
>> arch/arm/mach-exynos/mct.c | 49 +++
>> 3 files changed, 105 insertions(+), 18 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>> new file mode 100644
>> index 000..cb47bfb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>> @@ -0,0 +1,68 @@
>> +Samsung's Multi Core Timer (MCT)
>> +
>> +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
>> +global timer and CPU local timers. The global timer is a 64-bit free running
>> +up-counter and can generate 4 interrupts when the counter reaches one of the
>> +four preset counter values. The CPU local timers are 32-bit free running
>> +down-counters and generate an interrupt when the counter expires. There is
>> +one CPU local timer instantiated in MCT for every CPU in the system.
>> +
>> +Required properties:
>> +
>> +- compatible: should be "samsung,exynos4210-mct".
>> + (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
>> + (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
>> +
>> +- reg: base address of the mct controller and length of the address space
>> + it occupies.
>> +
>> +- interrupts: the list of interrupts generated by the controller. The
>> following
>> + should be the order of the interrupts specified. The local timer
>> interrupts
>> + should be specified after the four global timer interrupts have been
>> + specified.
>> +
>> + 0: Global Timer Interrupt 0
>> + 1: Global Timer Interrupt 1
>> + 2: Global Timer Interrupt 2
>> + 3: Global Timer Interrupt 3
>> + 4: Local Timer Interrupt 0
>> + 5: Local Timer Interrupt 1
>> + 6: ..
>> + 7: ..
>> + i: Local Timer Interrupt n
>> +
>> +Example 1: In this example, the system uses only the first global timer
>> +interrupt generated by MCT and the remaining three global timer
>> +interrupts are unused. Two local timer interrupts have been
>> +specified.
>> +
>> + mct@1005 {
>> + compatible = "samsung,exynos4210-mct";
>> + reg = <0x1005 0x800>;
>> + interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
>> + <0 42 0>, <0 48 0>;
>
> Rather than padding the interrupts list with nonexistent interrupts, could you
> not use something like a #global-interrupts property?
>
> That way you don't have to list fake interrupts, you know exactly how many
> global interrupts to expect (so you can sanity-check the list without any
> special knowledge of the interrupt controller), and it's easier to support
> future revisions which could have more interrupts, in a backwards-compatible
> fashion.
Yes, you are right. I will do this change in the next version. Thanks
for your suggestion.
Thanks,
Thomas.
>
>> + };
>> +
>> +Example 2: In this example, the MCT global and local timer interrupts are
>> +connected to two seperate interrupt controllers. Hence, an
>> +interrupt-map is created to map the interrupts to the respective
>> +interrupt controllers.
>> +
>> + mct@101C {
>> + compatible = "samsung,exynos4210-mct";
>> + reg = <0x101C 0x800>;
>> + interrupt-controller;
>> + #interrups-cells = <2>;
>> + interrupt-parent = <&mct_map>;
>> + interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
>> + <4 0>, <5 0>;
>> +
>> + mct_map: mct-map {
>> + #interrupt-cells = <2>;
>> + #address-cells = <0>;
>> + #size-cells = <0>;
>> + interrupt-map = <0x0 0 &combiner 23 3>,
>> + <0x4 0 &gic 0 120 0>,
>> + <0x5 0 &gic 0 121 0>;
>> + };
>> + };
>
>
> [...]
>
> Thanks,
> Mark.
>
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Re: [PATCH v4 3/7] ARM: Exynos: add device tree support for MCT controller driver
On Mon, Jan 21, 2013 at 10:02:18AM +, Thomas Abraham wrote:
> Allow the MCT controller base address and interrupts to be obtained from
> device tree and remove unused static definitions of these. The non-dt support
> for Exynos5250 is removed but retained for Exynos4210 based platforms.
>
> Cc: Changhwan Youn
> Signed-off-by: Thomas Abraham
> ---
> .../bindings/timer/samsung,exynos4210-mct.txt | 68
>
> arch/arm/mach-exynos/include/mach/irqs.h |6 --
> arch/arm/mach-exynos/mct.c | 49 +++
> 3 files changed, 105 insertions(+), 18 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>
> diff --git
> a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> new file mode 100644
> index 000..cb47bfb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> @@ -0,0 +1,68 @@
> +Samsung's Multi Core Timer (MCT)
> +
> +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
> +global timer and CPU local timers. The global timer is a 64-bit free running
> +up-counter and can generate 4 interrupts when the counter reaches one of the
> +four preset counter values. The CPU local timers are 32-bit free running
> +down-counters and generate an interrupt when the counter expires. There is
> +one CPU local timer instantiated in MCT for every CPU in the system.
> +
> +Required properties:
> +
> +- compatible: should be "samsung,exynos4210-mct".
> + (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
> + (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
> +
> +- reg: base address of the mct controller and length of the address space
> + it occupies.
> +
> +- interrupts: the list of interrupts generated by the controller. The
> following
> + should be the order of the interrupts specified. The local timer interrupts
> + should be specified after the four global timer interrupts have been
> + specified.
> +
> + 0: Global Timer Interrupt 0
> + 1: Global Timer Interrupt 1
> + 2: Global Timer Interrupt 2
> + 3: Global Timer Interrupt 3
> + 4: Local Timer Interrupt 0
> + 5: Local Timer Interrupt 1
> + 6: ..
> + 7: ..
> + i: Local Timer Interrupt n
> +
> +Example 1: In this example, the system uses only the first global timer
> +interrupt generated by MCT and the remaining three global timer
> +interrupts are unused. Two local timer interrupts have been
> +specified.
> +
> + mct@1005 {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x1005 0x800>;
> + interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
> + <0 42 0>, <0 48 0>;
Rather than padding the interrupts list with nonexistent interrupts, could you
not use something like a #global-interrupts property?
That way you don't have to list fake interrupts, you know exactly how many
global interrupts to expect (so you can sanity-check the list without any
special knowledge of the interrupt controller), and it's easier to support
future revisions which could have more interrupts, in a backwards-compatible
fashion.
> + };
> +
> +Example 2: In this example, the MCT global and local timer interrupts are
> +connected to two seperate interrupt controllers. Hence, an
> +interrupt-map is created to map the interrupts to the respective
> +interrupt controllers.
> +
> + mct@101C {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x101C 0x800>;
> + interrupt-controller;
> + #interrups-cells = <2>;
> + interrupt-parent = <&mct_map>;
> + interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
> + <4 0>, <5 0>;
> +
> + mct_map: mct-map {
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + #size-cells = <0>;
> + interrupt-map = <0x0 0 &combiner 23 3>,
> + <0x4 0 &gic 0 120 0>,
> + <0x5 0 &gic 0 121 0>;
> + };
> + };
[...]
Thanks,
Mark.
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[PATCH v4 3/7] ARM: Exynos: add device tree support for MCT controller driver
Allow the MCT controller base address and interrupts to be obtained from
device tree and remove unused static definitions of these. The non-dt support
for Exynos5250 is removed but retained for Exynos4210 based platforms.
Cc: Changhwan Youn
Signed-off-by: Thomas Abraham
---
.../bindings/timer/samsung,exynos4210-mct.txt | 68
arch/arm/mach-exynos/include/mach/irqs.h |6 --
arch/arm/mach-exynos/mct.c | 49 +++
3 files changed, 105 insertions(+), 18 deletions(-)
create mode 100644
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 000..cb47bfb
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,68 @@
+Samsung's Multi Core Timer (MCT)
+
+The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
+global timer and CPU local timers. The global timer is a 64-bit free running
+up-counter and can generate 4 interrupts when the counter reaches one of the
+four preset counter values. The CPU local timers are 32-bit free running
+down-counters and generate an interrupt when the counter expires. There is
+one CPU local timer instantiated in MCT for every CPU in the system.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-mct".
+ (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
+ (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
+
+- reg: base address of the mct controller and length of the address space
+ it occupies.
+
+- interrupts: the list of interrupts generated by the controller. The following
+ should be the order of the interrupts specified. The local timer interrupts
+ should be specified after the four global timer interrupts have been
+ specified.
+
+ 0: Global Timer Interrupt 0
+ 1: Global Timer Interrupt 1
+ 2: Global Timer Interrupt 2
+ 3: Global Timer Interrupt 3
+ 4: Local Timer Interrupt 0
+ 5: Local Timer Interrupt 1
+ 6: ..
+ 7: ..
+ i: Local Timer Interrupt n
+
+Example 1: In this example, the system uses only the first global timer
+ interrupt generated by MCT and the remaining three global timer
+ interrupts are unused. Two local timer interrupts have been
+ specified.
+
+ mct@1005 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x1005 0x800>;
+ interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+<0 42 0>, <0 48 0>;
+ };
+
+Example 2: In this example, the MCT global and local timer interrupts are
+ connected to two seperate interrupt controllers. Hence, an
+ interrupt-map is created to map the interrupts to the respective
+ interrupt controllers.
+
+ mct@101C {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C 0x800>;
+ interrupt-controller;
+ #interrups-cells = <2>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+<4 0>, <5 0>;
+
+ mct_map: mct-map {
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0x0 0 &combiner 23 3>,
+ <0x4 0 &gic 0 120 0>,
+ <0x5 0 &gic 0 121 0>;
+ };
+ };
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 6794292..35fe6d5 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
/* For EXYNOS4 and EXYNOS5 */
-#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
-
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
/* For EXYNOS4 SoCs */
@@ -330,8 +328,6 @@
#define EXYNOS5_IRQ_CECIRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
-#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -426,8 +422,6 @@
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach
