Chander Kashyap wrote:
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.
This patch adds support for core power down idle state.
Entry latency for core power down idle state is calculated as follows:
1. Time
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.
This patch adds support for core power down idle state.
Entry latency for core power down idle state is calculated as follows:
1. Time difference is measured between
